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Sun, 15 Jan 2023 23:22:33 -0800 (PST) Received: from LAP568U.mistral.in ([106.51.227.150]) by smtp.gmail.com with ESMTPSA id d17-20020a170902ced100b001895f7c8a71sm1770346plg.97.2023.01.15.23.22.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 15 Jan 2023 23:22:32 -0800 (PST) From: Sinthu Raja X-Google-Original-From: Sinthu Raja To: Nishanth Menon , Tero Kristo , Rob Herring Cc: Vignesh Raghavendra , Krzysztof Kozlowski , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Sinthu Raja , Krzysztof Kozlowski Subject: [PATCH V5 1/3] dt-bindings: arm: ti: Add binding for AM68 SK Date: Mon, 16 Jan 2023 12:44:44 +0530 Message-Id: <20230116071446.28867-2-sinthu.raja@ti.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20230116071446.28867-1-sinthu.raja@ti.com> References: <20230116071446.28867-1-sinthu.raja@ti.com> MIME-Version: 1.0 X-BESS-ID: 1673853754-305424-5383-505-1 X-BESS-VER: 2019.1_20221214.2106 X-BESS-Apparent-Source-IP: 209.85.216.69 X-BESS-Outbound-Spam-Score: 0.00 X-BESS-Outbound-Spam-Report: Code version 3.2, rules version 3.2.2.245498 [from cloudscan23-233.eu-central-1b.ess.aws.cudaops.com] Rule breakdown below pts rule name description ---- ---------------------- -------------------------------- 0.00 BSF_SC0_MISMATCH_TO META: Envelope rcpt doesn't match header 0.00 BSF_BESS_OUTBOUND META: BESS Outbound X-BESS-Outbound-Spam-Status: SCORE=0.00 using account:ESS91090 scores of KILL_LEVEL=7.0 tests=BSF_SC0_MISMATCH_TO, BSF_BESS_OUTBOUND X-BESS-BRTS-Status: 1 X-Spam-Status: No, score=-2.8 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_LOW, RCVD_IN_MSPIKE_H2,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1755162937209106841?= X-GMAIL-MSGID: =?utf-8?q?1755162937209106841?= From: Sinthu Raja AM68 Starter Kit is a low cost, small form factor board designed for TI's AM68 SoC which is optimized to provide best in class performance for industrial applications and add binding for the same. Signed-off-by: Sinthu Raja Acked-by: Krzysztof Kozlowski --- No changes in V4 & V5 Changes in V3: ============= Add Acked-by tag. Changes in V2: ============= *Address review comment - add entry in alphabetical order. Documentation/devicetree/bindings/arm/ti/k3.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/ti/k3.yaml b/Documentation/devicetree/bindings/arm/ti/k3.yaml index 203faab80142..acbc25108533 100644 --- a/Documentation/devicetree/bindings/arm/ti/k3.yaml +++ b/Documentation/devicetree/bindings/arm/ti/k3.yaml @@ -69,6 +69,7 @@ properties: - description: K3 J721s2 SoC items: - enum: + - ti,am68-sk - ti,j721s2-evm - const: ti,j721s2 From patchwork Mon Jan 16 07:14:45 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Sinthu Raja X-Patchwork-Id: 44000 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:eb09:0:0:0:0:0 with SMTP id s9csp1061204wrn; Sun, 15 Jan 2023 23:24:49 -0800 (PST) X-Google-Smtp-Source: AMrXdXtlZbqfgMoNusyt+g+sWl2glyt2GO7Nj2iZCd3pWx7jq4Bf3zXU0P+IFeY/VurUOe7+SnrZ X-Received: by 2002:a17:90b:51c5:b0:223:2aa6:7f0f with SMTP id sf5-20020a17090b51c500b002232aa67f0fmr96260559pjb.7.1673853889247; Sun, 15 Jan 2023 23:24:49 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1673853889; cv=none; d=google.com; s=arc-20160816; b=l0Jy8MVEFjBnBiHku/k6Dmk3xFSId2e7WkcyB7VzztQX/d7VClVQ/BRyaQEiG6rj36 aVfI8oQvNQZoxBVzofXLeOk1o8VekuuLlAvTH9TwUYJopFezR20pzQFbQ8afEFs9Stnx mCwLkmGrj9qpASNOxk1sUB2UyRO5gOB+VMzvXGAdhKUk6qRx4dzOXsya8SK/3GKqO+Dq xFMGJJu1IfPpDl9o8FoQ8814Bx145cX9fP3i0gwpSXag9N2SG78dkQcKyIimyimMvnpf qrVqmv1c1LzaJv0qcYSS8ljJOqo8TFxVxtbw219Or4cQ4R7b6WK7+ZcMFvZzdMp0Tv5S gpDA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=gN3DM3KkWcZR5XsGbUD2vNQk/vk7I/JC/dpmGMxqX58=; b=Nr3nMrRRiP8oHgexoi4xy6GcoHB/pS/h+EGv7cyIn2hefr5Dumwp2imjJ+N/H2l+cS gI36iD/jRXD+zObEuLbKtnIqSWzBzGR+hJ3nIz06OYw6MpmC7RKhI8Ly6KU/dlYa0mw2 roBmomuxmoGToeaDJnHew5M+oNDHiWv5r0EQ8ISDdIJ9jPcAvY6cQ07jkdPS2zjAlUIh XOUWkt4UWu0uVOBinqxs3fPazykz4CHfOlsYyHeW0oTxWy5KIzlpw98kKQU5PcaV0Hch LMql3d5MunJmNUQ4cYCHZNhEN1dlXs9KpzQ2pc1n+tetlKDTD1OcqAsbqV5kiNtVVR49 4asw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@mistralsolutions.com header.s=google header.b=oj4He+vC; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=mistralsolutions.com Received: from out1.vger.email (out1.vger.email. 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Sun, 15 Jan 2023 23:22:36 -0800 (PST) Received: from LAP568U.mistral.in ([106.51.227.150]) by smtp.gmail.com with ESMTPSA id d17-20020a170902ced100b001895f7c8a71sm1770346plg.97.2023.01.15.23.22.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 15 Jan 2023 23:22:36 -0800 (PST) From: Sinthu Raja X-Google-Original-From: Sinthu Raja To: Nishanth Menon , Tero Kristo , Rob Herring Cc: Vignesh Raghavendra , Krzysztof Kozlowski , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Sinthu Raja Subject: [PATCH V5 2/3] arm64: dts: ti: Add initial support for AM68 SK System on Module Date: Mon, 16 Jan 2023 12:44:45 +0530 Message-Id: <20230116071446.28867-3-sinthu.raja@ti.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20230116071446.28867-1-sinthu.raja@ti.com> References: <20230116071446.28867-1-sinthu.raja@ti.com> MIME-Version: 1.0 X-BESS-ID: 1673853757-303489-5384-466-1 X-BESS-VER: 2019.1_20221214.2106 X-BESS-Apparent-Source-IP: 209.85.216.69 X-BESS-Outbound-Spam-Score: 0.40 X-BESS-Outbound-Spam-Report: Code version 3.2, rules version 3.2.2.245498 [from cloudscan18-235.eu-central-1b.ess.aws.cudaops.com] Rule breakdown below pts rule name description ---- ---------------------- -------------------------------- 0.40 BSF_SC0_SA085b META: Custom Rule SA085b 0.00 BSF_BESS_OUTBOUND META: BESS Outbound 0.00 BSF_SC0_MISMATCH_TO META: Envelope rcpt doesn't match header X-BESS-Outbound-Spam-Status: SCORE=0.40 using account:ESS91090 scores of KILL_LEVEL=7.0 tests=BSF_SC0_SA085b, BSF_BESS_OUTBOUND, BSF_SC0_MISMATCH_TO X-BESS-BRTS-Status: 1 X-Spam-Status: No, score=-2.8 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_LOW, RCVD_IN_MSPIKE_H2,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1755163015999402900?= X-GMAIL-MSGID: =?utf-8?q?1755163015999402900?= From: Sinthu Raja AM68 Starter Kit (SK) is a low cost, small form factor board designed for TI’s AM68 SoC. TI’s AM68 SoC comprises of dual core A72, high performance vision accelerators, hardware accelerators, latest C71x DSP, high bandwidth real-time IPs for capture and display. The SoC is power optimized to provide best in class performance for industrial applications. AM68 SK supports the following interfaces: * 16 GB LPDDR4 RAM * x1 Gigabit Ethernet interface * x1 USB 3.1 Type-C port * x2 USB 3.1 Type-A ports * x1 PCIe M.2 M Key * 512 Mbit OSPI flash * x2 CSI2 Camera interface (RPi and TI Camera connector) * 40-pin Raspberry Pi GPIO header SK's System on Module (SoM) contains the SoC and DDR. Therefore, add DT node for the SOC and DDR on the SoM. Schematics: https://www.ti.com/lit/zip/SPRR463 TRM: http://www.ti.com/lit/pdf/spruj28 Signed-off-by: Sinthu Raja Tested-by: Vaishnav Achath --- Changes in V5: ============= Address review comments: - Remove the unessential comment. - Remove alignment property from secure-ddr node, as no memory is allocated out of this region. No changes in V4. Changes in V3: ============= Addressed review comments - Removed the unused nodes that are disabled by default. OSPI support will be added once the OSPI node is enabled for J721s2/AM68 in main DTSI. Changes in V2: ============= Address review comments - drop the empty lines. V1: https://lore.kernel.org/linux-arm-kernel/20221018123849.23695-3-sinthu.raja@ti.com/ V2: https://lore.kernel.org/lkml/20221107123852.8063-3-sinthu.raja@ti.com/ V3: https://lore.kernel.org/lkml/20230110110052.14851-3-sinthu.raja@ti.com/ V4: https://lore.kernel.org/lkml/20230105151740.29436-3-sinthu.raja@ti.com/ arch/arm64/boot/dts/ti/k3-am68-sk-som.dtsi | 29 ++++++++++++++++++++++ 1 file changed, 29 insertions(+) create mode 100644 arch/arm64/boot/dts/ti/k3-am68-sk-som.dtsi diff --git a/arch/arm64/boot/dts/ti/k3-am68-sk-som.dtsi b/arch/arm64/boot/dts/ti/k3-am68-sk-som.dtsi new file mode 100644 index 000000000000..e92431250729 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am68-sk-som.dtsi @@ -0,0 +1,29 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; + +#include "k3-j721s2.dtsi" +#include + +/ { + memory@80000000 { + device_type = "memory"; + /* 16 GB RAM */ + reg = <0x00 0x80000000 0x00 0x80000000>, + <0x08 0x80000000 0x03 0x80000000>; + }; + + reserved_memory: reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + secure_ddr: optee@9e800000 { + reg = <0x00 0x9e800000 0x00 0x01800000>; + no-map; + }; + }; +}; From patchwork Mon Jan 16 07:14:46 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sinthu Raja X-Patchwork-Id: 43999 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:eb09:0:0:0:0:0 with SMTP id s9csp1061028wrn; Sun, 15 Jan 2023 23:24:06 -0800 (PST) X-Google-Smtp-Source: AMrXdXsWivHtpw44D4/lGaMT0o7U9pgMjbudMSE+ba3qmsTqeQcg3J2D8xKUE6KAGtUWfr8Nupv3 X-Received: by 2002:a17:903:2113:b0:194:55df:4fe with SMTP id o19-20020a170903211300b0019455df04femr15336225ple.35.1673853845785; Sun, 15 Jan 2023 23:24:05 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1673853845; cv=none; d=google.com; s=arc-20160816; b=Hmz4uX/Wcb7zjDkgVB/g4b5R6LpwC47J/trFpi6wwZXyBNkz9BiLrDvCroXQJ2e2JK zQjEpkI12vlURUkm618OzzyY0pzPqIbb3IM+QRPHND7xkfioCJcthGEamyX6fPZ+GJtm RQqrAo2Yw2IQCY61V1Og03LJpcKBGOHrR8Lhr0Yw7TNXMOqXUCWvnyH6TuRYdYbxzGKG PP0iQQGrhY30HF0rEe5ooKcMuYHSEQp7BOs3F0+I015xHSR0SmPLBKzvFBTr5D9LB5a8 RQ/74jztzreEmOnALMGYW2yN63DjqgwtbjoCdxGVeaSSd2QwnlV+Q0F4uD2mys8qAi/D tKYQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=cUPtI99MwjncOEF6bRvr7n98rdiXOxsTy+T+CnHKJEI=; b=M3NCIaptVT4pH5QjTNfUM7259/YHsx7FAGCLRgMVmRvjKTlDK/zzZjGolXCRlu8xFd qh+IqxQfHkj7ks+yMFwt5wpJMilOlpFi1TmdAZQLN0O4nfKQbLSCQ+AZKdEl0CabTLPi YX8rNjk6FrSrZfhNz9ZXWEtnQX4JKW59AK7E2RfbglRIOIYRFdB8KdmMuA7uyL7nHMYV ZzwfjaKuSXrmmFC/H+6kwmPb2zNalvN0/9USrc5m4HPY51MK4MHPXV3AeUiuTTLFjiGR wxi3TXzm1Sc1iXgElTHFzXcY4MGCVSDSSRhRMcJoJW0C5ezrSg/Q4HEMNv1UeDhOvXV/ M+pw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@mistralsolutions.com header.s=google header.b=jCMhYKom; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=mistralsolutions.com Received: from out1.vger.email (out1.vger.email. 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Sun, 15 Jan 2023 23:22:39 -0800 (PST) Received: from LAP568U.mistral.in ([106.51.227.150]) by smtp.gmail.com with ESMTPSA id d17-20020a170902ced100b001895f7c8a71sm1770346plg.97.2023.01.15.23.22.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 15 Jan 2023 23:22:39 -0800 (PST) From: Sinthu Raja X-Google-Original-From: Sinthu Raja To: Nishanth Menon , Tero Kristo , Rob Herring Cc: Vignesh Raghavendra , Krzysztof Kozlowski , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Sinthu Raja Subject: [PATCH V5 3/3] arm64: dts: ti: k3-am68-sk: Add support for AM68 SK base board Date: Mon, 16 Jan 2023 12:44:46 +0530 Message-Id: <20230116071446.28867-4-sinthu.raja@ti.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20230116071446.28867-1-sinthu.raja@ti.com> References: <20230116071446.28867-1-sinthu.raja@ti.com> MIME-Version: 1.0 X-BESS-ID: 1673853754-311789-5472-458-2 X-BESS-VER: 2019.1_20221214.2106 X-BESS-Apparent-Source-IP: 209.85.214.200 X-BESS-Outbound-Spam-Score: 0.90 X-BESS-Outbound-Spam-Report: Code version 3.2, rules version 3.2.2.245498 [from cloudscan23-42.eu-central-1b.ess.aws.cudaops.com] Rule breakdown below pts rule name description ---- ---------------------- -------------------------------- 0.40 BSF_SC0_SA085b META: Custom Rule SA085b 0.50 BSF_RULE7568M META: Custom Rule 7568M 0.00 BSF_BESS_OUTBOUND META: BESS Outbound 0.00 BSF_SC0_MISMATCH_TO META: Envelope rcpt doesn't match header X-BESS-Outbound-Spam-Status: SCORE=0.90 using account:ESS91090 scores of KILL_LEVEL=7.0 tests=BSF_SC0_SA085b, BSF_RULE7568M, BSF_BESS_OUTBOUND, BSF_SC0_MISMATCH_TO X-BESS-BRTS-Status: 1 X-Spam-Status: No, score=-2.8 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_LOW, RCVD_IN_MSPIKE_H2,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1755162970217844778?= X-GMAIL-MSGID: =?utf-8?q?1755162970217844778?= From: Sinthu Raja The SK architecture comprises of baseboard and a SOM board. The AM68 Starter Kit's baseboard contains most of the actual connectors, power supply etc. The System on Module (SoM) is plugged on to the base board. Therefore, add support for peripherals brought out in the base board. Schematics: https://www.ti.com/lit/zip/SPRR463 Signed-off-by: Sinthu Raja Tested-by: Vaishnav Achath --- No changes in V4 & V5 Changes in V3: ============= *Address review comments: - Remove the unused nodes that are disabled by default. - Update the gpio regulator node: gpio-regulator-tlv to "regulator-tlv". Changes in V2: ============= *Address the review comments: - Update the commit description. - Update the regulator nodes: fixedregulator to "regulator-" - Update the commit $subject to align with rest of the commits. - Drop the blank lines - Change the node names that are added with underscore("_") with "-" V1: https://lore.kernel.org/linux-arm-kernel/20221018123849.23695-4-sinthu.raja@ti.com/ V2: https://lore.kernel.org/lkml/20221107123852.8063-4-sinthu.raja@ti.com/ V3: https://lore.kernel.org/lkml/20230110110052.14851-4-sinthu.raja@ti.com/ V4: https://lore.kernel.org/lkml/20230105151740.29436-4-sinthu.raja@ti.com/ arch/arm64/boot/dts/ti/Makefile | 2 + .../boot/dts/ti/k3-am68-sk-base-board.dts | 335 ++++++++++++++++++ 2 files changed, 337 insertions(+) create mode 100644 arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile index cf7c509538a4..1b4e8b573de5 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -12,6 +12,8 @@ dtb-$(CONFIG_ARCH_K3) += k3-am6528-iot2050-basic-pg2.dtb dtb-$(CONFIG_ARCH_K3) += k3-am6548-iot2050-advanced.dtb dtb-$(CONFIG_ARCH_K3) += k3-am6548-iot2050-advanced-pg2.dtb +dtb-$(CONFIG_ARCH_K3) += k3-am68-sk-base-board.dtb + dtb-$(CONFIG_ARCH_K3) += k3-j721e-beagleboneai64.dtb dtb-$(CONFIG_ARCH_K3) += k3-j721e-common-proc-board.dtb dtb-$(CONFIG_ARCH_K3) += k3-j721e-sk.dtb diff --git a/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts b/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts new file mode 100644 index 000000000000..2091cd2431fb --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts @@ -0,0 +1,335 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + * + * Base Board: https://www.ti.com/lit/zip/SPRR463 + */ + +/dts-v1/; + +#include "k3-am68-sk-som.dtsi" +#include +#include +#include +#include + +/ { + compatible = "ti,am68-sk", "ti,j721s2"; + model = "Texas Instruments AM68 SK"; + + chosen { + stdout-path = "serial2:115200n8"; + }; + + aliases { + serial2 = &main_uart8; + mmc1 = &main_sdhci1; + can0 = &mcu_mcan0; + can1 = &mcu_mcan1; + can2 = &main_mcan6; + can3 = &main_mcan7; + }; + + vusb_main: regulator-vusb-main5v0 { + /* USB MAIN INPUT 5V DC */ + compatible = "regulator-fixed"; + regulator-name = "vusb-main5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; + + vsys_3v3: regulator-vsys3v3 { + /* Output of LM5141 */ + compatible = "regulator-fixed"; + regulator-name = "vsys_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vusb_main>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_mmc1: regulator-sd { + /* Output of TPS22918 */ + compatible = "regulator-fixed"; + regulator-name = "vdd_mmc1"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + enable-active-high; + vin-supply = <&vsys_3v3>; + gpio = <&exp1 10 GPIO_ACTIVE_HIGH>; + }; + + vdd_sd_dv: regulator-tlv71033 { + /* Output of TLV71033 */ + compatible = "regulator-gpio"; + regulator-name = "tlv71033"; + pinctrl-names = "default"; + pinctrl-0 = <&vdd_sd_dv_pins_default>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + vin-supply = <&vsys_3v3>; + gpios = <&main_gpio0 49 GPIO_ACTIVE_HIGH>; + states = <1800000 0x0>, + <3300000 0x1>; + }; + + vsys_io_1v8: regulator-vsys-io-1v8 { + compatible = "regulator-fixed"; + regulator-name = "vsys_io_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + vsys_io_1v2: regulator-vsys-io-1v2 { + compatible = "regulator-fixed"; + regulator-name = "vsys_io_1v2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + regulator-boot-on; + }; + + transceiver1: can-phy0 { + compatible = "ti,tcan1042"; + #phy-cells = <0>; + max-bitrate = <5000000>; + }; + + transceiver2: can-phy1 { + compatible = "ti,tcan1042"; + #phy-cells = <0>; + max-bitrate = <5000000>; + }; + + transceiver3: can-phy2 { + compatible = "ti,tcan1042"; + #phy-cells = <0>; + max-bitrate = <5000000>; + }; + + transceiver4: can-phy3 { + compatible = "ti,tcan1042"; + #phy-cells = <0>; + max-bitrate = <5000000>; + }; +}; + +&main_pmx0 { + main_uart8_pins_default: main-uart8-pins-default { + pinctrl-single,pins = < + J721S2_IOPAD(0x0d0, PIN_INPUT, 11) /* (AF26) SPI0_CS1.UART8_RXD */ + J721S2_IOPAD(0x0d4, PIN_OUTPUT, 11) /* (AH27) SPI0_CLK.UART8_TXD */ + >; + }; + + main_i2c0_pins_default: main-i2c0-pins-default { + pinctrl-single,pins = < + J721S2_IOPAD(0x0e0, PIN_INPUT, 0) /* (AH25) I2C0_SCL */ + J721S2_IOPAD(0x0e4, PIN_INPUT, 0) /* (AE24) I2C0_SDA */ + >; + }; + + main_mmc1_pins_default: main-mmc1-pins-default { + pinctrl-single,pins = < + J721S2_IOPAD(0x104, PIN_INPUT, 0) /* (P23) MMC1_CLK */ + J721S2_IOPAD(0x108, PIN_INPUT, 0) /* (N24) MMC1_CMD */ + J721S2_IOPAD(0x0fc, PIN_INPUT, 0) /* (M23) MMC1_DAT0 */ + J721S2_IOPAD(0x0f8, PIN_INPUT, 0) /* (P24) MMC1_DAT1 */ + J721S2_IOPAD(0x0f4, PIN_INPUT, 0) /* (R24) MMC1_DAT2 */ + J721S2_IOPAD(0x0f0, PIN_INPUT, 0) /* (R22) MMC1_DAT3 */ + J721S2_IOPAD(0x0e8, PIN_INPUT, 8) /* (AE25) TIMER_IO0.MMC1_SDCD */ + >; + }; + + vdd_sd_dv_pins_default: vdd-sd-dv-pins-default { + pinctrl-single,pins = < + J721S2_IOPAD(0x0c4, PIN_INPUT, 7) /* (AB26) ECAP0_IN_APWM_OUT.GPIO0_49 */ + >; + }; + + main_usbss0_pins_default: main-usbss0-pins-default { + pinctrl-single,pins = < + J721S2_IOPAD(0x0ec, PIN_OUTPUT, 6) /* (AG25) TIMER_IO1.USB0_DRVVBUS */ + >; + }; + + main_mcan6_pins_default: main-mcan6-pins-default { + pinctrl-single,pins = < + J721S2_IOPAD(0x098, PIN_INPUT, 0) /* (V25) MCASP0_AXR10.MCAN6_RX */ + J721S2_IOPAD(0x094, PIN_INPUT, 0) /* (AA25) MCASP0_AXR9.MCAN6_TX */ + >; + }; + + main_mcan7_pins_default: main-mcan7-pins-default { + pinctrl-single,pins = < + J721S2_IOPAD(0x0a0, PIN_INPUT, 0) /* (AB25) MCASP0_AXR12.MCAN7_RX */ + J721S2_IOPAD(0x09c, PIN_INPUT, 0) /* (T24) MCASP0_AXR11.MCAN7_TX */ + >; + }; +}; + +&wkup_pmx0 { + mcu_cpsw_pins_default: mcu-cpsw-pins-default { + pinctrl-single,pins = < + J721S2_WKUP_IOPAD(0x094, PIN_INPUT, 0) /* (B22) MCU_RGMII1_RD0 */ + J721S2_WKUP_IOPAD(0x090, PIN_INPUT, 0) /* (B21) MCU_RGMII1_RD1 */ + J721S2_WKUP_IOPAD(0x08c, PIN_INPUT, 0) /* (C22) MCU_RGMII1_RD2 */ + J721S2_WKUP_IOPAD(0x088, PIN_INPUT, 0) /* (D23) MCU_RGMII1_RD3 */ + J721S2_WKUP_IOPAD(0x084, PIN_INPUT, 0) /* (D22) MCU_RGMII1_RXC */ + J721S2_WKUP_IOPAD(0x06c, PIN_INPUT, 0) /* (E23) MCU_RGMII1_RX_CTL */ + J721S2_WKUP_IOPAD(0x07c, PIN_OUTPUT, 0) /* (F23) MCU_RGMII1_TD0 */ + J721S2_WKUP_IOPAD(0x078, PIN_OUTPUT, 0) /* (G22) MCU_RGMII1_TD1 */ + J721S2_WKUP_IOPAD(0x074, PIN_OUTPUT, 0) /* (E21) MCU_RGMII1_TD2 */ + J721S2_WKUP_IOPAD(0x070, PIN_OUTPUT, 0) /* (E22) MCU_RGMII1_TD3 */ + J721S2_WKUP_IOPAD(0x080, PIN_OUTPUT, 0) /* (F21) MCU_RGMII1_TXC */ + J721S2_WKUP_IOPAD(0x068, PIN_OUTPUT, 0) /* (F22) MCU_RGMII1_TX_CTL */ + >; + }; + + mcu_mdio_pins_default: mcu-mdio-pins-default { + pinctrl-single,pins = < + J721S2_WKUP_IOPAD(0x09c, PIN_OUTPUT, 0) /* (A21) MCU_MDIO0_MDC */ + J721S2_WKUP_IOPAD(0x098, PIN_INPUT, 0) /* (A22) MCU_MDIO0_MDIO */ + >; + }; + + mcu_mcan0_pins_default: mcu-mcan0-pins-default { + pinctrl-single,pins = < + J721S2_WKUP_IOPAD(0x0bc, PIN_INPUT, 0) /* (E28) MCU_MCAN0_RX */ + J721S2_WKUP_IOPAD(0x0b8, PIN_OUTPUT, 0) /* (E27) MCU_MCAN0_TX */ + >; + }; + + mcu_mcan1_pins_default: mcu-mcan1-pins-default { + pinctrl-single,pins = < + J721S2_WKUP_IOPAD(0x0d4, PIN_INPUT, 0) /* (F26) WKUP_GPIO0_5.MCU_MCAN1_RX */ + J721S2_WKUP_IOPAD(0x0d0, PIN_OUTPUT, 0) /* (C23) WKUP_GPIO0_4.MCU_MCAN1_TX*/ + >; + }; + + mcu_i2c1_pins_default: mcu-i2c1-pins-default { + pinctrl-single,pins = < + J721S2_WKUP_IOPAD(0x0e0, PIN_INPUT, 0) /* (F24) WKUP_GPIO0_8.MCU_I2C1_SCL */ + J721S2_WKUP_IOPAD(0x0e4, PIN_INPUT, 0) /* (H26) WKUP_GPIO0_9.MCU_I2C1_SDA */ + >; + }; +}; + +&main_gpio2 { + status = "disabled"; +}; + +&main_gpio4 { + status = "disabled"; +}; + +&main_gpio6 { + status = "disabled"; +}; + +&wkup_gpio0 { + status = "disabled"; +}; + +&wkup_gpio1 { + status = "disabled"; +}; + +&wkup_uart0 { + status = "reserved"; +}; + +&main_uart8 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_uart8_pins_default>; + /* Shared with TFA on this platform */ + power-domains = <&k3_pds 357 TI_SCI_PD_SHARED>; +}; + +&main_i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c0_pins_default>; + clock-frequency = <400000>; + + exp1: gpio@21 { + compatible = "ti,tca6416"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = "CSI_VIO_SEL", "CSI_SEL_FPC_EXPn", "HDMI_PDn", + "HDMI_LS_OE", "DP0_3V3 _EN", "BOARDID_EEPROM_WP", + "CAN_STB", " ", "GPIO_uSD_PWR_EN", "eDP_ENABLE", + "IO_EXP_PCIe1_M.2_RTSz", "IO_EXP_MCU_RGMII_RSTz", + "IO_EXP_CSI2_EXP_RSTz", " ", "CSI0_B_GPIO1", + "CSI1_B_GPIO1"; + }; +}; + +&main_sdhci0 { + /* Unused */ + status = "disabled"; +}; + +&main_sdhci1 { + /* SD card */ + pinctrl-0 = <&main_mmc1_pins_default>; + pinctrl-names = "default"; + disable-wp; + vmmc-supply = <&vdd_mmc1>; + vqmmc-supply = <&vdd_sd_dv>; +}; + +&mcu_cpsw { + pinctrl-names = "default"; + pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>; +}; + +&davinci_mdio { + phy0: ethernet-phy@0 { + reg = <0>; + ti,rx-internal-delay = ; + ti,fifo-depth = ; + ti,min-output-impedance; + }; +}; + +&cpsw_port1 { + phy-mode = "rgmii-rxid"; + phy-handle = <&phy0>; +}; + +&mcu_mcan0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mcu_mcan0_pins_default>; + phys = <&transceiver1>; +}; + +&mcu_mcan1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mcu_mcan1_pins_default>; + phys = <&transceiver2>; +}; + +&main_mcan6 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_mcan6_pins_default>; + phys = <&transceiver3>; +}; + +&main_mcan7 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_mcan7_pins_default>; + phys = <&transceiver4>; +};