From patchwork Fri Jan 13 10:16:04 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benjamin Gaignard X-Patchwork-Id: 43132 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4e01:0:0:0:0:0 with SMTP id p1csp189136wrt; Fri, 13 Jan 2023 02:19:41 -0800 (PST) X-Google-Smtp-Source: AMrXdXvXg72eGrML+/mxzVkFKxqGtgxu8CsPn0AxJaP3oBLPa2KNu0RBUVhu1z6sPN1TCaI3YKKH X-Received: by 2002:a17:903:25d6:b0:188:5e99:d84f with SMTP id jc22-20020a17090325d600b001885e99d84fmr10298589plb.42.1673605181415; Fri, 13 Jan 2023 02:19:41 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1673605181; cv=none; d=google.com; s=arc-20160816; b=do28iqJ1sKucD3ZADLjccvjFpWg5GKthY3bVxAYkocp6t+ofBBgLAAEUdUTTa9+29X 1o7dyOXxZgEWu4B483IemZjhzHiFThYXGNi5VZges7hR6kEtZOz2Z8CCOGLzyNziTel8 +Ud7jGzrZEReq7mY49zPz2f9vBBGWObcEo//NMOZY9Zwo6xqTvRVe4y1EshRxHDQLJ5K po37irMs6eKPP513vAp/O1khWB0S5oUPdCBbayTSD82DWawzfkLOIHZdv2Q5WQG+8sei bB+Gl9VCMPhDHcJ52TdSWdXY9Bc7frUOg5KhYQ9UdLqtF8mgwsEmip7VawDZtEWKWJZy B5eg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :message-id:date:subject:cc:to:from:dkim-signature; bh=eoAN4GI2/yT3R95zM/HDNv1uYNxXxDMAw5+X8UjTuAs=; b=XwTHJteeoLfeIoXg9jWS6Jo8y6eOdCW92Je7Ik0oNVY+FwfTC3ZEljyoMaPqAOKHxN cQ2PU/U42VgtG44MlWwp2cTj9z8lI3ODs7a1w5yBVmbEaTSsXCYqEyVl72J4ZpdVdntV OzjHnQh2cCZSInJlKmxn5Dt+yqLr/GEuwt4HhgqZvpBPgL6YDyF8pH/QZJ+fIOMuHYdj AADfRwdfLQ049RveGoPKnakAeH8hVwG35ZzrtqAe1sYu1du8dlY4gdcoUigm2cLaSJ2y tFs8EJba9pamCf+Ox0RGqQfsyV/nukYPP2nEV0wQFq4dNHUnALEEVsON7jHUBH6Pik7a 47Dw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@collabora.com header.s=mail header.b=CB35nnrx; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=collabora.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id x76-20020a63314f000000b004ad26bbd901si20551107pgx.693.2023.01.13.02.19.29; Fri, 13 Jan 2023 02:19:41 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@collabora.com header.s=mail header.b=CB35nnrx; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=collabora.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233019AbjAMKQT (ORCPT + 99 others); Fri, 13 Jan 2023 05:16:19 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54902 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231351AbjAMKQQ (ORCPT ); Fri, 13 Jan 2023 05:16:16 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 97793EBC; Fri, 13 Jan 2023 02:16:13 -0800 (PST) Received: from benjamin-XPS-13-9310.. (unknown [IPv6:2a01:e0a:120:3210:299b:2170:fef0:26ee]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: benjamin.gaignard) by madras.collabora.co.uk (Postfix) with ESMTPSA id BE14A6602CCE; Fri, 13 Jan 2023 10:16:11 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1673604972; bh=uvLHq13CAGAoG5W+OuGNtmqdHKgq7qLWvksrMYmsUYk=; h=From:To:Cc:Subject:Date:From; b=CB35nnrxX+A7tXdRtYYNRX5ZsjQQrcwd+zppfC3orQ1+P/Vp1cXmpgYPabLpckzfN Gp24WIMFMn+dL49BB0zCqPxDFH+D2xddU89kQY5etC/N2s8QTpE07jXmQoDystaRkX S5bLGIoY35+q/ueWDSvI3NOhL0tQyqb9yYo38ckgadHecycElJHDpOH3ZuA7EK3C4B feCvHyOoBziQpJg2NxrlwffTxuM7m7zOqE/+AqbZt2RviDlFjz4XhNQ64ViTdnrbjP foxvwEISfhhrvDpoFPcDnG+smRMY4lVkAdclfPHuLQwwiSzDaCpt6I8ysVyvvQGol2 QFNJvdLCdMiTA== From: Benjamin Gaignard To: ezequiel@vanguardiasur.com.ar, p.zabel@pengutronix.de, mchehab@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, heiko@sntech.de, nicolas.dufresne@collabora.co.uk Cc: linux-media@vger.kernel.org, linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kernel@collabora.com, Benjamin Gaignard Subject: [PATCH] media: verisilicon: HEVC: Only propose 10 bits compatible pixels formats Date: Fri, 13 Jan 2023 11:16:04 +0100 Message-Id: <20230113101604.261429-1-benjamin.gaignard@collabora.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1754902226540416371?= X-GMAIL-MSGID: =?utf-8?q?1754902226540416371?= When decoding a 10bits bitstreams HEVC driver should only expose 10bits pixel formats. To fulfill this requirement it is needed to call hantro_reset_raw_fmt() when bit depth change and to correctly set match_depth in pixel formats enumeration. Fixes: dc39473d0340 ("media: hantro: imx8m: Enable 10bit decoding") Signed-off-by: Benjamin Gaignard Tested-by: Nicolas Dufresne --- .../media/platform/verisilicon/hantro_drv.c | 35 +++++++++++++++++-- .../media/platform/verisilicon/hantro_v4l2.c | 2 +- .../media/platform/verisilicon/hantro_v4l2.h | 1 + .../media/platform/verisilicon/imx8m_vpu_hw.c | 2 ++ 4 files changed, 36 insertions(+), 4 deletions(-) diff --git a/drivers/media/platform/verisilicon/hantro_drv.c b/drivers/media/platform/verisilicon/hantro_drv.c index 8cb4a68c9119..78ea05294004 100644 --- a/drivers/media/platform/verisilicon/hantro_drv.c +++ b/drivers/media/platform/verisilicon/hantro_drv.c @@ -274,8 +274,6 @@ static int hantro_try_ctrl(struct v4l2_ctrl *ctrl) if (sps->bit_depth_luma_minus8 != 0 && sps->bit_depth_luma_minus8 != 2) /* Only 8-bit and 10-bit are supported */ return -EINVAL; - - ctx->bit_depth = sps->bit_depth_luma_minus8 + 8; } else if (ctrl->id == V4L2_CID_STATELESS_VP9_FRAME) { const struct v4l2_ctrl_vp9_frame *dec_params = ctrl->p_new.p_vp9_frame; @@ -286,6 +284,32 @@ static int hantro_try_ctrl(struct v4l2_ctrl *ctrl) return 0; } +static int hantro_hevc_s_ctrl(struct v4l2_ctrl *ctrl) +{ + struct hantro_ctx *ctx; + + ctx = container_of(ctrl->handler, + struct hantro_ctx, ctrl_handler); + + vpu_debug(1, "s_ctrl: id = %d, val = %d\n", ctrl->id, ctrl->val); + + switch (ctrl->id) { + case V4L2_CID_STATELESS_HEVC_SPS: + const struct v4l2_ctrl_hevc_sps *sps = ctrl->p_new.p_hevc_sps; + int bit_depth = sps->bit_depth_luma_minus8 + 8; + + if (ctx->bit_depth != bit_depth) { + ctx->bit_depth = bit_depth; + hantro_reset_raw_fmt(ctx); + } + break; + default: + return -EINVAL; + } + + return 0; +} + static int hantro_jpeg_s_ctrl(struct v4l2_ctrl *ctrl) { struct hantro_ctx *ctx; @@ -328,6 +352,11 @@ static const struct v4l2_ctrl_ops hantro_ctrl_ops = { .try_ctrl = hantro_try_ctrl, }; +static const struct v4l2_ctrl_ops hantro_hevc_ctrl_ops = { + .s_ctrl = hantro_hevc_s_ctrl, + .try_ctrl = hantro_try_ctrl, +}; + static const struct v4l2_ctrl_ops hantro_jpeg_ctrl_ops = { .s_ctrl = hantro_jpeg_s_ctrl, }; @@ -470,7 +499,7 @@ static const struct hantro_ctrl controls[] = { .codec = HANTRO_HEVC_DECODER, .cfg = { .id = V4L2_CID_STATELESS_HEVC_SPS, - .ops = &hantro_ctrl_ops, + .ops = &hantro_hevc_ctrl_ops, }, }, { .codec = HANTRO_HEVC_DECODER, diff --git a/drivers/media/platform/verisilicon/hantro_v4l2.c b/drivers/media/platform/verisilicon/hantro_v4l2.c index 2c7a805289e7..0025e049dd26 100644 --- a/drivers/media/platform/verisilicon/hantro_v4l2.c +++ b/drivers/media/platform/verisilicon/hantro_v4l2.c @@ -398,7 +398,7 @@ hantro_reset_encoded_fmt(struct hantro_ctx *ctx) hantro_set_fmt_out(ctx, fmt); } -static void +void hantro_reset_raw_fmt(struct hantro_ctx *ctx) { const struct hantro_fmt *raw_vpu_fmt; diff --git a/drivers/media/platform/verisilicon/hantro_v4l2.h b/drivers/media/platform/verisilicon/hantro_v4l2.h index 64f6f57e9d7a..f642560aed93 100644 --- a/drivers/media/platform/verisilicon/hantro_v4l2.h +++ b/drivers/media/platform/verisilicon/hantro_v4l2.h @@ -21,6 +21,7 @@ extern const struct v4l2_ioctl_ops hantro_ioctl_ops; extern const struct vb2_ops hantro_queue_ops; +void hantro_reset_raw_fmt(struct hantro_ctx *ctx); void hantro_reset_fmts(struct hantro_ctx *ctx); int hantro_get_format_depth(u32 fourcc); const struct hantro_fmt * diff --git a/drivers/media/platform/verisilicon/imx8m_vpu_hw.c b/drivers/media/platform/verisilicon/imx8m_vpu_hw.c index b390228fd3b4..f850d8bddef6 100644 --- a/drivers/media/platform/verisilicon/imx8m_vpu_hw.c +++ b/drivers/media/platform/verisilicon/imx8m_vpu_hw.c @@ -152,6 +152,7 @@ static const struct hantro_fmt imx8m_vpu_g2_postproc_fmts[] = { { .fourcc = V4L2_PIX_FMT_NV12, .codec_mode = HANTRO_MODE_NONE, + .match_depth = true, .postprocessed = true, .frmsize = { .min_width = FMT_MIN_WIDTH, @@ -165,6 +166,7 @@ static const struct hantro_fmt imx8m_vpu_g2_postproc_fmts[] = { { .fourcc = V4L2_PIX_FMT_P010, .codec_mode = HANTRO_MODE_NONE, + .match_depth = true, .postprocessed = true, .frmsize = { .min_width = FMT_MIN_WIDTH,