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[2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id m12-20020a056402510c00b004379c601345si20436051edd.569.2022.07.26.22.10.27 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 Jul 2022 22:10:28 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=o3njIkUK; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id A7644385780D for ; Wed, 27 Jul 2022 05:10:26 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org A7644385780D DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1658898626; bh=JBtRmay2PbekvB/SeRAEAPFYNodmzDFiN5982B0VhXc=; h=To:Subject:Date:List-Id:List-Unsubscribe:List-Archive:List-Post: List-Help:List-Subscribe:From:Reply-To:Cc:From; b=o3njIkUKfzCV6iXUS/Wdz+x6rLWxhzHQTaBkv/ToAURyBzaXN+1ltswIPge9ep9zt X/dvEJmSYfyi1lrCNIa7bosRRWJKoGXm3P9gHF7QWma+h4b+4zfme+zM33604Vlhsx tdpY64UD21a9Z6oBQZLbMER//t4Sz1E00M3chldc= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from rock.gnat.com (rock.gnat.com [IPv6:2620:20:4000:0:a9e:1ff:fe9b:1d1]) by sourceware.org (Postfix) with ESMTPS id 96AB43857BA8 for ; Wed, 27 Jul 2022 05:09:43 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 96AB43857BA8 Received: from localhost (localhost.localdomain [127.0.0.1]) by filtered-rock.gnat.com (Postfix) with ESMTP id B8D2C11677B; Wed, 27 Jul 2022 01:09:40 -0400 (EDT) X-Virus-Scanned: Debian amavisd-new at gnat.com Received: from rock.gnat.com ([127.0.0.1]) by localhost (rock.gnat.com [127.0.0.1]) (amavisd-new, port 10024) with LMTP id owK-Kn4iBGe7; Wed, 27 Jul 2022 01:09:40 -0400 (EDT) Received: from free.home (tron.gnat.com [IPv6:2620:20:4000:0:46a8:42ff:fe0e:e294]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by rock.gnat.com (Postfix) with ESMTPS id 040B8116771; Wed, 27 Jul 2022 01:09:39 -0400 (EDT) Received: from livre (livre.home [172.31.160.2]) by free.home (8.15.2/8.15.2) with ESMTPS id 26R59NUS1759904 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 27 Jul 2022 02:09:25 -0300 To: gcc-patches@gcc.gnu.org Subject: [PATCH] i386 PIE: accept @GOTOFF in load/store multi base address Organization: Free thinker, does not speak for AdaCore Date: Wed, 27 Jul 2022 02:09:23 -0300 Message-ID: User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/25.2 (gnu/linux) MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.84 X-Spam-Status: No, score=-12.3 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_SHORT, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Alexandre Oliva via Gcc-patches From: Alexandre Oliva Reply-To: Alexandre Oliva Cc: hubicka@ucw.cz Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1739481287676122992?= X-GMAIL-MSGID: =?utf-8?q?1739481287676122992?= Looking at the code generated for sse2-{load,store}-multi.c with PIE, I realized we could use UNSPEC_GOTOFF as a base address, and that this would enable the test to use the vector insns expected by the tests even with PIC, so I extended the base + offset logic used by the SSE2 multi-load/store peepholes to accept reg + symbolic base + offset too, so that the test generated the expected insns even with PIE. Regstrapped on x86_64-linux-gnu; also tested, along with other patches I'm posting today with "i386 PIE" in the subject, and compared default-PIE and default-nonPIE results on it, and on i686-linux-gnu. Ok to install? for gcc/ChangeLog * config/i386/i386.cc (symbolic_base_address_p, base_address_p): New, factored out from... (extract_base_offset_in_addr): ... here and extended to recognize REG+GOTOFF, as in gcc.target/i386/sse2-load-multi.c and sse2-store-multi.c with PIE enabled by default. --- gcc/config/i386/i386.cc | 89 ++++++++++++++++++++++++++++++++++++++++------- 1 file changed, 75 insertions(+), 14 deletions(-) diff --git a/gcc/config/i386/i386.cc b/gcc/config/i386/i386.cc index e03f86d4a2386..aab28da4b5d4b 100644 --- a/gcc/config/i386/i386.cc +++ b/gcc/config/i386/i386.cc @@ -23910,11 +23910,40 @@ ix86_reloc_rw_mask (void) } #endif -/* If MEM is in the form of [base+offset], extract the two parts - of address and set to BASE and OFFSET, otherwise return false. */ +/* Return true iff ADDR can be used as a symbolic base address. */ static bool -extract_base_offset_in_addr (rtx mem, rtx *base, rtx *offset) +symbolic_base_address_p (rtx addr) +{ + if (GET_CODE (addr) == SYMBOL_REF) + return true; + + if (GET_CODE (addr) == UNSPEC && XINT (addr, 1) == UNSPEC_GOTOFF) + return true; + + return false; +} + +/* Return true iff ADDR can be used as a base address. */ + +static bool +base_address_p (rtx addr) +{ + if (REG_P (addr)) + return true; + + if (symbolic_base_address_p (addr)) + return true; + + return false; +} + +/* If MEM is in the form of [(base+symbase)+offset], extract the three + parts of address and set to BASE, SYMBASE and OFFSET, otherwise + return false. */ + +static bool +extract_base_offset_in_addr (rtx mem, rtx *base, rtx *symbase, rtx *offset) { rtx addr; @@ -23925,21 +23954,52 @@ extract_base_offset_in_addr (rtx mem, rtx *base, rtx *offset) if (GET_CODE (addr) == CONST) addr = XEXP (addr, 0); - if (REG_P (addr) || GET_CODE (addr) == SYMBOL_REF) + if (base_address_p (addr)) { *base = addr; + *symbase = const0_rtx; *offset = const0_rtx; return true; } if (GET_CODE (addr) == PLUS - && (REG_P (XEXP (addr, 0)) - || GET_CODE (XEXP (addr, 0)) == SYMBOL_REF) - && CONST_INT_P (XEXP (addr, 1))) + && base_address_p (XEXP (addr, 0))) { - *base = XEXP (addr, 0); - *offset = XEXP (addr, 1); - return true; + rtx addend = XEXP (addr, 1); + + if (GET_CODE (addend) == CONST) + addend = XEXP (addend, 0); + + if (CONST_INT_P (addend)) + { + *base = XEXP (addr, 0); + *symbase = const0_rtx; + *offset = addend; + return true; + } + + /* Also accept REG + symbolic ref, with or without a CONST_INT + offset. */ + if (REG_P (XEXP (addr, 0))) + { + if (symbolic_base_address_p (addend)) + { + *base = XEXP (addr, 0); + *symbase = addend; + *offset = const0_rtx; + return true; + } + + if (GET_CODE (addend) == PLUS + && symbolic_base_address_p (XEXP (addend, 0)) + && CONST_INT_P (XEXP (addend, 1))) + { + *base = XEXP (addr, 0); + *symbase = XEXP (addend, 0); + *offset = XEXP (addend, 1); + return true; + } + } } return false; @@ -23954,7 +24014,8 @@ ix86_operands_ok_for_move_multiple (rtx *operands, bool load, machine_mode mode) { HOST_WIDE_INT offval_1, offval_2, msize; - rtx mem_1, mem_2, reg_1, reg_2, base_1, base_2, offset_1, offset_2; + rtx mem_1, mem_2, reg_1, reg_2, base_1, base_2, + symbase_1, symbase_2, offset_1, offset_2; if (load) { @@ -23977,13 +24038,13 @@ ix86_operands_ok_for_move_multiple (rtx *operands, bool load, return false; /* Check if the addresses are in the form of [base+offset]. */ - if (!extract_base_offset_in_addr (mem_1, &base_1, &offset_1)) + if (!extract_base_offset_in_addr (mem_1, &base_1, &symbase_1, &offset_1)) return false; - if (!extract_base_offset_in_addr (mem_2, &base_2, &offset_2)) + if (!extract_base_offset_in_addr (mem_2, &base_2, &symbase_2, &offset_2)) return false; /* Check if the bases are the same. */ - if (!rtx_equal_p (base_1, base_2)) + if (!rtx_equal_p (base_1, base_2) || !rtx_equal_p (symbase_1, symbase_2)) return false; offval_1 = INTVAL (offset_1);