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([172.25.112.68]) by orsmga006.jf.intel.com with ESMTP; 11 Jan 2023 23:44:20 -0800 From: Xin Li To: linux-kernel@vger.kernel.org, x86@kernel.org Cc: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, hpa@zytor.com, peterz@infradead.org, brgerst@gmail.com, chang.seok.bae@intel.com, jgross@suse.com Subject: [PATCH v6 1/5] x86/cpufeature: add the cpu feature bit for LKGS Date: Wed, 11 Jan 2023 23:20:28 -0800 Message-Id: <20230112072032.35626-2-xin3.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230112072032.35626-1-xin3.li@intel.com> References: <20230112072032.35626-1-xin3.li@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1754802080597072890?= X-GMAIL-MSGID: =?utf-8?q?1754802080597072890?= From: "H. Peter Anvin (Intel)" Add the CPU feature bit for LKGS (Load "Kernel" GS). LKGS instruction is introduced with Intel FRED (flexible return and event delivery) specification. Search for the latest FRED spec in most search engines by doing: site:intel.com FRED (flexible return and event delivery) specification LKGS behaves like the MOV to GS instruction except that it loads the base address into the IA32_KERNEL_GS_BASE MSR instead of the GS segment’s descriptor cache, which is exactly what Linux kernel does to load a user level GS base. Thus, with LKGS, there is no need to SWAPGS away from the kernel GS base. Signed-off-by: H. Peter Anvin (Intel) Signed-off-by: Xin Li --- Changes since v5: * Recommend to search for the latest FRED spec instead of providing a FRED spec URL, which is likely to be unstable (Borislav Petkov). Changes since v2: * Add "" not to show "lkgs" in /proc/cpuinfo (Chang S. Bae). --- arch/x86/include/asm/cpufeatures.h | 1 + tools/arch/x86/include/asm/cpufeatures.h | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h index 61012476d66e..4d93c60407fe 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -312,6 +312,7 @@ #define X86_FEATURE_AVX_VNNI (12*32+ 4) /* AVX VNNI instructions */ #define X86_FEATURE_AVX512_BF16 (12*32+ 5) /* AVX512 BFLOAT16 instructions */ #define X86_FEATURE_CMPCCXADD (12*32+ 7) /* "" CMPccXADD instructions */ +#define X86_FEATURE_LKGS (12*32+18) /* "" Load "kernel" (userspace) gs */ #define X86_FEATURE_AMX_FP16 (12*32+21) /* "" AMX fp16 Support */ #define X86_FEATURE_AVX_IFMA (12*32+23) /* "" Support for VPMADD52[H,L]UQ */ diff --git a/tools/arch/x86/include/asm/cpufeatures.h b/tools/arch/x86/include/asm/cpufeatures.h index 61012476d66e..4d93c60407fe 100644 --- a/tools/arch/x86/include/asm/cpufeatures.h +++ b/tools/arch/x86/include/asm/cpufeatures.h @@ -312,6 +312,7 @@ #define X86_FEATURE_AVX_VNNI (12*32+ 4) /* AVX VNNI instructions */ #define X86_FEATURE_AVX512_BF16 (12*32+ 5) /* AVX512 BFLOAT16 instructions */ #define X86_FEATURE_CMPCCXADD (12*32+ 7) /* "" CMPccXADD instructions */ +#define X86_FEATURE_LKGS (12*32+18) /* "" Load "kernel" (userspace) gs */ #define X86_FEATURE_AMX_FP16 (12*32+21) /* "" AMX fp16 Support */ #define X86_FEATURE_AVX_IFMA (12*32+23) /* "" Support for VPMADD52[H,L]UQ */ From patchwork Thu Jan 12 07:20:29 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Xin3" X-Patchwork-Id: 42276 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4e01:0:0:0:0:0 with SMTP id p1csp3748700wrt; Wed, 11 Jan 2023 23:47:50 -0800 (PST) X-Google-Smtp-Source: AMrXdXvsKC43oJLJRpVJC/vExjXVcIOsFHSGjyGwOk7VQr6LOk6ehSorPC0hHWGkVZWawTNo27uP X-Received: by 2002:a17:906:2a49:b0:812:d53e:11f6 with SMTP id k9-20020a1709062a4900b00812d53e11f6mr62065523eje.70.1673509670413; Wed, 11 Jan 2023 23:47:50 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1673509670; cv=none; d=google.com; s=arc-20160816; b=QrxnPVTD4AoWdZm9jnhdf/NY5yIFU34f6Fw4rjwWWrIU085kIA2LCsOugDIvHAGKjD YiSJr3+lk9UOIr+i0a0rqicfzaOMsOZSeCxFfBOdkKQJBeSe4P0zLwKQXtatEZR+UTw9 L7Z5uOpkL1oyPMa37j8kvl9NSk3IH87vKLmZs7BuVJy4pNwKCqeulI/4j/oO8MUSJOqG /kFvBWVZ0nnNmzvKH2SLsK0JWId1A39ECbuK1K6i39m0rbPqV3s8BBNEdwtcrHDNMX1v 0D2TEom9C31M5jTCq/6ERYjQRQQwJ0BU4ECAxyxXa4GSLV8AtJRNU+1W67zgggGR8NO/ WeMA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=eJsKmgq7cZ4PvvkyHtyDuB9Yk24qiDeyA141LpQLnUo=; b=HuZkC9Iq9MuTz5bRE2P/nf8n4qbowODH72k2A+xjbgeeJGo58RfSW+YMEANany3FCt kJzaocaWQJMPSp49t3+Ao+dgN47TMnzllUpRQ+JiqJOTpxfu5mgHKYOH/vcoq0IVPEAS AS0d4KPxwm5vhf8vSxlQr+f7Lipwld1mcL57+bEb5zUUMhdUYHzBQf6DLzcaT2402sOB jyVXj/hSJOYPUsFX36FGKbuzHoZXcR/ktj3GuJ6ZwWFG99/e+RSc1r23l6ou5dWD0L15 TBeheta8Klvh6Dl7HKENqPmLW0IJlSSwaLf6M1W6TXrOc8RtgBdDRtLcvAMwG1uf/OCU pGSQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=nPwNZO0C; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. 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([172.25.112.68]) by orsmga006.jf.intel.com with ESMTP; 11 Jan 2023 23:44:21 -0800 From: Xin Li To: linux-kernel@vger.kernel.org, x86@kernel.org Cc: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, hpa@zytor.com, peterz@infradead.org, brgerst@gmail.com, chang.seok.bae@intel.com, jgross@suse.com Subject: [PATCH v6 2/5] x86/opcode: add the LKGS instruction to x86-opcode-map Date: Wed, 11 Jan 2023 23:20:29 -0800 Message-Id: <20230112072032.35626-3-xin3.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230112072032.35626-1-xin3.li@intel.com> References: <20230112072032.35626-1-xin3.li@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1754802075683938887?= X-GMAIL-MSGID: =?utf-8?q?1754802075683938887?= From: "H. Peter Anvin (Intel)" Add the instruction opcode used by LKGS to x86-opcode-map. Opcode number is per public FRED draft spec v3.0. Signed-off-by: H. Peter Anvin (Intel) Signed-off-by: Xin Li --- arch/x86/lib/x86-opcode-map.txt | 1 + tools/arch/x86/lib/x86-opcode-map.txt | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/x86/lib/x86-opcode-map.txt b/arch/x86/lib/x86-opcode-map.txt index d12d1358f96d..5168ee0360b2 100644 --- a/arch/x86/lib/x86-opcode-map.txt +++ b/arch/x86/lib/x86-opcode-map.txt @@ -1047,6 +1047,7 @@ GrpTable: Grp6 3: LTR Ew 4: VERR Ew 5: VERW Ew +6: LKGS Ew (F2) EndTable GrpTable: Grp7 diff --git a/tools/arch/x86/lib/x86-opcode-map.txt b/tools/arch/x86/lib/x86-opcode-map.txt index d12d1358f96d..5168ee0360b2 100644 --- a/tools/arch/x86/lib/x86-opcode-map.txt +++ b/tools/arch/x86/lib/x86-opcode-map.txt @@ -1047,6 +1047,7 @@ GrpTable: Grp6 3: LTR Ew 4: VERR Ew 5: VERW Ew +6: LKGS Ew (F2) EndTable GrpTable: Grp7 From patchwork Thu Jan 12 07:20:30 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Xin3" X-Patchwork-Id: 42278 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4e01:0:0:0:0:0 with SMTP id p1csp3748999wrt; Wed, 11 Jan 2023 23:48:39 -0800 (PST) X-Google-Smtp-Source: AMrXdXtmo6vn1uSxWFn0pNmqC9hzwCDmYu1HYz1NXiHEptGopLUpB26/YtTSehsBzCe2nqqU0fP2 X-Received: by 2002:a05:6402:e0a:b0:46c:b25a:6d7f with SMTP id h10-20020a0564020e0a00b0046cb25a6d7fmr74736515edh.8.1673509719063; Wed, 11 Jan 2023 23:48:39 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1673509719; cv=none; d=google.com; s=arc-20160816; b=1CHSSlxsQVssFw/32+08SimM9KLXw6iqLJ9OtWCcdJvAXg1w+uaUwT/tYNKdcRHov9 ocjkWDQeWnzw1Ijzj6H/ztE8+9EcjFz8TyB4sdQI32vFMk2x76TQt6FaSXRt4hCcxQzV SYoIjBCAt1RTkkZw1NIPTyDQZLR6rykOOckhZcy2ovhoQ9tlI9njU+N8JcDPCkQw0hW8 dp1IhsNwoHKb9pxyg9mopBDCtdGSbK9R4KeQYYuj0Qyy6j97L9iCtPUfwN5PuhfgpqNo yZpC0B/5nkqoBxYaKlKrAdrafKk+/BItMG6iWIWo6ED6Rmaq0X5WswhCHJ37BvXXSSfm 4H6Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=o61mGWGF3CI7a4YSsBNgSFAAtmSOuQLpyKUcYQ2czGs=; b=EbUQh2OdAjg+su1eomGnWgpFm78rydWi85GoSkMXVgfOFdWQPPdITbyg7rkTbk3GAM gbGFCKBuijXZqlZ4nbyYCslLIKCpv76nm/hWd9wkeSPgX6wqrZQoLNjbo4XzQ0CcITjL gZVnXvcgY2QOdsepUAoRE8vuuK+pY+rq33QNHmngxSxntBuNMr/J6IXREBcw1R/tBIhr ZYbUcubyv39wyT7bPuTBowuHDo0qo98XLemOp4BkRDTx+oJk0gpe9JHVo+OoPR7WV6al Udu0XblkfdDBEYYoi5A/zpq4lUmCA19z/liaOZI4lLI4YbG/iSTzTMAjb2cRyzCv44eL VSWw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b="gc/JXR5l"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. 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([172.25.112.68]) by orsmga006.jf.intel.com with ESMTP; 11 Jan 2023 23:44:22 -0800 From: Xin Li To: linux-kernel@vger.kernel.org, x86@kernel.org Cc: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, hpa@zytor.com, peterz@infradead.org, brgerst@gmail.com, chang.seok.bae@intel.com, jgross@suse.com Subject: [PATCH v6 3/5] x86/gsseg: make asm_load_gs_index() take an u16 Date: Wed, 11 Jan 2023 23:20:30 -0800 Message-Id: <20230112072032.35626-4-xin3.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230112072032.35626-1-xin3.li@intel.com> References: <20230112072032.35626-1-xin3.li@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1754802127377749728?= X-GMAIL-MSGID: =?utf-8?q?1754802127377749728?= From: "H. Peter Anvin (Intel)" Let gcc know that only the low 16 bits of load_gs_index() argument actually matter. It might allow it to create slightly better code. However, do not propagate this into the prototypes of functions that end up being paravirtualized, to avoid unnecessary changes. Signed-off-by: H. Peter Anvin (Intel) Signed-off-by: Xin Li --- arch/x86/entry/entry_64.S | 2 +- arch/x86/include/asm/special_insns.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/x86/entry/entry_64.S b/arch/x86/entry/entry_64.S index 15739a2c0983..7ecd2aeeeffc 100644 --- a/arch/x86/entry/entry_64.S +++ b/arch/x86/entry/entry_64.S @@ -782,7 +782,7 @@ _ASM_NOKPROBE(common_interrupt_return) /* * Reload gs selector with exception handling - * edi: new selector + * di: new selector * * Is in entry.text as it shouldn't be instrumented. */ diff --git a/arch/x86/include/asm/special_insns.h b/arch/x86/include/asm/special_insns.h index 35f709f619fb..a71d0e8d4684 100644 --- a/arch/x86/include/asm/special_insns.h +++ b/arch/x86/include/asm/special_insns.h @@ -120,7 +120,7 @@ static inline void native_wbinvd(void) asm volatile("wbinvd": : :"memory"); } -extern asmlinkage void asm_load_gs_index(unsigned int selector); +extern asmlinkage void asm_load_gs_index(u16 selector); static inline void native_load_gs_index(unsigned int selector) { From patchwork Thu Jan 12 07:20:31 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Xin3" X-Patchwork-Id: 42279 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4e01:0:0:0:0:0 with SMTP id p1csp3749000wrt; Wed, 11 Jan 2023 23:48:39 -0800 (PST) X-Google-Smtp-Source: AMrXdXsz22QIlh3TteorVNJ2QBJcRRs1nDBnK+zk73AI48qO7B3uMc7t0mTht23qJdHFTCAb7in5 X-Received: by 2002:a17:906:3ec8:b0:846:cdd9:d23 with SMTP id d8-20020a1709063ec800b00846cdd90d23mr61013454ejj.19.1673509719095; Wed, 11 Jan 2023 23:48:39 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1673509719; cv=none; d=google.com; s=arc-20160816; b=NgaALDNXM2ZqO6ahHpbqwGQHytnfaODkzohN5WlwGhu9yYFs8DNmIOdKX+ynVl0mTX f/ljcIPJO3xioHw9LTlKQucDMLgL5j4GEYjOfUdlXtUaBJEB+/91AUApxOJh2e5cZgU8 fqect3lyQQc2dWjeW7aNV6b2TNdNC1vb3BowKFmFSAQdMQFsSwYncdl6E4ctw1TbXJ+z +l7/wfRPoC2jWqzRhbIO/MrcTeyeMykYlydHJmXAqp7kxfPwhk9VnILtKJ4A3pHvLCa4 IX0YuNDOv894qJFdJPphq5aX/d/Meen2ecMF5m92Bk3qe+QZZs4aeFU6Gi11eC4dU4ez UE7Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=LJUfqOmPeIzPKldbkfIrg95BhrBRzuink1ZvFz2ArvQ=; b=bPTzpJBjpYYZCC75UXokujRWQWKZ51PUePCcMuSTtE7MCKy7EYMZ/zwWKOXkLLYyrp W+/0KIOwg4YUb+rf6KldccsF9DprRmtExFgZBBli7pbL4GCQK3ub54E2mQ0l+ZXAgM07 5nbvxdwvKam2LMDiGiqt4eD9py9nkvdncu4ZgWsT5T9iQl3qICKDXCrEEGcWS0IFTYsj cKbtxMEbbRZq5T4+aYgd+Du0XEI/MD361SyF2HHTftExf5smNZhenTwoh86nxEYcKNyz yso0gLGHs/Euuvy1jgNRivOBe2F8dEhQcAqU/jBIT+A7SoQ8yJipz0WTI0uOpoA7dD6P L3Wg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=bJINky6+; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. 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([172.25.112.68]) by orsmga006.jf.intel.com with ESMTP; 11 Jan 2023 23:44:22 -0800 From: Xin Li To: linux-kernel@vger.kernel.org, x86@kernel.org Cc: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, hpa@zytor.com, peterz@infradead.org, brgerst@gmail.com, chang.seok.bae@intel.com, jgross@suse.com Subject: [PATCH v6 4/5] x86/gsseg: move load_gs_index() to its own new header file Date: Wed, 11 Jan 2023 23:20:31 -0800 Message-Id: <20230112072032.35626-5-xin3.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230112072032.35626-1-xin3.li@intel.com> References: <20230112072032.35626-1-xin3.li@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1754802127308308560?= X-GMAIL-MSGID: =?utf-8?q?1754802127308308560?= From: "H. Peter Anvin (Intel)" GS is a special segment on x86_64, move load_gs_index() to its own new header file to simplify header inclusion. Signed-off-by: H. Peter Anvin (Intel) Signed-off-by: Xin Li --- arch/x86/include/asm/gsseg.h | 41 ++++++++++++++++++++++++++++ arch/x86/include/asm/mmu_context.h | 1 + arch/x86/include/asm/special_insns.h | 21 -------------- arch/x86/kernel/paravirt.c | 1 + arch/x86/kernel/signal_32.c | 1 + arch/x86/kernel/tls.c | 1 + 6 files changed, 45 insertions(+), 21 deletions(-) create mode 100644 arch/x86/include/asm/gsseg.h diff --git a/arch/x86/include/asm/gsseg.h b/arch/x86/include/asm/gsseg.h new file mode 100644 index 000000000000..d15577c39e8d --- /dev/null +++ b/arch/x86/include/asm/gsseg.h @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#ifndef _ASM_X86_GSSEG_H +#define _ASM_X86_GSSEG_H + +#include + +#include +#include +#include +#include +#include + +#ifdef CONFIG_X86_64 + +extern asmlinkage void asm_load_gs_index(u16 selector); + +static inline void native_load_gs_index(unsigned int selector) +{ + unsigned long flags; + + local_irq_save(flags); + asm_load_gs_index(selector); + local_irq_restore(flags); +} + +#endif /* CONFIG_X86_64 */ + +#ifndef CONFIG_PARAVIRT_XXL + +static inline void load_gs_index(unsigned int selector) +{ +#ifdef CONFIG_X86_64 + native_load_gs_index(selector); +#else + loadsegment(gs, selector); +#endif +} + +#endif /* CONFIG_PARAVIRT_XXL */ + +#endif /* _ASM_X86_GSSEG_H */ diff --git a/arch/x86/include/asm/mmu_context.h b/arch/x86/include/asm/mmu_context.h index b8d40ddeab00..e01aa74a6de7 100644 --- a/arch/x86/include/asm/mmu_context.h +++ b/arch/x86/include/asm/mmu_context.h @@ -12,6 +12,7 @@ #include #include #include +#include extern atomic64_t last_mm_ctx_id; diff --git a/arch/x86/include/asm/special_insns.h b/arch/x86/include/asm/special_insns.h index a71d0e8d4684..cfd9499b617c 100644 --- a/arch/x86/include/asm/special_insns.h +++ b/arch/x86/include/asm/special_insns.h @@ -120,17 +120,6 @@ static inline void native_wbinvd(void) asm volatile("wbinvd": : :"memory"); } -extern asmlinkage void asm_load_gs_index(u16 selector); - -static inline void native_load_gs_index(unsigned int selector) -{ - unsigned long flags; - - local_irq_save(flags); - asm_load_gs_index(selector); - local_irq_restore(flags); -} - static inline unsigned long __read_cr4(void) { return native_read_cr4(); @@ -184,16 +173,6 @@ static inline void wbinvd(void) native_wbinvd(); } - -static inline void load_gs_index(unsigned int selector) -{ -#ifdef CONFIG_X86_64 - native_load_gs_index(selector); -#else - loadsegment(gs, selector); -#endif -} - #endif /* CONFIG_PARAVIRT_XXL */ static inline void clflush(volatile void *__p) diff --git a/arch/x86/kernel/paravirt.c b/arch/x86/kernel/paravirt.c index 327757afb027..bdc886c3f13a 100644 --- a/arch/x86/kernel/paravirt.c +++ b/arch/x86/kernel/paravirt.c @@ -32,6 +32,7 @@ #include #include #include +#include /* * nop stub, which must not clobber anything *including the stack* to diff --git a/arch/x86/kernel/signal_32.c b/arch/x86/kernel/signal_32.c index 2553136cf39b..bb4f3f3b1c84 100644 --- a/arch/x86/kernel/signal_32.c +++ b/arch/x86/kernel/signal_32.c @@ -31,6 +31,7 @@ #include #include #include +#include #ifdef CONFIG_IA32_EMULATION #include diff --git a/arch/x86/kernel/tls.c b/arch/x86/kernel/tls.c index 3c883e064242..3ffbab0081f4 100644 --- a/arch/x86/kernel/tls.c +++ b/arch/x86/kernel/tls.c @@ -12,6 +12,7 @@ #include #include #include +#include #include "tls.h" From patchwork Thu Jan 12 07:20:32 2023 Content-Type: text/plain; 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([172.25.112.68]) by orsmga006.jf.intel.com with ESMTP; 11 Jan 2023 23:44:23 -0800 From: Xin Li To: linux-kernel@vger.kernel.org, x86@kernel.org Cc: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, hpa@zytor.com, peterz@infradead.org, brgerst@gmail.com, chang.seok.bae@intel.com, jgross@suse.com Subject: [PATCH v6 5/5] x86/gsseg: use the LKGS instruction if available for load_gs_index() Date: Wed, 11 Jan 2023 23:20:32 -0800 Message-Id: <20230112072032.35626-6-xin3.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230112072032.35626-1-xin3.li@intel.com> References: <20230112072032.35626-1-xin3.li@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1754802233385622679?= X-GMAIL-MSGID: =?utf-8?q?1754802233385622679?= From: "H. Peter Anvin (Intel)" The LKGS instruction atomically loads a segment descriptor into the %gs descriptor registers, *except* that %gs.base is unchanged, and the base is instead loaded into MSR_IA32_KERNEL_GS_BASE, which is exactly what we want this function to do. Signed-off-by: H. Peter Anvin (Intel) Signed-off-by: Xin Li --- Changes since v5: * Remove reviewers' SOBs (Borislav Petkov). Changes since v4: * Clear the LKGS feature from Xen PV guests (Juergen Gross). Changes since v3: * We want less ASM not more, thus keep local_irq_{save,restore}() inside native_load_gs_index() (Thomas Gleixner). * For paravirt enabled kernels, initialize pv_ops.cpu.load_gs_index to native_lkgs (Thomas Gleixner). Changes since v2: * Mark DI as input and output (+D) as in v1, since the exception handler modifies it (Brian Gerst). Changes since v1: * Use EX_TYPE_ZERO_REG instead of fixup code in the obsolete .fixup code section (Peter Zijlstra). * Add a comment that states the LKGS_DI macro will be replaced with "lkgs %di" once the binutils support the LKGS instruction (Peter Zijlstra). --- arch/x86/include/asm/gsseg.h | 33 +++++++++++++++++++++++++++++---- arch/x86/kernel/cpu/common.c | 1 + arch/x86/xen/enlighten_pv.c | 1 + 3 files changed, 31 insertions(+), 4 deletions(-) diff --git a/arch/x86/include/asm/gsseg.h b/arch/x86/include/asm/gsseg.h index d15577c39e8d..ab6a595cea70 100644 --- a/arch/x86/include/asm/gsseg.h +++ b/arch/x86/include/asm/gsseg.h @@ -14,17 +14,42 @@ extern asmlinkage void asm_load_gs_index(u16 selector); +/* Replace with "lkgs %di" once binutils support LKGS instruction */ +#define LKGS_DI _ASM_BYTES(0xf2,0x0f,0x00,0xf7) + +static inline void native_lkgs(unsigned int selector) +{ + u16 sel = selector; + asm_inline volatile("1: " LKGS_DI + _ASM_EXTABLE_TYPE_REG(1b, 1b, EX_TYPE_ZERO_REG, %k[sel]) + : [sel] "+D" (sel)); +} + static inline void native_load_gs_index(unsigned int selector) { - unsigned long flags; + if (cpu_feature_enabled(X86_FEATURE_LKGS)) { + native_lkgs(selector); + } else { + unsigned long flags; - local_irq_save(flags); - asm_load_gs_index(selector); - local_irq_restore(flags); + local_irq_save(flags); + asm_load_gs_index(selector); + local_irq_restore(flags); + } } #endif /* CONFIG_X86_64 */ +static inline void __init lkgs_init(void) +{ +#ifdef CONFIG_PARAVIRT_XXL +#ifdef CONFIG_X86_64 + if (cpu_feature_enabled(X86_FEATURE_LKGS)) + pv_ops.cpu.load_gs_index = native_lkgs; +#endif +#endif +} + #ifndef CONFIG_PARAVIRT_XXL static inline void load_gs_index(unsigned int selector) diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c index 9cfca3d7d0e2..b7ac85a1e5df 100644 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -1960,6 +1960,7 @@ void __init identify_boot_cpu(void) setup_cr_pinning(); tsx_init(); + lkgs_init(); } void identify_secondary_cpu(struct cpuinfo_x86 *c) diff --git a/arch/x86/xen/enlighten_pv.c b/arch/x86/xen/enlighten_pv.c index 5b1379662877..ce2f19ee4bfc 100644 --- a/arch/x86/xen/enlighten_pv.c +++ b/arch/x86/xen/enlighten_pv.c @@ -276,6 +276,7 @@ static void __init xen_init_capabilities(void) setup_clear_cpu_cap(X86_FEATURE_ACC); setup_clear_cpu_cap(X86_FEATURE_X2APIC); setup_clear_cpu_cap(X86_FEATURE_SME); + setup_clear_cpu_cap(X86_FEATURE_LKGS); /* * Xen PV would need some work to support PCID: CR3 handling as well