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Thu, 12 Jan 2023 01:15:47 -0600 Received: from SATLEXMB04.amd.com (10.181.40.145) by SATLEXMB06.amd.com (10.181.40.147) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.34; Thu, 12 Jan 2023 01:15:47 -0600 Received: from xhdmubinusm40.xilinx.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server id 15.1.2375.34 via Frontend Transport; Thu, 12 Jan 2023 01:15:43 -0600 From: Mubin Sayyed To: , , , , , CC: , , , , , Mubin Sayyed Subject: [LINUX PATCH 1/3] clocksource: timer-cadence-ttc: Do not probe TTC device configured as PWM Date: Thu, 12 Jan 2023 12:45:24 +0530 Message-ID: <20230112071526.3035949-2-mubin.sayyed@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230112071526.3035949-1-mubin.sayyed@amd.com> References: <20230112071526.3035949-1-mubin.sayyed@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1NAM11FT034:EE_|CY8PR12MB7586:EE_ X-MS-Office365-Filtering-Correlation-Id: e6d88814-02ec-4da6-dbbc-08daf46cd4e2 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Jan 2023 07:15:48.9910 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e6d88814-02ec-4da6-dbbc-08daf46cd4e2 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT034.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY8PR12MB7586 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1754800170940964394?= X-GMAIL-MSGID: =?utf-8?q?1754800170940964394?= TTC device can act either as clocksource/clockevent or PWM generator, it would be decided by pwm-cells property. TTC PWM feature would be supported through separate driver based on PWM framework. If pwm-cells property is present in TTC node, it would be treated as PWM device, and clocksource driver should just skip it. Signed-off-by: Mubin Sayyed --- drivers/clocksource/timer-cadence-ttc.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/clocksource/timer-cadence-ttc.c b/drivers/clocksource/timer-cadence-ttc.c index 4efd0cf3b602..ba46649148b1 100644 --- a/drivers/clocksource/timer-cadence-ttc.c +++ b/drivers/clocksource/timer-cadence-ttc.c @@ -476,6 +476,9 @@ static int __init ttc_timer_probe(struct platform_device *pdev) u32 timer_width = 16; struct device_node *timer = pdev->dev.of_node; + if (of_property_read_bool(timer, "#pwm-cells")) + return -ENODEV; + if (initialized) return 0; From patchwork Thu Jan 12 07:15:25 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mubin Sayyed X-Patchwork-Id: 42270 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4e01:0:0:0:0:0 with SMTP id p1csp3739403wrt; Wed, 11 Jan 2023 23:18:36 -0800 (PST) X-Google-Smtp-Source: AMrXdXsvi2pscVIw99RY1jSas/RNCOI+HHgNeqle/yxYpIMTJ0z0GYMCARb8Umr0qs7i1gwa/1hn X-Received: by 2002:a17:902:9a03:b0:192:d0a7:a0f4 with SMTP id v3-20020a1709029a0300b00192d0a7a0f4mr34101799plp.51.1673507916213; Wed, 11 Jan 2023 23:18:36 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1673507916; cv=pass; d=google.com; s=arc-20160816; b=K+QpwWtN2voiuC+nOn8F0J66DdCk9jl8QFlJTpplPFUDxJ1IPP9fFHAah/JI01572p KRil/2gV+Le5o9pj8NWcdk4X//JyWKndOhraftoABxITiy7MmScoa11mWDMMnjsz7PxT rTkH3xAoMToQU8oVGVz29y/XkrYFGFL3WtBJur+5cvoZiNuvJFd1RhDNqbGzIdm+K7B1 W7xM2Alz9k3Q0PLePdMkQuvUTgyhkV15uOWrfhDFJ6CY2peHao8MWSGF4H05U87obfb5 JSTbqM++/SH9y+MeqVBR9LpeW9QgBVhRgHo0a26xVjuZt3oYQtQiYBZIheTFV3NZy2tM M45A== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=iNO+9HxQ3nWY7GvGKfUOxnnoWl4ZDx49Gd+tZ5M82hA=; b=pusaZFUA6hF46WFddOaiJfah2Y90E/93TnQl7hTB1FZwib7go0k7UTvl78Ew+sm0ed ZCI0w1u/3szXpmVjDcyWk7BmzSwvkPPP+auJKBXZYsLSvL1YqhqMNyJvGZQgi3wVf8Y2 0j9sOhcOWm1HQXw0krqoB9El75e5NDpTU8IS09RT+dYqzkZ+6wjZk9wmjTw0NlttZ0Dq JPgp6tw2+UMFyXot7rHFHxwHUE0t6UWwxZh8BTdA8mKf09YkjH865LtGiGhD1p7RXMf0 IZLTPDAXwHWa2MrFj/wRcbnH4U79xvuTR8Yd9JRbmFr2ViN0w/6d0JBcEZ64SjBE2GKB sUEg== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amd.com header.s=selector1 header.b=WzRX0yxJ; arc=pass (i=1 spf=pass spfdomain=amd.com dmarc=pass fromdomain=amd.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=amd.com Received: from out1.vger.email (out1.vger.email. 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Jan 2023 07:15:52.2141 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: fc96fe43-ad86-4f34-96a9-08daf46cd6bb X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT109.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR12MB4967 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1754800236532468177?= X-GMAIL-MSGID: =?utf-8?q?1754800236532468177?= Cadence TTC can act as PWM device, it is supported through separate PWM framework based driver. Decision to configure specific TTC device as PWM or clocksource/clockevent would be done based on presence of "#pwm-cells" property. Also, interrupt property is not required for TTC PWM driver. Updated bindings to support TTC PWM configuration. Signed-off-by: Mubin Sayyed --- .../devicetree/bindings/timer/cdns,ttc.yaml | 25 ++++++++++++++++++- 1 file changed, 24 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/timer/cdns,ttc.yaml b/Documentation/devicetree/bindings/timer/cdns,ttc.yaml index 7d821fd480f6..2855e92e02e3 100644 --- a/Documentation/devicetree/bindings/timer/cdns,ttc.yaml +++ b/Documentation/devicetree/bindings/timer/cdns,ttc.yaml @@ -32,12 +32,26 @@ properties: description: | Bit width of the timer, necessary if not 16. + "#pwm-cells": + description: | + Required to configure TTC as PWM device, supported cells are 0 to 3. + minimum: 0 + maximum: 3 + required: - compatible - reg - - interrupts - clocks +allOf: + - if: + not: + required: + - "#pwm-cells" + then: + required: + - interrupts + additionalProperties: false examples: @@ -50,3 +64,12 @@ examples: clocks = <&cpu_clk 3>; timer-width = <32>; }; + + - | + ttc1: ttc1@f8002000 { + compatible = "cdns,ttc"; + reg = <0xF8002000 0x1000>; + clocks = <&cpu_clk 3>; + timer-width = <32>; + #pwm-cells = <3>; + }; From patchwork Thu Jan 12 07:15:26 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mubin Sayyed X-Patchwork-Id: 42269 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4e01:0:0:0:0:0 with SMTP id p1csp3739324wrt; Wed, 11 Jan 2023 23:18:20 -0800 (PST) X-Google-Smtp-Source: AMrXdXt3GTVxHr/KrK80rjKhbuF/8JSBUw02KXfe8A70bQfttsTW5hmQMHDk/BenZ6b8i/uvJRCR X-Received: by 2002:a17:90a:5206:b0:226:bcbe:dfc0 with SMTP id v6-20020a17090a520600b00226bcbedfc0mr27268781pjh.27.1673507899774; Wed, 11 Jan 2023 23:18:19 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1673507899; cv=pass; d=google.com; s=arc-20160816; b=XV6xPj5bO+RcTSzFjW2ie/XtPAwWf1MEamyUH0kHCQ4PhhMZSeLddnJ7uS5uE6IXEr 9pOXVGOwglgQ3OCJJasQFbntafnyM0ie2KKzHP/7iOw6VbeKc2L3/3LtFJM2yGwn4Nrm gxRZn52maHsJreeAD6VFiUqOpYZkI0S5JlgqHbKz6JjXf3P73FyRWi3v8mHxvi+KBs29 braH/8chtABu2yozntoP8hz1SgwooTWLDzcMhXS2rkXjoGzbuP9TBFCvs94N/hE7IB6o hnWNxMQ09iXQsqn3qLVC8VUJTR2jtDlIQioCi8BRnDyqbYxHRGHcZDmrExoxSvd8xBai QAvw== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=WwiKKghS/QICyHE5AlfqeYtx5+H4vzRxqfEINLH2+uM=; b=T2b9+eYxU9EdyRhL3qbdhIVuK+qE9vvNBw3LXfZ1p9OFpkT5IQQL+aWcCqNmhPuyjc SXnv25Z4foIxUpoV4y87NNkRxheJxHboPumSnBvKZA/bW+LvUQKHzHnO9GP8gZMjLyJm pvmYj4GWzO/VHkVQoT9bgHFdpWh0t/mcigCJxASlIEW0mP5XEkY3Ko19lSJMrts5c8qM KdQtWvfHUGA1C5kKbPZUXS2zitexadcn5ZvabeUFkemrjhNALYMZ2vcCluO0uLTo++yq JEtvnwqOXkKGt9lWO3Ae943dMOph0wTgCbf9nu3P594hyGFy0KgmDOytDmr7/4uB6f8Q e0xQ== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amd.com header.s=selector1 header.b=XCuxpwMC; arc=pass (i=1 spf=pass spfdomain=amd.com dmarc=pass fromdomain=amd.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=amd.com Received: from out1.vger.email (out1.vger.email. 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Thu, 12 Jan 2023 01:16:07 -0600 Received: from SATLEXMB04.amd.com (10.181.40.145) by SATLEXMB08.amd.com (10.181.40.132) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.34; Wed, 11 Jan 2023 23:15:54 -0800 Received: from xhdmubinusm40.xilinx.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server id 15.1.2375.34 via Frontend Transport; Thu, 12 Jan 2023 01:15:51 -0600 From: Mubin Sayyed To: , , , , , CC: , , , , , Mubin Sayyed Subject: [LINUX PATCH 3/3] pwm: pwm-cadence: Add support for TTC PWM Date: Thu, 12 Jan 2023 12:45:26 +0530 Message-ID: <20230112071526.3035949-4-mubin.sayyed@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230112071526.3035949-1-mubin.sayyed@amd.com> References: <20230112071526.3035949-1-mubin.sayyed@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1NAM11FT029:EE_|SN7PR12MB8004:EE_ X-MS-Office365-Filtering-Correlation-Id: 2a8a1a05-3858-4170-8962-08daf46ce2fa X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Jan 2023 07:16:12.6343 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2a8a1a05-3858-4170-8962-08daf46ce2fa X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT029.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB8004 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_PASS,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1754800219383152644?= X-GMAIL-MSGID: =?utf-8?q?1754800219383152644?= Cadence TTC timer can be configured as clocksource/clockevent or PWM device. Specific TTC device would be configured as PWM device, if pwm-cells property is present in the device tree node. In case of Zynq, ZynqMP and Versal SoC's, each TTC device has 3 timers/counters, so maximum 3 PWM channels can be configured for each TTC IP instance. Also, output of 0th PWM channel of each TTC device can be routed to MIO or EMIO, and output of 2nd and 3rd PWM channel can be routed only to EMIO. Period for given PWM channel is configured through interval timer and duty cycle through match counter. Signed-off-by: Mubin Sayyed --- drivers/pwm/Kconfig | 11 ++ drivers/pwm/Makefile | 1 + drivers/pwm/pwm-cadence.c | 363 ++++++++++++++++++++++++++++++++++++++ 3 files changed, 375 insertions(+) create mode 100644 drivers/pwm/pwm-cadence.c diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig index dae023d783a2..9e0f1fae4711 100644 --- a/drivers/pwm/Kconfig +++ b/drivers/pwm/Kconfig @@ -504,6 +504,17 @@ config PWM_SIFIVE To compile this driver as a module, choose M here: the module will be called pwm-sifive. +config PWM_CADENCE + tristate "Cadence PWM support" + depends on OF + depends on COMMON_CLK + help + Generic PWM framework driver for cadence TTC IP found on + Xilinx Zynq/ZynqMP/Versal SOCs. Each TTC device has 3 PWM + channels. Output of 0th PWM channel of each TTC device can + be routed to MIO or EMIO, and output of 1st and 2nd PWM + channels can be routed only to EMIO. + config PWM_SL28CPLD tristate "Kontron sl28cpld PWM support" depends on MFD_SL28CPLD || COMPILE_TEST diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile index 7bf1a29f02b8..f744f021be0f 100644 --- a/drivers/pwm/Makefile +++ b/drivers/pwm/Makefile @@ -46,6 +46,7 @@ obj-$(CONFIG_PWM_RENESAS_TPU) += pwm-renesas-tpu.o obj-$(CONFIG_PWM_ROCKCHIP) += pwm-rockchip.o obj-$(CONFIG_PWM_SAMSUNG) += pwm-samsung.o obj-$(CONFIG_PWM_SIFIVE) += pwm-sifive.o +obj-$(CONFIG_PWM_CADENCE) += pwm-cadence.o obj-$(CONFIG_PWM_SL28CPLD) += pwm-sl28cpld.o obj-$(CONFIG_PWM_SPEAR) += pwm-spear.o obj-$(CONFIG_PWM_SPRD) += pwm-sprd.o diff --git a/drivers/pwm/pwm-cadence.c b/drivers/pwm/pwm-cadence.c new file mode 100644 index 000000000000..de981df3ec5a --- /dev/null +++ b/drivers/pwm/pwm-cadence.c @@ -0,0 +1,363 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Driver to configure cadence TTC timer as PWM + * generator + * + * Copyright (C) 2022, Advanced Micro Devices, Inc. + */ + +#include +#include +#include +#include +#include +#include +#include + +#define TTC_CLK_CNTRL_OFFSET 0x00 +#define TTC_CNT_CNTRL_OFFSET 0x0C +#define TTC_MATCH_CNT_VAL_OFFSET 0x30 +#define TTC_COUNT_VAL_OFFSET 0x18 +#define TTC_INTR_VAL_OFFSET 0x24 +#define TTC_ISR_OFFSET 0x54 +#define TTC_IER_OFFSET 0x60 +#define TTC_PWM_CHANNEL_OFFSET 0x4 + +#define TTC_CLK_CNTRL_CSRC_MASK BIT(5) +#define TTC_CLK_CNTRL_PSV_MASK GENMASK(4, 1) + +#define TTC_CNTR_CTRL_DIS_MASK BIT(0) +#define TTC_CNTR_CTRL_INTR_MODE_EN_MASK BIT(1) +#define TTC_CNTR_CTRL_MATCH_MODE_EN_MASK BIT(3) +#define TTC_CNTR_CTRL_RST_MASK BIT(4) +#define TTC_CNTR_CTRL_WAVE_EN_MASK BIT(5) +#define TTC_CNTR_CTRL_WAVE_POL_MASK BIT(6) + +#define TTC_CLK_CNTRL_PSV_SHIFT 1 + +#define TTC_PWM_MAX_CH 3 + +/** + * struct ttc_pwm_priv - Private data for TTC PWM drivers + * @chip: PWM chip structure representing PWM controller + * @clk: TTC input clock + * @max: Maximum value of the counters + * @base: Base address of TTC instance + */ +struct ttc_pwm_priv { + struct pwm_chip chip; + struct clk *clk; + u32 max; + void __iomem *base; +}; + +static inline u32 ttc_pwm_readl(struct ttc_pwm_priv *priv, + unsigned long offset) +{ + return readl_relaxed(priv->base + offset); +} + +static inline void ttc_pwm_writel(struct ttc_pwm_priv *priv, + unsigned long offset, + unsigned long val) +{ + writel_relaxed(val, priv->base + offset); +} + +static inline u32 ttc_pwm_ch_readl(struct ttc_pwm_priv *priv, + struct pwm_device *pwm, + unsigned long offset) +{ + unsigned long pwm_ch_offset = offset + + (TTC_PWM_CHANNEL_OFFSET * pwm->hwpwm); + + return ttc_pwm_readl(priv, pwm_ch_offset); +} + +static inline void ttc_pwm_ch_writel(struct ttc_pwm_priv *priv, + struct pwm_device *pwm, + unsigned long offset, + unsigned long val) +{ + unsigned long pwm_ch_offset = offset + + (TTC_PWM_CHANNEL_OFFSET * pwm->hwpwm); + + ttc_pwm_writel(priv, pwm_ch_offset, val); +} + +static inline struct ttc_pwm_priv *xilinx_pwm_chip_to_priv(struct pwm_chip *chip) +{ + return container_of(chip, struct ttc_pwm_priv, chip); +} + +static void ttc_pwm_enable(struct ttc_pwm_priv *priv, struct pwm_device *pwm) +{ + u32 ctrl_reg; + + ctrl_reg = ttc_pwm_ch_readl(priv, pwm, TTC_CNT_CNTRL_OFFSET); + ctrl_reg |= (TTC_CNTR_CTRL_INTR_MODE_EN_MASK + | TTC_CNTR_CTRL_MATCH_MODE_EN_MASK | TTC_CNTR_CTRL_RST_MASK); + ctrl_reg &= (~(TTC_CNTR_CTRL_DIS_MASK | TTC_CNTR_CTRL_WAVE_EN_MASK)); + ttc_pwm_ch_writel(priv, pwm, TTC_CNT_CNTRL_OFFSET, ctrl_reg); +} + +static void ttc_pwm_disable(struct ttc_pwm_priv *priv, struct pwm_device *pwm) +{ + u32 ctrl_reg; + + ctrl_reg = ttc_pwm_ch_readl(priv, pwm, TTC_CNT_CNTRL_OFFSET); + ctrl_reg |= TTC_CNTR_CTRL_DIS_MASK; + + ttc_pwm_ch_writel(priv, pwm, TTC_CNT_CNTRL_OFFSET, ctrl_reg); +} + +static void ttc_pwm_rev_polarity(struct ttc_pwm_priv *priv, struct pwm_device *pwm) +{ + u32 ctrl_reg; + + ctrl_reg = ttc_pwm_ch_readl(priv, pwm, TTC_CNT_CNTRL_OFFSET); + ctrl_reg ^= TTC_CNTR_CTRL_WAVE_POL_MASK; + ttc_pwm_ch_writel(priv, pwm, TTC_CNT_CNTRL_OFFSET, ctrl_reg); +} + +static void ttc_pwm_set_counters(struct ttc_pwm_priv *priv, + struct pwm_device *pwm, + u32 div, + u32 period_cycles, + u32 duty_cycles) +{ + u32 clk_reg; + + /* Set up prescalar */ + clk_reg = ttc_pwm_ch_readl(priv, pwm, TTC_CLK_CNTRL_OFFSET); + clk_reg &= ~TTC_CLK_CNTRL_PSV_MASK; + clk_reg |= div; + ttc_pwm_ch_writel(priv, pwm, TTC_CLK_CNTRL_OFFSET, clk_reg); + + /* Set up period */ + ttc_pwm_ch_writel(priv, pwm, TTC_INTR_VAL_OFFSET, period_cycles); + + /* Set up duty cycle */ + ttc_pwm_ch_writel(priv, pwm, TTC_MATCH_CNT_VAL_OFFSET, duty_cycles); +} + +static int ttc_pwm_apply(struct pwm_chip *chip, + struct pwm_device *pwm, + const struct pwm_state *state) +{ + u32 div = 0; + u64 period_cycles; + u64 duty_cycles; + unsigned long rate; + struct pwm_state cstate; + struct ttc_pwm_priv *priv = xilinx_pwm_chip_to_priv(chip); + + pwm_get_state(pwm, &cstate); + + if (state->polarity != cstate.polarity) { + if (cstate.enabled) + ttc_pwm_disable(priv, pwm); + + ttc_pwm_rev_polarity(priv, pwm); + + if (cstate.enabled) + ttc_pwm_enable(priv, pwm); + } + + if (state->period != cstate.period || + state->duty_cycle != cstate.duty_cycle) { + rate = clk_get_rate(priv->clk); + + /* Prevent overflow by limiting to the maximum possible period */ + period_cycles = min_t(u64, state->period, ULONG_MAX * NSEC_PER_SEC); + period_cycles = DIV_ROUND_CLOSEST(period_cycles * rate, NSEC_PER_SEC); + + if (period_cycles > priv->max) { + /* prescale frequency to fit requested period cycles within limit */ + div = 1; + + while ((period_cycles > priv->max) && (div < 65536)) { + rate = DIV_ROUND_CLOSEST(rate, BIT(div)); + period_cycles = DIV_ROUND_CLOSEST(state->period * rate, + NSEC_PER_SEC); + if (period_cycles < priv->max) + break; + div++; + } + + if (period_cycles > priv->max) + return -ERANGE; + } + + duty_cycles = DIV_ROUND_CLOSEST(state->duty_cycle * rate, + NSEC_PER_SEC); + if (cstate.enabled) + ttc_pwm_disable(priv, pwm); + + ttc_pwm_set_counters(priv, pwm, div, period_cycles, duty_cycles); + + if (cstate.enabled) + ttc_pwm_enable(priv, pwm); + } + + if (state->enabled != cstate.enabled) { + if (state->enabled) + ttc_pwm_enable(priv, pwm); + else + ttc_pwm_disable(priv, pwm); + } + + return 0; +} + +static int ttc_pwm_get_state(struct pwm_chip *chip, + struct pwm_device *pwm, + struct pwm_state *state) +{ + struct ttc_pwm_priv *priv = xilinx_pwm_chip_to_priv(chip); + unsigned long rate; + u32 value; + u64 tmp; + + value = ttc_pwm_ch_readl(priv, pwm, TTC_CNT_CNTRL_OFFSET); + + if (value & TTC_CNTR_CTRL_WAVE_POL_MASK) + state->polarity = PWM_POLARITY_INVERSED; + else + state->polarity = PWM_POLARITY_NORMAL; + + if (value & TTC_CNTR_CTRL_DIS_MASK) + state->enabled = false; + else + state->enabled = true; + + rate = clk_get_rate(priv->clk); + + tmp = ttc_pwm_ch_readl(priv, pwm, TTC_INTR_VAL_OFFSET); + state->period = DIV_ROUND_CLOSEST_ULL(tmp, rate); + + tmp = ttc_pwm_ch_readl(priv, pwm, TTC_MATCH_CNT_VAL_OFFSET); + state->duty_cycle = DIV_ROUND_CLOSEST_ULL(tmp, rate); + + return 0; +} + +static struct pwm_device * +ttc_pwm_of_xlate(struct pwm_chip *chip, const struct of_phandle_args *args) +{ + struct pwm_device *pwm; + + if (args->args[0] >= TTC_PWM_MAX_CH) + return NULL; + + pwm = pwm_request_from_chip(chip, args->args[0], NULL); + if (IS_ERR(pwm)) + return pwm; + + if (args->args[1]) + pwm->args.period = args->args[1]; + + if (args->args[2]) + pwm->args.polarity = args->args[2]; + + return pwm; +} + +static const struct pwm_ops ttc_pwm_ops = { + .apply = ttc_pwm_apply, + .get_state = ttc_pwm_get_state, + .owner = THIS_MODULE, +}; + +static int ttc_pwm_probe(struct platform_device *pdev) +{ + int ret; + int clksel; + struct device *dev = &pdev->dev; + struct device_node *np = dev->of_node; + struct ttc_pwm_priv *priv; + u32 pwm_cells; + u32 timer_width; + struct clk *clk_cs; + + ret = of_property_read_u32(np, "#pwm-cells", &pwm_cells); + if (ret == -EINVAL) + return -ENODEV; + + if (ret) + return dev_err_probe(dev, ret, "could not read #pwm-cells\n"); + + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(priv->base)) + return PTR_ERR(priv->base); + + ret = of_property_read_u32(np, "timer-width", &timer_width); + if (ret) + timer_width = 16; + + priv->max = BIT(timer_width) - 1; + + clksel = ttc_pwm_readl(priv, TTC_CLK_CNTRL_OFFSET); + clksel = !!(clksel & TTC_CLK_CNTRL_CSRC_MASK); + clk_cs = of_clk_get(np, clksel); + if (IS_ERR(clk_cs)) + return dev_err_probe(dev, PTR_ERR(clk_cs), + "ERROR: timer input clock not found\n"); + + priv->clk = clk_cs; + ret = clk_prepare_enable(priv->clk); + if (ret) + return dev_err_probe(dev, ret, "Clock enable failed\n"); + + clk_rate_exclusive_get(priv->clk); + + priv->chip.dev = dev; + priv->chip.ops = &ttc_pwm_ops; + priv->chip.npwm = TTC_PWM_MAX_CH; + priv->chip.of_xlate = ttc_pwm_of_xlate; + ret = pwmchip_add(&priv->chip); + if (ret) { + clk_rate_exclusive_put(priv->clk); + clk_disable_unprepare(priv->clk); + return dev_err_probe(dev, ret, "Could not register PWM chip\n"); + } + + platform_set_drvdata(pdev, priv); + + return 0; +} + +static int ttc_pwm_remove(struct platform_device *pdev) +{ + struct ttc_pwm_priv *priv = platform_get_drvdata(pdev); + + pwmchip_remove(&priv->chip); + clk_rate_exclusive_put(priv->clk); + clk_disable_unprepare(priv->clk); + + return 0; +} + +static const struct of_device_id ttc_pwm_of_match[] = { + { .compatible = "cdns,ttc"}, + {}, +}; +MODULE_DEVICE_TABLE(of, ttc_pwm_of_match); + +static struct platform_driver ttc_pwm_driver = { + .probe = ttc_pwm_probe, + .remove = ttc_pwm_remove, + .driver = { + .name = "ttc-pwm", + .of_match_table = of_match_ptr(ttc_pwm_of_match), + }, +}; +module_platform_driver(ttc_pwm_driver); + +MODULE_AUTHOR("Mubin Sayyed "); +MODULE_DESCRIPTION("Cadence TTC PWM driver"); +MODULE_LICENSE("GPL");