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[2620:137:e000::1:20]) by mx.google.com with ESMTP id t14-20020aa7d70e000000b0044ec8b62ee3si16160198edq.120.2022.10.13.04.04.49; Thu, 13 Oct 2022 04:05:27 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229541AbiJMKv6 (ORCPT + 99 others); Thu, 13 Oct 2022 06:51:58 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44900 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229552AbiJMKvx (ORCPT ); Thu, 13 Oct 2022 06:51:53 -0400 Received: from ironport.ite.com.tw (60-251-196-230.hinet-ip.hinet.net [60.251.196.230]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 59D42FF279; Thu, 13 Oct 2022 03:51:36 -0700 (PDT) Received: from unknown (HELO mse.ite.com.tw) ([192.168.35.30]) by ironport.ite.com.tw with ESMTP; 13 Oct 2022 18:51:35 +0800 Received: from CSBMAIL1.internal.ite.com.tw (CSBMAIL1.internal.ite.com.tw [192.168.65.58]) by mse.ite.com.tw with ESMTP id 29DApTjX073258; Thu, 13 Oct 2022 18:51:29 +0800 (GMT-8) (envelope-from allen.chen@ite.com.tw) Received: from VirtualBox.internal.ite.com.tw (192.168.70.46) by CSBMAIL1.internal.ite.com.tw (192.168.65.58) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.14; Thu, 13 Oct 2022 18:51:29 +0800 From: allen CC: Allen Chen , Pin-yen Lin , Jau-Chih Tseng , Kenneth Hung , Hermes Wu , Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , "open list:DRM DRIVERS" , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , open list Subject: [PATCH v4 1/2] dt-bindings: it6505: add properties to restrict output bandwidth Date: Thu, 13 Oct 2022 18:51:13 +0800 Message-ID: <20221013105116.180380-2-allen.chen@ite.com.tw> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221013105116.180380-1-allen.chen@ite.com.tw> References: <20221013105116.180380-1-allen.chen@ite.com.tw> MIME-Version: 1.0 X-Originating-IP: [192.168.70.46] X-ClientProxiedBy: CSBMAIL1.internal.ite.com.tw (192.168.65.58) To CSBMAIL1.internal.ite.com.tw (192.168.65.58) X-TM-SNTS-SMTP: C902D7E551BA36576A4CA1E87E219A4A356FAF4AE9A8A8A4F6E008F209DF59172002:8 X-MAIL: mse.ite.com.tw 29DApTjX073258 X-Spam-Status: No, score=-0.9 required=5.0 tests=BAYES_00,PDS_RDNS_DYNAMIC_FP, RDNS_DYNAMIC,SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1746570185863264345?= X-GMAIL-MSGID: =?utf-8?q?1746570185863264345?= From: allen chen Add properties to restrict dp output data-lanes and clock. Signed-off-by: Pin-Yen Lin Signed-off-by: Allen Chen --- .../bindings/display/bridge/ite,it6505.yaml | 43 +++++++++++++++++++ 1 file changed, 43 insertions(+) diff --git a/Documentation/devicetree/bindings/display/bridge/ite,it6505.yaml b/Documentation/devicetree/bindings/display/bridge/ite,it6505.yaml index 833d11b2303a7..f2c3d1d10359e 100644 --- a/Documentation/devicetree/bindings/display/bridge/ite,it6505.yaml +++ b/Documentation/devicetree/bindings/display/bridge/ite,it6505.yaml @@ -52,10 +52,51 @@ properties: maxItems: 1 description: extcon specifier for the Power Delivery + data-lanes: + oneOf: + - minItems: 1 + maxItems: 1 + uniqueItems: true + items: + enum: + - 0 + - 1 + description: For one lane operation. + + - minItems: 2 + maxItems: 2 + uniqueItems: true + items: + enum: + - 0 + - 1 + description: For two lanes operation. + + - minItems: 4 + maxItems: 4 + uniqueItems: true + items: + enum: + - 0 + - 1 + - 2 + - 3 + description: For four lanes operation. + port: $ref: /schemas/graph.yaml#/properties/port description: A port node pointing to DPI host port node + properties: + endpoint: + $ref: /schemas/graph.yaml#/$defs/endpoint-base + + properties: + link-frequencies: + minItems: 1 + maxItems: 1 + description: Allowed max link frequencies in Hz. + required: - compatible - ovdd-supply @@ -84,10 +125,12 @@ examples: pwr18-supply = <&it6505_pp18_reg>; reset-gpios = <&pio 179 1>; extcon = <&usbc_extcon>; + data-lanes = <0 1>; port { it6505_in: endpoint { remote-endpoint = <&dpi_out>; + link-frequencies = /bits/ 64 <150000000>; }; }; }; From patchwork Thu Oct 13 10:51:14 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: allen X-Patchwork-Id: 2015 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4ac7:0:0:0:0:0 with SMTP id y7csp203151wrs; Thu, 13 Oct 2022 03:57:19 -0700 (PDT) X-Google-Smtp-Source: AMsMyM4Cr5Xqep72rz0EcwqbPhRjsNaxS7xMe5xglzcs2CXsefbqadqYvk05I3BYE1jIEHrePVIC X-Received: by 2002:a05:6402:298b:b0:44f:20a:2db2 with SMTP id eq11-20020a056402298b00b0044f020a2db2mr32102455edb.138.1665658639078; Thu, 13 Oct 2022 03:57:19 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1665658639; cv=none; d=google.com; s=arc-20160816; b=LtJw3AXUuRJEPdlE0918zH7d+Oq2QZrfC+K+JlY43+5j9fGHk+HKPIjuV/Cne+g8G2 b9K0jFbVoadw9u0chb+w0XGR+VCzqR5YDTfrdg910i4mrLN2zlgxDvjeRysZxEbAww1/ L0HY/0SMEFMl4FptUpVa9ByH32C5vwcZNdx5E6ERLGEgVq1UwpEk4zwzWzwQn1Fi30oE GIQfXr6YpLcijq5SiH0O8ae8ZLuY9NkWI6Wcgtwx19l8Oo0SgWe15MoZo4DUKXfDl5vC szgQ33BA25xMR1L7kBEH5JT3Y9yMfuokq1h7ydg/E0ka03ZjpLjD0TQxaM7FKJPru25Y yBiQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:to:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:from; bh=vUevMDrf9LcTHwDTbU6Nl4mruK/S68BvVKeF7znpqGQ=; b=rrwJBFOpOfvzT5JM4EeuMlgZAOnM/z9vAEuWUQjpxeLUvRQjtLGtlCBxq4wKYZp5aj c8jxKFkO8uPsDyf6iQY8B/LEjTRYE36KaP1zbv8UmDnU7Ij/t4zlOHA4rkJ/n+mxYr/4 HELMuXsFRyx+mamsqhgiEnJfWXPjjxJOiVGCtzrMKcc/m/Gmt8tg9VOOTwx4O1gk1dqi GUTB0DU5yc+idHM6dV4U/Kx59H16G4571Ig3duaZmzF2aTp4JIjk8Z9ERnAE34NikzeV UzAtIRWDyEBUCKXLIiwtO+MbYrWeKnUZ2XXofk0ABsB2tYeEtJwnp2pmc1S62hn0Btci BYXg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Allen chen Signed-off-by: Pin-yen Lin --- drivers/gpu/drm/bridge/ite-it6505.c | 54 +++++++++++++++++++++++++++-- 1 file changed, 51 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/bridge/ite-it6505.c b/drivers/gpu/drm/bridge/ite-it6505.c index a4302492cf8df..653ab38465b98 100644 --- a/drivers/gpu/drm/bridge/ite-it6505.c +++ b/drivers/gpu/drm/bridge/ite-it6505.c @@ -437,6 +437,8 @@ struct it6505 { bool powered; bool hpd_state; u32 afe_setting; + u32 max_dpi_pixel_clock; + u32 max_lane_count; enum hdcp_state hdcp_status; struct delayed_work hdcp_work; struct work_struct hdcp_wait_ksv_list; @@ -1476,7 +1478,8 @@ static void it6505_parse_link_capabilities(struct it6505 *it6505) it6505->lane_count = link->num_lanes; DRM_DEV_DEBUG_DRIVER(dev, "Sink support %d lanes training", it6505->lane_count); - it6505->lane_count = min_t(int, it6505->lane_count, MAX_LANE_COUNT); + it6505->lane_count = min_t(int, it6505->lane_count, + it6505->max_lane_count); it6505->branch_device = drm_dp_is_branch(it6505->dpcd); DRM_DEV_DEBUG_DRIVER(dev, "Sink %sbranch device", @@ -2912,7 +2915,7 @@ it6505_bridge_mode_valid(struct drm_bridge *bridge, if (mode->flags & DRM_MODE_FLAG_INTERLACE) return MODE_NO_INTERLACE; - if (mode->clock > DPI_PIXEL_CLK_MAX) + if (mode->clock > it6505->max_dpi_pixel_clock) return MODE_CLOCK_HIGH; it6505->video_info.clock = mode->clock; @@ -3102,7 +3105,13 @@ static int it6505_init_pdata(struct it6505 *it6505) static void it6505_parse_dt(struct it6505 *it6505) { struct device *dev = &it6505->client->dev; + struct device_node *np = dev->of_node, *ep = NULL; + int len; + u64 link_frequencies; + u32 data_lanes[4]; u32 *afe_setting = &it6505->afe_setting; + u32 *max_lane_count = &it6505->max_lane_count; + u32 *max_dpi_pixel_clock = &it6505->max_dpi_pixel_clock; it6505->lane_swap_disabled = device_property_read_bool(dev, "no-laneswap"); @@ -3118,7 +3127,46 @@ static void it6505_parse_dt(struct it6505 *it6505) } else { *afe_setting = 0; } - DRM_DEV_DEBUG_DRIVER(dev, "using afe_setting: %d", *afe_setting); + + len = of_property_read_variable_u32_array(np, "data-lanes", + data_lanes, 0, + ARRAY_SIZE(data_lanes)); + *max_lane_count = len; + + if (len < 0 || *max_lane_count == 3 || *max_lane_count > 4) { + dev_err(dev, "error data-lanes, use default"); + *max_lane_count = MAX_LANE_COUNT; + } + + ep = of_graph_get_endpoint_by_regs(np, 0, 0); + + if (ep) { + len = of_property_read_variable_u64_array(ep, + "link-frequencies", + &link_frequencies, 0, + 1); + if (len >= 0) { + link_frequencies /= 1000; + if (link_frequencies > 297000) { + dev_err(dev, + "max pixel clock error, use default"); + *max_dpi_pixel_clock = DPI_PIXEL_CLK_MAX; + } else { + *max_dpi_pixel_clock = link_frequencies; + } + } else { + dev_err(dev, "error link frequencies, use default"); + *max_dpi_pixel_clock = DPI_PIXEL_CLK_MAX; + } + } else { + dev_err(dev, "error endpoint, use default"); + *max_dpi_pixel_clock = DPI_PIXEL_CLK_MAX; + } + + DRM_DEV_DEBUG_DRIVER(dev, "using afe_setting: %u, max_lane_count: %u", + it6505->afe_setting, it6505->max_lane_count); + DRM_DEV_DEBUG_DRIVER(dev, "using max_dpi_pixel_clock: %u kHz", + it6505->max_dpi_pixel_clock); } static ssize_t receive_timing_debugfs_show(struct file *file, char __user *buf,