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[93.34.92.88]) by smtp.googlemail.com with ESMTPSA id r126-20020a1c2b84000000b003d35c845cbbsm19927757wmr.21.2023.01.10.10.33.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Jan 2023 10:33:07 -0800 (PST) From: Christian Marangi To: Rob Herring , Krzysztof Kozlowski , Andy Gross , Bjorn Andersson , Konrad Dybcio , Michael Turquette , Stephen Boyd , Christian Marangi , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org Cc: Krzysztof Kozlowski , Rob Herring Subject: [PATCH v6 1/6] dt-bindings: clock: Convert qcom,krait-cc to yaml Date: Tue, 10 Jan 2023 19:32:54 +0100 Message-Id: <20230110183259.19142-2-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230110183259.19142-1-ansuelsmth@gmail.com> References: <20230110183259.19142-1-ansuelsmth@gmail.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM, RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1754661923027878984?= X-GMAIL-MSGID: =?utf-8?q?1754661923027878984?= Convert qcom,krait-cc to yaml Documentation. Signed-off-by: Christian Marangi Reviewed-by: Krzysztof Kozlowski Acked-by: Rob Herring --- .../bindings/clock/qcom,krait-cc.txt | 34 ----------- .../bindings/clock/qcom,krait-cc.yaml | 59 +++++++++++++++++++ 2 files changed, 59 insertions(+), 34 deletions(-) delete mode 100644 Documentation/devicetree/bindings/clock/qcom,krait-cc.txt create mode 100644 Documentation/devicetree/bindings/clock/qcom,krait-cc.yaml diff --git a/Documentation/devicetree/bindings/clock/qcom,krait-cc.txt b/Documentation/devicetree/bindings/clock/qcom,krait-cc.txt deleted file mode 100644 index 030ba60dab08..000000000000 --- a/Documentation/devicetree/bindings/clock/qcom,krait-cc.txt +++ /dev/null @@ -1,34 +0,0 @@ -Krait Clock Controller - -PROPERTIES - -- compatible: - Usage: required - Value type: - Definition: must be one of: - "qcom,krait-cc-v1" - "qcom,krait-cc-v2" - -- #clock-cells: - Usage: required - Value type: - Definition: must be 1 - -- clocks: - Usage: required - Value type: - Definition: reference to the clock parents of hfpll, secondary muxes. - -- clock-names: - Usage: required - Value type: - Definition: must be "hfpll0", "hfpll1", "acpu0_aux", "acpu1_aux", "qsb". - -Example: - - kraitcc: clock-controller { - compatible = "qcom,krait-cc-v1"; - clocks = <&hfpll0>, <&hfpll1>, <&acpu0_aux>, <&acpu1_aux>, ; - clock-names = "hfpll0", "hfpll1", "acpu0_aux", "acpu1_aux", "qsb"; - #clock-cells = <1>; - }; diff --git a/Documentation/devicetree/bindings/clock/qcom,krait-cc.yaml b/Documentation/devicetree/bindings/clock/qcom,krait-cc.yaml new file mode 100644 index 000000000000..8caa5a677394 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,krait-cc.yaml @@ -0,0 +1,59 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,krait-cc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Krait Clock Controller + +maintainers: + - Christian Marangi + +description: | + Qualcomm Krait Clock Controller used to correctly scale the CPU and the L2 + rates. + +properties: + compatible: + enum: + - qcom,krait-cc-v1 + - qcom,krait-cc-v2 + + clocks: + items: + - description: phandle to hfpll for CPU0 mux + - description: phandle to hfpll for CPU1 mux + - description: phandle to CPU0 aux clock + - description: phandle to CPU1 aux clock + - description: phandle to QSB fixed clk + + clock-names: + items: + - const: hfpll0 + - const: hfpll1 + - const: acpu0_aux + - const: acpu1_aux + - const: qsb + + '#clock-cells': + const: 1 + +required: + - compatible + - clocks + - clock-names + - '#clock-cells' + +additionalProperties: false + +examples: + - | + clock-controller { + compatible = "qcom,krait-cc-v1"; + clocks = <&hfpll0>, <&hfpll1>, + <&acpu0_aux>, <&acpu1_aux>, <&qsb>; + clock-names = "hfpll0", "hfpll1", + "acpu0_aux", "acpu1_aux", "qsb"; + #clock-cells = <1>; + }; +... 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[93.34.92.88]) by smtp.googlemail.com with ESMTPSA id r126-20020a1c2b84000000b003d35c845cbbsm19927757wmr.21.2023.01.10.10.33.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Jan 2023 10:33:08 -0800 (PST) From: Christian Marangi To: Rob Herring , Krzysztof Kozlowski , Andy Gross , Bjorn Andersson , Konrad Dybcio , Michael Turquette , Stephen Boyd , Christian Marangi , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH v6 2/6] dt-bindings: arm: msm: Convert and split kpss-acc driver Documentation to yaml Date: Tue, 10 Jan 2023 19:32:55 +0100 Message-Id: <20230110183259.19142-3-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230110183259.19142-1-ansuelsmth@gmail.com> References: <20230110183259.19142-1-ansuelsmth@gmail.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM, RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1754661917106619403?= X-GMAIL-MSGID: =?utf-8?q?1754661917106619403?= Convert kpss-acc driver Documentation to yaml. The original Documentation was wrong all along. Fix it while we are converting it. The example was wrong as kpss-acc-v2 should only expose the regs but we don't have any driver that expose additional clocks. The kpss-acc driver is only specific to v1. For this exact reason, split the Documentation to 2 different schema, v1 as clock-controller and v2 for power-controller as per msm-3.10 specification, the exposed regs handle power domains. Signed-off-by: Christian Marangi --- .../bindings/arm/msm/qcom,kpss-acc.txt | 49 ------------- .../bindings/clock/qcom,kpss-acc-v1.yaml | 72 +++++++++++++++++++ .../bindings/power/qcom,kpss-acc-v2.yaml | 47 ++++++++++++ 3 files changed, 119 insertions(+), 49 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/msm/qcom,kpss-acc.txt create mode 100644 Documentation/devicetree/bindings/clock/qcom,kpss-acc-v1.yaml create mode 100644 Documentation/devicetree/bindings/power/qcom,kpss-acc-v2.yaml diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,kpss-acc.txt b/Documentation/devicetree/bindings/arm/msm/qcom,kpss-acc.txt deleted file mode 100644 index 7f696362a4a1..000000000000 --- a/Documentation/devicetree/bindings/arm/msm/qcom,kpss-acc.txt +++ /dev/null @@ -1,49 +0,0 @@ -Krait Processor Sub-system (KPSS) Application Clock Controller (ACC) - -The KPSS ACC provides clock, power domain, and reset control to a Krait CPU. -There is one ACC register region per CPU within the KPSS remapped region as -well as an alias register region that remaps accesses to the ACC associated -with the CPU accessing the region. - -PROPERTIES - -- compatible: - Usage: required - Value type: - Definition: should be one of: - "qcom,kpss-acc-v1" - "qcom,kpss-acc-v2" - -- reg: - Usage: required - Value type: - Definition: the first element specifies the base address and size of - the register region. An optional second element specifies - the base address and size of the alias register region. - -- clocks: - Usage: required - Value type: - Definition: reference to the pll parents. - -- clock-names: - Usage: required - Value type: - Definition: must be "pll8_vote", "pxo". - -- clock-output-names: - Usage: optional - Value type: - Definition: Name of the output clock. Typically acpuX_aux where X is a - CPU number starting at 0. - -Example: - - clock-controller@2088000 { - compatible = "qcom,kpss-acc-v2"; - reg = <0x02088000 0x1000>, - <0x02008000 0x1000>; - clocks = <&gcc PLL8_VOTE>, <&gcc PXO_SRC>; - clock-names = "pll8_vote", "pxo"; - clock-output-names = "acpu0_aux"; - }; diff --git a/Documentation/devicetree/bindings/clock/qcom,kpss-acc-v1.yaml b/Documentation/devicetree/bindings/clock/qcom,kpss-acc-v1.yaml new file mode 100644 index 000000000000..a466e4e8aacd --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,kpss-acc-v1.yaml @@ -0,0 +1,72 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,kpss-acc-v1.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Krait Processor Sub-system (KPSS) Application Clock Controller (ACC) v1 + +maintainers: + - Christian Marangi + +description: + The KPSS ACC provides clock, power domain, and reset control to a Krait CPU. + There is one ACC register region per CPU within the KPSS remapped region as + well as an alias register region that remaps accesses to the ACC associated + with the CPU accessing the region. ACC v1 is currently used as a + clock-controller for enabling the cpu and hanling the aux clocks. + +properties: + compatible: + const: qcom,kpss-acc-v1 + + reg: + items: + - description: Base address and size of the register region + - description: Optional base address and size of the alias register region + minItems: 1 + + clocks: + minItems: 2 + maxItems: 2 + + clock-names: + items: + - const: pll8_vote + - const: pxo + + clock-output-names: + description: Name of the aux clock. Krait can have at most 4 cpu. + enum: + - acpu0_aux + - acpu1_aux + - acpu2_aux + - acpu3_aux + + '#clock-cells': + const: 0 + +required: + - compatible + - reg + - clocks + - clock-names + - clock-output-names + - '#clock-cells' + +additionalProperties: false + +examples: + - | + #include + + clock-controller@2088000 { + compatible = "qcom,kpss-acc-v1"; + reg = <0x02088000 0x1000>, <0x02008000 0x1000>; + clocks = <&gcc PLL8_VOTE>, <&pxo_board>; + clock-names = "pll8_vote", "pxo"; + clock-output-names = "acpu0_aux"; + #clock-cells = <0>; + }; + +... diff --git a/Documentation/devicetree/bindings/power/qcom,kpss-acc-v2.yaml b/Documentation/devicetree/bindings/power/qcom,kpss-acc-v2.yaml new file mode 100644 index 000000000000..91af95569ae6 --- /dev/null +++ b/Documentation/devicetree/bindings/power/qcom,kpss-acc-v2.yaml @@ -0,0 +1,47 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/power/qcom,kpss-acc-v2.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Krait Processor Sub-system (KPSS) Application Clock Controller (ACC) v2 + +maintainers: + - Christian Marangi + +description: + The KPSS ACC provides clock, power domain, and reset control to a Krait CPU. + There is one ACC register region per CPU within the KPSS remapped region as + well as an alias register region that remaps accesses to the ACC associated + with the CPU accessing the region. ACC v2 is currently used as a + power-controller for enabling the cpu. + +properties: + compatible: + const: qcom,kpss-acc-v2 + + reg: + items: + - description: Base address and size of the register region + - description: Optional base address and size of the alias register region + minItems: 1 + + '#power-domain-cells': + const: 0 + +required: + - compatible + - reg + - '#power-domain-cells' + +additionalProperties: false + +examples: + - | + power-controller@f9088000 { + compatible = "qcom,kpss-acc-v2"; + reg = <0xf9088000 0x1000>, + <0xf9008000 0x1000>; + #power-domain-cells = <0>; + }; +... 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[93.34.92.88]) by smtp.googlemail.com with ESMTPSA id r126-20020a1c2b84000000b003d35c845cbbsm19927757wmr.21.2023.01.10.10.33.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Jan 2023 10:33:09 -0800 (PST) From: Christian Marangi To: Rob Herring , Krzysztof Kozlowski , Andy Gross , Bjorn Andersson , Konrad Dybcio , Michael Turquette , Stephen Boyd , Christian Marangi , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH v6 3/6] dt-bindings: arm: msm: Rework kpss-gcc driver Documentation to yaml Date: Tue, 10 Jan 2023 19:32:56 +0100 Message-Id: <20230110183259.19142-4-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230110183259.19142-1-ansuelsmth@gmail.com> References: <20230110183259.19142-1-ansuelsmth@gmail.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM, RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1754661908840842214?= X-GMAIL-MSGID: =?utf-8?q?1754661908840842214?= Rework kpss-gcc driver Documentation to yaml Documentation and move it to clock as it's a clock-controller. The current kpss-gcc Documentation have major problems and can't be converted directly. Introduce various changes to the original Documentation. Add #clock-cells additional binding as this clock outputs a static clk named acpu_l2_aux with supported compatible. Only some compatible require and outputs a clock, for the others, set only the reg as a required binding to correctly export the kpss-gcc registers. As the reg is shared also add the required syscon compatible. Signed-off-by: Christian Marangi Reviewed-by: Rob Herring --- .../bindings/arm/msm/qcom,kpss-gcc.txt | 44 ---------- .../bindings/clock/qcom,kpss-gcc.yaml | 88 +++++++++++++++++++ 2 files changed, 88 insertions(+), 44 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/msm/qcom,kpss-gcc.txt create mode 100644 Documentation/devicetree/bindings/clock/qcom,kpss-gcc.yaml diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,kpss-gcc.txt b/Documentation/devicetree/bindings/arm/msm/qcom,kpss-gcc.txt deleted file mode 100644 index e628758950e1..000000000000 --- a/Documentation/devicetree/bindings/arm/msm/qcom,kpss-gcc.txt +++ /dev/null @@ -1,44 +0,0 @@ -Krait Processor Sub-system (KPSS) Global Clock Controller (GCC) - -PROPERTIES - -- compatible: - Usage: required - Value type: - Definition: should be one of the following. The generic compatible - "qcom,kpss-gcc" should also be included. - "qcom,kpss-gcc-ipq8064", "qcom,kpss-gcc" - "qcom,kpss-gcc-apq8064", "qcom,kpss-gcc" - "qcom,kpss-gcc-msm8974", "qcom,kpss-gcc" - "qcom,kpss-gcc-msm8960", "qcom,kpss-gcc" - -- reg: - Usage: required - Value type: - Definition: base address and size of the register region - -- clocks: - Usage: required - Value type: - Definition: reference to the pll parents. - -- clock-names: - Usage: required - Value type: - Definition: must be "pll8_vote", "pxo". - -- clock-output-names: - Usage: required - Value type: - Definition: Name of the output clock. Typically acpu_l2_aux indicating - an L2 cache auxiliary clock. - -Example: - - l2cc: clock-controller@2011000 { - compatible = "qcom,kpss-gcc-ipq8064", "qcom,kpss-gcc"; - reg = <0x2011000 0x1000>; - clocks = <&gcc PLL8_VOTE>, <&gcc PXO_SRC>; - clock-names = "pll8_vote", "pxo"; - clock-output-names = "acpu_l2_aux"; - }; diff --git a/Documentation/devicetree/bindings/clock/qcom,kpss-gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,kpss-gcc.yaml new file mode 100644 index 000000000000..88b7672123a0 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,kpss-gcc.yaml @@ -0,0 +1,88 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,kpss-gcc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Krait Processor Sub-system (KPSS) Global Clock Controller (GCC) + +maintainers: + - Christian Marangi + +description: + Krait Processor Sub-system (KPSS) Global Clock Controller (GCC). Used + to control L2 mux (in the current implementation) and provide access + to the kpss-gcc registers. + +properties: + compatible: + items: + - enum: + - qcom,kpss-gcc-ipq8064 + - qcom,kpss-gcc-apq8064 + - qcom,kpss-gcc-msm8974 + - qcom,kpss-gcc-msm8960 + - qcom,kpss-gcc-msm8660 + - qcom,kpss-gcc-mdm9615 + - const: qcom,kpss-gcc + - const: syscon + + reg: + maxItems: 1 + + clocks: + minItems: 2 + maxItems: 2 + + clock-names: + items: + - const: pll8_vote + - const: pxo + + '#clock-cells': + const: 0 + +required: + - compatible + - reg + +if: + properties: + compatible: + contains: + enum: + - qcom,kpss-gcc-ipq8064 + - qcom,kpss-gcc-apq8064 + - qcom,kpss-gcc-msm8974 + - qcom,kpss-gcc-msm8960 +then: + required: + - clocks + - clock-names + - '#clock-cells' +else: + properties: + clock: false + clock-names: false + '#clock-cells': false + +additionalProperties: false + +examples: + - | + #include + + clock-controller@2011000 { + compatible = "qcom,kpss-gcc-ipq8064", "qcom,kpss-gcc", "syscon"; + reg = <0x2011000 0x1000>; + clocks = <&gcc PLL8_VOTE>, <&pxo_board>; + clock-names = "pll8_vote", "pxo"; + #clock-cells = <0>; + }; + + - | + clock-controller@2011000 { + compatible = "qcom,kpss-gcc-mdm9615", "qcom,kpss-gcc", "syscon"; + reg = <0x02011000 0x1000>; + }; +... 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[93.34.92.88]) by smtp.googlemail.com with ESMTPSA id r126-20020a1c2b84000000b003d35c845cbbsm19927757wmr.21.2023.01.10.10.33.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Jan 2023 10:33:10 -0800 (PST) From: Christian Marangi To: Rob Herring , Krzysztof Kozlowski , Andy Gross , Bjorn Andersson , Konrad Dybcio , Michael Turquette , Stephen Boyd , Christian Marangi , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH v6 4/6] ARM: dts: qcom: fix various wrong definition for kpss-gcc node Date: Tue, 10 Jan 2023 19:32:57 +0100 Message-Id: <20230110183259.19142-5-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230110183259.19142-1-ansuelsmth@gmail.com> References: <20230110183259.19142-1-ansuelsmth@gmail.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM, RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1754661922622008610?= X-GMAIL-MSGID: =?utf-8?q?1754661922622008610?= Fix dtbs_check warning now that we have a correct kpss-gcc yaml schema. Add additional qcom,kpss-gcc compatible to differentiate devices where kpss-gcc should provide a clk and where kpss-gcc should just provide the registers and the syscon phandle. Add missing #clock-cells and remove useless clock-output-names for ipq806x. Add missing bindings for msm8960 and apq8064 kpss-gcc node. Signed-off-by: Christian Marangi --- arch/arm/boot/dts/qcom-apq8064.dtsi | 5 ++++- arch/arm/boot/dts/qcom-ipq8064.dtsi | 4 ++-- arch/arm/boot/dts/qcom-mdm9615.dtsi | 2 +- arch/arm/boot/dts/qcom-msm8660.dtsi | 2 +- arch/arm/boot/dts/qcom-msm8960.dtsi | 5 ++++- 5 files changed, 12 insertions(+), 6 deletions(-) diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi index 1f3e0aa9ab0c..1e68b42acb91 100644 --- a/arch/arm/boot/dts/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom-apq8064.dtsi @@ -880,8 +880,11 @@ mmcc: clock-controller@4000000 { }; l2cc: clock-controller@2011000 { - compatible = "qcom,kpss-gcc", "syscon"; + compatible = "qcom,kpss-gcc-apq8064", "qcom,kpss-gcc", "syscon"; reg = <0x2011000 0x1000>; + clocks = <&gcc PLL8_VOTE>, <&pxo_board>; + clock-names = "pll8_vote", "pxo"; + #clock-cells = <0>; }; rpm: rpm@108000 { diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi index 7e784b0995da..de87fcaaa836 100644 --- a/arch/arm/boot/dts/qcom-ipq8064.dtsi +++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi @@ -570,11 +570,11 @@ IRQ_TYPE_EDGE_RISING)>, }; l2cc: clock-controller@2011000 { - compatible = "qcom,kpss-gcc", "syscon"; + compatible = "qcom,kpss-gcc-ipq8064", "qcom,kpss-gcc", "syscon"; reg = <0x02011000 0x1000>; clocks = <&gcc PLL8_VOTE>, <&pxo_board>; clock-names = "pll8_vote", "pxo"; - clock-output-names = "acpu_l2_aux"; + #clock-cells = <0>; }; acc0: clock-controller@2088000 { diff --git a/arch/arm/boot/dts/qcom-mdm9615.dtsi b/arch/arm/boot/dts/qcom-mdm9615.dtsi index b0fe1d95d88f..61dfec3b9037 100644 --- a/arch/arm/boot/dts/qcom-mdm9615.dtsi +++ b/arch/arm/boot/dts/qcom-mdm9615.dtsi @@ -116,7 +116,7 @@ lcc: clock-controller@28000000 { }; l2cc: clock-controller@2011000 { - compatible = "qcom,kpss-gcc", "syscon"; + compatible = "qcom,kpss-gcc-mdm9615", "qcom,kpss-gcc", "syscon"; reg = <0x02011000 0x1000>; }; diff --git a/arch/arm/boot/dts/qcom-msm8660.dtsi b/arch/arm/boot/dts/qcom-msm8660.dtsi index 86f76d0feff4..f601b40ebcf4 100644 --- a/arch/arm/boot/dts/qcom-msm8660.dtsi +++ b/arch/arm/boot/dts/qcom-msm8660.dtsi @@ -473,7 +473,7 @@ pm8058_led133: led@133 { }; l2cc: clock-controller@2082000 { - compatible = "qcom,kpss-gcc", "syscon"; + compatible = "qcom,kpss-gcc-msm8660", "qcom,kpss-gcc", "syscon"; reg = <0x02082000 0x1000>; }; diff --git a/arch/arm/boot/dts/qcom-msm8960.dtsi b/arch/arm/boot/dts/qcom-msm8960.dtsi index 7debf9db7cb1..3bd07cac315b 100644 --- a/arch/arm/boot/dts/qcom-msm8960.dtsi +++ b/arch/arm/boot/dts/qcom-msm8960.dtsi @@ -183,8 +183,11 @@ clock-controller@4000000 { }; l2cc: clock-controller@2011000 { - compatible = "qcom,kpss-gcc", "syscon"; + compatible = "qcom,kpss-gcc-msm8960", "qcom,kpss-gcc", "syscon"; reg = <0x2011000 0x1000>; + clocks = <&gcc PLL8_VOTE>, <&pxo_board>; + clock-names = "pll8_vote", "pxo"; + #clock-cells = <0>; }; rpm: rpm@108000 { From patchwork Tue Jan 10 18:32:58 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 41584 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4e01:0:0:0:0:0 with SMTP id p1csp2908926wrt; Tue, 10 Jan 2023 10:40:30 -0800 (PST) X-Google-Smtp-Source: AMrXdXs7kWJ9wT1ZT/VpZiUOl3lBeMABYtWCCP9UDRj8odOgiDuIn5WYj3qE8LtsZ8pwLycUfTGF X-Received: by 2002:a17:90a:45:b0:225:e016:e2fe with SMTP id 5-20020a17090a004500b00225e016e2femr66692898pjb.31.1673376029778; Tue, 10 Jan 2023 10:40:29 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1673376029; cv=none; d=google.com; s=arc-20160816; b=Fk+dZvRDqyhlJz2vB4qtWG4Cc4qttGAOEDnrL2FwL4oNsraNeFn8BfhZYB2ohpLfJX 3JY/iQzpS6rsJx3YpoIISXptk72/HknZZv1JCbyWnEEsYjnusrBCfeXMCeY5V/OEj1L8 X30OYHj4JMXNaaBKr7BWy7VA/EJ73ujZ+1CfgbdcrvbMBCny78up34JPc0wNwU6j1ltQ DbgzvtkMXhB3S3+sGa2kAe+bWrvqKPfWQIU3olVCDEwKBRbNkl2PM15t6qt8LUA7IUWb OQZqRox1QBp4poQkg5WiTDNBF2F+lUcIMY3keIGtn98v2xdW8p4Ao3DZPco6KEu5n72b 5O0A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=0GJ8ePTx035rcaOd/R7rMyibrkKO9qKgvXnxhtNv8wo=; b=Tvax1XmMNin5yz+7m1jZIthtXruuce+1ueCl5a7pMMMWIbWl8afUcsNcori7Rkqm4y 0t9KzpT/v4nOFxeZqdvpASfnRDo6/u0h7hH3ZaMAm0Qi56qeoIlo2NNsDMoKr/3cypw3 Bl0nO+sTEJSiDjK1fBlMmJAP0y7wiP3PIsCuYmEIZX4Z3t16cFMjZ4Q5m/cedGGqH883 /VPGDfvpKz1IVRqJ8gxhUo60GwhHaIna+jBdL7ab0B6oi3jmhRV7laCP+dPWluBrAf6z aDAFURiUWrJtIimJS4GIF8fafDq3G2eXHc+1HuRMr6rz+6AS/UiMZvn6AoqcJXa4c/Bm wdUg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20210112 header.b=jVcHTQCV; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: from out1.vger.email (out1.vger.email. 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[93.34.92.88]) by smtp.googlemail.com with ESMTPSA id r126-20020a1c2b84000000b003d35c845cbbsm19927757wmr.21.2023.01.10.10.33.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Jan 2023 10:33:11 -0800 (PST) From: Christian Marangi To: Rob Herring , Krzysztof Kozlowski , Andy Gross , Bjorn Andersson , Konrad Dybcio , Michael Turquette , Stephen Boyd , Christian Marangi , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH v6 5/6] ARM: dts: qcom: fix various wrong definition for kpss-acc-v1 Date: Tue, 10 Jan 2023 19:32:58 +0100 Message-Id: <20230110183259.19142-6-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230110183259.19142-1-ansuelsmth@gmail.com> References: <20230110183259.19142-1-ansuelsmth@gmail.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM, RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1754661943964068602?= X-GMAIL-MSGID: =?utf-8?q?1754661943964068602?= Fix dtbs_check warning now that we have a correct kpss-acc-v1 yaml schema. Add missing clocks, clock-names, clock-output-names and #clock-cells bindings for each kpss-acc-v1 clock-controller to reflect Documentation schema. Signed-off-by: Christian Marangi Reviewed-by: Dmitry Baryshkov --- arch/arm/boot/dts/qcom-apq8064.dtsi | 16 ++++++++++++++++ arch/arm/boot/dts/qcom-ipq8064.dtsi | 8 ++++++++ arch/arm/boot/dts/qcom-msm8960.dtsi | 8 ++++++++ 3 files changed, 32 insertions(+) diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi index 1e68b42acb91..af84f2d350ef 100644 --- a/arch/arm/boot/dts/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom-apq8064.dtsi @@ -389,21 +389,37 @@ timer@200a000 { acc0: clock-controller@2088000 { compatible = "qcom,kpss-acc-v1"; reg = <0x02088000 0x1000>, <0x02008000 0x1000>; + clocks = <&gcc PLL8_VOTE>, <&pxo_board>; + clock-names = "pll8_vote", "pxo"; + clock-output-names = "acpu0_aux"; + #clock-cells = <0>; }; acc1: clock-controller@2098000 { compatible = "qcom,kpss-acc-v1"; reg = <0x02098000 0x1000>, <0x02008000 0x1000>; + clocks = <&gcc PLL8_VOTE>, <&pxo_board>; + clock-names = "pll8_vote", "pxo"; + clock-output-names = "acpu1_aux"; + #clock-cells = <0>; }; acc2: clock-controller@20a8000 { compatible = "qcom,kpss-acc-v1"; reg = <0x020a8000 0x1000>, <0x02008000 0x1000>; + clocks = <&gcc PLL8_VOTE>, <&pxo_board>; + clock-names = "pll8_vote", "pxo"; + clock-output-names = "acpu2_aux"; + #clock-cells = <0>; }; acc3: clock-controller@20b8000 { compatible = "qcom,kpss-acc-v1"; reg = <0x020b8000 0x1000>, <0x02008000 0x1000>; + clocks = <&gcc PLL8_VOTE>, <&pxo_board>; + clock-names = "pll8_vote", "pxo"; + clock-output-names = "acpu3_aux"; + #clock-cells = <0>; }; saw0: power-controller@2089000 { diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi index de87fcaaa836..e796094a7af5 100644 --- a/arch/arm/boot/dts/qcom-ipq8064.dtsi +++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi @@ -580,6 +580,10 @@ l2cc: clock-controller@2011000 { acc0: clock-controller@2088000 { compatible = "qcom,kpss-acc-v1"; reg = <0x02088000 0x1000>, <0x02008000 0x1000>; + clocks = <&gcc PLL8_VOTE>, <&pxo_board>; + clock-names = "pll8_vote", "pxo"; + clock-output-names = "acpu0_aux"; + #clock-cells = <0>; }; saw0: regulator@2089000 { @@ -591,6 +595,10 @@ saw0: regulator@2089000 { acc1: clock-controller@2098000 { compatible = "qcom,kpss-acc-v1"; reg = <0x02098000 0x1000>, <0x02008000 0x1000>; + clocks = <&gcc PLL8_VOTE>, <&pxo_board>; + clock-names = "pll8_vote", "pxo"; + clock-output-names = "acpu1_aux"; + #clock-cells = <0>; }; saw1: regulator@2099000 { diff --git a/arch/arm/boot/dts/qcom-msm8960.dtsi b/arch/arm/boot/dts/qcom-msm8960.dtsi index 3bd07cac315b..4fd56d85be3f 100644 --- a/arch/arm/boot/dts/qcom-msm8960.dtsi +++ b/arch/arm/boot/dts/qcom-msm8960.dtsi @@ -208,11 +208,19 @@ regulators { acc0: clock-controller@2088000 { compatible = "qcom,kpss-acc-v1"; reg = <0x02088000 0x1000>, <0x02008000 0x1000>; + clocks = <&gcc PLL8_VOTE>, <&pxo_board>; + clock-names = "pll8_vote", "pxo"; + clock-output-names = "acpu0_aux"; + #clock-cells = <0>; }; acc1: clock-controller@2098000 { compatible = "qcom,kpss-acc-v1"; reg = <0x02098000 0x1000>, <0x02008000 0x1000>; + clocks = <&gcc PLL8_VOTE>, <&pxo_board>; + clock-names = "pll8_vote", "pxo"; + clock-output-names = "acpu1_aux"; + #clock-cells = <0>; }; saw0: regulator@2089000 { From patchwork Tue Jan 10 18:32:59 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 41583 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4e01:0:0:0:0:0 with SMTP id p1csp2908832wrt; Tue, 10 Jan 2023 10:40:16 -0800 (PST) X-Google-Smtp-Source: AMrXdXvmjvYRz6oYIK3GJJWMMmOy8EmWIw+P70GnYAtNhwTvI3fTbRKk7Wef5en7XtdnnV0kz8BQ X-Received: by 2002:a17:902:aa0b:b0:189:cb96:1529 with SMTP id be11-20020a170902aa0b00b00189cb961529mr62532542plb.44.1673376016615; Tue, 10 Jan 2023 10:40:16 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1673376016; cv=none; d=google.com; s=arc-20160816; b=UvuqK2Ex7V9jDoR56s20XIvDVv0Nk3hEqa79Im/DAuCDkbBtguAtnowgiueTUsWSZ/ iGF/v0+HctLvP4N62cJETml+1E7X5gmpyE34LTn6o9SasDJ2MJaBr/DsO5FSkmNHN4oc WjevEOiMV0Q8UWzWT1v8ER/knlvDNxRPgzCwfRZRQoF0Mc9p/Lop2LmQO9SU8fWRqS3+ XS0tBIzTWzuTieBXB8+s8Tjr9GCjdhSAk8oWLiqG26TO1muU5gQVaUXfNGe6YGf3U1rU RfeHLvNchoJ6rMQSv+BksyT0eVte5p38R0fIwixtTGOoSomJ7yJb2vSOyJdlTK0MEx8d h+mA== ARC-Message-Signature: i=1; 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[93.34.92.88]) by smtp.googlemail.com with ESMTPSA id r126-20020a1c2b84000000b003d35c845cbbsm19927757wmr.21.2023.01.10.10.33.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Jan 2023 10:33:12 -0800 (PST) From: Christian Marangi To: Rob Herring , Krzysztof Kozlowski , Andy Gross , Bjorn Andersson , Konrad Dybcio , Michael Turquette , Stephen Boyd , Christian Marangi , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH v6 6/6] ARM: dts: qcom: fix various wrong definition for kpss-acc-v2 Date: Tue, 10 Jan 2023 19:32:59 +0100 Message-Id: <20230110183259.19142-7-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230110183259.19142-1-ansuelsmth@gmail.com> References: <20230110183259.19142-1-ansuelsmth@gmail.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM, RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1754661930158838932?= X-GMAIL-MSGID: =?utf-8?q?1754661930158838932?= Fix dtbs_check warning now that we have a correct kpss-acc-v2 yaml schema. Change acc node naming to power-controller and add missing binding #power-domain-cells for each kpss-acc-v2 power-controller to reflect Documentation schema. Signed-off-by: Christian Marangi --- arch/arm/boot/dts/qcom-apq8084.dtsi | 12 ++++++++---- arch/arm/boot/dts/qcom-ipq4019.dtsi | 12 ++++++++---- arch/arm/boot/dts/qcom-msm8974.dtsi | 12 ++++++++---- 3 files changed, 24 insertions(+), 12 deletions(-) diff --git a/arch/arm/boot/dts/qcom-apq8084.dtsi b/arch/arm/boot/dts/qcom-apq8084.dtsi index 4b0d2b4f4b6a..51c5867eb950 100644 --- a/arch/arm/boot/dts/qcom-apq8084.dtsi +++ b/arch/arm/boot/dts/qcom-apq8084.dtsi @@ -353,28 +353,32 @@ saw_l2: power-controller@f9012000 { regulator; }; - acc0: clock-controller@f9088000 { + acc0: power-controller@f9088000 { compatible = "qcom,kpss-acc-v2"; reg = <0xf9088000 0x1000>, <0xf9008000 0x1000>; + #power-domain-cells = <0>; }; - acc1: clock-controller@f9098000 { + acc1: power-controller@f9098000 { compatible = "qcom,kpss-acc-v2"; reg = <0xf9098000 0x1000>, <0xf9008000 0x1000>; + #power-domain-cells = <0>; }; - acc2: clock-controller@f90a8000 { + acc2: power-controller@f90a8000 { compatible = "qcom,kpss-acc-v2"; reg = <0xf90a8000 0x1000>, <0xf9008000 0x1000>; + #power-domain-cells = <0>; }; - acc3: clock-controller@f90b8000 { + acc3: power-controller@f90b8000 { compatible = "qcom,kpss-acc-v2"; reg = <0xf90b8000 0x1000>, <0xf9008000 0x1000>; + #power-domain-cells = <0>; }; restart@fc4ab000 { diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom-ipq4019.dtsi index acb08dcf9442..ee464aedece9 100644 --- a/arch/arm/boot/dts/qcom-ipq4019.dtsi +++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi @@ -325,24 +325,28 @@ crypto: crypto@8e3a000 { status = "disabled"; }; - acc0: clock-controller@b088000 { + acc0: power-controller@b088000 { compatible = "qcom,kpss-acc-v2"; reg = <0x0b088000 0x1000>, <0xb008000 0x1000>; + #power-domain-cells = <0>; }; - acc1: clock-controller@b098000 { + acc1: power-controller@b098000 { compatible = "qcom,kpss-acc-v2"; reg = <0x0b098000 0x1000>, <0xb008000 0x1000>; + #power-domain-cells = <0>; }; - acc2: clock-controller@b0a8000 { + acc2: power-controller@b0a8000 { compatible = "qcom,kpss-acc-v2"; reg = <0x0b0a8000 0x1000>, <0xb008000 0x1000>; + #power-domain-cells = <0>; }; - acc3: clock-controller@b0b8000 { + acc3: power-controller@b0b8000 { compatible = "qcom,kpss-acc-v2"; reg = <0x0b0b8000 0x1000>, <0xb008000 0x1000>; + #power-domain-cells = <0>; }; saw0: regulator@b089000 { diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi index 4b485f5612c4..59613aa52e25 100644 --- a/arch/arm/boot/dts/qcom-msm8974.dtsi +++ b/arch/arm/boot/dts/qcom-msm8974.dtsi @@ -416,24 +416,28 @@ saw_l2: power-controller@f9012000 { regulator; }; - acc0: clock-controller@f9088000 { + acc0: power-controller@f9088000 { compatible = "qcom,kpss-acc-v2"; reg = <0xf9088000 0x1000>, <0xf9008000 0x1000>; + #power-domain-cells = <0>; }; - acc1: clock-controller@f9098000 { + acc1: power-controller@f9098000 { compatible = "qcom,kpss-acc-v2"; reg = <0xf9098000 0x1000>, <0xf9008000 0x1000>; + #power-domain-cells = <0>; }; - acc2: clock-controller@f90a8000 { + acc2: power-controller@f90a8000 { compatible = "qcom,kpss-acc-v2"; reg = <0xf90a8000 0x1000>, <0xf9008000 0x1000>; + #power-domain-cells = <0>; }; - acc3: clock-controller@f90b8000 { + acc3: power-controller@f90b8000 { compatible = "qcom,kpss-acc-v2"; reg = <0xf90b8000 0x1000>, <0xf9008000 0x1000>; + #power-domain-cells = <0>; }; sdhc_1: mmc@f9824900 {