From patchwork Tue Jan 10 00:30:26 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Matthew Gerlach X-Patchwork-Id: 41237 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4e01:0:0:0:0:0 with SMTP id p1csp2461012wrt; Mon, 9 Jan 2023 16:31:07 -0800 (PST) X-Google-Smtp-Source: AMrXdXuYZAYBQ4no9pIdurzNp5ERHA4/adAwBiJJhvDWlntNpe5kPdZzkpaUSfPKql3qZzwyoRhY X-Received: by 2002:aa7:8a45:0:b0:586:ad46:ed6c with SMTP id n5-20020aa78a45000000b00586ad46ed6cmr8762032pfa.22.1673310667078; Mon, 09 Jan 2023 16:31:07 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1673310667; cv=none; d=google.com; s=arc-20160816; b=lGkQysPTbE90hi/91ADWq0xJle1u0sD5C3YjbVh0Q0NhSdx/M+JP4MfYSqm0Ktw/pN 1gA9U49llWZgixrJoJtgXqoFb4kx07Zukk+mt2Inn68xfGQko/VhqyAQZushBgbtEruZ yfnCsTyde4ZYTa3yXkaEAVHgX+AUm+u9ekvdmJqmayWuCtMJzpti3PRg9cawf6KwAfbT pfG34+MBitwgXbbdAEteI3Wp4/MQqOcDBJrMtTBn3BPdsKuCaSe+74kFIgjDHHUImEXm dFGTBzSFR3WAehn+btfOeK41Rctpm+/95w46TFJaaRjCeRZPjjtjf4r2qNo6wIG9w2oI xMOw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=Vl4B3aMFIdj2m7Jd/IVn34OGNoAZ/mpUQYu2s2j2bLM=; b=gWEhKkqb5GsOKf5+FKS4L6WmZ+5eWTuuvX9lIUq0yOxKpVNJp6R6UgZujBqVB+QoS1 MbzyWuv2/wdbie8iIvR5PX166GOmuyj+3w4eoUr4GNbbisr4Nzdw0yA5ru4MyAdGuIkG K+cCeTSyO9bKbASPkuXbjRtyWKRDLMafWNCHKHodQta6van3nC+Y3sZiBTycDrgiM2u/ KLAR0NzUNDOh/Qzprm5c5uTRbVw5glBMX5jXV+0ucQjNsZmtMGink1kdj9yAPlkvXLGW O7Ubx98Z1Qj6iWfzGFoi+M8M2s1P8YwA48hj0AglMG8i3K2AqPcQs4VPNHWqk/tZgYen q/pg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=XpxmB1FW; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id u13-20020a056a00124d00b00574b1311362si841023pfi.104.2023.01.09.16.30.54; Mon, 09 Jan 2023 16:31:07 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=XpxmB1FW; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235332AbjAJAaD (ORCPT + 99 others); Mon, 9 Jan 2023 19:30:03 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59864 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235767AbjAJA35 (ORCPT ); Mon, 9 Jan 2023 19:29:57 -0500 Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E81F03E0E6; Mon, 9 Jan 2023 16:29:55 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1673310596; x=1704846596; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=NObn6stZidq+7SmPoutFtJ/EZSc2Sfj2qbCIi9/idig=; b=XpxmB1FWubz11FE9wKTi2Snuix9IuvFZwENu1XlwIaK4ggj1qfdS2DMo N1smhxXdtZHAItbmamr6RN6PFI0JVrl2gKbFJaRetnDNUWsQRuIQC3wx+ KrsQJqhtG7xzni6njqh//xSX1UCQeWpjsI245XWYlfjKdApDVb7eFqsmc Lmvj1Xn8h1pWdjLbb/Q+DZTSKJo9QY0zhpDlHix6YJICV74Sp3NPtArmG p+sKCkH8ipN9XO9jX9fQNzYkcCMSk9vqpZsjKBK5n1q6QUqjdB8WMUoLR 09eGoIbJU0tAh7iLkitnf5i/3ecM0SqA5G0Ecb9ULyvpSIVHdmIovNOq4 A==; X-IronPort-AV: E=McAfee;i="6500,9779,10585"; a="324265537" X-IronPort-AV: E=Sophos;i="5.96,313,1665471600"; d="scan'208";a="324265537" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Jan 2023 16:29:53 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10585"; a="687381575" X-IronPort-AV: E=Sophos;i="5.96,313,1665471600"; d="scan'208";a="687381575" Received: from rhweight-wrk1.ra.intel.com ([137.102.106.43]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Jan 2023 16:29:53 -0800 From: matthew.gerlach@linux.intel.com To: hao.wu@intel.com, yilun.xu@intel.com, russell.h.weight@intel.com, basheer.ahmed.muddebihal@intel.com, trix@redhat.com, mdf@kernel.org, linux-fpga@vger.kernel.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, tianfei.zhang@intel.com, corbet@lwn.net, gregkh@linuxfoundation.org, linux-serial@vger.kernel.org, jirislaby@kernel.org, geert+renesas@glider.be, andriy.shevchenko@linux.intel.com, niklas.soderlund+renesas@ragnatech.se, macro@orcam.me.uk, johan@kernel.org, lukas@wunner.de, ilpo.jarvinen@linux.intel.com, marpagan@redhat.com, bagasdotme@gmail.com Cc: Matthew Gerlach Subject: [PATCH v10 1/4] Documentation: fpga: dfl: Add documentation for DFHv1 Date: Mon, 9 Jan 2023 16:30:26 -0800 Message-Id: <20230110003029.806022-2-matthew.gerlach@linux.intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230110003029.806022-1-matthew.gerlach@linux.intel.com> References: <20230110003029.806022-1-matthew.gerlach@linux.intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.3 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, RCVD_IN_MSPIKE_H3,RCVD_IN_MSPIKE_WL,SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1754593406235802513?= X-GMAIL-MSGID: =?utf-8?q?1754593406235802513?= From: Matthew Gerlach Add documentation describing the extensions provided by Version 1 of the Device Feature Header (DFHv1). Signed-off-by: Matthew Gerlach Reviewed-by: Ilpo Järvinen Reviewed-by: Tom Rix --- v10: ad Rb Tom Rix v9: move DFH definitions to after the Overview fix name of feature revision field clarify next field in DFH v8: fix section titles v7: shorten long lines and wording suggestions by bagasdotme@gmail.com v6: no change v5: use nested list for field descriptions clean up prose add reviewed-by and comments from Ilpo Järvinen v4: Remove marketing speak and separate v0 and v1 descriptions. Fix errors reported by "make htmldocs". v3: no change v2: s/GUILD/GUID/ add picture --- Documentation/fpga/dfl.rst | 117 +++++++++++++++++++++++++++++++++++++ 1 file changed, 117 insertions(+) diff --git a/Documentation/fpga/dfl.rst b/Documentation/fpga/dfl.rst index 15b670926084..7e015249785b 100644 --- a/Documentation/fpga/dfl.rst +++ b/Documentation/fpga/dfl.rst @@ -75,6 +75,123 @@ convenient for software to locate each feature by walking through this list, and can be implemented in register regions of any FPGA device. +Device Feature Header - Version 0 +================================= +Version 0 (DFHv0) is the original version of the Device Feature Header. +The format of DFHv0 is shown below:: + + +-----------------------------------------------------------------------+ + |63 Type 60|59 DFH VER 52|51 Rsvd 41|40 EOL|39 Next 16|15 REV 12|11 ID 0| 0x00 + +-----------------------------------------------------------------------+ + |63 GUID_L 0| 0x08 + +-----------------------------------------------------------------------+ + |63 GUID_H 0| 0x10 + +-----------------------------------------------------------------------+ + +- Offset 0x00 + + * Type - The type of DFH (e.g. FME, AFU, or private feature). + * DFH VER - The version of the DFH. + * Rsvd - Currently unused. + * EOL - Set if the DFH is the end of the Device Feature List (DFL). + * Next - The offset in bytes of the next DFH in the DFL from the DFH start, + and the start of a DFH must be aligned to an 8 byte boundary. + If EOL is set, Next is the size of MMIO of the last feature in the list. + * REV - The revision of the feature associated with this header. + * ID - The feature ID if Type is private feature. + +- Offset 0x08 + + * GUID_L - Least significant 64 bits of a 128-bit Globally Unique Identifier + (present only if Type is FME or AFU). + +- Offset 0x10 + + * GUID_H - Most significant 64 bits of a 128-bit Globally Unique Identifier + (present only if Type is FME or AFU). + + +Device Feature Header - Version 1 +================================= +Version 1 (DFHv1) of the Device Feature Header adds the following functionality: + +* Provides a standardized mechanism for features to describe + parameters/capabilities to software. +* Standardize the use of a GUID for all DFHv1 types. +* Decouples the DFH location from the register space of the feature itself. + +The format of Version 1 of the Device Feature Header (DFH) is shown below:: + + +-----------------------------------------------------------------------+ + |63 Type 60|59 DFH VER 52|51 Rsvd 41|40 EOL|39 Next 16|15 REV 12|11 ID 0| 0x00 + +-----------------------------------------------------------------------+ + |63 GUID_L 0| 0x08 + +-----------------------------------------------------------------------+ + |63 GUID_H 0| 0x10 + +-----------------------------------------------------------------------+ + |63 Reg Address/Offset 1| Rel 0| 0x18 + +-----------------------------------------------------------------------+ + |63 Reg Size 32|Params 31|30 Group 16|15 Instance 0| 0x20 + +-----------------------------------------------------------------------+ + |63 Next 35|34RSV33|EOP32|31 Param Version 16|15 Param ID 0| 0x28 + +-----------------------------------------------------------------------+ + |63 Parameter Data 0| 0x30 + +-----------------------------------------------------------------------+ + + ... + + +-----------------------------------------------------------------------+ + |63 Next 35|34RSV33|EOP32|31 Param Version 16|15 Param ID 0| + +-----------------------------------------------------------------------+ + |63 Parameter Data 0| + +-----------------------------------------------------------------------+ + +- Offset 0x00 + + * Type - The type of DFH (e.g. FME, AFU, or private feature). + * DFH VER - The version of the DFH. + * Rsvd - Currently unused. + * EOL - Set if the DFH is the end of the Device Feature List (DFL). + * Next - The offset in bytes of the next DFH in the DFL from the DFH start, + and the start of a DFH must be aligned to an 8 byte boundary. + If EOL is set, Next is the size of MMIO of the last feature in the list. + * REV - The revision of the feature associated with this header. + * ID - The feature ID if Type is private feature. + +- Offset 0x08 + + * GUID_L - Least significant 64 bits of a 128-bit Globally Unique Identifier. + +- Offset 0x10 + + * GUID_H - Most significant 64 bits of a 128-bit Globally Unique Identifier. + +- Offset 0x18 + + * Reg Address/Offset - If Rel bit is set, then the value is the high 63 bits + of a 16-bit aligned absolute address of the feature's registers. Otherwise + the value is the offset from the start of the DFH of the feature's registers. + +- Offset 0x20 + + * Reg Size - Size of feature's register set in bytes. + * Params - Set if DFH has a list of parameter blocks. + * Group - Id of group if feature is part of a group. + * Instance - Id of feature instance within a group. + +- Offset 0x28 if feature has parameters + + * Next - Offset to the next parameter block in 8 byte words. If EOP set, + size in 8 byte words of last parameter. + * Param Version - Version of Param ID. + * Param ID - ID of parameter. + +- Offset 0x30 + + * Parameter Data - Parameter data whose size and format is defined by + version and ID of the parameter. + + FIU - FME (FPGA Management Engine) ================================== The FPGA Management Engine performs reconfiguration and other infrastructure From patchwork Tue Jan 10 00:30:27 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Matthew Gerlach X-Patchwork-Id: 41235 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4e01:0:0:0:0:0 with SMTP id p1csp2460929wrt; Mon, 9 Jan 2023 16:30:56 -0800 (PST) X-Google-Smtp-Source: AMrXdXtOzBqv6opa2OGwpAJHoBF4buLnQXcZvKYTTpNyzwkWZz8bvTPFdKcb2DkmBR+pv5kx+3vd X-Received: by 2002:a05:6a21:e384:b0:b0:25ba:1769 with SMTP id cc4-20020a056a21e38400b000b025ba1769mr91188278pzc.58.1673310655959; Mon, 09 Jan 2023 16:30:55 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1673310655; cv=none; d=google.com; s=arc-20160816; b=XlSasjaLHf79VbftYs47a6EkThv3qOUJQ1evmS54nh29L9VgnnZxIeGxzXQUuqOPk2 EDXANB86lRUxXziyOKc//qF52iA+CMzShhnl+GDM0vCZ6TCML1f16gGO3mlmAaV8t58p P7MAKIYfYU7hPq48OQAcZA66Tzn/YRJFShBZxosaKEeBd98EaUSXA+08i7KBzFWe4g+8 bxyqu4BvKxt0SOYVP+R8+P2P3SJF8fAwaZ+LgFsEKS7iHzjExyM4vBH97BvYuxjSDWto W7jus7wsA56ruOrhGX0KjjeAqBzE2xoZpefhFhq4shqla/J8dEVFtVnE7szb7PazwFm1 9w2w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=4TPDv/0PnT0HVkGcy6ThpoAkGiNIXvzFb+E+8+337aQ=; b=MRSt2tl8iJIhQt9LJvvYTkU4WVCp4bbPylprJQxxvNGboRNbfFJhY2vB/CFAMZeD1u iHT5bo2pnL34Yg+TGuAODLgnAVM93O1Epz6pQtT0pWx2nZ37F9jX3/T4QRW+KKuzUfaD hjk4s0LsONMDQpMG3TV1SGvyeXDFmWu4YEtHUWNSfKmBs40zpW7td8ns5ZNLpWd8FOLa O2uqfrTNNZcdJiUSmB++w/b5QQIXQ36auw7faoh+Az9ET2sIfD0lXXgY4uypYUqLHAQc jwZyQiG2IHGTPvgHjnuNQR/IozJ7v8dQxSWK99ri5OvCwIDLCNyTEec5faLGDp+/lUto i6fQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=cfjSN26K; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id b7-20020a656687000000b004b147c3301bsi6711627pgw.194.2023.01.09.16.30.42; Mon, 09 Jan 2023 16:30:55 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=cfjSN26K; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237854AbjAJAaH (ORCPT + 99 others); Mon, 9 Jan 2023 19:30:07 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59866 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237022AbjAJA35 (ORCPT ); Mon, 9 Jan 2023 19:29:57 -0500 Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 20D003E0F5; Mon, 9 Jan 2023 16:29:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1673310596; x=1704846596; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=97E2BSirr4B+fKCh/DPTUyzjDzPfoMnNZocI//RrRj0=; b=cfjSN26KHT5HuX1ttfgFOyU4CQRTj4ort2jydFqctEfukUOVSUKrkhtr IvYCXhYJKesYjXO8asatUOoXKWYvSr6CkB/s+42JKZUg8/27szFrjIIcp zrDAKCg6b41aV4ac8tTX4KQ2NpeHTAWIJ1oFTFvJgIFCkwmBkFcCCA7NT iRPxc6kgtvr+wwehrC5O2DaWc05xgbp48h6/h+Flz28QiUm3O96qmJspd 1kMzHcPbI4P12LjLDXkv6hFoX71rh0WC1lqlDJph/XpmkPfZd3+cEJeTr nO3bG44PiyA1EacOhs0jJ86k1wOIPvjFJyPCQq+IOHAHCsGrouhOMYlZO g==; X-IronPort-AV: E=McAfee;i="6500,9779,10585"; a="324265548" X-IronPort-AV: E=Sophos;i="5.96,313,1665471600"; d="scan'208";a="324265548" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Jan 2023 16:29:53 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10585"; a="687381578" X-IronPort-AV: E=Sophos;i="5.96,313,1665471600"; d="scan'208";a="687381578" Received: from rhweight-wrk1.ra.intel.com ([137.102.106.43]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Jan 2023 16:29:53 -0800 From: matthew.gerlach@linux.intel.com To: hao.wu@intel.com, yilun.xu@intel.com, russell.h.weight@intel.com, basheer.ahmed.muddebihal@intel.com, trix@redhat.com, mdf@kernel.org, linux-fpga@vger.kernel.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, tianfei.zhang@intel.com, corbet@lwn.net, gregkh@linuxfoundation.org, linux-serial@vger.kernel.org, jirislaby@kernel.org, geert+renesas@glider.be, andriy.shevchenko@linux.intel.com, niklas.soderlund+renesas@ragnatech.se, macro@orcam.me.uk, johan@kernel.org, lukas@wunner.de, ilpo.jarvinen@linux.intel.com, marpagan@redhat.com, bagasdotme@gmail.com Cc: Basheer Ahmed Muddebihal , Matthew Gerlach Subject: [PATCH v10 2/4] fpga: dfl: Add DFHv1 Register Definitions Date: Mon, 9 Jan 2023 16:30:27 -0800 Message-Id: <20230110003029.806022-3-matthew.gerlach@linux.intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230110003029.806022-1-matthew.gerlach@linux.intel.com> References: <20230110003029.806022-1-matthew.gerlach@linux.intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.3 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, RCVD_IN_MSPIKE_H3,RCVD_IN_MSPIKE_WL,SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1754593394346446839?= X-GMAIL-MSGID: =?utf-8?q?1754593394346446839?= From: Basheer Ahmed Muddebihal This patch adds the definitions for DFHv1 header and related register bitfields. Signed-off-by: Basheer Ahmed Muddebihal Co-developed-by: Matthew Gerlach Signed-off-by: Matthew Gerlach Reviewed-by: Ilpo Järvinen Reviewed-by: Andy Shevchenko --- v10: no change v9: no change v8: add Rb Andy Shevchenko v7: no change v6: remove parameter definitions from include/linux/dfl.h v5: consistently use fields for parameter data s/EOL/EOP/ to match doc remove unneeded mask added Co-developed-by v4: s/MSIX/MSI_X/g move kerneldoc to implementation don't change copyright date v3: keep DFHv1 definitions "hidden" in drivers/fpga/dfl.h v2: clean up white space and one line comments remove extra space in commit use uniform number of digits in constants don't change copyright date because of removed content --- drivers/fpga/dfl.h | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/drivers/fpga/dfl.h b/drivers/fpga/dfl.h index 06cfcd5e84bb..fc59f33367ee 100644 --- a/drivers/fpga/dfl.h +++ b/drivers/fpga/dfl.h @@ -74,11 +74,43 @@ #define DFH_REVISION GENMASK_ULL(15, 12) /* Feature revision */ #define DFH_NEXT_HDR_OFST GENMASK_ULL(39, 16) /* Offset to next DFH */ #define DFH_EOL BIT_ULL(40) /* End of list */ +#define DFH_VERSION GENMASK_ULL(59, 52) /* DFH version */ #define DFH_TYPE GENMASK_ULL(63, 60) /* Feature type */ #define DFH_TYPE_AFU 1 #define DFH_TYPE_PRIVATE 3 #define DFH_TYPE_FIU 4 +/* + * DFHv1 Register Offset definitons + * In DHFv1, DFH + GUID + CSR_START + CSR_SIZE_GROUP + PARAM_HDR + PARAM_DATA + * as common header registers + */ +#define DFHv1_CSR_ADDR 0x18 /* CSR Register start address */ +#define DFHv1_CSR_SIZE_GRP 0x20 /* Size of Reg Block and Group/tag */ +#define DFHv1_PARAM_HDR 0x28 /* Optional First Param header */ + +/* + * CSR Rel Bit, 1'b0 = relative (offset from feature DFH start), + * 1'b1 = absolute (ARM or other non-PCIe use) + */ +#define DFHv1_CSR_ADDR_REL BIT_ULL(0) + +/* CSR Header Register Bit Definitions */ +#define DFHv1_CSR_ADDR_MASK GENMASK_ULL(63, 1) /* 63:1 of CSR address */ + +/* CSR SIZE Goup Register Bit Definitions */ +#define DFHv1_CSR_SIZE_GRP_INSTANCE_ID GENMASK_ULL(15, 0) /* Enumeration instantiated IP */ +#define DFHv1_CSR_SIZE_GRP_GROUPING_ID GENMASK_ULL(30, 16) /* Group Features/interfaces */ +#define DFHv1_CSR_SIZE_GRP_HAS_PARAMS BIT_ULL(31) /* Presence of Parameters */ +#define DFHv1_CSR_SIZE_GRP_SIZE GENMASK_ULL(63, 32) /* Size of CSR Block in bytes */ + +/* PARAM Header Register Bit Definitions */ +#define DFHv1_PARAM_HDR_ID GENMASK_ULL(15, 0) /* Id of this Param */ +#define DFHv1_PARAM_HDR_VER GENMASK_ULL(31, 16) /* Version Param */ +#define DFHv1_PARAM_HDR_NEXT_OFFSET GENMASK_ULL(63, 35) /* Offset of next Param */ +#define DFHv1_PARAM_HDR_NEXT_EOP BIT_ULL(32) +#define DFHv1_PARAM_DATA 0x08 /* Offset of Param data from Param header */ + /* Next AFU Register Bitfield */ #define NEXT_AFU_NEXT_DFH_OFST GENMASK_ULL(23, 0) /* Offset to next AFU */ From patchwork Tue Jan 10 00:30:28 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Matthew Gerlach X-Patchwork-Id: 41238 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4e01:0:0:0:0:0 with SMTP id p1csp2461295wrt; Mon, 9 Jan 2023 16:31:40 -0800 (PST) X-Google-Smtp-Source: AMrXdXsPxo6Sf/z2M1n/ZypSYsRTKtb+gWLP5uEyyR+S52bFPRzllbhlGwlncUAYsKLLnIqSZFsf X-Received: by 2002:a17:902:c10a:b0:188:bc62:276f with SMTP id 10-20020a170902c10a00b00188bc62276fmr67285948pli.3.1673310700045; Mon, 09 Jan 2023 16:31:40 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1673310700; cv=none; d=google.com; s=arc-20160816; b=sOtIKJolif1ew9XavpaLcZJgqzXzP79GjNjDkmnrGYNZw7eZkPzEcb9NwaswvvXMiL 2tepg+8Xsx2aclDDq/EfXzIW1ACE5eCylW5HRCy2BMe4oCXOUqhoszSY9GMmYKT9FjXL 4M0zEMM/IY6K2L0BTIEDC4iLecfGuR2Hs5BKstePw5x5SkN5UT1BQZIAEzx1N1CQwCwX dAhWvRkPBglY+xvtTONPZLV+KXfE2VRbSGd3O/k8gPfIrh1PZ0Hw/Nt+iRW0gNUq2n3U QRMGPDKRdJA1Mb+k84RFk3CrGm9FTEdGZebl5UUpZQaj7S/+nJQoGU5Iqv1tmlQbfHm9 jbzA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=qiMKsiw54/2ut8GKwD28824nwGwbpIArKP+FQu1Mzs4=; b=oeeihtLOGRSJxsQm9XvthQASFE2zjsd3SpCQ8WEh0Rg6hW9ep1R2qJxeai6sFjQ0MJ TQIP5pYXP4ojOc9zietJmF0+OgfSEAQwlMwAVfeorSsSIj+9juzHnT+WfHUwT4iE8Jbk sDgMsdvuceK/91TAC5DnGfTjPZcbqbkSdYduC96/kEwrnij1zpa9kzwaz7/fbh6kv6FE u+ga5NcI1CyeU20BpoD0+CBF8DopMGk0tzewMQNphI3f6Oc+Ia41UFuHb2qM1wXdSQEv SMvV1x6BAmq4zvo+NRVB3HvygAIljy06No6sWMPDendWZNMbBhv1PHvf2i/P4qL9efg4 oBaA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=bgs6Keki; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id p9-20020a170902bd0900b00176c9015627si9436898pls.94.2023.01.09.16.31.27; Mon, 09 Jan 2023 16:31:40 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=bgs6Keki; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237795AbjAJAad (ORCPT + 99 others); Mon, 9 Jan 2023 19:30:33 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59904 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237550AbjAJA36 (ORCPT ); Mon, 9 Jan 2023 19:29:58 -0500 Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1F3C13E0F2; Mon, 9 Jan 2023 16:29:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1673310597; x=1704846597; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=0BhFniL3Yz8pdVzP4uZQ0k2jL0WHYQ2W1tu2F6MEQ58=; b=bgs6KekiCyYVfaUZwUMds+Ur+NTCSRfcL9Dah5FW6ZjCnpu5uS4kOtbm RNylIEvhCTWJGpsGcSElpoeHdwgecRC031wEXCvR2qM3Q+ZxBrtaTBoUD 44qzNbsMwR5crWB4z8phnBb/aflc31NU+ozdrH3CTWCrZp8gJwVkIlWAY hI5Pwi/lvD7uyYTmHwR9EpIr9Cj7rHRKpOpLgjh6Wfs0bkstya+Ae1/9c vfRJ2TZdpVBEIYFgOOY6SdQ3MaqkQLoB3DkKRJivCzbQCocbsXoPK6KzO 9xTno6hfXo0S8rttwyRfAJXdqi0T4mmTWW5OfBQdp3wejyelTZ5IEPOq8 w==; X-IronPort-AV: E=McAfee;i="6500,9779,10585"; a="324265559" X-IronPort-AV: E=Sophos;i="5.96,313,1665471600"; d="scan'208";a="324265559" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Jan 2023 16:29:53 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10585"; a="687381581" X-IronPort-AV: E=Sophos;i="5.96,313,1665471600"; d="scan'208";a="687381581" Received: from rhweight-wrk1.ra.intel.com ([137.102.106.43]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Jan 2023 16:29:53 -0800 From: matthew.gerlach@linux.intel.com To: hao.wu@intel.com, yilun.xu@intel.com, russell.h.weight@intel.com, basheer.ahmed.muddebihal@intel.com, trix@redhat.com, mdf@kernel.org, linux-fpga@vger.kernel.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, tianfei.zhang@intel.com, corbet@lwn.net, gregkh@linuxfoundation.org, linux-serial@vger.kernel.org, jirislaby@kernel.org, geert+renesas@glider.be, andriy.shevchenko@linux.intel.com, niklas.soderlund+renesas@ragnatech.se, macro@orcam.me.uk, johan@kernel.org, lukas@wunner.de, ilpo.jarvinen@linux.intel.com, marpagan@redhat.com, bagasdotme@gmail.com Cc: Matthew Gerlach Subject: [PATCH v10 3/4] fpga: dfl: add basic support for DFHv1 Date: Mon, 9 Jan 2023 16:30:28 -0800 Message-Id: <20230110003029.806022-4-matthew.gerlach@linux.intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230110003029.806022-1-matthew.gerlach@linux.intel.com> References: <20230110003029.806022-1-matthew.gerlach@linux.intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.3 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, RCVD_IN_MSPIKE_H3,RCVD_IN_MSPIKE_WL,SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1754593440251760197?= X-GMAIL-MSGID: =?utf-8?q?1754593440251760197?= From: Matthew Gerlach Version 1 of the Device Feature Header (DFH) definition adds functionality to the Device Feature List (DFL) bus. A DFHv1 header may have one or more parameter blocks that further describes the HW to SW. Add support to the DFL bus to parse the MSI-X parameter. The location of a feature's register set is explicitly described in DFHv1 and can be relative to the base of the DFHv1 or an absolute address. Parse the location and pass the information to DFL driver. Signed-off-by: Matthew Gerlach Reviewed-by: Ilpo Järvinen --- v10: change dfh_find_param to return size of parameter data in bytes v9: fix spacing errors in commit message and code s/dfh_get_psize/dfh_get_param_size/ put new structure members at the end of the stucture update dfh_find_param API remove dfh_get_u64_param_vals v8: use struct_size() from overflow.h add dfh_get_u64_param_vals() v7: no change v6: move MSI_X parameter definitions to drivers/fpga/dfl.h v5: update field names fix find_param/dfh_get_psize clean up mmio_res assignments use u64* instead of void* use FIELD_GET instead of masking v4: s/MSIX/MSI_X move kernel doc to implementation use structure assignment fix decode of absolute address clean up comment in parse_feature_irqs remove use of csr_res v3: remove unneeded blank line use clearer variable name pass finfo into parse_feature_irqs() refactor code for better indentation use switch statement for irq parsing squash in code parsing register location v2: fix kernel doc clarify use of DFH_VERSION field --- drivers/fpga/dfl.c | 245 +++++++++++++++++++++++++++++++++++--------- drivers/fpga/dfl.h | 11 ++ include/linux/dfl.h | 8 ++ 3 files changed, 213 insertions(+), 51 deletions(-) diff --git a/drivers/fpga/dfl.c b/drivers/fpga/dfl.c index b9aae85ba930..0a4227bc9462 100644 --- a/drivers/fpga/dfl.c +++ b/drivers/fpga/dfl.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include "dfl.h" @@ -342,6 +343,8 @@ static void release_dfl_dev(struct device *dev) if (ddev->mmio_res.parent) release_resource(&ddev->mmio_res); + kfree(ddev->params); + ida_free(&dfl_device_ida, ddev->id); kfree(ddev->irqs); kfree(ddev); @@ -380,7 +383,16 @@ dfl_dev_add(struct dfl_feature_platform_data *pdata, ddev->type = feature_dev_id_type(pdev); ddev->feature_id = feature->id; ddev->revision = feature->revision; + ddev->dfh_version = feature->dfh_version; ddev->cdev = pdata->dfl_cdev; + if (feature->param_size) { + ddev->params = kmemdup(feature->params, feature->param_size, GFP_KERNEL); + if (!ddev->params) { + ret = -ENOMEM; + goto put_dev; + } + ddev->param_size = feature->param_size; + } /* add mmio resource */ parent_res = &pdev->resource[feature->resource_index]; @@ -708,20 +720,27 @@ struct build_feature_devs_info { * struct dfl_feature_info - sub feature info collected during feature dev build * * @fid: id of this sub feature. + * @revision: revision of this sub feature + * @dfh_version: version of Device Feature Header (DFH) * @mmio_res: mmio resource of this sub feature. * @ioaddr: mapped base address of mmio resource. * @node: node in sub_features linked list. * @irq_base: start of irq index in this sub feature. * @nr_irqs: number of irqs of this sub feature. + * @param_size: size DFH parameters. + * @params: DFH parameter data. */ struct dfl_feature_info { u16 fid; u8 revision; + u8 dfh_version; struct resource mmio_res; void __iomem *ioaddr; struct list_head node; unsigned int irq_base; unsigned int nr_irqs; + unsigned int param_size; + u64 params[]; }; static void dfl_fpga_cdev_add_port_dev(struct dfl_fpga_cdev *cdev, @@ -797,7 +816,17 @@ static int build_info_commit_dev(struct build_feature_devs_info *binfo) feature->dev = fdev; feature->id = finfo->fid; feature->revision = finfo->revision; + feature->dfh_version = finfo->dfh_version; + if (finfo->param_size) { + feature->params = devm_kmemdup(binfo->dev, + finfo->params, finfo->param_size, + GFP_KERNEL); + if (!feature->params) + return -ENOMEM; + + feature->param_size = finfo->param_size; + } /* * the FIU header feature has some fundamental functions (sriov * set, port enable/disable) needed for the dfl bus device and @@ -934,56 +963,115 @@ static u16 feature_id(u64 value) return 0; } +static u64 *find_param(u64 *params, resource_size_t max, int param_id) +{ + u64 *end = params + max / sizeof(u64); + u64 v, next; + + while (params < end) { + v = *params; + if (param_id == FIELD_GET(DFHv1_PARAM_HDR_ID, v)) + return params; + + if (FIELD_GET(DFHv1_PARAM_HDR_NEXT_EOP, v)) + break; + + next = FIELD_GET(DFHv1_PARAM_HDR_NEXT_OFFSET, v); + params += next; + } + + return NULL; +} + +/** + * dfh_find_param() - find parameter block for the given parameter id + * @dfl_dev: dfl device + * @param_id: id of dfl parameter + * @psize: destination to store size of parameter data in bytes + * + * Return: pointer to start of parameter data, PTR_ERR otherwise. + */ +void *dfh_find_param(struct dfl_device *dfl_dev, int param_id, size_t *psize) +{ + u64 *phdr = find_param(dfl_dev->params, dfl_dev->param_size, param_id); + + if (!phdr) + return ERR_PTR(-ENOENT); + + if (psize) + *psize = (FIELD_GET(DFHv1_PARAM_HDR_NEXT_OFFSET, *phdr) - 1) * sizeof(u64); + + return phdr + 1; +} +EXPORT_SYMBOL_GPL(dfh_find_param); + static int parse_feature_irqs(struct build_feature_devs_info *binfo, - resource_size_t ofst, u16 fid, - unsigned int *irq_base, unsigned int *nr_irqs) + resource_size_t ofst, struct dfl_feature_info *finfo) { void __iomem *base = binfo->ioaddr + ofst; unsigned int i, ibase, inr = 0; + void *params = finfo->params; enum dfl_id_type type; + u16 fid = finfo->fid; int virq; + u64 *p; u64 v; - type = feature_dev_id_type(binfo->feature_dev); + switch (finfo->dfh_version) { + case 0: + /* + * DFHv0 only provides MMIO resource information for each feature + * in the DFL header. There is no generic interrupt information. + * Instead, features with interrupt functionality provide + * the information in feature specific registers. + */ + type = feature_dev_id_type(binfo->feature_dev); + if (type == PORT_ID) { + switch (fid) { + case PORT_FEATURE_ID_UINT: + v = readq(base + PORT_UINT_CAP); + ibase = FIELD_GET(PORT_UINT_CAP_FST_VECT, v); + inr = FIELD_GET(PORT_UINT_CAP_INT_NUM, v); + break; + case PORT_FEATURE_ID_ERROR: + v = readq(base + PORT_ERROR_CAP); + ibase = FIELD_GET(PORT_ERROR_CAP_INT_VECT, v); + inr = FIELD_GET(PORT_ERROR_CAP_SUPP_INT, v); + break; + } + } else if (type == FME_ID) { + switch (fid) { + case FME_FEATURE_ID_GLOBAL_ERR: + v = readq(base + FME_ERROR_CAP); + ibase = FIELD_GET(FME_ERROR_CAP_INT_VECT, v); + inr = FIELD_GET(FME_ERROR_CAP_SUPP_INT, v); + break; + } + } + break; - /* - * Ideally DFL framework should only read info from DFL header, but - * current version DFL only provides mmio resources information for - * each feature in DFL Header, no field for interrupt resources. - * Interrupt resource information is provided by specific mmio - * registers of each private feature which supports interrupt. So in - * order to parse and assign irq resources, DFL framework has to look - * into specific capability registers of these private features. - * - * Once future DFL version supports generic interrupt resource - * information in common DFL headers, the generic interrupt parsing - * code will be added. But in order to be compatible to old version - * DFL, the driver may still fall back to these quirks. - */ - if (type == PORT_ID) { - switch (fid) { - case PORT_FEATURE_ID_UINT: - v = readq(base + PORT_UINT_CAP); - ibase = FIELD_GET(PORT_UINT_CAP_FST_VECT, v); - inr = FIELD_GET(PORT_UINT_CAP_INT_NUM, v); - break; - case PORT_FEATURE_ID_ERROR: - v = readq(base + PORT_ERROR_CAP); - ibase = FIELD_GET(PORT_ERROR_CAP_INT_VECT, v); - inr = FIELD_GET(PORT_ERROR_CAP_SUPP_INT, v); + case 1: + /* + * DFHv1 provides interrupt resource information in DFHv1 + * parameter blocks. + */ + p = find_param(params, finfo->param_size, DFHv1_PARAM_ID_MSI_X); + if (!p) break; - } - } else if (type == FME_ID) { - if (fid == FME_FEATURE_ID_GLOBAL_ERR) { - v = readq(base + FME_ERROR_CAP); - ibase = FIELD_GET(FME_ERROR_CAP_INT_VECT, v); - inr = FIELD_GET(FME_ERROR_CAP_SUPP_INT, v); - } + + p++; + ibase = FIELD_GET(DFHv1_PARAM_MSI_X_STARTV, *p); + inr = FIELD_GET(DFHv1_PARAM_MSI_X_NUMV, *p); + break; + + default: + dev_warn(binfo->dev, "unexpected DFH version %d\n", finfo->dfh_version); + break; } if (!inr) { - *irq_base = 0; - *nr_irqs = 0; + finfo->irq_base = 0; + finfo->nr_irqs = 0; return 0; } @@ -1006,12 +1094,37 @@ static int parse_feature_irqs(struct build_feature_devs_info *binfo, } } - *irq_base = ibase; - *nr_irqs = inr; + finfo->irq_base = ibase; + finfo->nr_irqs = inr; return 0; } +static int dfh_get_param_size(void __iomem *dfh_base, resource_size_t max) +{ + int size = 0; + u64 v, next; + + if (!FIELD_GET(DFHv1_CSR_SIZE_GRP_HAS_PARAMS, + readq(dfh_base + DFHv1_CSR_SIZE_GRP))) + return 0; + + while (size + DFHv1_PARAM_HDR < max) { + v = readq(dfh_base + DFHv1_PARAM_HDR + size); + + next = FIELD_GET(DFHv1_PARAM_HDR_NEXT_OFFSET, v); + if (!next) + return -EINVAL; + + size += next * sizeof(u64); + + if (FIELD_GET(DFHv1_PARAM_HDR_NEXT_EOP, v)) + return size; + } + + return -ENOENT; +} + /* * when create sub feature instances, for private features, it doesn't need * to provide resource size and feature id as they could be read from DFH @@ -1023,39 +1136,69 @@ static int create_feature_instance(struct build_feature_devs_info *binfo, resource_size_t ofst, resource_size_t size, u16 fid) { - unsigned int irq_base, nr_irqs; struct dfl_feature_info *finfo; + resource_size_t start, end; + int dfh_psize = 0; u8 revision = 0; + u64 v, addr_off; + u8 dfh_ver = 0; int ret; - u64 v; if (fid != FEATURE_ID_AFU) { v = readq(binfo->ioaddr + ofst); revision = FIELD_GET(DFH_REVISION, v); - + dfh_ver = FIELD_GET(DFH_VERSION, v); /* read feature size and id if inputs are invalid */ size = size ? size : feature_size(v); fid = fid ? fid : feature_id(v); + if (dfh_ver == 1) { + dfh_psize = dfh_get_param_size(binfo->ioaddr + ofst, size); + if (dfh_psize < 0) { + dev_err(binfo->dev, + "failed to read size of DFHv1 parameters %d\n", + dfh_psize); + return dfh_psize; + } + dev_dbg(binfo->dev, "dfhv1_psize %d\n", dfh_psize); + } } if (binfo->len - ofst < size) return -EINVAL; - ret = parse_feature_irqs(binfo, ofst, fid, &irq_base, &nr_irqs); - if (ret) - return ret; - - finfo = kzalloc(sizeof(*finfo), GFP_KERNEL); + finfo = kzalloc(struct_size(finfo, params, dfh_psize / sizeof(u64)), GFP_KERNEL); if (!finfo) return -ENOMEM; + memcpy_fromio(finfo->params, binfo->ioaddr + ofst + DFHv1_PARAM_HDR, dfh_psize); + finfo->param_size = dfh_psize; + finfo->fid = fid; finfo->revision = revision; - finfo->mmio_res.start = binfo->start + ofst; - finfo->mmio_res.end = finfo->mmio_res.start + size - 1; + finfo->dfh_version = dfh_ver; + if (dfh_ver == 1) { + v = readq(binfo->ioaddr + ofst + DFHv1_CSR_ADDR); + addr_off = FIELD_GET(DFHv1_CSR_ADDR_MASK, v); + if (FIELD_GET(DFHv1_CSR_ADDR_REL, v)) + start = addr_off << 1; + else + start = binfo->start + ofst + addr_off; + + v = readq(binfo->ioaddr + ofst + DFHv1_CSR_SIZE_GRP); + end = start + FIELD_GET(DFHv1_CSR_SIZE_GRP_SIZE, v) - 1; + } else { + start = binfo->start + ofst; + end = start + size - 1; + } finfo->mmio_res.flags = IORESOURCE_MEM; - finfo->irq_base = irq_base; - finfo->nr_irqs = nr_irqs; + finfo->mmio_res.start = start; + finfo->mmio_res.end = end; + + ret = parse_feature_irqs(binfo, ofst, finfo); + if (ret) { + kfree(finfo); + return ret; + } list_add_tail(&finfo->node, &binfo->sub_features); binfo->feature_num++; diff --git a/drivers/fpga/dfl.h b/drivers/fpga/dfl.h index fc59f33367ee..20eaddce6988 100644 --- a/drivers/fpga/dfl.h +++ b/drivers/fpga/dfl.h @@ -111,6 +111,10 @@ #define DFHv1_PARAM_HDR_NEXT_EOP BIT_ULL(32) #define DFHv1_PARAM_DATA 0x08 /* Offset of Param data from Param header */ +#define DFHv1_PARAM_ID_MSI_X 0x1 +#define DFHv1_PARAM_MSI_X_NUMV GENMASK_ULL(63, 32) +#define DFHv1_PARAM_MSI_X_STARTV GENMASK_ULL(31, 0) + /* Next AFU Register Bitfield */ #define NEXT_AFU_NEXT_DFH_OFST GENMASK_ULL(23, 0) /* Offset to next AFU */ @@ -263,6 +267,7 @@ struct dfl_feature_irq_ctx { * * @dev: ptr to pdev of the feature device which has the sub feature. * @id: sub feature id. + * @revision: revisition of the instance of a feature. * @resource_index: each sub feature has one mmio resource for its registers. * this index is used to find its mmio resource from the * feature dev (platform device)'s resources. @@ -272,6 +277,9 @@ struct dfl_feature_irq_ctx { * @ops: ops of this sub feature. * @ddev: ptr to the dfl device of this sub feature. * @priv: priv data of this feature. + * @dfh_version: version of the DFH + * @param_size: size of dfh parameters + * @params: point to memory copy of dfh parameters */ struct dfl_feature { struct platform_device *dev; @@ -284,6 +292,9 @@ struct dfl_feature { const struct dfl_feature_ops *ops; struct dfl_device *ddev; void *priv; + u8 dfh_version; + unsigned int param_size; + void *params; }; #define FEATURE_DEV_ID_UNUSED (-1) diff --git a/include/linux/dfl.h b/include/linux/dfl.h index 431636a0dc78..0a7a00a0ee7f 100644 --- a/include/linux/dfl.h +++ b/include/linux/dfl.h @@ -27,11 +27,15 @@ enum dfl_id_type { * @id: id of the dfl device. * @type: type of DFL FIU of the device. See enum dfl_id_type. * @feature_id: feature identifier local to its DFL FIU type. + * @revision: revision of this dfl device feature. * @mmio_res: mmio resource of this dfl device. * @irqs: list of Linux IRQ numbers of this dfl device. * @num_irqs: number of IRQs supported by this dfl device. * @cdev: pointer to DFL FPGA container device this dfl device belongs to. * @id_entry: matched id entry in dfl driver's id table. + * @dfh_version: version of DFH for the device + * @param_size: size of the block parameters in bytes + * @params: pointer to block of parameters copied memory */ struct dfl_device { struct device dev; @@ -44,6 +48,9 @@ struct dfl_device { unsigned int num_irqs; struct dfl_fpga_cdev *cdev; const struct dfl_device_id *id_entry; + u8 dfh_version; + unsigned int param_size; + void *params; }; /** @@ -84,4 +91,5 @@ void dfl_driver_unregister(struct dfl_driver *dfl_drv); module_driver(__dfl_driver, dfl_driver_register, \ dfl_driver_unregister) +void *dfh_find_param(struct dfl_device *dfl_dev, int param_id, size_t *pcount); #endif /* __LINUX_DFL_H */ From patchwork Tue Jan 10 00:30:29 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Matthew Gerlach X-Patchwork-Id: 41236 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4e01:0:0:0:0:0 with SMTP id p1csp2460938wrt; Mon, 9 Jan 2023 16:30:57 -0800 (PST) X-Google-Smtp-Source: AMrXdXvTOEuRjeDBHSJ5rZpeTc+TQQ0FuGLQJwJad7NPrWAQpaxXMlDtRP1LrscAIH/F5/1ncWYr X-Received: by 2002:a05:6a20:3d16:b0:9d:efbf:48c7 with SMTP id y22-20020a056a203d1600b0009defbf48c7mr97902662pzi.11.1673310657475; Mon, 09 Jan 2023 16:30:57 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1673310657; cv=none; d=google.com; s=arc-20160816; b=E/NlGcBekkIO6zQAO5jCRtDKSgyzG1ZVfzCy8PH6Lsu/ZTA7Ug3W1tnM09QSLnLzzT VaeOUx3EDA7CA/AziF6RO90hKe039SYtZabd9ydtBuxOluFiQuqfMDz0lIjoeCBrxRkD Acmy6LMHavpTnBEGgEAx/oTQa4B0eP3lC8cl3TbK89RfCsj+76J56nmcB1e1w+3ikcoa q0SF8vo2HCV2pbQUwYqKwtrK72I1hGBpj8Q0qcZVRRZMDW9Qf4rmc246QoJV46bgTv+Z rxLuswpWarbJUVI2UKLVkRmBzOP9VFQ1eOJm6iAj7jj9qLnmeVPHVQmdf5xPN60sSv5L hQjA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=+/PeUQAl3xCVFzX7XsnILsy8tojuT1tI8+a6Wu8Jies=; b=PQTTezEpYfGX74j2KyG8AqyF2sM+wgCYlGyaXkkQPf8VdcoX/0x6KGGvq37B8v2jDU DfNyzuOLF0z8GkogwwRm7gSjeG81wM6JRAlPNG0iAzsIcW9Gx6ZEC4DxYPbV7AErBwcs WF2KZ9d/BWY0zSrKOSyggTBiI1S3eB9tr1cy+VBpc82pmntDfq02p5f4efCXkvVZiQRI rewzOb65WwHfXMJDuIipi2MZe2YHYVoGNZ/LpqBLBAXoWSYPRnm58IuN15yXpxFhILyJ wsmp7/WAWAsq1ZE8DeO6v7YgQ4Wrze8Cmi9YVaHQ/UWrWhkZw0ExESrozPwOsOQuHLuh bbYw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=i7X7MDRz; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id 126-20020a630184000000b00476fdba9e11si10020599pgb.622.2023.01.09.16.30.44; Mon, 09 Jan 2023 16:30:57 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=i7X7MDRz; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237857AbjAJAaN (ORCPT + 99 others); Mon, 9 Jan 2023 19:30:13 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59896 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237486AbjAJA35 (ORCPT ); Mon, 9 Jan 2023 19:29:57 -0500 Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1F4883F114; Mon, 9 Jan 2023 16:29:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1673310597; x=1704846597; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=N3L6uklDTD5RH/HovFT3ZTmePQvuPs1vn2oU+ecGJ/M=; b=i7X7MDRz3nXGumiUI9UoML1Z4OsrXO5Vnu7d0O29V0gIES2j66Ae680q d+/4ylyJStCDg+tLm6pDBQorEAzBiTACvDl0aWwe8O4R53bG4IjEKZoNv KLlx5zIKJ5spH7aaUyz9ONPeDqZfe8RMyTkq5t0C7fdT3kfW/TG4izdzO F9CO02uQxkT9OUH4brMbBZLqjYJ4SUIaAcO692Kayj2PQBS9HyWlmLo6c V4ZE3XVXQ+BQBCd5xbclPg7TbpBjSeoJd8TRMshaxU/s2LXZQpmsT6QSD meNRKAm9m+kVK1lxIltCUIe1KQ7m5kE6reilodjtPsucxMSLhb/ejYUAN A==; X-IronPort-AV: E=McAfee;i="6500,9779,10585"; a="324265569" X-IronPort-AV: E=Sophos;i="5.96,313,1665471600"; d="scan'208";a="324265569" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Jan 2023 16:29:53 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10585"; a="687381584" X-IronPort-AV: E=Sophos;i="5.96,313,1665471600"; d="scan'208";a="687381584" Received: from rhweight-wrk1.ra.intel.com ([137.102.106.43]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Jan 2023 16:29:53 -0800 From: matthew.gerlach@linux.intel.com To: hao.wu@intel.com, yilun.xu@intel.com, russell.h.weight@intel.com, basheer.ahmed.muddebihal@intel.com, trix@redhat.com, mdf@kernel.org, linux-fpga@vger.kernel.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, tianfei.zhang@intel.com, corbet@lwn.net, gregkh@linuxfoundation.org, linux-serial@vger.kernel.org, jirislaby@kernel.org, geert+renesas@glider.be, andriy.shevchenko@linux.intel.com, niklas.soderlund+renesas@ragnatech.se, macro@orcam.me.uk, johan@kernel.org, lukas@wunner.de, ilpo.jarvinen@linux.intel.com, marpagan@redhat.com, bagasdotme@gmail.com Cc: Matthew Gerlach Subject: [PATCH v10 4/4] tty: serial: 8250: add DFL bus driver for Altera 16550. Date: Mon, 9 Jan 2023 16:30:29 -0800 Message-Id: <20230110003029.806022-5-matthew.gerlach@linux.intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230110003029.806022-1-matthew.gerlach@linux.intel.com> References: <20230110003029.806022-1-matthew.gerlach@linux.intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.3 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, RCVD_IN_MSPIKE_H3,RCVD_IN_MSPIKE_WL,SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1754593395889692529?= X-GMAIL-MSGID: =?utf-8?q?1754593395889692529?= From: Matthew Gerlach Add a Device Feature List (DFL) bus driver for the Altera 16550 implementation of UART. Signed-off-by: Matthew Gerlach Reviewed-by: Ilpo Järvinen Reviewed-by: Andy Shevchenko --- v10: track change to dfh_find_param() v9: add Rb Andy Shevchenko move dfh_get_u64_param_vals to static version of dfh_get_u64_param_val v8: use dfh_get_u64_param_vals() v7: no change v6: move driver specific parameter definitions to limit scope v5: removed unneeded blank line removed unneeded includes included device.h and types.h removed unneeded local variable remove calls to dev_dbg memset -> { } remove space after period explicitly include used headers remove redundant Inc from Copyright fix format specifier v4: use dev_err_probe() everywhere that is appropriate clean up noise change error messages to use the word, unsupported tried again to sort Makefile and KConfig better reorder probe function for easier error handling use new dfh_find_param API v3: use passed in location of registers use cleaned up functions for parsing parameters v2: clean up error messages alphabetize header files fix 'missing prototype' error by making function static tried to sort Makefile and Kconfig better 8250 --- drivers/tty/serial/8250/8250_dfl.c | 167 +++++++++++++++++++++++++++++ drivers/tty/serial/8250/Kconfig | 12 +++ drivers/tty/serial/8250/Makefile | 1 + 3 files changed, 180 insertions(+) create mode 100644 drivers/tty/serial/8250/8250_dfl.c diff --git a/drivers/tty/serial/8250/8250_dfl.c b/drivers/tty/serial/8250/8250_dfl.c new file mode 100644 index 000000000000..1df443cab02e --- /dev/null +++ b/drivers/tty/serial/8250/8250_dfl.c @@ -0,0 +1,167 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Driver for FPGA UART + * + * Copyright (C) 2022 Intel Corporation. + * + * Authors: + * Ananda Ravuri + * Matthew Gerlach + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#define DFHv1_PARAM_ID_CLK_FRQ 0x2 +#define DFHv1_PARAM_ID_FIFO_LEN 0x3 + +#define DFHv1_PARAM_ID_REG_LAYOUT 0x4 +#define DFHv1_PARAM_REG_LAYOUT_WIDTH GENMASK_ULL(63, 32) +#define DFHv1_PARAM_REG_LAYOUT_SHIFT GENMASK_ULL(31, 0) + +struct dfl_uart { + int line; +}; + +static int dfh_get_u64_param_val(struct dfl_device *dfl_dev, int param_id, u64 *pval) +{ + size_t psize; + u64 *p; + + p = dfh_find_param(dfl_dev, param_id, &psize); + if (IS_ERR(p)) + return PTR_ERR(p); + + if (psize != sizeof(u64)) + return -EINVAL; + + *pval = *p; + + return 0; +} + +static int dfl_uart_get_params(struct dfl_device *dfl_dev, struct uart_8250_port *uart) +{ + struct device *dev = &dfl_dev->dev; + u64 fifo_len, clk_freq, reg_layout; + u32 reg_width; + int ret; + + ret = dfh_get_u64_param_val(dfl_dev, DFHv1_PARAM_ID_CLK_FRQ, &clk_freq); + if (ret) + return dev_err_probe(dev, ret, "missing CLK_FRQ param\n"); + + uart->port.uartclk = clk_freq; + + ret = dfh_get_u64_param_val(dfl_dev, DFHv1_PARAM_ID_FIFO_LEN, &fifo_len); + if (ret) + return dev_err_probe(dev, ret, "missing FIFO_LEN param\n"); + + switch (fifo_len) { + case 32: + uart->port.type = PORT_ALTR_16550_F32; + break; + + case 64: + uart->port.type = PORT_ALTR_16550_F64; + break; + + case 128: + uart->port.type = PORT_ALTR_16550_F128; + break; + + default: + return dev_err_probe(dev, -EINVAL, "unsupported FIFO_LEN %llu\n", fifo_len); + } + + ret = dfh_get_u64_param_val(dfl_dev, DFHv1_PARAM_ID_REG_LAYOUT, ®_layout); + if (ret) + return dev_err_probe(dev, ret, "missing REG_LAYOUT param\n"); + + uart->port.regshift = FIELD_GET(DFHv1_PARAM_REG_LAYOUT_SHIFT, reg_layout); + reg_width = FIELD_GET(DFHv1_PARAM_REG_LAYOUT_WIDTH, reg_layout); + switch (reg_width) { + case 4: + uart->port.iotype = UPIO_MEM32; + break; + + case 2: + uart->port.iotype = UPIO_MEM16; + break; + + default: + return dev_err_probe(dev, -EINVAL, "unsupported reg-width %u\n", reg_width); + + } + + return 0; +} + +static int dfl_uart_probe(struct dfl_device *dfl_dev) +{ + struct device *dev = &dfl_dev->dev; + struct uart_8250_port uart = { }; + struct dfl_uart *dfluart; + int ret; + + uart.port.flags = UPF_IOREMAP; + uart.port.mapbase = dfl_dev->mmio_res.start; + uart.port.mapsize = resource_size(&dfl_dev->mmio_res); + + ret = dfl_uart_get_params(dfl_dev, &uart); + if (ret < 0) + return dev_err_probe(dev, ret, "failed uart feature walk\n"); + + if (dfl_dev->num_irqs == 1) + uart.port.irq = dfl_dev->irqs[0]; + + dfluart = devm_kzalloc(dev, sizeof(*dfluart), GFP_KERNEL); + if (!dfluart) + return -ENOMEM; + + dfluart->line = serial8250_register_8250_port(&uart); + if (dfluart->line < 0) + return dev_err_probe(dev, dfluart->line, "unable to register 8250 port.\n"); + + dev_set_drvdata(dev, dfluart); + + return 0; +} + +static void dfl_uart_remove(struct dfl_device *dfl_dev) +{ + struct dfl_uart *dfluart = dev_get_drvdata(&dfl_dev->dev); + + serial8250_unregister_port(dfluart->line); +} + +#define FME_FEATURE_ID_UART 0x24 + +static const struct dfl_device_id dfl_uart_ids[] = { + { FME_ID, FME_FEATURE_ID_UART }, + { } +}; +MODULE_DEVICE_TABLE(dfl, dfl_uart_ids); + +static struct dfl_driver dfl_uart_driver = { + .drv = { + .name = "dfl-uart", + }, + .id_table = dfl_uart_ids, + .probe = dfl_uart_probe, + .remove = dfl_uart_remove, +}; +module_dfl_driver(dfl_uart_driver); + +MODULE_DESCRIPTION("DFL Intel UART driver"); +MODULE_AUTHOR("Intel Corporation"); +MODULE_LICENSE("GPL"); diff --git a/drivers/tty/serial/8250/Kconfig b/drivers/tty/serial/8250/Kconfig index b0f62345bc84..08af2acd4645 100644 --- a/drivers/tty/serial/8250/Kconfig +++ b/drivers/tty/serial/8250/Kconfig @@ -370,6 +370,18 @@ config SERIAL_8250_FSL erratum for Freescale 16550 UARTs in the 8250 driver. It also enables support for ACPI enumeration. +config SERIAL_8250_DFL + tristate "DFL bus driver for Altera 16550 UART" + depends on SERIAL_8250 && FPGA_DFL + help + This option enables support for a Device Feature List (DFL) bus + driver for the Altera 16650 UART. One or more Altera 16650 UARTs + can be instantiated in a FPGA and then be discovered during + enumeration of the DFL bus. + + To compile this driver as a module, chose M here: the + module will be called 8250_dfl. + config SERIAL_8250_DW tristate "Support for Synopsys DesignWare 8250 quirks" depends on SERIAL_8250 diff --git a/drivers/tty/serial/8250/Makefile b/drivers/tty/serial/8250/Makefile index 1615bfdde2a0..4e1a32812683 100644 --- a/drivers/tty/serial/8250/Makefile +++ b/drivers/tty/serial/8250/Makefile @@ -28,6 +28,7 @@ obj-$(CONFIG_SERIAL_8250_EXAR_ST16C554) += 8250_exar_st16c554.o obj-$(CONFIG_SERIAL_8250_HUB6) += 8250_hub6.o obj-$(CONFIG_SERIAL_8250_FSL) += 8250_fsl.o obj-$(CONFIG_SERIAL_8250_MEN_MCB) += 8250_men_mcb.o +obj-$(CONFIG_SERIAL_8250_DFL) += 8250_dfl.o obj-$(CONFIG_SERIAL_8250_DW) += 8250_dw.o obj-$(CONFIG_SERIAL_8250_EM) += 8250_em.o obj-$(CONFIG_SERIAL_8250_IOC3) += 8250_ioc3.o