From patchwork Mon Jan 9 15:35:50 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ashok Raj X-Patchwork-Id: 40942 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4e01:0:0:0:0:0 with SMTP id p1csp2224948wrt; Mon, 9 Jan 2023 07:41:20 -0800 (PST) X-Google-Smtp-Source: AMrXdXu/lOxnlCSaXdZ92x0jPKHjNqNOqHLD9Wjr00peawde8nRQoSpcI4DkxyT8AiEjfdETEYt3 X-Received: by 2002:a17:90a:8d06:b0:223:fa54:4315 with SMTP id c6-20020a17090a8d0600b00223fa544315mr67678088pjo.19.1673278879644; Mon, 09 Jan 2023 07:41:19 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1673278879; cv=none; d=google.com; s=arc-20160816; b=N/nQ2CwQhQlgvQiO8DqL5onDCba57JSuueYs11+t1ghGSVlwrp4sUN2KVy1XGmRn1h dg27qvV21g/J9pwlPkOb7F7IJoTfwvsDSdEDp7yvz6R+CoVoC7pnnOBn9dxWy/fN3nK5 C+lb86dI6Uo/lyuJLSrHIHqmUOhRyX2jpUJw7bWgTP2MYqXi7GG4dBOUSWFW42xZtaBQ VDOairRrsLhjgESu+4zRoGQnrQbVB+KA89PgpvGJltptyBOUbFrWAdwxwS5yJ06izaR8 YKbt9J0qjLNUbbEhiEQukKvBACURm+zh7/4wwNAujI+5u85FP+WRechBh/2KBA2vX73/ JFSQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=0EA+J2HjnKiU8uGmbNvM+25UyrHIozTWTbPIq/Nc1Lk=; b=pnyXbC1jYbzO97l2GrE5mJLJwfDXeurWIbmQ7T2LnkXOmwOTMfTIw2z4ccnVtBPUAL cjgDjc8j7Y4w7p8qPh1qCQgL7gkuLmcXAEg9rNgJLDUeNOmuEsymIBYxfp+vCPNqS/1p bDGcG3HimAoFOKSCt0IivO1tNaNFM4Azzig3at6dEG24y206BMml8Yo57V5coIANHLZ9 tyh2L+CebGHzqcb96HyCv4k0cqcIYIWMgI4ZMi3trgCBQt0PQ8+/saDKm8rSDj81M1Ia Zehc/PKuU4z46qTj0fYKdZbzqfWSsCbpjGSp/2gxtUaki+iSAQl5mh1UZ/irY6pJALSm THaw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=GAzmxuIv; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id mi13-20020a17090b4b4d00b0021f249ab6acsi13558699pjb.139.2023.01.09.07.41.06; Mon, 09 Jan 2023 07:41:19 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=GAzmxuIv; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229694AbjAIPkt (ORCPT + 99 others); Mon, 9 Jan 2023 10:40:49 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52832 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237256AbjAIPkQ (ORCPT ); Mon, 9 Jan 2023 10:40:16 -0500 Received: from mga06.intel.com (mga06b.intel.com [134.134.136.31]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 36F3B40849 for ; Mon, 9 Jan 2023 07:36:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1673278574; x=1704814574; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=r8x3W673a81adlsPw3G0WD1BeN7NIeYVAWdht6PQCa8=; b=GAzmxuIv3hvFSwnIKe2NT6QJVHxo9UxvpGZpbyXa/ItjsZVOeMawuzGK 10d6UHwW3aPVgzztmnxJzwoKX5R7C9hlSThBcWU2qz8AFk+2AaFkQ8l/o 6Y6gzKOeKeX1eAlxr9uY/66VeiO6y0npcHAcH4oUAgksE0YTt+I821tuJ sKqiIchzxOgp+OUP21liJXJuexB77FCGfL4ssjnEDzcawyUxDCTHMJD0s RUFMF0sDo72FnnB6V7Zo6LfYAoWPzj0sIm4qFets9dqlm7r+AHgkt8EaW Cg0SauwqrbQ1IyZeZFN6aL4czHN2py11I6yqv6Dwe4MWwMS8knszT+VsA w==; X-IronPort-AV: E=McAfee;i="6500,9779,10585"; a="385203559" X-IronPort-AV: E=Sophos;i="5.96,311,1665471600"; d="scan'208";a="385203559" Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Jan 2023 07:36:11 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10585"; a="902023878" X-IronPort-AV: E=Sophos;i="5.96,311,1665471600"; d="scan'208";a="902023878" Received: from araj-ucode.jf.intel.com ([10.23.0.19]) by fmsmga006-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Jan 2023 07:36:11 -0800 From: Ashok Raj To: Borislav Petkov , Thomas Gleixner Cc: X86-kernel , LKML Mailing List , Ashok Raj , Dave Hansen , Tony Luck , Ingo Molnar , alison.schofield@intel.com, reinette.chatre@intel.com, Tom Lendacky Subject: [PATCH v4 1/6] x86/microcode: Add a parameter to microcode_check() to store CPU capabilities Date: Mon, 9 Jan 2023 07:35:50 -0800 Message-Id: <20230109153555.4986-2-ashok.raj@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230109153555.4986-1-ashok.raj@intel.com> References: <20230109153555.4986-1-ashok.raj@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1754560074339055975?= X-GMAIL-MSGID: =?utf-8?q?1754560074339055975?= Add a parameter to store CPU capabilities before performing a microcode update so that the code later can compare CPU capabilities before and after performing the update. Signed-off-by: Ashok Raj Cc: LKML Cc: x86 Cc: Tony Luck Cc: Dave Hansen Cc: Alison Schofield Cc: Reinette Chatre Cc: Thomas Gleixner Cc: Tom Lendacky Cc: Ingo Molnar --- Changes since V3 Boris: - Fix commit log to drop "next patch". - Add documentation to new parameter to microcode_check() --- arch/x86/include/asm/processor.h | 2 +- arch/x86/kernel/cpu/common.c | 21 +++++++++++++-------- arch/x86/kernel/cpu/microcode/core.c | 3 ++- 3 files changed, 16 insertions(+), 10 deletions(-) diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/processor.h index 4e35c66edeb7..f256a4ddd25d 100644 --- a/arch/x86/include/asm/processor.h +++ b/arch/x86/include/asm/processor.h @@ -697,7 +697,7 @@ bool xen_set_default_idle(void); #endif void __noreturn stop_this_cpu(void *dummy); -void microcode_check(void); +void microcode_check(struct cpuinfo_x86 *prev_info); enum l1tf_mitigations { L1TF_MITIGATION_OFF, diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c index 9cfca3d7d0e2..0f5a173d0871 100644 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -2297,30 +2297,35 @@ void cpu_init_secondary(void) #endif #ifdef CONFIG_MICROCODE_LATE_LOADING -/* +/** + * microcode_check() - Check if any CPU capabilities changed after an update. + * @prev_info: CPU capabilities stored before an update. + * * The microcode loader calls this upon late microcode load to recheck features, * only when microcode has been updated. Caller holds microcode_mutex and CPU * hotplug lock. + * + * Return: None */ -void microcode_check(void) +void microcode_check(struct cpuinfo_x86 *prev_info) { - struct cpuinfo_x86 info; - perf_check_microcode(); /* Reload CPUID max function as it might've changed. */ - info.cpuid_level = cpuid_eax(0); + prev_info->cpuid_level = cpuid_eax(0); /* * Copy all capability leafs to pick up the synthetic ones so that * memcmp() below doesn't fail on that. The ones coming from CPUID will * get overwritten in get_cpu_cap(). */ - memcpy(&info.x86_capability, &boot_cpu_data.x86_capability, sizeof(info.x86_capability)); + memcpy(&prev_info->x86_capability, &boot_cpu_data.x86_capability, + sizeof(prev_info->x86_capability)); - get_cpu_cap(&info); + get_cpu_cap(prev_info); - if (!memcmp(&info.x86_capability, &boot_cpu_data.x86_capability, sizeof(info.x86_capability))) + if (!memcmp(&prev_info->x86_capability, &boot_cpu_data.x86_capability, + sizeof(prev_info->x86_capability))) return; pr_warn("x86/CPU: CPU features have changed after loading microcode, but might not take effect.\n"); diff --git a/arch/x86/kernel/cpu/microcode/core.c b/arch/x86/kernel/cpu/microcode/core.c index c4cd7328177b..e39d83be794b 100644 --- a/arch/x86/kernel/cpu/microcode/core.c +++ b/arch/x86/kernel/cpu/microcode/core.c @@ -439,6 +439,7 @@ static int __reload_late(void *info) static int microcode_reload_late(void) { int old = boot_cpu_data.microcode, ret; + struct cpuinfo_x86 prev_info; pr_err("Attempting late microcode loading - it is dangerous and taints the kernel.\n"); pr_err("You should switch to early loading, if possible.\n"); @@ -448,7 +449,7 @@ static int microcode_reload_late(void) ret = stop_machine_cpuslocked(__reload_late, NULL, cpu_online_mask); if (ret == 0) - microcode_check(); + microcode_check(&prev_info); pr_info("Reload completed, microcode revision: 0x%x -> 0x%x\n", old, boot_cpu_data.microcode); From patchwork Mon Jan 9 15:35:51 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ashok Raj X-Patchwork-Id: 40944 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4e01:0:0:0:0:0 with SMTP id p1csp2225037wrt; Mon, 9 Jan 2023 07:41:30 -0800 (PST) X-Google-Smtp-Source: AMrXdXv9wsBUUby+CUaF/d5WPAU77BMPeBZKRvuN5kKtQkv43psB8FjkoqE9u+vSeviGurDV9/JQ X-Received: by 2002:a05:6a21:8697:b0:ad:5747:9f6e with SMTP id ox23-20020a056a21869700b000ad57479f6emr66131427pzb.39.1673278890615; Mon, 09 Jan 2023 07:41:30 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1673278890; cv=none; d=google.com; s=arc-20160816; b=VfOPqhlPbnHdm7OYhK0qoLftDjRwPzfoodWaVN83oXQIHvcRKhM0bgffUcNRNgzExd tjcImKYeLrI1kcPwCzjBdg+zD4kjRckOlJ8ciuonIDeS7yUyFVKwpP647LT++IQlf6cE xwNbpo19r3niQIqOGcBySQFe966Sc9IvE4+1RC4Ekfy4ULPOBS8nzfqNeL7snfY7GpTx 186iMjncm1uRsvaf7sl2t+Bxj4t3BKzrxmDBt1DMUWnPE+uMRe49LvmtubVIgBZWLcZs SPOreZrPet4TvizOZ3hBY3Dosk7OwPyB9lLE/e7vuv0ncmXYiOG1dr7KTIL3vbvYDa44 Yowg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=gDHPfv9C4Hq8is0ZVpQUFlbI7XWT2nT7BBsjkp9+NM8=; b=ybfn6PjkzmNFZO29PXUOr1Z4p+3zjv72e9NJHHDVYn0bX/tiG54mcTafEaE3+y31Ns TE+jtSxotn1aosPz0V02ImiVV0cvGS4wfzZWolJSPWZxJYjMQ+VOKNNgSodNWbTHWkfb VpeuKwAc4KGcrpF0nS2fYxYgOI7o3/+Lyj7lsApOz/ykUE6mOIkzZwv0NhAHCbloudq3 MFiwVS5oKiULwztNAiJyROYlvRIPI95nk2wOHGcqBJMYTwfQewsNUY2A1+5Yn9IxdxuM oijk+xZTsgY+yCVU+2EITtxLNsNHyvklAPnNhTS2Laqy6fA3+NHGXekXkurs1UKLbkgc LPqA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=JEUZr6MU; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id b11-20020a63d30b000000b0047875582864si10149135pgg.263.2023.01.09.07.41.18; Mon, 09 Jan 2023 07:41:30 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=JEUZr6MU; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234334AbjAIPlB (ORCPT + 99 others); Mon, 9 Jan 2023 10:41:01 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52848 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237270AbjAIPkS (ORCPT ); Mon, 9 Jan 2023 10:40:18 -0500 Received: from mga06.intel.com (mga06b.intel.com [134.134.136.31]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 52B7B40C0D for ; Mon, 9 Jan 2023 07:36:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1673278578; x=1704814578; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=5jjcFZaBdHqUBN/poJjyv4ZtShGVhA9wItTWkhuMVPg=; b=JEUZr6MUNmAxK8oOIna6QQmldrSjXw2Sxa1P5JjnlrySOaIUaFajcHNB hGD+QTmgWt2hxT1bPZRx6MQM4dXZ0vk5NwneJmdWv/Nt5gX52qH9s/abT AvgCRPeoN4ZftCUGW2BuSJAL/G6EL9WXW8/Pwb2FPA5dfZE9LME7O2DUf qjImo6vX46w5T3MsIIrnime65mYcIEFBdQBe4ZNTzMCCQjIviVi03aVhv y58v5264qDQRqFLVpGqaqqH13qkf8/TNZUOOOt5Y0j0MyzjxjnJUBOEjn r68SicYjWtROD62bG2N9im6gM/siliszh7l+JYug997pazefl+Npp5gKd w==; X-IronPort-AV: E=McAfee;i="6500,9779,10585"; a="385203565" X-IronPort-AV: E=Sophos;i="5.96,311,1665471600"; d="scan'208";a="385203565" Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Jan 2023 07:36:12 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10585"; a="902023883" X-IronPort-AV: E=Sophos;i="5.96,311,1665471600"; d="scan'208";a="902023883" Received: from araj-ucode.jf.intel.com ([10.23.0.19]) by fmsmga006-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Jan 2023 07:36:11 -0800 From: Ashok Raj To: Borislav Petkov , Thomas Gleixner Cc: X86-kernel , LKML Mailing List , Ashok Raj , Dave Hansen , Tony Luck , Ingo Molnar , alison.schofield@intel.com, reinette.chatre@intel.com, Tom Lendacky Subject: [PATCH v4 2/6] x86/microcode/core: Take a snapshot before and after applying microcode Date: Mon, 9 Jan 2023 07:35:51 -0800 Message-Id: <20230109153555.4986-3-ashok.raj@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230109153555.4986-1-ashok.raj@intel.com> References: <20230109153555.4986-1-ashok.raj@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1754560085917721791?= X-GMAIL-MSGID: =?utf-8?q?1754560085917721791?= The kernel caches features about each CPU's features at boot in an x86_capability[] structure. The microcode update takes one snapshot and compares it with the saved copy at boot. However, the capabilities in the boot copy can be turned off as a result of certain command line parameters or configuration restrictions. This can cause a mismatch when comparing the values before and after the microcode update. microcode_check() is called after an update to report any previously cached CPUID bits might have changed due to the update. store_cpu_caps() basically stores the original CPU reported values and not the OS modified values. This will avoid giving a false warning even when no capabilities have changed. Ignore the capabilities recorded at boot. Take a new snapshot before the update and compare with a snapshot after the update to eliminate the false warning. Signed-off-by: Ashok Raj Fixes: 1008c52c09dc ("x86/CPU: Add a microcode loader callback") Cc: LKML Cc: x86 Cc: Tony Luck Cc: Dave Hansen Cc: Alison Schofield Cc: Reinette Chatre Cc: Thomas Gleixner Cc: Tom Lendacky Cc: Ingo Molnar --- Changes since V3: - Boris - Change function from microcode_store_cpu_caps -> store_cpu_caps - Split comments in store_cpu_caps(). - Dave Hansen - Change parameters names to something meaninful. - Cleaned up some commit log. Changes since V2: - Boris - Keep microcode_check() inside cpu/common.c and not bleed get_cpu_caps() outside of core code. - Thomas - Commit log changes. --- arch/x86/include/asm/processor.h | 1 + arch/x86/kernel/cpu/common.c | 39 ++++++++++++++++++++-------- arch/x86/kernel/cpu/microcode/core.c | 7 +++++ 3 files changed, 36 insertions(+), 11 deletions(-) diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/processor.h index f256a4ddd25d..a77dee6a2bf2 100644 --- a/arch/x86/include/asm/processor.h +++ b/arch/x86/include/asm/processor.h @@ -698,6 +698,7 @@ bool xen_set_default_idle(void); void __noreturn stop_this_cpu(void *dummy); void microcode_check(struct cpuinfo_x86 *prev_info); +void store_cpu_caps(struct cpuinfo_x86 *info); enum l1tf_mitigations { L1TF_MITIGATION_OFF, diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c index 0f5a173d0871..f5c6feed6c26 100644 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -2297,6 +2297,29 @@ void cpu_init_secondary(void) #endif #ifdef CONFIG_MICROCODE_LATE_LOADING +/** + * store_cpu_caps() - Store a snapshot of CPU capabilities + * + * Returns: None + */ +void store_cpu_caps(struct cpuinfo_x86 *curr_info) +{ + /* Reload CPUID max function as it might've changed. */ + curr_info->cpuid_level = cpuid_eax(0); + + /* + * Copy all capability leafs to pick up the synthetic ones + */ + memcpy(&curr_info->x86_capability, &boot_cpu_data.x86_capability, + sizeof(curr_info->x86_capability)); + + /* + * Capabilities copied from BSP will get overwritten + * with the snapshot below + */ + get_cpu_cap(curr_info); +} + /** * microcode_check() - Check if any CPU capabilities changed after an update. * @prev_info: CPU capabilities stored before an update. @@ -2309,22 +2332,16 @@ void cpu_init_secondary(void) */ void microcode_check(struct cpuinfo_x86 *prev_info) { - perf_check_microcode(); + struct cpuinfo_x86 curr_info; - /* Reload CPUID max function as it might've changed. */ - prev_info->cpuid_level = cpuid_eax(0); + perf_check_microcode(); /* - * Copy all capability leafs to pick up the synthetic ones so that - * memcmp() below doesn't fail on that. The ones coming from CPUID will - * get overwritten in get_cpu_cap(). + * Get a snapshot of CPU capabilities */ - memcpy(&prev_info->x86_capability, &boot_cpu_data.x86_capability, - sizeof(prev_info->x86_capability)); - - get_cpu_cap(prev_info); + store_cpu_caps(&curr_info); - if (!memcmp(&prev_info->x86_capability, &boot_cpu_data.x86_capability, + if (!memcmp(&prev_info->x86_capability, &curr_info.x86_capability, sizeof(prev_info->x86_capability))) return; diff --git a/arch/x86/kernel/cpu/microcode/core.c b/arch/x86/kernel/cpu/microcode/core.c index e39d83be794b..bb943a91a364 100644 --- a/arch/x86/kernel/cpu/microcode/core.c +++ b/arch/x86/kernel/cpu/microcode/core.c @@ -447,6 +447,13 @@ static int microcode_reload_late(void) atomic_set(&late_cpus_in, 0); atomic_set(&late_cpus_out, 0); + /* + * Take a snapshot before the microcode update, so we can compare + * them after the update is successful to check for any bits + * changed. + */ + store_cpu_caps(&prev_info); + ret = stop_machine_cpuslocked(__reload_late, NULL, cpu_online_mask); if (ret == 0) microcode_check(&prev_info); From patchwork Mon Jan 9 15:35:52 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ashok Raj X-Patchwork-Id: 40943 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4e01:0:0:0:0:0 with SMTP id p1csp2225017wrt; Mon, 9 Jan 2023 07:41:27 -0800 (PST) X-Google-Smtp-Source: AMrXdXuKM8SMWr9dUu7Rc45A3+/+DQRKibzWlM4ThcnP2tZiAEZbCB71t41G7Ob/SQCg1dj6IWil X-Received: by 2002:a17:902:aa8a:b0:192:c930:a7e2 with SMTP id d10-20020a170902aa8a00b00192c930a7e2mr27577109plr.58.1673278887352; Mon, 09 Jan 2023 07:41:27 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1673278887; cv=none; d=google.com; s=arc-20160816; b=atl1EES/aP5woMlp2Le4UNaYMNCmt1Ujp/54wlIVZRJijWqM0a/iPh6WfPP2kIJGH8 LT5Fjx5PrwNAFDGj9aQ+783QxbBCjHjxMV9q1lXp/9PChX+y2GO5zcGXCjR/PmgTHljY wgg+IsF7pU5CELX5WB0++CyOlP+wCWCrpoiQjedrqXxHl5IL3M/3vm2Rh8jQYEBWAaZM Swnypv5ghnX84quNC/85dO8+nYW+9GWRVb0BElmjSyBYPJAO3ySvDHpYuDvxxCj+T3AA j/hQ6vY+6SIWgXyI996eZroYYf7T52Xrfv1/V9YibRSeTYL5tY3MxA7JDDexqL81f2Ts a75Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=7UNbK+NX3DwWo5J2hrd53CGurLTbOCxT1BXmgNzjyNw=; b=uoz2vbuMegFxMUd3M6VpEihZrQVayTsD73fBAJw9MrhB33R2g54T5qPxsFmTCfJLGn wqiPf1QUj9O9asKCyq0dC3LAIUSBYJ7XCU4F8pzUR9pKEwMK6ws42tkTv1ZQ9lLWD1DO k3+BoiIBElxT5na8+94uyuZxsDMNeW6IQFI0h6ZruUKU5fTjLFWpv7N2cSDLPMMuZH7p Mq8foKeXi+XblnCBjgufduIJkMB4RW4FH4fnhlDE8j8Y5ErZ0YV9Ja4l+N2pIf+5Df4K vwXfOrk6hDcRzCFcBtithu/JR4F2IihuuP5sh2/1cuM1OQwF5J5+1/ZF8nLkcDLNqqiv hKug== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=D7g61m+3; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id o11-20020a170902778b00b0017123d2abd5si9103785pll.457.2023.01.09.07.41.14; Mon, 09 Jan 2023 07:41:27 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=D7g61m+3; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233336AbjAIPkx (ORCPT + 99 others); Mon, 9 Jan 2023 10:40:53 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52838 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237264AbjAIPkR (ORCPT ); Mon, 9 Jan 2023 10:40:17 -0500 Received: from mga06.intel.com (mga06b.intel.com [134.134.136.31]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5255B40C0C for ; Mon, 9 Jan 2023 07:36:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1673278578; x=1704814578; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=z6CTujcMHROo8G6A9RLI+GRnUF8GPfe/fb1oxgWV3u0=; b=D7g61m+3ySQMlN4ebKkALhQ0JGlZQTWtQvRq8tC8tav/u4oMCrqui+ki mdeSa1leYgTZwcAz0sbjL3blVz+IyvTaoedqDYcgb5VbIX3xSJF7K7H5x eQTQaz/8okWR4VfdNXBP7zPjIpOgRRGRhC/kGV+m+a3EsVp16NgcgtYpz 7gLfQWeHlBAL+PUcu1ghYD+S4u61sdfP2VGevRIHIOGty8tyvS1FMG98Y XOZ0cB4ohebjB3jlHdHxkRMM6pzSXqSGm5PKQ1UQ7dOBxnpBLWL0pm9LS 7mFENRjgNQMz2NvpNKacVrdRSRibph1G5iBLHTb23/6iCLtD+CRqrRB8U A==; X-IronPort-AV: E=McAfee;i="6500,9779,10585"; a="385203571" X-IronPort-AV: E=Sophos;i="5.96,311,1665471600"; d="scan'208";a="385203571" Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Jan 2023 07:36:12 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10585"; a="902023886" X-IronPort-AV: E=Sophos;i="5.96,311,1665471600"; d="scan'208";a="902023886" Received: from araj-ucode.jf.intel.com ([10.23.0.19]) by fmsmga006-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Jan 2023 07:36:12 -0800 From: Ashok Raj To: Borislav Petkov , Thomas Gleixner Cc: X86-kernel , LKML Mailing List , Ashok Raj , Dave Hansen , Tony Luck , Ingo Molnar , alison.schofield@intel.com, reinette.chatre@intel.com, Tom Lendacky Subject: [PATCH v4 3/6] x86/microcode: Display revisions only when update is successful Date: Mon, 9 Jan 2023 07:35:52 -0800 Message-Id: <20230109153555.4986-4-ashok.raj@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230109153555.4986-1-ashok.raj@intel.com> References: <20230109153555.4986-1-ashok.raj@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1754560082625442598?= X-GMAIL-MSGID: =?utf-8?q?1754560082625442598?= Right now, microcode loading failures and successes print the same message "Reloading completed". This is misleading to users. Display the updated revision number only if an update was successful. Display "Reload completed" only if the update was successful, otherwise report the update failed. Signed-off-by: Ashok Raj Fixes: 9bd681251b7c ("x86/microcode: Announce reload operation's completion") Suggested-by: Thomas Gleixner Reviewed-by: Tony Luck Link: https://lore.kernel.org/lkml/874judpqqd.ffs@tglx/ Cc: LKML Cc: x86 Cc: Tony Luck Cc: Dave Hansen Cc: Alison Schofield Cc: Reinette Chatre Cc: Thomas Gleixner Cc: Tom Lendacky Cc: Ingo Molnar --- Changes since V3: Tony, Ingo - Print clear message if the update was successful or not. --- arch/x86/kernel/cpu/microcode/core.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/arch/x86/kernel/cpu/microcode/core.c b/arch/x86/kernel/cpu/microcode/core.c index bb943a91a364..d7cbc83df9b6 100644 --- a/arch/x86/kernel/cpu/microcode/core.c +++ b/arch/x86/kernel/cpu/microcode/core.c @@ -455,11 +455,15 @@ static int microcode_reload_late(void) store_cpu_caps(&prev_info); ret = stop_machine_cpuslocked(__reload_late, NULL, cpu_online_mask); - if (ret == 0) - microcode_check(&prev_info); - pr_info("Reload completed, microcode revision: 0x%x -> 0x%x\n", - old, boot_cpu_data.microcode); + if (ret == 0) { + pr_info("Reload completed, microcode revision: 0x%x -> 0x%x\n", + old, boot_cpu_data.microcode); + microcode_check(&prev_info); + } else { + pr_info("Reload failed, current microcode revision: 0x%x\n", + boot_cpu_data.microcode); + } return ret; } From patchwork Mon Jan 9 15:35:53 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ashok Raj X-Patchwork-Id: 40945 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4e01:0:0:0:0:0 with SMTP id p1csp2227475wrt; Mon, 9 Jan 2023 07:46:31 -0800 (PST) X-Google-Smtp-Source: AMrXdXsYiQxNcf8cgYqXMm+rWLRuFHPmPcABHZmSrsq/ez2iIXgjHL3Wj8LSKPpwHGdQbAinle59 X-Received: by 2002:a05:6a20:1455:b0:af:730d:204a with SMTP id a21-20020a056a20145500b000af730d204amr88625980pzi.8.1673279190862; Mon, 09 Jan 2023 07:46:30 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1673279190; cv=none; d=google.com; s=arc-20160816; b=dWV7gv7PxTHJP5WVpLuy2q9UX9Ur6RX/Y4hz5SjLVMkbo7J/lY1JKvoSxIROcOSAHE yUr6XnQGMEDAlwuDuvBpZ9p7cfaN4+epbmCRv7nK3IjD0IlMuJuaNUmNNMy1A/7vBrve /V4M9tPUcjUB8YygQzPQWpMXdmrmztGubVpjN01TRQLG6Q3zNUXp+asApCFRJ7eTLTCX NFEZ45RSwus/xrJKhWmi/6cu0/FcChJ17eyb4AQULevC1YSexwZ9OGWyHkC2MCmOYM3o xO8BLL+Z127W8Y9HofxOlIlLTtqV163DIzKGp7vY1LEEOaT805XXkS4IpH3za3jw/65W XJfw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=Ra0ZaVmG0Wyj0ekifRhvCmyW/jBQvzdl1nEyulH6RAU=; b=bcE4j4hzGlvhYmhy+Lea1EHTnP19GW7cnkIxZdYJaSYaJexwBGYZA4FgDxTHsix8P7 KeFDacRjS5PCVFxGZ82ZcGvnymaLPn0w3T5m+H3cR3/lGXayfvGVGeAaeuGlyRZubAj5 8He18b22zdh47QY7xtOIMRjdzo89aAatyrLu6QZT6y6oAe3AFkEZTkei6vlE9AgPdBnR 5IcJYFjrhedBzynX955Ox5rooNFKrJQsWjlS7q6R5kOD09y/jJhXZvOE/w1wJaetaZl5 uBBjZFzlGmIDPpaOD5F0uhDmKP4OjfKpn3SKJto/WagnSrmyWygIOTrVpj3MisYXicjR VGjw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=UklwSdFW; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id j72-20020a638b4b000000b004b2f01f4c46si4127066pge.27.2023.01.09.07.46.11; Mon, 09 Jan 2023 07:46:30 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=UklwSdFW; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235031AbjAIPlF (ORCPT + 99 others); Mon, 9 Jan 2023 10:41:05 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52858 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237273AbjAIPkS (ORCPT ); Mon, 9 Jan 2023 10:40:18 -0500 Received: from mga06.intel.com (mga06b.intel.com [134.134.136.31]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DCF0C40C18 for ; Mon, 9 Jan 2023 07:36:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1673278578; x=1704814578; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=oyjz6XJwnWS6TtsCd6s9DEyvm+PHR2WDUT1F7iZ6FqM=; b=UklwSdFWE8e8lGt6XHSRo/YZ6RGdRgVP8qLKeqzDv7hkfP+eIeDdUNSe 1dHe04NLldtZIaqfs8VPpxlaPx9xzSX9ZcDi+21dRCZVm0ck3SuXLTy69 kKr5bidWpgN4ZrVNJWobHHUOEmuPy3I89lHEGLMV58D+bjvmj/5lpZ5Yx PTivUlxuWhhF8/ojcSgeQCNwcsrxhxpXNoZCyYIpjADPwEpKxC96pS2U+ h2T88zv/UEZ6l+jjDlcD09xhvVKaa+RVqxFVHRuWMPgbZQqxWyrRX9rT/ +rEyUx4epiC9grBQUawj5g8YfYAM3Olu1lw/Y7ScwkCtkYr6RKvtZuvgv A==; X-IronPort-AV: E=McAfee;i="6500,9779,10585"; a="385203578" X-IronPort-AV: E=Sophos;i="5.96,311,1665471600"; d="scan'208";a="385203578" Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Jan 2023 07:36:13 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10585"; a="902023890" X-IronPort-AV: E=Sophos;i="5.96,311,1665471600"; d="scan'208";a="902023890" Received: from araj-ucode.jf.intel.com ([10.23.0.19]) by fmsmga006-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Jan 2023 07:36:12 -0800 From: Ashok Raj To: Borislav Petkov , Thomas Gleixner Cc: X86-kernel , LKML Mailing List , Ashok Raj , Dave Hansen , Tony Luck , Ingo Molnar , alison.schofield@intel.com, reinette.chatre@intel.com, Tom Lendacky Subject: [PATCH v4 4/6] x86/microcode/intel: Use a plain revision argument for print_ucode_rev() Date: Mon, 9 Jan 2023 07:35:53 -0800 Message-Id: <20230109153555.4986-5-ashok.raj@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230109153555.4986-1-ashok.raj@intel.com> References: <20230109153555.4986-1-ashok.raj@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1754560400502878157?= X-GMAIL-MSGID: =?utf-8?q?1754560400502878157?= print_ucode_rev() takes a struct ucode_cpu_info argument. The sole purpose of it is to print the microcode revision. The only available ucode_cpu_info always describes the currently loaded microcode revision. After a microcode update is successful, this is the new revision, or on failure it is the original revision. Subsequent changes need to print both the original and new revision, but the original version will be cached in a plain integer, which makes the code inconsistent. Replace the struct ucode_cpu_info argument with a plain integer which contains the revision number and adjust the call sites accordingly. No functional change. Signed-off-by: Ashok Raj Reviewed-by: Thomas Gleixner Cc: LKML Cc: x86 Cc: Tony Luck Cc: Dave Hansen Cc: Alison Schofield Cc: Reinette Chatre Cc: Thomas Gleixner Cc: Tom Lendacky Cc: Ingo Molnar --- Changes since V1: Thomas: - Updated commit log as suggested - Remove the line break after static void before print_ucode_info --- arch/x86/kernel/cpu/microcode/intel.c | 31 ++++++++------------------- 1 file changed, 9 insertions(+), 22 deletions(-) diff --git a/arch/x86/kernel/cpu/microcode/intel.c b/arch/x86/kernel/cpu/microcode/intel.c index 6bebc46ad8b1..1d709b72cfd0 100644 --- a/arch/x86/kernel/cpu/microcode/intel.c +++ b/arch/x86/kernel/cpu/microcode/intel.c @@ -310,13 +310,10 @@ static bool load_builtin_intel_microcode(struct cpio_data *cp) /* * Print ucode update info. */ -static void -print_ucode_info(struct ucode_cpu_info *uci, unsigned int date) +static void print_ucode_info(unsigned int new_rev, unsigned int date) { pr_info_once("microcode updated early to revision 0x%x, date = %04x-%02x-%02x\n", - uci->cpu_sig.rev, - date & 0xffff, - date >> 24, + new_rev, date & 0xffff, date >> 24, (date >> 16) & 0xff); } @@ -334,7 +331,7 @@ void show_ucode_info_early(void) if (delay_ucode_info) { intel_cpu_collect_info(&uci); - print_ucode_info(&uci, current_mc_date); + print_ucode_info(uci.cpu_sig.rev. current_mc_date); delay_ucode_info = 0; } } @@ -343,33 +340,23 @@ void show_ucode_info_early(void) * At this point, we can not call printk() yet. Delay printing microcode info in * show_ucode_info_early() until printk() works. */ -static void print_ucode(struct ucode_cpu_info *uci) +static void print_ucode(int new_rev, int date) { struct microcode_intel *mc; int *delay_ucode_info_p; int *current_mc_date_p; - mc = uci->mc; - if (!mc) - return; - delay_ucode_info_p = (int *)__pa_nodebug(&delay_ucode_info); current_mc_date_p = (int *)__pa_nodebug(¤t_mc_date); *delay_ucode_info_p = 1; - *current_mc_date_p = mc->hdr.date; + *current_mc_date_p = date; } #else -static inline void print_ucode(struct ucode_cpu_info *uci) +static inline void print_ucode(int new_rev, int date) { - struct microcode_intel *mc; - - mc = uci->mc; - if (!mc) - return; - - print_ucode_info(uci, mc->hdr.date); + print_ucode_info(new_rev, date); } #endif @@ -409,9 +396,9 @@ static int apply_microcode_early(struct ucode_cpu_info *uci, bool early) uci->cpu_sig.rev = rev; if (early) - print_ucode(uci); + print_ucode(uci->cpu_sig.rev, mc->hdr.date); else - print_ucode_info(uci, mc->hdr.date); + print_ucode_info(uci->cpu_sig.rev, mc->hdr.date); return 0; } From patchwork Mon Jan 9 15:35:54 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ashok Raj X-Patchwork-Id: 40946 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4e01:0:0:0:0:0 with SMTP id p1csp2228267wrt; Mon, 9 Jan 2023 07:48:11 -0800 (PST) X-Google-Smtp-Source: AMrXdXsBDspxSGsaA0fn42jrxTCxz9kfnlfjUsXUO+TW34CtscfEEuElORCSBoP1fSJIW9t6gr35 X-Received: by 2002:a05:6402:3784:b0:46b:eadf:8d34 with SMTP id et4-20020a056402378400b0046beadf8d34mr53872366edb.7.1673279291338; Mon, 09 Jan 2023 07:48:11 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1673279291; cv=none; d=google.com; s=arc-20160816; b=Ueiq8+iRvGM8GHaGc+DSw2ZgweCzNSFBQrYGMr2tD7DjaM20WuRAYjaLEOQbBinBqE f5Pw+w3nduYoE1z1yGOTwXuR2dw+oCSLexYaxt3jHT8YdXOQnEUf06KLt0TtNXk93ADi Cf3nFJDCgOtR/wxNuamhMzw59cn1rAG9Dk8jl8wBYjrkdlORyJNFo6t4gqSJRSlbCkNV HnWpKPMS/brQLFAZinbCwTZlvGyD+ftqqJ6LWTuXWuexFf2pZBB1U2BtJI9aInCvvFcL 73h/aYddE9kZJMV3d/yd6CLJ1XnvBRrl3vCYd4a6DFN2sv3vU+Lut2+s/lN6AqbuszjI IyAA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=wEiwU9Wnk/Vk4JOxRHWZTXVKixaAtPtNoIC1UcELYHk=; b=m2JTw7tpfpG01UkLesJXbE9gknU3iq1FetNZe/lq+QiMoIzbnMRQ6TUcPh/fZfkDeA AQCoGDNxHKzlb7PlECC95SqPFBGrhsgyg33fzo5gqDOjugg/B7wFDENI3F7V8QIOtR4Y aIQGjzmJEJf21UVzVrtiDOauvzwyPx65uVqNn8oPxypGxecDXWztSXYMS+c99cU4Dt0l C0rqH7u0qdMjioWh6IoGgrKyRSsE0ELAseBbMFmiT1sQZ1OY2UefePTBuS1YJAUUKRJZ exJCFjgXNGyabLQ9rupMDnnh+vnLZwsVx3mf1QpXXPhVN7O3WrVNWUbxEP4n3gyX7PUj YYew== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=i82XtK2o; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id s4-20020a17090699c400b007c16e4d5e9esi10103984ejn.412.2023.01.09.07.47.47; Mon, 09 Jan 2023 07:48:11 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=i82XtK2o; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234538AbjAIPlK (ORCPT + 99 others); Mon, 9 Jan 2023 10:41:10 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52026 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234001AbjAIPkS (ORCPT ); Mon, 9 Jan 2023 10:40:18 -0500 Received: from mga06.intel.com (mga06b.intel.com [134.134.136.31]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 32F3E40C00 for ; Mon, 9 Jan 2023 07:36:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1673278579; x=1704814579; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=xdjl9pGXxNvh2LhHThzo3G8n2sH1qvrqMnZU/btrLb0=; b=i82XtK2o/0GM5i1XNjEqUYQhRuKzn+PP5xyI8y5vYIQeb06KtbsJE0Hq +gmplA3IT9L55O+pDWuXdHqLCuCr4fTuSYuCrlHLi+cPwjhbJIhwWUhpF 7ISmD+PJ87uLsK8E2CHgOCQ1kA87Ix7UdVPsR8Yezpgl+0KTQyFxGvF/V 4fTYxI8L3CF0a1p9BQeTLXeh1AzulZ3GqW5aVHwnQBnFcRC7wmUl1cOEQ e1X/2W+MrGdSF1FgxqsbNgWPP0ql1gVL3WnJwSdCgBwWd64hfMLYoLivU BLCeSJrFh6Y4oM0jFIhJ+3nWS7IDIs9OaCl0KjAlMRmes7o0WTzyY7mhj Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10585"; a="385203585" X-IronPort-AV: E=Sophos;i="5.96,311,1665471600"; d="scan'208";a="385203585" Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Jan 2023 07:36:13 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10585"; a="902023893" X-IronPort-AV: E=Sophos;i="5.96,311,1665471600"; d="scan'208";a="902023893" Received: from araj-ucode.jf.intel.com ([10.23.0.19]) by fmsmga006-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Jan 2023 07:36:13 -0800 From: Ashok Raj To: Borislav Petkov , Thomas Gleixner Cc: X86-kernel , LKML Mailing List , Ashok Raj , Dave Hansen , Tony Luck , Ingo Molnar , alison.schofield@intel.com, reinette.chatre@intel.com, Tom Lendacky Subject: [PATCH v4 5/6] x86/microcode/intel: Print old and new rev during early boot Date: Mon, 9 Jan 2023 07:35:54 -0800 Message-Id: <20230109153555.4986-6-ashok.raj@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230109153555.4986-1-ashok.raj@intel.com> References: <20230109153555.4986-1-ashok.raj@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1754560506095470404?= X-GMAIL-MSGID: =?utf-8?q?1754560506095470404?= Make early loading message to match late loading messages. Print both old and new revisions. This is helpful to know what the BIOS loaded revision is before an early update. New dmesg log is shown below. microcode: early update: 0x2b000041 -> 0x2b000070 date = 2000-01-01 Cache the early BIOS revision before the microcode update and change the print_ucode_info() so it prints both the old and new revision in the same format as microcode_reload_late(). Signed-off-by: Ashok Raj Reviewed-by: Thomas Gleixner Cc: LKML Cc: x86 Cc: Tony Luck Cc: Dave Hansen Cc: Alison Schofield Cc: Reinette Chatre Cc: Thomas Gleixner Cc: Tom Lendacky Cc: Ingo Molnar --- Updates since V1: Thomas: Commit log updates as suggested. --- arch/x86/kernel/cpu/microcode/intel.c | 25 +++++++++++++++---------- 1 file changed, 15 insertions(+), 10 deletions(-) diff --git a/arch/x86/kernel/cpu/microcode/intel.c b/arch/x86/kernel/cpu/microcode/intel.c index 1d709b72cfd0..f24300830ed7 100644 --- a/arch/x86/kernel/cpu/microcode/intel.c +++ b/arch/x86/kernel/cpu/microcode/intel.c @@ -310,10 +310,10 @@ static bool load_builtin_intel_microcode(struct cpio_data *cp) /* * Print ucode update info. */ -static void print_ucode_info(unsigned int new_rev, unsigned int date) +static void print_ucode_info(int old_rev, int new_rev, unsigned int date) { - pr_info_once("microcode updated early to revision 0x%x, date = %04x-%02x-%02x\n", - new_rev, date & 0xffff, date >> 24, + pr_info_once("early update: 0x%x -> 0x%x, date = %04x-%02x-%02x\n", + old_rev, new_rev, date & 0xffff, date >> 24, (date >> 16) & 0xff); } @@ -321,6 +321,7 @@ static void print_ucode_info(unsigned int new_rev, unsigned int date) static int delay_ucode_info; static int current_mc_date; +static int early_old_rev; /* * Print early updated ucode info after printk works. This is delayed info dump. @@ -331,7 +332,7 @@ void show_ucode_info_early(void) if (delay_ucode_info) { intel_cpu_collect_info(&uci); - print_ucode_info(uci.cpu_sig.rev. current_mc_date); + print_ucode_info(early_old_rev, uci.cpu_sig.rev, current_mc_date); delay_ucode_info = 0; } } @@ -340,30 +341,33 @@ void show_ucode_info_early(void) * At this point, we can not call printk() yet. Delay printing microcode info in * show_ucode_info_early() until printk() works. */ -static void print_ucode(int new_rev, int date) +static void print_ucode(int old_rev, int new_rev, int date) { struct microcode_intel *mc; int *delay_ucode_info_p; int *current_mc_date_p; + int *early_old_rev_p; delay_ucode_info_p = (int *)__pa_nodebug(&delay_ucode_info); current_mc_date_p = (int *)__pa_nodebug(¤t_mc_date); + early_old_rev_p = (int *)__pa_nodebug(&early_old_rev); *delay_ucode_info_p = 1; *current_mc_date_p = date; + *early_old_rev_p = old_rev; } #else -static inline void print_ucode(int new_rev, int date) +static inline void print_ucode(int old_rev, int new_rev, int date) { - print_ucode_info(new_rev, date); + print_ucode_info(old_rev, new_rev, date); } #endif static int apply_microcode_early(struct ucode_cpu_info *uci, bool early) { struct microcode_intel *mc; - u32 rev; + u32 rev, old_rev; mc = uci->mc; if (!mc) @@ -389,6 +393,7 @@ static int apply_microcode_early(struct ucode_cpu_info *uci, bool early) /* write microcode via MSR 0x79 */ native_wrmsrl(MSR_IA32_UCODE_WRITE, (unsigned long)mc->bits); + old_rev = rev; rev = intel_get_microcode_revision(); if (rev != mc->hdr.rev) return -1; @@ -396,9 +401,9 @@ static int apply_microcode_early(struct ucode_cpu_info *uci, bool early) uci->cpu_sig.rev = rev; if (early) - print_ucode(uci->cpu_sig.rev, mc->hdr.date); + print_ucode(old_rev, uci->cpu_sig.rev, mc->hdr.date); else - print_ucode_info(uci->cpu_sig.rev, mc->hdr.date); + print_ucode_info(old_rev, uci->cpu_sig.rev, mc->hdr.date); return 0; } From patchwork Mon Jan 9 15:35:55 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ashok Raj X-Patchwork-Id: 40947 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4e01:0:0:0:0:0 with SMTP id p1csp2228449wrt; Mon, 9 Jan 2023 07:48:35 -0800 (PST) X-Google-Smtp-Source: AMrXdXt809C+yMCeZBH6uzYQx6H/YfDd/TWonWUBfNY4miKDsjN98BL8XHkEOZnf2IlDfNCbOhh/ X-Received: by 2002:a05:6402:4141:b0:479:971e:5da8 with SMTP id x1-20020a056402414100b00479971e5da8mr60949659eda.13.1673279315025; Mon, 09 Jan 2023 07:48:35 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1673279315; cv=none; d=google.com; s=arc-20160816; b=jRFuI7bxv557OFQBHz3Q7SuigAL0/L76LbfU+2LRnML/WFnkS3Er+1dOcAyo59pzBo 7X7ni32N+1INQGufSU+5XMKWZyTzQkF13H2dzGG/sH0s7YM4tcTtm5/W37XzsOdJoDhx 4Xpu2ut3Lca0cVnFS+ClorlCYrvgjT5gXxYg3JwLssfZ6kISEyBl7gNt/74E87oVVqQu W+iwgaVYGiK5iIl6XnSy3tr+upqLy2zL7MligAEhjNgIBJVhh5U4iVIpfxCidtKLujPj tLmMUZpV9NjvmCo2V4I//+wCTQyml87TZxSi68Cgculw6MBpMoBXi37RU8xpb/lIoeh4 RIVA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=WXZ1LMLF0xeLUALqZvS/dizG4cvFDd0U5MODsHu5tNs=; b=WEq6zXBlc4GlzVpprlQHjUb8ZXX3ZI8TJK4t1c9EO5BqDHeDI7DD0VCRMp3m4j2OFx sYETU9eLtKYBmaSukpuBeHgO6oPnqtam/N+A7g+jclzCrLyjSsJqnp/JIw294dGgl71+ M4uGq4F7YYxgW88oGaVEwuFNCrSYfB1abhqlkZInpl1RqAb5fYHyQG0yAEfmIZw1wnul 57aL8dm6PTzlnx8rw/6ayF1zTQ9n9qBOWbozd7rTnvx245ZR8wskKvb6aN8YOTzGTYJb 4Nut5ieGGHigyAOU5BdjmK+8AuGjYLgqu3wob8YLiKXqg22UlhQB6OI9bUAIlntG0YDR m8lA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=WN+p0Lo1; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id q11-20020a056402518b00b0046fa5a78da1si10737702edd.355.2023.01.09.07.48.11; Mon, 09 Jan 2023 07:48:34 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=WN+p0Lo1; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235096AbjAIPlM (ORCPT + 99 others); Mon, 9 Jan 2023 10:41:12 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52856 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231365AbjAIPkT (ORCPT ); Mon, 9 Jan 2023 10:40:19 -0500 Received: from mga06.intel.com (mga06b.intel.com [134.134.136.31]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id ABB7040C1A for ; Mon, 9 Jan 2023 07:36:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1673278579; x=1704814579; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=QXXGi44wA/1GusubxcaRaGB7tWBbRqkEstVsOgmVeSs=; b=WN+p0Lo1aXEdTYaFloozKoHzX2EocmSvk3Ntfa6qW3o1/r4dW2+pocez EFk5PFqttOFe3lDtF5O9XW3Totq86Ew8IB6nqkGX0uAxnoXqjv6I1tIaL pGOepCCeEscv53fPszjRlT+24InFpn86iw4LjamiCrLiNL91dnPdEppHB LjbzyP4gcc69U5ykTEaGL44/kGAEzvXxvaYdxyQot9A4DIPwc2/YUAhS/ /Z8ffwF4acSKfbzaOVkRcenv/r4kSfrStkMEVne9/T6AMicTKyr8QA02t QYyCGZL87fGqiaL5cvji1havSqtdIr8kz8B4qeFfGe1T9JXePdEGMu9ZA g==; X-IronPort-AV: E=McAfee;i="6500,9779,10585"; a="385203590" X-IronPort-AV: E=Sophos;i="5.96,311,1665471600"; d="scan'208";a="385203590" Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Jan 2023 07:36:14 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10585"; a="902023896" X-IronPort-AV: E=Sophos;i="5.96,311,1665471600"; d="scan'208";a="902023896" Received: from araj-ucode.jf.intel.com ([10.23.0.19]) by fmsmga006-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Jan 2023 07:36:13 -0800 From: Ashok Raj To: Borislav Petkov , Thomas Gleixner Cc: X86-kernel , LKML Mailing List , Ashok Raj , Dave Hansen , Tony Luck , Ingo Molnar , alison.schofield@intel.com, reinette.chatre@intel.com, Tom Lendacky Subject: [PATCH v4 6/6] x86/microcode/intel: Print when early microcode loading fails Date: Mon, 9 Jan 2023 07:35:55 -0800 Message-Id: <20230109153555.4986-7-ashok.raj@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230109153555.4986-1-ashok.raj@intel.com> References: <20230109153555.4986-1-ashok.raj@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1754560531138372699?= X-GMAIL-MSGID: =?utf-8?q?1754560531138372699?= Currently when early microcode loading fails there is no way for the user to know that the update failed. Store the failed status and pass it to print_ucode_info() so that early loading failures are captured in dmesg. Signed-off-by: Ashok Raj Cc: LKML Cc: x86 Cc: Tony Luck Cc: Dave Hansen Cc: Alison Schofield Cc: Reinette Chatre Cc: Thomas Gleixner Cc: Tom Lendacky Cc: Ingo Molnar --- Changes since V1: Thomas: Fix commit log as suggested. --- arch/x86/kernel/cpu/microcode/intel.c | 28 +++++++++++++++------------ 1 file changed, 16 insertions(+), 12 deletions(-) diff --git a/arch/x86/kernel/cpu/microcode/intel.c b/arch/x86/kernel/cpu/microcode/intel.c index f24300830ed7..0cdff9ed2a4e 100644 --- a/arch/x86/kernel/cpu/microcode/intel.c +++ b/arch/x86/kernel/cpu/microcode/intel.c @@ -310,11 +310,11 @@ static bool load_builtin_intel_microcode(struct cpio_data *cp) /* * Print ucode update info. */ -static void print_ucode_info(int old_rev, int new_rev, unsigned int date) +static void print_ucode_info(bool failed, int old_rev, int new_rev, unsigned int date) { - pr_info_once("early update: 0x%x -> 0x%x, date = %04x-%02x-%02x\n", + pr_info_once("early update: 0x%x -> 0x%x, date = %04x-%02x-%02x %s\n", old_rev, new_rev, date & 0xffff, date >> 24, - (date >> 16) & 0xff); + (date >> 16) & 0xff, failed ? "FAILED" : ""); } #ifdef CONFIG_X86_32 @@ -322,6 +322,7 @@ static void print_ucode_info(int old_rev, int new_rev, unsigned int date) static int delay_ucode_info; static int current_mc_date; static int early_old_rev; +static bool early_failed; /* * Print early updated ucode info after printk works. This is delayed info dump. @@ -332,7 +333,7 @@ void show_ucode_info_early(void) if (delay_ucode_info) { intel_cpu_collect_info(&uci); - print_ucode_info(early_old_rev, uci.cpu_sig.rev, current_mc_date); + print_ucode_info(early_failed, early_old_rev, uci.cpu_sig.rev, current_mc_date); delay_ucode_info = 0; } } @@ -341,26 +342,28 @@ void show_ucode_info_early(void) * At this point, we can not call printk() yet. Delay printing microcode info in * show_ucode_info_early() until printk() works. */ -static void print_ucode(int old_rev, int new_rev, int date) +static void print_ucode(bool failed, int old_rev, int new_rev, int date) { - struct microcode_intel *mc; int *delay_ucode_info_p; int *current_mc_date_p; int *early_old_rev_p; + bool *early_failed_p; delay_ucode_info_p = (int *)__pa_nodebug(&delay_ucode_info); current_mc_date_p = (int *)__pa_nodebug(¤t_mc_date); early_old_rev_p = (int *)__pa_nodebug(&early_old_rev); + early_failed_p = (bool *)__pa_nodebug(&early_failed); *delay_ucode_info_p = 1; *current_mc_date_p = date; *early_old_rev_p = old_rev; + *early_failed_p = failed; } #else -static inline void print_ucode(int old_rev, int new_rev, int date) +static inline void print_ucode(bool failed, int old_rev, int new_rev, int date) { - print_ucode_info(old_rev, new_rev, date); + print_ucode_info(failed, old_rev, new_rev, date); } #endif @@ -368,6 +371,7 @@ static int apply_microcode_early(struct ucode_cpu_info *uci, bool early) { struct microcode_intel *mc; u32 rev, old_rev; + int retval = 0; mc = uci->mc; if (!mc) @@ -396,16 +400,16 @@ static int apply_microcode_early(struct ucode_cpu_info *uci, bool early) old_rev = rev; rev = intel_get_microcode_revision(); if (rev != mc->hdr.rev) - return -1; + retval = -1; uci->cpu_sig.rev = rev; if (early) - print_ucode(old_rev, uci->cpu_sig.rev, mc->hdr.date); + print_ucode(retval, old_rev, mc->hdr.rev, mc->hdr.date); else - print_ucode_info(old_rev, uci->cpu_sig.rev, mc->hdr.date); + print_ucode_info(retval, old_rev, uci->cpu_sig.rev, mc->hdr.date); - return 0; + return retval; } int __init save_microcode_in_initrd_intel(void)