From patchwork Fri Jan 6 20:07:53 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: William Zhang X-Patchwork-Id: 40258 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4e01:0:0:0:0:0 with SMTP id p1csp1008838wrt; Fri, 6 Jan 2023 12:18:23 -0800 (PST) X-Google-Smtp-Source: AMrXdXvQy1PyXNLhWiq+yGDRAvs8B5v5NjpsEcpWTUEBqjp80rj8V5swUjj9wa15Ou556ByivQwU X-Received: by 2002:a17:907:86a6:b0:7c0:fd1a:79f0 with SMTP id qa38-20020a17090786a600b007c0fd1a79f0mr68422230ejc.21.1673036303591; Fri, 06 Jan 2023 12:18:23 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1673036303; cv=none; d=google.com; s=arc-20160816; b=yOLKNBXF7AB8QBBvosh9bWIj5PPeBsIUMkcE9H9Bp/2fNMzQZ86J0tCmQAjbmuGB/V uhI+EmPAsrc+5SoZI7GBJ6kz3t/Ac37WNlZ1Y/hkMC7ZaU7VGTuNM4x0cw544TNAeWPg 1qKNNxVzWOkvrUj0V5TRanopOl/dZVHNWVztSVxCxLAw4o9NmzLPfwAtMetFJRTPxZFe q3QLknf/YmnBpHAHIOpQg6fCipJWk7g/9l5i6cCMho9UxnCws2aAhlty2D9mgXgVXWPA cYwIF26KID/eAosq/qLdAIyWuhTLHX04W0gLtI3woXq50tLfSsA5Re5k2kRH0WTuLk1e NCMg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature:dkim-filter; bh=21TidiRTCCpbzSmO1piSrDtDDfRsxhbpoCOOo+kJCgM=; b=k2PHIh3SeTwIhFU9sN48qzKZA3OB/ZIUzXGsFmH8OBXG2wIaqx392wtO8bmc4qj0sJ 7zruNjJeM2gVYcpeG420CppI6rTJzeuaFVSor/zu1If4BZx1CC1a8RKNSpdtThb2/4bG XVmGvJLH0Z3UpI3Agjv9GCa4X57YnxDgGEMQ/aIvZ0jZZt2mjuBcAlHhwepZc65O784t ICH9Q6RBYK4dbl8Q8u1GMCf4KzpD0QL1rl30mo0yo9SbLc3szBYltmi1Q3Hf1T2Df0wW 8eyoAVf8vO3rEmSylLnb8TjihXdxReCHapbQpuk+8yhSgLWmwAKfhxMNBQiXtnp1ra9O PlHA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@broadcom.com header.s=dkimrelay header.b=AfLvtJq3; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=broadcom.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id jg24-20020a170907971800b007c0dcc79ec5si2576021ejc.161.2023.01.06.12.17.59; Fri, 06 Jan 2023 12:18:23 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@broadcom.com header.s=dkimrelay header.b=AfLvtJq3; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=broadcom.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236270AbjAFURf (ORCPT + 99 others); Fri, 6 Jan 2023 15:17:35 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57278 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236551AbjAFURL (ORCPT ); Fri, 6 Jan 2023 15:17:11 -0500 Received: from relay.smtp-ext.broadcom.com (relay.smtp-ext.broadcom.com [192.19.166.228]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7F2258461A; Fri, 6 Jan 2023 12:15:12 -0800 (PST) Received: from mail-lvn-it-01.lvn.broadcom.net (mail-lvn-it-01.lvn.broadcom.net [10.75.146.107]) by relay.smtp-ext.broadcom.com (Postfix) with ESMTP id E5D73C0000DF; Fri, 6 Jan 2023 12:09:01 -0800 (PST) DKIM-Filter: OpenDKIM Filter v2.11.0 relay.smtp-ext.broadcom.com E5D73C0000DF DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=broadcom.com; s=dkimrelay; t=1673035741; bh=4tmxociq74DzqIKjaR1HWJny/pYlXg9f+mpHVbW2wPs=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=AfLvtJq3X7BtYJ5i5HEZp7214sF6oACd661afFz9l9vvQaJEpxTy8fBpX1kIZ1Aa8 Vf/A3/nuaNZKh0lEz9Az0biiz9sLlZVRPI8FMl4Bf7H8hMsQsl8ovKE9BsNyQJeOu3 MDUK5zjgW5S+BcfYiJKI5o6Br9TXmXM0VGM9iDNs= Received: from bcacpedev-irv-3.lvn.broadcom.net (bcacpedev-irv-3.lvn.broadcom.net [10.75.138.105]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail-lvn-it-01.lvn.broadcom.net (Postfix) with ESMTPS id DA94B18041CAC6; Fri, 6 Jan 2023 12:09:01 -0800 (PST) Received: by bcacpedev-irv-3.lvn.broadcom.net (Postfix, from userid 28376) id C68C7101B3C; Fri, 6 Jan 2023 12:09:01 -0800 (PST) From: William Zhang To: Linux SPI List , Broadcom Kernel List Cc: anand.gore@broadcom.com, tomer.yacoby@broadcom.com, dan.beygelman@broadcom.com, joel.peshkin@broadcom.com, f.fainelli@gmail.com, jonas.gorski@gmail.com, kursad.oney@broadcom.com, dregan@mail.com, William Zhang , Krzysztof Kozlowski , Mark Brown , Rob Herring , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 01/16] dt-bindings: spi: Convert bcm63xx-hsspi bindings to json-schema Date: Fri, 6 Jan 2023 12:07:53 -0800 Message-Id: <20230106200809.330769-2-william.zhang@broadcom.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20230106200809.330769-1-william.zhang@broadcom.com> References: <20230106200809.330769-1-william.zhang@broadcom.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE, SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1754305715361508883?= X-GMAIL-MSGID: =?utf-8?q?1754305715361508883?= This is the preparation for updates on the bcm63xx hsspi driver. Convert the text based bindings to json-schema per new dts requirement. Signed-off-by: William Zhang --- .../bindings/spi/brcm,bcm63xx-hsspi.yaml | 52 +++++++++++++++++++ .../bindings/spi/spi-bcm63xx-hsspi.txt | 33 ------------ 2 files changed, 52 insertions(+), 33 deletions(-) create mode 100644 Documentation/devicetree/bindings/spi/brcm,bcm63xx-hsspi.yaml delete mode 100644 Documentation/devicetree/bindings/spi/spi-bcm63xx-hsspi.txt diff --git a/Documentation/devicetree/bindings/spi/brcm,bcm63xx-hsspi.yaml b/Documentation/devicetree/bindings/spi/brcm,bcm63xx-hsspi.yaml new file mode 100644 index 000000000000..45f1417b1213 --- /dev/null +++ b/Documentation/devicetree/bindings/spi/brcm,bcm63xx-hsspi.yaml @@ -0,0 +1,52 @@ +# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/spi/brcm,bcm63xx-hsspi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Broadcom BCM6328 High Speed SPI controller + +maintainers: + - Jonas Gorski + +properties: + compatible: + const: brcm,bcm6328-hsspi + + reg: + maxItems: 1 + + clocks: + items: + - description: spi master reference clock + - description: spi master pll clock + + clock-names: + items: + - const: hsspi + - const: pll + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - interrupts + +unevaluatedProperties: false + +examples: + - | + spi@10001000 { + compatible = "brcm,bcm6328-hsspi"; + reg = <0x10001000 0x600>; + interrupts = <29>; + clocks = <&clkctl 9>, <&hsspi_pll>; + clock-names = "hsspi", "pll"; + num-cs = <2>; + #address-cells = <1>; + #size-cells = <0>; + }; diff --git a/Documentation/devicetree/bindings/spi/spi-bcm63xx-hsspi.txt b/Documentation/devicetree/bindings/spi/spi-bcm63xx-hsspi.txt deleted file mode 100644 index 37b29ee13860..000000000000 --- a/Documentation/devicetree/bindings/spi/spi-bcm63xx-hsspi.txt +++ /dev/null @@ -1,33 +0,0 @@ -Binding for Broadcom BCM6328 High Speed SPI controller - -Required properties: -- compatible: must contain of "brcm,bcm6328-hsspi". -- reg: Base address and size of the controllers memory area. -- interrupts: Interrupt for the SPI block. -- clocks: phandles of the SPI clock and the PLL clock. -- clock-names: must be "hsspi", "pll". -- #address-cells: <1>, as required by generic SPI binding. -- #size-cells: <0>, also as required by generic SPI binding. - -Optional properties: -- num-cs: some controllers have less than 8 cs signals. Defaults to 8 - if absent. - -Child nodes as per the generic SPI binding. - -Example: - - spi@10001000 { - compatible = "brcm,bcm6328-hsspi"; - reg = <0x10001000 0x600>; - - interrupts = <29>; - - clocks = <&clkctl 9>, <&hsspi_pll>; - clock-names = "hsspi", "pll"; - - num-cs = <2>; - - #address-cells = <1>; - #size-cells = <0>; - }; From patchwork Fri Jan 6 20:07:54 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: William Zhang X-Patchwork-Id: 40260 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4e01:0:0:0:0:0 with SMTP id p1csp1010294wrt; Fri, 6 Jan 2023 12:22:37 -0800 (PST) X-Google-Smtp-Source: AMrXdXvtOibpTEmeLF8m0QKcaZgismjKf/laQ5MZJvoJQIP5OhQ1UcAaA0e42rO48CTfzXTaw6wi X-Received: by 2002:a05:6402:528f:b0:47e:eaae:9a69 with SMTP id en15-20020a056402528f00b0047eeaae9a69mr49323629edb.41.1673036557687; Fri, 06 Jan 2023 12:22:37 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1673036557; cv=none; d=google.com; s=arc-20160816; b=pUWP/xWIpwAsDvjZnaPEVPRg8v/KFSSoJjwbwZPlrsXIVxxvn0shtx9R01Cz6JNRuA tzWTxvn7A15jj+7TgnH24a1mjJ04lPj9npRapIBlTVT70T774sgbm0vHPXkeGAis3F11 4IvdP994KAvB7VNpW1bvVRq0I6Bj9bfshBLn1HCSV0xHUR8XsCyuR+D4Bam+WIzVtiOm t9VUu+Wn/8y4q6xkjgJ0OFcqZ1SK8Z03CS8xFO7VUuS5/Z4m4Tb8v2uYKHlcvabFFLyr Ne5JvZkSG2Cj8JoN3eL1cwymDyE5cuwgKBJ2pPAojMA2wNHqvTNQdzWgDm8QQjTlksGH 8buw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature:dkim-filter; bh=RZB79cM8clzFNWrfjsjFoo6cISS7Nw9v7ScknFe5LpE=; b=dmLsMnI7Y3rqxh7J+96/3S6r62mv6vTZNXOC6QdVuPU801Sh0tLRQnDPYxlJTbOefD 1ZdphSLqdeOTp06GBujQRnLSWmZ7DOuCxMmGF5DgGhRS/3O70GgsYDEpTctKudmi0cm+ OwZqMn0nAF6nYDTWCgaZir+dbrnKMGZlzNx91iOCI2lKBkehKPnxYH51CPL/V8MSNdtV kbiidAClxFQC75NUTjC44f8FKzMLQK/QrUEOQjIW7qcxAz27OJBsZpRhgYXUH025XJ0z wmcz0JNksZNAVNf5vwuzT1beiN2+4siOK5iCyXLEl3VqTa2K25znYNEk//eqspzjCnMC LZOA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@broadcom.com header.s=dkimrelay header.b=Uq6Jb+tn; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=broadcom.com Received: from out1.vger.email (out1.vger.email. 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Add a new compatible string and required fields for the new driver. Also add myself and Kursad as the maintainers. Signed-off-by: William Zhang --- .../bindings/spi/brcm,bcm63xx-hsspi.yaml | 84 +++++++++++++++++-- 1 file changed, 78 insertions(+), 6 deletions(-) diff --git a/Documentation/devicetree/bindings/spi/brcm,bcm63xx-hsspi.yaml b/Documentation/devicetree/bindings/spi/brcm,bcm63xx-hsspi.yaml index 45f1417b1213..56e69d4a1faf 100644 --- a/Documentation/devicetree/bindings/spi/brcm,bcm63xx-hsspi.yaml +++ b/Documentation/devicetree/bindings/spi/brcm,bcm63xx-hsspi.yaml @@ -4,22 +4,51 @@ $id: http://devicetree.org/schemas/spi/brcm,bcm63xx-hsspi.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Broadcom BCM6328 High Speed SPI controller +title: Broadcom Broadband SoC High Speed SPI controller maintainers: + + - William Zhang + - Kursad Oney - Jonas Gorski +description: | + Broadcom Broadband SoC supports High Speed SPI master controller since the + early MIPS based chips such as BCM6328 and BCM63268. This controller was + carried over to recent ARM based chips, such as BCM63138, BCM4908 and BCM6858. + + It has a limitation that can not keep the chip select line active between + the SPI transfers within the same SPI message. This can terminate the + transaction to some SPI devices prematurely. The issue can be worked around by + either the controller's prepend mode or using the dummy chip select + workaround. This controller uses the compatible string brcm,bcm6328-hsspi. + + The newer SoCs such as BCM6756, BCM4912 and BCM6855 include an updated SPI + controller that add the capability to allow the driver to control chip select + explicitly. This solves the issue in the old controller. This new controller + uses the compatible string brcm,bcmbca-hsspi. + properties: compatible: - const: brcm,bcm6328-hsspi + enum: + - brcm,bcm6328-hsspi + - brcm,bcmbca-hsspi reg: - maxItems: 1 + items: + - description: main registers + - description: miscellaneous control registers + minItems: 1 + + reg-names: + items: + - const: hsspi + - const: spim-ctrl clocks: items: - - description: spi master reference clock - - description: spi master pll clock + - description: SPI master reference clock + - description: SPI master pll clock clock-names: items: @@ -29,12 +58,43 @@ properties: interrupts: maxItems: 1 + brcm,use-cs-workaround: + $ref: /schemas/types.yaml#/definitions/flag + description: | + Enable dummy chip select workaround for SPI transfers that can not be + supported by the default controller's prepend mode, i.e. delay or cs + change needed between SPI transfers. + required: - compatible - reg - clocks - clock-names - - interrupts + +allOf: + - $ref: "spi-controller.yaml#" + - if: + properties: + compatible: + contains: + enum: + - brcm,bcm6328-hsspi + then: + properties: + reg: + minItems: 1 + maxItems: 1 + else: + properties: + reg: + minItems: 2 + maxItems: 2 + reg-names: + minItems: 2 + maxItems: 2 + brcm,use-cs-workaround: false + required: + - reg-names unevaluatedProperties: false @@ -50,3 +110,15 @@ examples: #address-cells = <1>; #size-cells = <0>; }; + - | + spi@ff801000 { + compatible = "brcm,bcmbca-hsspi"; + reg = <0xff801000 0x1000>, + <0xff802610 0x4>; + reg-names = "hsspi", "spim-ctrl"; + clocks = <&hsspi>, <&hsspi_pll>; + clock-names = "hsspi", "pll"; + num-cs = <8>; + #address-cells = <1>; + #size-cells = <0>; + }; From patchwork Fri Jan 6 20:07:55 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: William Zhang X-Patchwork-Id: 40262 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4e01:0:0:0:0:0 with SMTP id p1csp1010770wrt; Fri, 6 Jan 2023 12:24:04 -0800 (PST) X-Google-Smtp-Source: AMrXdXtcCO8qEUUreRRzZYIJQfAPUgd6YqlWluj6zy745gKu0Yu+UmOxGcvcC0tGASTvz41yVJrx X-Received: by 2002:a17:906:f854:b0:849:7688:3e3e with SMTP id ks20-20020a170906f85400b0084976883e3emr38468609ejb.44.1673036644349; Fri, 06 Jan 2023 12:24:04 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1673036644; cv=none; d=google.com; s=arc-20160816; b=wB+00ilQ1sJ+AusLaRKEuQJuoypa15mHC5u9L79Dzhi/ZipyI/nP8MkiBqj/p3Ya9q E8wuquDrJ0XL6RrBzNDjzKk1P5sz5mlrx1R7H7dW6w48MhA3BkIapeXEHT7xr2WGNFfa mRjxahrgAyLtCSYnFxeSbXw1Fm1bj5Ah7ZsoRJEbZIu7gzxZAYlnJyARU3LtL986YAB1 6boyC9TkCqub05ohk81v7G8wp9POT/CfbOO3TqX0mWWWf0TbD5Z6QMkSYVRiPYj++Vpe CUhWKRx2qTFrczqcLmHW1x4wi2pKAKVW9/aE7FZvKB3vA3i7TxV+xFygOVtqNRv1OfU7 pvmg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature:dkim-filter; bh=YqkBXqAp9252hafC4MtWUNFxwc6/MZaBDqZ+9PQ5Xz4=; b=rf7vIpVGuftyVAmyOalon7Bef4ixxXorENgLZv7gwuZc0bQNkxBIFXQ/fBYHr1RBGX +uha7YJ4wPX44M75r0dJu5XLm0arCajegZAV69MY4DIJrbPQJ+DIugBiGxfuGEwdOTb3 XYCEHPdqvwNL8LjwcjX4pkLFHq3DBiLULfSfCJPmwwONWth6gV9iSizyBiuZf4eoxxQV qaop/Y92eoKs8+eFv7Lpj5TXkfou68ThHGsmQKVNejZb9OCqps52Wi/z7svjbzEF6Sn2 mkPPWjXfhS5tpebi5l3M9k33/Vh9j3hk4NctmkCTO1C1tBlL4bXgj8Zn61xKW56VFvK3 PovQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@broadcom.com header.s=dkimrelay header.b=iQXhfdoe; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=broadcom.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id wy11-20020a170906fe0b00b0084d2e5c063asi382875ejb.481.2023.01.06.12.23.38; Fri, 06 Jan 2023 12:24:04 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@broadcom.com header.s=dkimrelay header.b=iQXhfdoe; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=broadcom.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235605AbjAFUTv (ORCPT + 99 others); Fri, 6 Jan 2023 15:19:51 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57388 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236111AbjAFUS7 (ORCPT ); Fri, 6 Jan 2023 15:18:59 -0500 Received: from relay.smtp-ext.broadcom.com (relay.smtp-ext.broadcom.com [192.19.144.205]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DB3AB3C700; Fri, 6 Jan 2023 12:18:26 -0800 (PST) Received: from mail-lvn-it-01.lvn.broadcom.net (mail-lvn-it-01.lvn.broadcom.net [10.75.146.107]) by relay.smtp-ext.broadcom.com (Postfix) with ESMTP id AB68DC0003C8; Fri, 6 Jan 2023 12:09:30 -0800 (PST) DKIM-Filter: OpenDKIM Filter v2.11.0 relay.smtp-ext.broadcom.com AB68DC0003C8 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=broadcom.com; s=dkimrelay; t=1673035770; bh=z13ASkxUuc4fajnr4hl+GEimGjj6wHKe2iHsFsjdvoU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=iQXhfdoeh6FAHyJia1sRh/e8Gz5cVwMKFPtQy282HYXI70iHn9AkT1F3c/dIymVzi +XgOKmH1psWI3PZRJ0DGkSh2dEieVrcEyYEYhXiY0W6l+d8Rn501rWqkr1SyN6PK5b 8npFKA5EYhA87JjmE9xJg3H36qBQj9ArV58g5E0c= Received: from bcacpedev-irv-3.lvn.broadcom.net (bcacpedev-irv-3.lvn.broadcom.net [10.75.138.105]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail-lvn-it-01.lvn.broadcom.net (Postfix) with ESMTPS id 73E4C18041CAC6; Fri, 6 Jan 2023 12:09:30 -0800 (PST) Received: by bcacpedev-irv-3.lvn.broadcom.net (Postfix, from userid 28376) id BB1E2101B33; Fri, 6 Jan 2023 12:09:20 -0800 (PST) From: William Zhang To: Linux SPI List , Broadcom Kernel List Cc: anand.gore@broadcom.com, tomer.yacoby@broadcom.com, dan.beygelman@broadcom.com, joel.peshkin@broadcom.com, f.fainelli@gmail.com, jonas.gorski@gmail.com, kursad.oney@broadcom.com, dregan@mail.com, William Zhang , Krzysztof Kozlowski , Mark Brown , Rob Herring , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 03/16] dt-bindings: spi: Add spi peripheral specific property Date: Fri, 6 Jan 2023 12:07:55 -0800 Message-Id: <20230106200809.330769-4-william.zhang@broadcom.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20230106200809.330769-1-william.zhang@broadcom.com> References: <20230106200809.330769-1-william.zhang@broadcom.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE, SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1754306071987684495?= X-GMAIL-MSGID: =?utf-8?q?1754306071987684495?= brcm,no-clk-gate is a Broadcom Broadband HS SPI controller specific property for certain SPI device such as Broadcom ISI voice daughtercard to work properly. It disables the clock gating feature when the chip select is deasserted for any device that wants to keep the clock running. Signed-off-by: William Zhang --- .../brcm,bcm63xx-hsspi-peripheral-props.yaml | 27 +++++++++++++++++++ .../bindings/spi/spi-peripheral-props.yaml | 1 + 2 files changed, 28 insertions(+) create mode 100644 Documentation/devicetree/bindings/spi/brcm,bcm63xx-hsspi-peripheral-props.yaml diff --git a/Documentation/devicetree/bindings/spi/brcm,bcm63xx-hsspi-peripheral-props.yaml b/Documentation/devicetree/bindings/spi/brcm,bcm63xx-hsspi-peripheral-props.yaml new file mode 100644 index 000000000000..81884e2cc42d --- /dev/null +++ b/Documentation/devicetree/bindings/spi/brcm,bcm63xx-hsspi-peripheral-props.yaml @@ -0,0 +1,27 @@ +# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/spi/brcm,bcm63xx-hsspi-peripheral-props.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Peripheral-specific properties for Broadcom Broadband SoC HSSPI controller + +description: + See spi-peripheral-props.yaml for more info. + +maintainers: + - William Zhang + - Kursad Oney + - Jonas Gorski + +properties: + brcm,no-clk-gate: + $ref: /schemas/types.yaml#/definitions/flag + description: + Some SPI device such as Broadcom ISI based voice daughtercard requires SPI + clock running even when chip select is deasserted. By default the + controller turns off or gate the clock when cs is not active to save + power. This flag tells the controller driver to keep the clock running + when chip select is not active. + +additionalProperties: true diff --git a/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml b/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml index ead2cccf658f..f85d777c7b67 100644 --- a/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml +++ b/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml @@ -108,5 +108,6 @@ allOf: - $ref: cdns,qspi-nor-peripheral-props.yaml# - $ref: samsung,spi-peripheral-props.yaml# - $ref: nvidia,tegra210-quad-peripheral-props.yaml# + - $ref: brcm,bcm63xx-hsspi-peripheral-props.yaml# additionalProperties: true From patchwork Fri Jan 6 20:07:56 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: William Zhang X-Patchwork-Id: 40261 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4e01:0:0:0:0:0 with SMTP id p1csp1010732wrt; Fri, 6 Jan 2023 12:23:59 -0800 (PST) X-Google-Smtp-Source: AMrXdXsf4/yLuUrt0GRsdvc7nYDIHIV03UlZFF7A6Pg17eh5YPAoGCCTyw0ngA2PjAProazR6ydq X-Received: by 2002:a17:907:a782:b0:7c1:6430:e5d0 with SMTP id vx2-20020a170907a78200b007c16430e5d0mr50419347ejc.4.1673036639035; Fri, 06 Jan 2023 12:23:59 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1673036639; cv=none; d=google.com; s=arc-20160816; b=t+kSLpj/3+Wt2asCZbiYmVSPJW4pZJ+KfimeqTlE7WNT8I7ZvDKZLRONf2BemlVvfm fQO1KiAVCvHq3fHRbzB+We6ApV2ze4MYDys/HY2gqAc4/RMdKK0fdaVVxG/Kstbjca1p vRufajOEUvPsyfj8AOFGy7QEos7AUajxUFg9B2Rsf02joO6exHb3jxWxdx5N2ffv5SkB ucTkciGF92nHGDSmzuaISuGyU66sLAiEUepMosaTJWUvlzn2gyWSQTfWLMCl+T+LyK5j oqN6DtZYj9xfaPgx/qftn4CH2fqLC48EmfeZZtDFpdjA6EEVgJbkrYS6vOK9ln9mepWS l1oA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature:dkim-filter; bh=9kzDPhIxOsjc9eRDE9ik48BO9vCdgRW4riMG7X0PRYc=; b=n8xnN5/ZQ/iR9Ea5G4JWfqGidtDjsR86sqF79igz3jOGjDB9q/6mYF7ijr+KHL+3hj zIpfdRUTazVzEInGO8a13oSXFDjf1iYLP8MhMHfU1rhJF5fiDl4A1AgO/hMQYPSUu1VR flWmFWA15rpDq3ToR8/MX5N9eaQ/g8vdCThgV91LkimFBEo2QHiWsN+HyArSrKfgr5AI 7fcX1AP+xIIjwVOmms9Ww7R40e6AJyrZEljA0Cn1tMRu8agi3pD61i1lCPIpFv2+RNZp faQ1i7Oq3M34a8sIEmlcAcFbrC1McEcr7vMFD8D5yEdwxoW7yXS79upIQxQirR8Mu/+C QdWQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@broadcom.com header.s=dkimrelay header.b=pT0P6pG4; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=broadcom.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id xe9-20020a170907318900b007c4fb4ee06fsi2379322ejb.531.2023.01.06.12.23.34; Fri, 06 Jan 2023 12:23:59 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@broadcom.com header.s=dkimrelay header.b=pT0P6pG4; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=broadcom.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235673AbjAFUTp (ORCPT + 99 others); Fri, 6 Jan 2023 15:19:45 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57378 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235891AbjAFUS6 (ORCPT ); Fri, 6 Jan 2023 15:18:58 -0500 X-Greylist: delayed 547 seconds by postgrey-1.37 at lindbergh.monkeyblade.net; Fri, 06 Jan 2023 12:18:26 PST Received: from relay.smtp-ext.broadcom.com (relay.smtp-ext.broadcom.com [192.19.144.205]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DAF9F3AB03; Fri, 6 Jan 2023 12:18:26 -0800 (PST) Received: from mail-lvn-it-01.lvn.broadcom.net (mail-lvn-it-01.lvn.broadcom.net [10.75.146.107]) by relay.smtp-ext.broadcom.com (Postfix) with ESMTP id 0FFF8C0003CA; Fri, 6 Jan 2023 12:09:33 -0800 (PST) DKIM-Filter: OpenDKIM Filter v2.11.0 relay.smtp-ext.broadcom.com 0FFF8C0003CA DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=broadcom.com; s=dkimrelay; t=1673035773; bh=IvHElhieoeG6ehpcVfKKnJWwfWVb9CrCRmCz4f0TsyY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=pT0P6pG4RQwlbn0muM+ogmkEyLytkpHaI2e3eBnoXKEwVkeiOmmV9RFtWI7P4GD2N ckhhxHFF/WzsITMTZA+fTcGA1Ly0iYivGOMy4NPg9o6XjoAGn1Rd/+JJMrk2B3Gx38 dywWSGdElENaS0vmBNa7uoR0QIMLcMivMgpv55Rc= Received: from bcacpedev-irv-3.lvn.broadcom.net (bcacpedev-irv-3.lvn.broadcom.net [10.75.138.105]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail-lvn-it-01.lvn.broadcom.net (Postfix) with ESMTPS id CA6D318041CAC6; Fri, 6 Jan 2023 12:09:32 -0800 (PST) Received: by bcacpedev-irv-3.lvn.broadcom.net (Postfix, from userid 28376) id C26F2101B33; Fri, 6 Jan 2023 12:09:32 -0800 (PST) From: William Zhang To: Linux SPI List , Broadcom Kernel List Cc: anand.gore@broadcom.com, tomer.yacoby@broadcom.com, dan.beygelman@broadcom.com, joel.peshkin@broadcom.com, f.fainelli@gmail.com, jonas.gorski@gmail.com, kursad.oney@broadcom.com, dregan@mail.com, William Zhang , Krzysztof Kozlowski , =?utf-8?b?UmFmYcWC?= =?utf-8?b?IE1pxYJlY2tp?= , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 04/16] ARM: dts: broadcom: bcmbca: Add spi controller node Date: Fri, 6 Jan 2023 12:07:56 -0800 Message-Id: <20230106200809.330769-5-william.zhang@broadcom.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20230106200809.330769-1-william.zhang@broadcom.com> References: <20230106200809.330769-1-william.zhang@broadcom.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE, SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1754306066943145298?= X-GMAIL-MSGID: =?utf-8?q?1754306066943145298?= Add support for HSSPI controller in ARMv7 chip dts files. Signed-off-by: William Zhang --- arch/arm/boot/dts/bcm47622.dtsi | 17 +++++++++++++++++ arch/arm/boot/dts/bcm63138.dtsi | 17 +++++++++++++++++ arch/arm/boot/dts/bcm63148.dtsi | 17 +++++++++++++++++ arch/arm/boot/dts/bcm63178.dtsi | 18 ++++++++++++++++++ arch/arm/boot/dts/bcm6756.dtsi | 18 ++++++++++++++++++ arch/arm/boot/dts/bcm6846.dtsi | 17 +++++++++++++++++ arch/arm/boot/dts/bcm6855.dtsi | 18 ++++++++++++++++++ arch/arm/boot/dts/bcm6878.dtsi | 18 ++++++++++++++++++ arch/arm/boot/dts/bcm947622.dts | 4 ++++ arch/arm/boot/dts/bcm963138.dts | 4 ++++ arch/arm/boot/dts/bcm963138dvt.dts | 4 ++++ arch/arm/boot/dts/bcm963148.dts | 4 ++++ arch/arm/boot/dts/bcm963178.dts | 4 ++++ arch/arm/boot/dts/bcm96756.dts | 4 ++++ arch/arm/boot/dts/bcm96846.dts | 4 ++++ arch/arm/boot/dts/bcm96855.dts | 4 ++++ arch/arm/boot/dts/bcm96878.dts | 4 ++++ 17 files changed, 176 insertions(+) diff --git a/arch/arm/boot/dts/bcm47622.dtsi b/arch/arm/boot/dts/bcm47622.dtsi index f4b2db9bc4ab..da4b71ef2471 100644 --- a/arch/arm/boot/dts/bcm47622.dtsi +++ b/arch/arm/boot/dts/bcm47622.dtsi @@ -88,6 +88,12 @@ uart_clk: uart-clk { clock-div = <4>; clock-mult = <1>; }; + + hsspi_pll: hsspi-pll { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <200000000>; + }; }; psci { @@ -119,6 +125,17 @@ bus@ff800000 { #size-cells = <1>; ranges = <0 0xff800000 0x800000>; + hsspi: spi@1000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "brcm,bcm6328-hsspi"; + reg = <0x1000 0x600>; + clocks = <&hsspi_pll &hsspi_pll>; + clock-names = "hsspi", "pll"; + num-cs = <8>; + status = "disabled"; + }; + uart0: serial@12000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x12000 0x1000>; diff --git a/arch/arm/boot/dts/bcm63138.dtsi b/arch/arm/boot/dts/bcm63138.dtsi index b774a8d63813..1631694c0496 100644 --- a/arch/arm/boot/dts/bcm63138.dtsi +++ b/arch/arm/boot/dts/bcm63138.dtsi @@ -66,6 +66,12 @@ apb_clk: apb_clk { clock-div = <4>; clock-mult = <1>; }; + + hsspi_pll: hsspi-pll { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <400000000>; + }; }; /* ARM bus */ @@ -203,6 +209,17 @@ serial1: serial@620 { status = "disabled"; }; + hsspi: spi@1000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "brcm,bcm6328-hsspi"; + reg = <0x1000 0x600>; + clocks = <&hsspi_pll &hsspi_pll>; + clock-names = "hsspi", "pll"; + num-cs = <8>; + status = "disabled"; + }; + nand_controller: nand-controller@2000 { #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/boot/dts/bcm63148.dtsi b/arch/arm/boot/dts/bcm63148.dtsi index 7cd55d64de71..6dccba705f5d 100644 --- a/arch/arm/boot/dts/bcm63148.dtsi +++ b/arch/arm/boot/dts/bcm63148.dtsi @@ -60,6 +60,12 @@ periph_clk: periph-clk { #clock-cells = <0>; clock-frequency = <50000000>; }; + + hsspi_pll: hsspi-pll { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <400000000>; + }; }; psci { @@ -100,5 +106,16 @@ uart0: serial@600 { clock-names = "refclk"; status = "disabled"; }; + + hsspi: spi@1000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "brcm,bcm6328-hsspi"; + reg = <0x1000 0x600>; + clocks = <&hsspi_pll &hsspi_pll>; + clock-names = "hsspi", "pll"; + num-cs = <8>; + status = "disabled"; + }; }; }; diff --git a/arch/arm/boot/dts/bcm63178.dtsi b/arch/arm/boot/dts/bcm63178.dtsi index 043e699cbc27..8db27e7ac9fd 100644 --- a/arch/arm/boot/dts/bcm63178.dtsi +++ b/arch/arm/boot/dts/bcm63178.dtsi @@ -71,6 +71,7 @@ periph_clk: periph-clk { #clock-cells = <0>; clock-frequency = <200000000>; }; + uart_clk: uart-clk { compatible = "fixed-factor-clock"; #clock-cells = <0>; @@ -78,6 +79,12 @@ uart_clk: uart-clk { clock-div = <4>; clock-mult = <1>; }; + + hsspi_pll: hsspi-pll { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <200000000>; + }; }; psci { @@ -109,6 +116,17 @@ bus@ff800000 { #size-cells = <1>; ranges = <0 0xff800000 0x800000>; + hsspi: spi@1000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "brcm,bcm6328-hsspi"; + reg = <0x1000 0x600>; + clocks = <&hsspi_pll &hsspi_pll>; + clock-names = "hsspi", "pll"; + num-cs = <8>; + status = "disabled"; + }; + uart0: serial@12000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x12000 0x1000>; diff --git a/arch/arm/boot/dts/bcm6756.dtsi b/arch/arm/boot/dts/bcm6756.dtsi index 5c72219bc194..2af35a48b6c3 100644 --- a/arch/arm/boot/dts/bcm6756.dtsi +++ b/arch/arm/boot/dts/bcm6756.dtsi @@ -88,6 +88,12 @@ uart_clk: uart-clk { clock-div = <4>; clock-mult = <1>; }; + + hsspi_pll: hsspi-pll { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <200000000>; + }; }; psci { @@ -119,6 +125,18 @@ bus@ff800000 { #size-cells = <1>; ranges = <0 0xff800000 0x800000>; + hsspi: spi@1000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "brcm,bcmbca-hsspi"; + reg = <0x1000 0x600>, <0x2610 0x4>; + reg-names = "hsspi", "spim-ctrl"; + clocks = <&hsspi_pll &hsspi_pll>; + clock-names = "hsspi", "pll"; + num-cs = <8>; + status = "disabled"; + }; + uart0: serial@12000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x12000 0x1000>; diff --git a/arch/arm/boot/dts/bcm6846.dtsi b/arch/arm/boot/dts/bcm6846.dtsi index 81513a793815..fa26b2107f93 100644 --- a/arch/arm/boot/dts/bcm6846.dtsi +++ b/arch/arm/boot/dts/bcm6846.dtsi @@ -61,6 +61,12 @@ periph_clk: periph-clk { #clock-cells = <0>; clock-frequency = <200000000>; }; + + hsspi_pll: hsspi-pll { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <400000000>; + }; }; psci { @@ -100,5 +106,16 @@ uart0: serial@640 { clock-names = "refclk"; status = "disabled"; }; + + hsspi: spi@1000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "brcm,bcm6328-hsspi"; + reg = <0x1000 0x600>; + clocks = <&hsspi_pll &hsspi_pll>; + clock-names = "hsspi", "pll"; + num-cs = <8>; + status = "disabled"; + }; }; }; diff --git a/arch/arm/boot/dts/bcm6855.dtsi b/arch/arm/boot/dts/bcm6855.dtsi index 5fa5feac0e29..bf028f0ad84c 100644 --- a/arch/arm/boot/dts/bcm6855.dtsi +++ b/arch/arm/boot/dts/bcm6855.dtsi @@ -78,6 +78,12 @@ uart_clk: uart-clk { clock-div = <4>; clock-mult = <1>; }; + + hsspi_pll: hsspi-pll { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <200000000>; + }; }; psci { @@ -109,6 +115,18 @@ bus@ff800000 { #size-cells = <1>; ranges = <0 0xff800000 0x800000>; + hsspi: spi@1000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "brcm,bcmbca-hsspi"; + reg = <0x1000 0x600>, <0x2610 0x4>; + reg-names = "hsspi", "spim-ctrl"; + clocks = <&hsspi_pll &hsspi_pll>; + clock-names = "hsspi", "pll"; + num-cs = <8>; + status = "disabled"; + }; + uart0: serial@12000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x12000 0x1000>; diff --git a/arch/arm/boot/dts/bcm6878.dtsi b/arch/arm/boot/dts/bcm6878.dtsi index 4ec836ac4baf..be7ab5f52da4 100644 --- a/arch/arm/boot/dts/bcm6878.dtsi +++ b/arch/arm/boot/dts/bcm6878.dtsi @@ -61,6 +61,7 @@ periph_clk: periph-clk { #clock-cells = <0>; clock-frequency = <200000000>; }; + uart_clk: uart-clk { compatible = "fixed-factor-clock"; #clock-cells = <0>; @@ -68,6 +69,12 @@ uart_clk: uart-clk { clock-div = <4>; clock-mult = <1>; }; + + hsspi_pll: hsspi-pll { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <200000000>; + }; }; psci { @@ -100,6 +107,17 @@ bus@ff800000 { #size-cells = <1>; ranges = <0 0xff800000 0x800000>; + hsspi: spi@1000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "brcm,bcm6328-hsspi"; + reg = <0x1000 0x600>; + clocks = <&hsspi_pll &hsspi_pll>; + clock-names = "hsspi", "pll"; + num-cs = <8>; + status = "disabled"; + }; + uart0: serial@12000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x12000 0x1000>; diff --git a/arch/arm/boot/dts/bcm947622.dts b/arch/arm/boot/dts/bcm947622.dts index 6f083724ab8e..93b8ce22678d 100644 --- a/arch/arm/boot/dts/bcm947622.dts +++ b/arch/arm/boot/dts/bcm947622.dts @@ -28,3 +28,7 @@ memory@0 { &uart0 { status = "okay"; }; + +&hsspi { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/bcm963138.dts b/arch/arm/boot/dts/bcm963138.dts index d28c4f130ca2..1b405c249213 100644 --- a/arch/arm/boot/dts/bcm963138.dts +++ b/arch/arm/boot/dts/bcm963138.dts @@ -25,3 +25,7 @@ memory@0 { &serial0 { status = "okay"; }; + +&hsspi { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/bcm963138dvt.dts b/arch/arm/boot/dts/bcm963138dvt.dts index 15bec75be74c..b5af61853a07 100644 --- a/arch/arm/boot/dts/bcm963138dvt.dts +++ b/arch/arm/boot/dts/bcm963138dvt.dts @@ -50,3 +50,7 @@ &ahci { &sata_phy { status = "okay"; }; + +&hsspi { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/bcm963148.dts b/arch/arm/boot/dts/bcm963148.dts index 98f6a6d09f50..1f5d6d783f09 100644 --- a/arch/arm/boot/dts/bcm963148.dts +++ b/arch/arm/boot/dts/bcm963148.dts @@ -28,3 +28,7 @@ memory@0 { &uart0 { status = "okay"; }; + +&hsspi { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/bcm963178.dts b/arch/arm/boot/dts/bcm963178.dts index fa096e9cde23..d036e99dd8d1 100644 --- a/arch/arm/boot/dts/bcm963178.dts +++ b/arch/arm/boot/dts/bcm963178.dts @@ -28,3 +28,7 @@ memory@0 { &uart0 { status = "okay"; }; + +&hsspi { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/bcm96756.dts b/arch/arm/boot/dts/bcm96756.dts index 9a4a87ba9c8a..8b104f3fb14a 100644 --- a/arch/arm/boot/dts/bcm96756.dts +++ b/arch/arm/boot/dts/bcm96756.dts @@ -28,3 +28,7 @@ memory@0 { &uart0 { status = "okay"; }; + +&hsspi { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/bcm96846.dts b/arch/arm/boot/dts/bcm96846.dts index c70ebccabc19..55852c229608 100644 --- a/arch/arm/boot/dts/bcm96846.dts +++ b/arch/arm/boot/dts/bcm96846.dts @@ -28,3 +28,7 @@ memory@0 { &uart0 { status = "okay"; }; + +&hsspi { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/bcm96855.dts b/arch/arm/boot/dts/bcm96855.dts index 4438152561ac..2ad880af2104 100644 --- a/arch/arm/boot/dts/bcm96855.dts +++ b/arch/arm/boot/dts/bcm96855.dts @@ -28,3 +28,7 @@ memory@0 { &uart0 { status = "okay"; }; + +&hsspi { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/bcm96878.dts b/arch/arm/boot/dts/bcm96878.dts index 8fbc175cb452..b7af8ade7a9d 100644 --- a/arch/arm/boot/dts/bcm96878.dts +++ b/arch/arm/boot/dts/bcm96878.dts @@ -28,3 +28,7 @@ memory@0 { &uart0 { status = "okay"; }; + +&hsspi { + status = "okay"; +}; From patchwork Fri Jan 6 20:07:57 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: William Zhang X-Patchwork-Id: 40263 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4e01:0:0:0:0:0 with SMTP id p1csp1010949wrt; Fri, 6 Jan 2023 12:24:40 -0800 (PST) X-Google-Smtp-Source: AMrXdXsdRswqhcdzIMKuTXThiXbJs10AdqHuImmNrx4ufLvKvzngSkYeSlJL/KUsiRV1F+uBVd9R X-Received: by 2002:a17:907:a08d:b0:7c1:6986:2b7c with SMTP id hu13-20020a170907a08d00b007c169862b7cmr43865284ejc.8.1673036680152; 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[2620:137:e000::1:20]) by mx.google.com with ESMTP id sc40-20020a1709078a2800b007c1705dded9si2810835ejc.415.2023.01.06.12.24.15; Fri, 06 Jan 2023 12:24:40 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@broadcom.com header.s=dkimrelay header.b=EPmsICo0; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=broadcom.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236034AbjAFUVA (ORCPT + 99 others); Fri, 6 Jan 2023 15:21:00 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57378 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236565AbjAFUU1 (ORCPT ); Fri, 6 Jan 2023 15:20:27 -0500 Received: from relay.smtp-ext.broadcom.com (lpdvsmtp11.broadcom.com [192.19.166.231]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CC75D82F59; Fri, 6 Jan 2023 12:19:31 -0800 (PST) Received: from mail-lvn-it-01.lvn.broadcom.net (mail-lvn-it-01.lvn.broadcom.net [10.75.146.107]) by relay.smtp-ext.broadcom.com (Postfix) with ESMTP id 93231C0000F1; Fri, 6 Jan 2023 12:09:46 -0800 (PST) DKIM-Filter: OpenDKIM Filter v2.11.0 relay.smtp-ext.broadcom.com 93231C0000F1 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=broadcom.com; s=dkimrelay; t=1673035786; bh=innN3QffeIqx22YomlXtF0nfh/Irr1auB90sJZaCAvw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=EPmsICo05wA1a4dNlAzF+NsVuftJZKDI8jkJWmSOdtC/+0r+mRFtF38kVtpCVnQou ycUqeGPFNbiZYw7GpDvBDEe+BHLrK5vHUSzmBoCeAniGFuQDvaqiJhxiEeovJhjLxQ P+kdLtws6OX/MvD34KnPRbEbRnT4dAv/MkoKWao0= Received: from bcacpedev-irv-3.lvn.broadcom.net (bcacpedev-irv-3.lvn.broadcom.net [10.75.138.105]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail-lvn-it-01.lvn.broadcom.net (Postfix) with ESMTPS id 9118918041CAC6; Fri, 6 Jan 2023 12:09:46 -0800 (PST) Received: by bcacpedev-irv-3.lvn.broadcom.net (Postfix, from userid 28376) id DDC8B101B33; Fri, 6 Jan 2023 12:09:35 -0800 (PST) From: William Zhang To: Linux SPI List , Broadcom Kernel List Cc: anand.gore@broadcom.com, tomer.yacoby@broadcom.com, dan.beygelman@broadcom.com, joel.peshkin@broadcom.com, f.fainelli@gmail.com, jonas.gorski@gmail.com, kursad.oney@broadcom.com, dregan@mail.com, William Zhang , Krzysztof Kozlowski , =?utf-8?b?UmFmYcWC?= =?utf-8?b?IE1pxYJlY2tp?= , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 05/16] arm64: dts: broadcom: bcmbca: Add spi controller node Date: Fri, 6 Jan 2023 12:07:57 -0800 Message-Id: <20230106200809.330769-6-william.zhang@broadcom.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20230106200809.330769-1-william.zhang@broadcom.com> References: <20230106200809.330769-1-william.zhang@broadcom.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE, SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1754306109501257454?= X-GMAIL-MSGID: =?utf-8?q?1754306109501257454?= Add support for HSSPI controller in ARMv8 chip dts files. Signed-off-by: William Zhang --- .../boot/dts/broadcom/bcmbca/bcm4908.dtsi | 17 +++++++++++++++++ .../boot/dts/broadcom/bcmbca/bcm4912.dtsi | 19 +++++++++++++++++++ .../boot/dts/broadcom/bcmbca/bcm63146.dtsi | 18 ++++++++++++++++++ .../boot/dts/broadcom/bcmbca/bcm63158.dtsi | 18 ++++++++++++++++++ .../boot/dts/broadcom/bcmbca/bcm6813.dtsi | 19 +++++++++++++++++++ .../boot/dts/broadcom/bcmbca/bcm6856.dtsi | 17 +++++++++++++++++ .../boot/dts/broadcom/bcmbca/bcm6858.dtsi | 17 +++++++++++++++++ .../boot/dts/broadcom/bcmbca/bcm94908.dts | 4 ++++ .../boot/dts/broadcom/bcmbca/bcm94912.dts | 4 ++++ .../boot/dts/broadcom/bcmbca/bcm963146.dts | 4 ++++ .../boot/dts/broadcom/bcmbca/bcm963158.dts | 4 ++++ .../boot/dts/broadcom/bcmbca/bcm96813.dts | 4 ++++ .../boot/dts/broadcom/bcmbca/bcm96856.dts | 4 ++++ .../boot/dts/broadcom/bcmbca/bcm96858.dts | 4 ++++ 14 files changed, 153 insertions(+) diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi index eb2a78f4e033..169045215d91 100644 --- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi +++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi @@ -107,6 +107,12 @@ periph_clk: periph_clk { clock-frequency = <50000000>; clock-output-names = "periph"; }; + + hsspi_pll: hsspi-pll { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <400000000>; + }; }; soc { @@ -531,6 +537,17 @@ leds: leds@800 { #size-cells = <0>; }; + hsspi: spi@1000{ + #address-cells = <1>; + #size-cells = <0>; + compatible = "brcm,bcm6328-hsspi"; + reg = <0x1000 0x600>; + clocks = <&hsspi_pll &hsspi_pll>; + clock-names = "hsspi", "pll"; + num-cs = <8>; + status = "disabled"; + }; + nand-controller@1800 { #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4912.dtsi b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4912.dtsi index d5bc31980f03..ebacfffc4264 100644 --- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4912.dtsi +++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4912.dtsi @@ -79,6 +79,7 @@ periph_clk: periph-clk { #clock-cells = <0>; clock-frequency = <200000000>; }; + uart_clk: uart-clk { compatible = "fixed-factor-clock"; #clock-cells = <0>; @@ -86,6 +87,12 @@ uart_clk: uart-clk { clock-div = <4>; clock-mult = <1>; }; + + hsspi_pll: hsspi-pll { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <200000000>; + }; }; psci { @@ -117,6 +124,18 @@ bus@ff800000 { #size-cells = <1>; ranges = <0x0 0x0 0xff800000 0x800000>; + hsspi: spi@1000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "brcm,bcmbca-hsspi"; + reg = <0x1000 0x600>, <0x2610 0x4>; + reg-names = "hsspi", "spim-ctrl"; + clocks = <&hsspi_pll &hsspi_pll>; + clock-names = "hsspi", "pll"; + num-cs = <8>; + status = "disabled"; + }; + uart0: serial@12000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x12000 0x1000>; diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm63146.dtsi b/arch/arm64/boot/dts/broadcom/bcmbca/bcm63146.dtsi index 6f805266d3c9..184f8975d8f2 100644 --- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm63146.dtsi +++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm63146.dtsi @@ -60,6 +60,7 @@ periph_clk: periph-clk { #clock-cells = <0>; clock-frequency = <200000000>; }; + uart_clk: uart-clk { compatible = "fixed-factor-clock"; #clock-cells = <0>; @@ -67,6 +68,12 @@ uart_clk: uart-clk { clock-div = <4>; clock-mult = <1>; }; + + hsspi_pll: hsspi-pll { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <200000000>; + }; }; psci { @@ -99,6 +106,17 @@ bus@ff800000 { #size-cells = <1>; ranges = <0x0 0x0 0xff800000 0x800000>; + hsspi: spi@1000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "brcm,bcm6328-hsspi"; + reg = <0x1000 0x600>; + clocks = <&hsspi_pll &hsspi_pll>; + clock-names = "hsspi", "pll"; + num-cs = <8>; + status = "disabled"; + }; + uart0: serial@12000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x12000 0x1000>; diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm63158.dtsi b/arch/arm64/boot/dts/broadcom/bcmbca/bcm63158.dtsi index b982249b80a2..4036ddc3c833 100644 --- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm63158.dtsi +++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm63158.dtsi @@ -79,6 +79,7 @@ periph_clk: periph-clk { #clock-cells = <0>; clock-frequency = <200000000>; }; + uart_clk: uart-clk { compatible = "fixed-factor-clock"; #clock-cells = <0>; @@ -86,6 +87,12 @@ uart_clk: uart-clk { clock-div = <4>; clock-mult = <1>; }; + + hsspi_pll: hsspi-pll { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <400000000>; + }; }; psci { @@ -117,6 +124,17 @@ bus@ff800000 { #size-cells = <1>; ranges = <0x0 0x0 0xff800000 0x800000>; + hsspi: spi@1000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "brcm,bcm6328-hsspi"; + reg = <0x1000 0x600>; + clocks = <&hsspi_pll &hsspi_pll>; + clock-names = "hsspi", "pll"; + num-cs = <8>; + status = "disabled"; + }; + uart0: serial@12000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x12000 0x1000>; diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm6813.dtsi b/arch/arm64/boot/dts/broadcom/bcmbca/bcm6813.dtsi index a996d436e977..d29738e6fd67 100644 --- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm6813.dtsi +++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm6813.dtsi @@ -79,6 +79,7 @@ periph_clk: periph-clk { #clock-cells = <0>; clock-frequency = <200000000>; }; + uart_clk: uart-clk { compatible = "fixed-factor-clock"; #clock-cells = <0>; @@ -86,6 +87,12 @@ uart_clk: uart-clk { clock-div = <4>; clock-mult = <1>; }; + + hsspi_pll: hsspi-pll { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <200000000>; + }; }; psci { @@ -117,6 +124,18 @@ bus@ff800000 { #size-cells = <1>; ranges = <0x0 0x0 0xff800000 0x800000>; + hsspi: spi@1000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "brcm,bcmbca-hsspi"; + reg = <0x1000 0x600>, <0x2610 0x4>; + reg-names = "hsspi", "spim-ctrl"; + clocks = <&hsspi_pll &hsspi_pll>; + clock-names = "hsspi", "pll"; + num-cs = <8>; + status = "disabled"; + }; + uart0: serial@12000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x12000 0x1000>; diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm6856.dtsi b/arch/arm64/boot/dts/broadcom/bcmbca/bcm6856.dtsi index 62c530d4b103..6c5faf175551 100644 --- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm6856.dtsi +++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm6856.dtsi @@ -60,6 +60,12 @@ periph_clk:periph-clk { #clock-cells = <0>; clock-frequency = <200000000>; }; + + hsspi_pll: hsspi-pll { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <400000000>; + }; }; psci { @@ -100,5 +106,16 @@ uart0: serial@640 { clock-names = "refclk"; status = "disabled"; }; + + hsspi: spi@1000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "brcm,bcm6328-hsspi"; + reg = <0x1000 0x600>; + clocks = <&hsspi_pll &hsspi_pll>; + clock-names = "hsspi", "pll"; + num-cs = <8>; + status = "disabled"; + }; }; }; diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm6858.dtsi b/arch/arm64/boot/dts/broadcom/bcmbca/bcm6858.dtsi index 34c7b513d363..edc0003457fd 100644 --- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm6858.dtsi +++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm6858.dtsi @@ -78,6 +78,12 @@ periph_clk:periph-clk { #clock-cells = <0>; clock-frequency = <200000000>; }; + + hsspi_pll: hsspi-pll { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <400000000>; + }; }; psci { @@ -137,5 +143,16 @@ uart0: serial@640 { clock-names = "refclk"; status = "disabled"; }; + + hsspi: spi@1000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "brcm,bcm6328-hsspi"; + reg = <0x1000 0x600>; + clocks = <&hsspi_pll &hsspi_pll>; + clock-names = "hsspi", "pll"; + num-cs = <8>; + status = "disabled"; + }; }; }; diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm94908.dts b/arch/arm64/boot/dts/broadcom/bcmbca/bcm94908.dts index fcbd3c430ace..c4e6e71f6310 100644 --- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm94908.dts +++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm94908.dts @@ -28,3 +28,7 @@ memory@0 { &uart0 { status = "okay"; }; + +&hsspi { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm94912.dts b/arch/arm64/boot/dts/broadcom/bcmbca/bcm94912.dts index a3623e6f6919..e69cd683211a 100644 --- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm94912.dts +++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm94912.dts @@ -28,3 +28,7 @@ memory@0 { &uart0 { status = "okay"; }; + +&hsspi { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm963146.dts b/arch/arm64/boot/dts/broadcom/bcmbca/bcm963146.dts index e39f1e6d4774..db2c82d6dfd8 100644 --- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm963146.dts +++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm963146.dts @@ -28,3 +28,7 @@ memory@0 { &uart0 { status = "okay"; }; + +&hsspi { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm963158.dts b/arch/arm64/boot/dts/broadcom/bcmbca/bcm963158.dts index eba07e0b1ca6..25c12bc63545 100644 --- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm963158.dts +++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm963158.dts @@ -28,3 +28,7 @@ memory@0 { &uart0 { status = "okay"; }; + +&hsspi { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm96813.dts b/arch/arm64/boot/dts/broadcom/bcmbca/bcm96813.dts index af17091ae764..faba21f03120 100644 --- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm96813.dts +++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm96813.dts @@ -28,3 +28,7 @@ memory@0 { &uart0 { status = "okay"; }; + +&hsspi { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm96856.dts b/arch/arm64/boot/dts/broadcom/bcmbca/bcm96856.dts index 032aeb75c983..9808331eede2 100644 --- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm96856.dts +++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm96856.dts @@ -28,3 +28,7 @@ memory@0 { &uart0 { status = "okay"; }; + +&hsspi { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm96858.dts b/arch/arm64/boot/dts/broadcom/bcmbca/bcm96858.dts index 0cbf582f5d54..1f561c8e13b0 100644 --- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm96858.dts +++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm96858.dts @@ -28,3 +28,7 @@ memory@0 { &uart0 { status = "okay"; }; + +&hsspi { + status = "okay"; +}; From patchwork Fri Jan 6 20:07:58 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: William Zhang X-Patchwork-Id: 40264 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4e01:0:0:0:0:0 with SMTP id p1csp1011054wrt; Fri, 6 Jan 2023 12:24:59 -0800 (PST) X-Google-Smtp-Source: AMrXdXuGX5GVAAv+ocnEk7VnXJE5tOOtMwvL9lGnktGb1ku/GKZrojyyVNIZogPHu/IXlLcPrH0D X-Received: by 2002:a05:6402:26d5:b0:495:d3fb:a244 with SMTP id x21-20020a05640226d500b00495d3fba244mr5319537edd.3.1673036698755; Fri, 06 Jan 2023 12:24:58 -0800 (PST) ARC-Seal: i=1; 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[2620:137:e000::1:20]) by mx.google.com with ESMTP id a17-20020aa7d751000000b0047ed405b4a7si2282722eds.224.2023.01.06.12.24.34; Fri, 06 Jan 2023 12:24:58 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@broadcom.com header.s=dkimrelay header.b=ZjnHv1LE; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=broadcom.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229817AbjAFUVZ (ORCPT + 99 others); Fri, 6 Jan 2023 15:21:25 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57294 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235773AbjAFUUz (ORCPT ); Fri, 6 Jan 2023 15:20:55 -0500 Received: from relay.smtp-ext.broadcom.com (relay.smtp-ext.broadcom.com [192.19.166.228]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9345684620; Fri, 6 Jan 2023 12:19:53 -0800 (PST) Received: from mail-lvn-it-01.lvn.broadcom.net (mail-lvn-it-01.lvn.broadcom.net [10.75.146.107]) by relay.smtp-ext.broadcom.com (Postfix) with ESMTP id D5160C0000E2; Fri, 6 Jan 2023 12:09:54 -0800 (PST) DKIM-Filter: OpenDKIM Filter v2.11.0 relay.smtp-ext.broadcom.com D5160C0000E2 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=broadcom.com; s=dkimrelay; t=1673035794; bh=SvLodN4cQ6TEbn+PEQP+YZBLKZOuvyU97FI3sOksrF0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ZjnHv1LEV8rVFlAGo9JwQxczlOuvzW/ybD7ZQ4by8uCkQham3Dj2vxv8adXm/aLVF ENZVCXrYP9pkTLNTxH3GlqKsir4ma60M+VBn4CWpSe4Bm6nuQk7qSU1NU8I0sqscoS giOhM1c7Ok/bFO4wn5ohRe6WVDhV0HAbdSrurcl8= Received: from bcacpedev-irv-3.lvn.broadcom.net (bcacpedev-irv-3.lvn.broadcom.net [10.75.138.105]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail-lvn-it-01.lvn.broadcom.net (Postfix) with ESMTPS id D32F618041CAC6; Fri, 6 Jan 2023 12:09:54 -0800 (PST) Received: by bcacpedev-irv-3.lvn.broadcom.net (Postfix, from userid 28376) id 2C07C101B33; Fri, 6 Jan 2023 12:09:48 -0800 (PST) From: William Zhang To: Linux SPI List , Broadcom Kernel List Cc: anand.gore@broadcom.com, tomer.yacoby@broadcom.com, dan.beygelman@broadcom.com, joel.peshkin@broadcom.com, f.fainelli@gmail.com, jonas.gorski@gmail.com, kursad.oney@broadcom.com, dregan@mail.com, William Zhang , Mark Brown , linux-kernel@vger.kernel.org Subject: [PATCH 06/16] spi: bcm63xx-hsspi: Endianness fix for ARM based SoC Date: Fri, 6 Jan 2023 12:07:58 -0800 Message-Id: <20230106200809.330769-7-william.zhang@broadcom.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20230106200809.330769-1-william.zhang@broadcom.com> References: <20230106200809.330769-1-william.zhang@broadcom.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE, SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1754306129635774304?= X-GMAIL-MSGID: =?utf-8?q?1754306129635774304?= HSSPI controller uses big endian for the opcode in the message to the controller ping pong buffer. Use cpu_to_be16 to properly handle the endianness for both big and little endian host. Fixes: 142168eba9dc ("spi: bcm63xx-hsspi: add bcm63xx HSSPI driver") Signed-off-by: Kursad Oney Signed-off-by: William Zhang --- drivers/spi/spi-bcm63xx-hsspi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/spi/spi-bcm63xx-hsspi.c b/drivers/spi/spi-bcm63xx-hsspi.c index b871fd810d80..63682c8ff955 100644 --- a/drivers/spi/spi-bcm63xx-hsspi.c +++ b/drivers/spi/spi-bcm63xx-hsspi.c @@ -194,7 +194,7 @@ static int bcm63xx_hsspi_do_txrx(struct spi_device *spi, struct spi_transfer *t) tx += curr_step; } - __raw_writew(opcode | curr_step, bs->fifo); + __raw_writew(cpu_to_be16(opcode | curr_step), bs->fifo); /* enable interrupt */ __raw_writel(HSSPI_PINGx_CMD_DONE(0), From patchwork Fri Jan 6 20:07:59 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: William Zhang X-Patchwork-Id: 40265 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4e01:0:0:0:0:0 with SMTP id p1csp1011056wrt; Fri, 6 Jan 2023 12:24:59 -0800 (PST) X-Google-Smtp-Source: AMrXdXsVHfooPKupFMXYjZbsENlNilN1o2LksG6NK5IjBm31KlJq6w3RbofIiQoHVWCQCY8LglOb X-Received: by 2002:a05:6402:a55:b0:46c:9a5d:239e with SMTP id bt21-20020a0564020a5500b0046c9a5d239emr47096496edb.13.1673036699365; Fri, 06 Jan 2023 12:24:59 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1673036699; cv=none; d=google.com; s=arc-20160816; b=yinGks8MpLXcziuKtZiBddZYFMuw1p0Q2/hthR9b5Y9k8oD2NYpKiXk6X0lvSB0n8s PFFKFqmR/WoEG2JJB5XerJsEpIjTb8+0rLRm61QTI5WQNsI7vx7OZqzKk8RCgJJSJx7l EXbDCRLjPjsSsrfuZUCLXG3BTKgjs8MpRXDdD4UpUhOT8uhZb7V5a3YFiNIgabl+9z5l AYPZkCLVtTkv6eE/2nC2YckXHRamNDd47sy5lgt5ubspalTmYZflr+tKRoPcQyV/Ni+5 PDriGo37ivFqhYTwHoIKntvuR7eKWlSOLr/OFtB2SaAbMKLKDZx2i5zqlqbH01sxMM6E qbIA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature:dkim-filter; bh=wRcYT7ojyYDd1zuQRkVHiwOLK71LCk+u1QOqaWQ9GZU=; b=UD6DZ/AbUmrYojy/C7ZBKtt7qptPjMpmeF0y3PucoqtYiDlznOyluWiV0tiRxjqhw5 KBCb7SH8IOFUYhBSvQY0WRZjSRxFXVf+MhF8gi5MlOmlDpEUYnBRk0cd6wqdexWBTEv4 9Llda/XK4Ieswpwgd7PU0+9tHuzhZFWwb1UNeMgOh3ncVwaJxv7+8dY21LCD+YuXjSGr nzhZQh7PGmVhmfGff4FzBnO3WvueutsqdrpBzoeIYsUYPCDB19YyDs4v3lxH28xyzGfH MH03re/OgLVVIRdSwQIQNPTHbyobNfOUpsNC8P1BRIZ2L9obWsCmcJU6PbnxYTz27KtK /FMQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@broadcom.com header.s=dkimrelay header.b=jmHte0+e; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=broadcom.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id q19-20020a056402519300b0047f0a0bc793si2963910edd.352.2023.01.06.12.24.34; Fri, 06 Jan 2023 12:24:59 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@broadcom.com header.s=dkimrelay header.b=jmHte0+e; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=broadcom.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236111AbjAFUVW (ORCPT + 99 others); Fri, 6 Jan 2023 15:21:22 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57298 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235695AbjAFUUy (ORCPT ); Fri, 6 Jan 2023 15:20:54 -0500 Received: from relay.smtp-ext.broadcom.com (lpdvsmtp09.broadcom.com [192.19.166.228]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7A3FE84619; Fri, 6 Jan 2023 12:19:53 -0800 (PST) Received: from mail-lvn-it-01.lvn.broadcom.net (mail-lvn-it-01.lvn.broadcom.net [10.75.146.107]) by relay.smtp-ext.broadcom.com (Postfix) with ESMTP id 20386C0000E4; Fri, 6 Jan 2023 12:09:58 -0800 (PST) DKIM-Filter: OpenDKIM Filter v2.11.0 relay.smtp-ext.broadcom.com 20386C0000E4 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=broadcom.com; s=dkimrelay; t=1673035798; bh=kULL+jS6s3TbEdnopz1j9+j+pURxcCnfZ3AKuAKy3OQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=jmHte0+eQgGwnKrnDzqyuIYcN4B6tEVTW0vuhnKH5r82KGvovBgImYq21oxPdHIi3 /dsOwQ9S682iFagZ5NnxbMBTw3AoftDU4/NHucTjkr9VRxrxz5ZYd2RvNRTc6F1H55 +VreAcBPuFYhH2BtcS0FdZExLnKTVne8769dWrVk= Received: from bcacpedev-irv-3.lvn.broadcom.net (bcacpedev-irv-3.lvn.broadcom.net [10.75.138.105]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail-lvn-it-01.lvn.broadcom.net (Postfix) with ESMTPS id 1E43918041CAC6; Fri, 6 Jan 2023 12:09:58 -0800 (PST) Received: by bcacpedev-irv-3.lvn.broadcom.net (Postfix, from userid 28376) id 16805101B33; Fri, 6 Jan 2023 12:09:58 -0800 (PST) From: William Zhang To: Linux SPI List , Broadcom Kernel List Cc: anand.gore@broadcom.com, tomer.yacoby@broadcom.com, dan.beygelman@broadcom.com, joel.peshkin@broadcom.com, f.fainelli@gmail.com, jonas.gorski@gmail.com, kursad.oney@broadcom.com, dregan@mail.com, William Zhang , Mark Brown , linux-kernel@vger.kernel.org Subject: [PATCH 07/16] spi: bcm63xx-hsspi: Add polling mode support Date: Fri, 6 Jan 2023 12:07:59 -0800 Message-Id: <20230106200809.330769-8-william.zhang@broadcom.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20230106200809.330769-1-william.zhang@broadcom.com> References: <20230106200809.330769-1-william.zhang@broadcom.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE, SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1754306130049947766?= X-GMAIL-MSGID: =?utf-8?q?1754306130049947766?= Polling mode provides better throughput in general by avoiding the interrupt overhead as the maximum data size one interrupt can handle is only 512 bytes. When interrupt is not defined in the HSSPI dts node, driver switches to polling mode for controller SPI message processing. Also add driver banner message when the driver is loaded successfully. When test on a Broadcom BCM47622(ARM A7 dual core) reference board with WINBOND W25N01GV SPI NAND chip at 100MHz SPI clock using the MTD speed test suite, it shows about 15% improvement on the write and 30% on the read: ** Interrupt mode ** mtd_speedtest: MTD device: 0 count: 16 mtd_speedtest: MTD device size 134217728, eraseblock size 131072, page size 2048, count of eraseblocks 1024, pages per eraseblock 64, OOB size 64 mtd_test: scanning for bad eraseblocks mtd_test: scanned 16 eraseblocks, 0 are bad mtd_speedtest: testing eraseblock write speed mtd_speedtest: eraseblock write speed is 3072 KiB/s mtd_speedtest: testing eraseblock read speed mtd_speedtest: eraseblock read speed is 6690 KiB/s mtd_speedtest: testing page write speed mtd_speedtest: page write speed is 3066 KiB/s mtd_speedtest: testing page read speed mtd_speedtest: page read speed is 6762 KiB/s mtd_speedtest: testing 2 page write speed mtd_speedtest: 2 page write speed is 3071 KiB/s mtd_speedtest: testing 2 page read speed mtd_speedtest: 2 page read speed is 6772 KiB/s ** Polling mode ** mtd_speedtest: MTD device: 0 count: 16 mtd_speedtest: MTD device size 134217728, eraseblock size 131072, page size 2048, count of eraseblocks 1024, pages per eraseblock 64, OOB size 64 mtd_test: scanning for bad eraseblocks mtd_test: scanned 16 eraseblocks, 0 are bad mtd_speedtest: testing eraseblock write speed mtd_speedtest: eraseblock write speed is 3542 KiB/s mtd_speedtest: testing eraseblock read speed mtd_speedtest: eraseblock read speed is 8825 KiB/s mtd_speedtest: testing page write speed mtd_speedtest: page write speed is 3563 KiB/s mtd_speedtest: testing page read speed mtd_speedtest: page read speed is 8787 KiB/s mtd_speedtest: testing 2 page write speed mtd_speedtest: 2 page write speed is 3572 KiB/s mtd_speedtest: testing 2 page read speed mtd_speedtest: 2 page read speed is 8806 KiB/s Signed-off-by: William Zhang --- drivers/spi/spi-bcm63xx-hsspi.c | 49 +++++++++++++++++++++++++-------- 1 file changed, 38 insertions(+), 11 deletions(-) diff --git a/drivers/spi/spi-bcm63xx-hsspi.c b/drivers/spi/spi-bcm63xx-hsspi.c index 63682c8ff955..2b4cdf7e7002 100644 --- a/drivers/spi/spi-bcm63xx-hsspi.c +++ b/drivers/spi/spi-bcm63xx-hsspi.c @@ -57,6 +57,7 @@ #define PINGPONG_CMD_SS_SHIFT 12 #define HSSPI_PINGPONG_STATUS_REG(x) (0x84 + (x) * 0x40) +#define HSSPI_PINGPONG_STATUS_SRC_BUSY BIT(1) #define HSSPI_PROFILE_CLK_CTRL_REG(x) (0x100 + (x) * 0x20) #define CLK_CTRL_FREQ_CTRL_MASK 0x0000ffff @@ -96,6 +97,7 @@ #define HSSPI_SPI_MAX_CS 8 #define HSSPI_BUS_NUM 1 /* 0 is legacy SPI */ +#define HSSPI_POLL_STATUS_TIMEOUT_MS 100 struct bcm63xx_hsspi { struct completion done; @@ -109,6 +111,7 @@ struct bcm63xx_hsspi { u32 speed_hz; u8 cs_polarity; + int irq; }; static void bcm63xx_hsspi_set_cs(struct bcm63xx_hsspi *bs, unsigned int cs, @@ -163,6 +166,8 @@ static int bcm63xx_hsspi_do_txrx(struct spi_device *spi, struct spi_transfer *t) int step_size = HSSPI_BUFFER_LEN; const u8 *tx = t->tx_buf; u8 *rx = t->rx_buf; + u32 val; + unsigned long limit; bcm63xx_hsspi_set_clk(bs, spi, t->speed_hz); bcm63xx_hsspi_set_cs(bs, spi->chip_select, true); @@ -197,8 +202,9 @@ static int bcm63xx_hsspi_do_txrx(struct spi_device *spi, struct spi_transfer *t) __raw_writew(cpu_to_be16(opcode | curr_step), bs->fifo); /* enable interrupt */ - __raw_writel(HSSPI_PINGx_CMD_DONE(0), - bs->regs + HSSPI_INT_MASK_REG); + if (bs->irq > 0) + __raw_writel(HSSPI_PINGx_CMD_DONE(0), + bs->regs + HSSPI_INT_MASK_REG); /* start the transfer */ __raw_writel(!chip_select << PINGPONG_CMD_SS_SHIFT | @@ -206,9 +212,21 @@ static int bcm63xx_hsspi_do_txrx(struct spi_device *spi, struct spi_transfer *t) PINGPONG_COMMAND_START_NOW, bs->regs + HSSPI_PINGPONG_COMMAND_REG(0)); - if (wait_for_completion_timeout(&bs->done, HZ) == 0) { - dev_err(&bs->pdev->dev, "transfer timed out!\n"); - return -ETIMEDOUT; + if (bs->irq > 0) { + if (wait_for_completion_timeout(&bs->done, HZ) == 0) + goto err_timeout; + } else { + /* polling mode checks for status busy bit */ + limit = jiffies + msecs_to_jiffies(HSSPI_POLL_STATUS_TIMEOUT_MS); + while (!time_after(jiffies, limit)) { + val = __raw_readl(bs->regs + HSSPI_PINGPONG_STATUS_REG(0)); + if (val & HSSPI_PINGPONG_STATUS_SRC_BUSY) + cpu_relax(); + else + break; + } + if (val & HSSPI_PINGPONG_STATUS_SRC_BUSY) + goto err_timeout; } if (rx) { @@ -220,6 +238,10 @@ static int bcm63xx_hsspi_do_txrx(struct spi_device *spi, struct spi_transfer *t) } return 0; + +err_timeout: + dev_err(&bs->pdev->dev, "transfer timed out!\n"); + return -ETIMEDOUT; } static int bcm63xx_hsspi_setup(struct spi_device *spi) @@ -338,8 +360,8 @@ static int bcm63xx_hsspi_probe(struct platform_device *pdev) u32 reg, rate, num_cs = HSSPI_SPI_MAX_CS; struct reset_control *reset; - irq = platform_get_irq(pdev, 0); - if (irq < 0) + irq = platform_get_irq_optional(pdev, 0); + if (irq < 0 && irq != -ENXIO) return irq; regs = devm_platform_ioremap_resource(pdev, 0); @@ -398,6 +420,7 @@ static int bcm63xx_hsspi_probe(struct platform_device *pdev) bs->regs = regs; bs->speed_hz = rate; bs->fifo = (u8 __iomem *)(bs->regs + HSSPI_FIFO_REG(0)); + bs->irq = irq; mutex_init(&bs->bus_mutex); init_completion(&bs->done); @@ -434,11 +457,13 @@ static int bcm63xx_hsspi_probe(struct platform_device *pdev) __raw_writel(reg | GLOBAL_CTRL_CLK_GATE_SSOFF, bs->regs + HSSPI_GLOBAL_CTRL_REG); - ret = devm_request_irq(dev, irq, bcm63xx_hsspi_interrupt, IRQF_SHARED, - pdev->name, bs); + if (bs->irq > 0) { + ret = devm_request_irq(dev, irq, bcm63xx_hsspi_interrupt, IRQF_SHARED, + pdev->name, bs); - if (ret) - goto out_put_master; + if (ret) + goto out_put_master; + } pm_runtime_enable(&pdev->dev); @@ -447,6 +472,8 @@ static int bcm63xx_hsspi_probe(struct platform_device *pdev) if (ret) goto out_pm_disable; + dev_info(dev, "Broadcom 63XX High Speed SPI Controller driver"); + return 0; out_pm_disable: From patchwork Fri Jan 6 20:08:00 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: William Zhang X-Patchwork-Id: 40249 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4e01:0:0:0:0:0 with SMTP id p1csp1007200wrt; Fri, 6 Jan 2023 12:14:13 -0800 (PST) X-Google-Smtp-Source: AMrXdXvexm0s9ICGhRW1tgJje0uoaxX+EzxeUEYDVjOUpJ9Nd1oM0vyfKw4NFOW3kQfyUS02CR3/ X-Received: by 2002:a17:906:b056:b0:7af:bc9:5e51 with SMTP id bj22-20020a170906b05600b007af0bc95e51mr45442379ejb.41.1673036052996; Fri, 06 Jan 2023 12:14:12 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1673036052; cv=none; d=google.com; s=arc-20160816; b=A9wT2xVrcLoi2Cdo2FHyO0V160eNxXN4i9yB5wU+iDFwmr/nFhWscVW8XLHsygA5hZ DY5BWt2Dhr3qJo1IKcW+iL+uAeLhjGPSzQXKnV+NN9L8og+tjp5u2YsrzwBhvllYPxol w10iRZFbVTbDd/EJZXZ8xpiD4KiUkJCppz1qtgNM1HFcnprDUUlGUkGTQg+kUv+reRRF eprcHQJh0/f45Lq2ulvZTvC5xQfdFlXW8OXEJoAVJWEYDMqm79SVuI4m7o1aCBNt51FN poifpTSg6eHmvaI1X6tiGCW53lSnyaTGdmPLpWu/xzZ1w11GIHxM7pteQoMs81Kv1rJ+ 8Ofw== ARC-Message-Signature: i=1; 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[2620:137:e000::1:20]) by mx.google.com with ESMTP id sh39-20020a1709076ea700b007c0a7286be2si2296491ejc.770.2023.01.06.12.13.48; Fri, 06 Jan 2023 12:14:12 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@broadcom.com header.s=dkimrelay header.b=ADlmj8ng; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=broadcom.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236232AbjAFUKX (ORCPT + 99 others); Fri, 6 Jan 2023 15:10:23 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48794 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236270AbjAFUKJ (ORCPT ); Fri, 6 Jan 2023 15:10:09 -0500 X-Greylist: delayed 65 seconds by postgrey-1.37 at lindbergh.monkeyblade.net; Fri, 06 Jan 2023 12:10:08 PST Received: from relay.smtp-ext.broadcom.com (lpdvsmtp11.broadcom.com [192.19.166.231]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F3BF4840A1; Fri, 6 Jan 2023 12:10:08 -0800 (PST) Received: from mail-lvn-it-01.lvn.broadcom.net (mail-lvn-it-01.lvn.broadcom.net [10.75.146.107]) by relay.smtp-ext.broadcom.com (Postfix) with ESMTP id 8933EC0000F3; Fri, 6 Jan 2023 12:10:08 -0800 (PST) DKIM-Filter: OpenDKIM Filter v2.11.0 relay.smtp-ext.broadcom.com 8933EC0000F3 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=broadcom.com; s=dkimrelay; t=1673035808; bh=PByAEycu10rflViW/6kaHG6GMcMou2/z7vIJQgSOhbY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ADlmj8ngphLysDXnVZdunyvPaZSKmSkxIBLrvhHwIXzFbuKV7k2lOAstPb72ONwLs KbTauncGWnyBaFePUYKueprnbm/BHLziYpRFlCFS/TeHyvfzdKX6FSQNdFmHvqoBAb 2CRvRFRNESP4ytkm6us3TodZMppMdcLww6lUog3w= Received: from bcacpedev-irv-3.lvn.broadcom.net (bcacpedev-irv-3.lvn.broadcom.net [10.75.138.105]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail-lvn-it-01.lvn.broadcom.net (Postfix) with ESMTPS id 8734618041CAC6; Fri, 6 Jan 2023 12:10:08 -0800 (PST) Received: by bcacpedev-irv-3.lvn.broadcom.net (Postfix, from userid 28376) id DDBE5101B33; Fri, 6 Jan 2023 12:10:01 -0800 (PST) From: William Zhang To: Linux SPI List , Broadcom Kernel List Cc: anand.gore@broadcom.com, tomer.yacoby@broadcom.com, dan.beygelman@broadcom.com, joel.peshkin@broadcom.com, f.fainelli@gmail.com, jonas.gorski@gmail.com, kursad.oney@broadcom.com, dregan@mail.com, William Zhang , Mark Brown , linux-kernel@vger.kernel.org Subject: [PATCH 08/16] spi: bcm63xx-hsspi: Handle cs_change correctly Date: Fri, 6 Jan 2023 12:08:00 -0800 Message-Id: <20230106200809.330769-9-william.zhang@broadcom.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20230106200809.330769-1-william.zhang@broadcom.com> References: <20230106200809.330769-1-william.zhang@broadcom.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE, SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1754305451992733154?= X-GMAIL-MSGID: =?utf-8?q?1754305451992733154?= The kernel SPI interface includes the cs_change flag that alters how the CS behaves. If we're in the middle of transfers, it tells us to unselect the CS momentarily since the target device requires that. If we're at the end of a transfer, it tells us to keep the CS selected, perhaps because the next transfer is likely targeted to the same device. We implement this scheme in the HSSPI driver in this change. Prior to this change, the CS would toggle momentarily if cs_change was set for the last transfer. This can be ignored by some or most devices, but the Microchip TPM2 device does not ignore it. With the change, the behavior is corrected and the 'glitch' is eliminated. Signed-off-by: Kursad Oney Signed-off-by: William Zhang --- drivers/spi/spi-bcm63xx-hsspi.c | 28 +++++++++++++++++++++------- 1 file changed, 21 insertions(+), 7 deletions(-) diff --git a/drivers/spi/spi-bcm63xx-hsspi.c b/drivers/spi/spi-bcm63xx-hsspi.c index 2b4cdf7e7002..f2b1b83bd6d4 100644 --- a/drivers/spi/spi-bcm63xx-hsspi.c +++ b/drivers/spi/spi-bcm63xx-hsspi.c @@ -290,6 +290,7 @@ static int bcm63xx_hsspi_transfer_one(struct spi_master *master, int status = -EINVAL; int dummy_cs; u32 reg; + bool restore_polarity = true; /* This controller does not support keeping CS active during idle. * To work around this, we use the following ugly hack: @@ -317,16 +318,29 @@ static int bcm63xx_hsspi_transfer_one(struct spi_master *master, spi_transfer_delay_exec(t); - if (t->cs_change) + /* + * cs_change rules: + * (1) cs_change = 0 && last_xfer = 0: + * Do not touch the CS. On to the next xfer. + * (2) cs_change = 1 && last_xfer = 0: + * Set cs = false before the next xfer. + * (3) cs_change = 0 && last_xfer = 1: + * We want CS to be deactivated. So do NOT set cs = false, + * instead just restore the original polarity. This has the + * same effect of deactivating the CS. + * (4) cs_change = 1 && last_xfer = 1: + * We want to keep CS active. So do NOT set cs = false, and + * make sure we do NOT reverse polarity. + */ + if (t->cs_change && !list_is_last(&t->transfer_list, &msg->transfers)) bcm63xx_hsspi_set_cs(bs, spi->chip_select, false); + + restore_polarity = !t->cs_change; } - mutex_lock(&bs->bus_mutex); - reg = __raw_readl(bs->regs + HSSPI_GLOBAL_CTRL_REG); - reg &= ~GLOBAL_CTRL_CS_POLARITY_MASK; - reg |= bs->cs_polarity; - __raw_writel(reg, bs->regs + HSSPI_GLOBAL_CTRL_REG); - mutex_unlock(&bs->bus_mutex); + bcm63xx_hsspi_set_cs(bs, dummy_cs, false); + if (restore_polarity) + bcm63xx_hsspi_set_cs(bs, spi->chip_select, false); msg->status = status; spi_finalize_current_message(master); From patchwork Fri Jan 6 20:08:01 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: William Zhang X-Patchwork-Id: 40240 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4e01:0:0:0:0:0 with SMTP id p1csp1006520wrt; Fri, 6 Jan 2023 12:12:32 -0800 (PST) X-Google-Smtp-Source: AMrXdXuTseFxAyYh75uhcuX696ZSZxPM4otlYEPzVgNdnXOyN4eJi3Q1U0uGCHbfJuoaAIJtsyF3 X-Received: by 2002:a17:906:8a58:b0:7c1:6981:d062 with SMTP id gx24-20020a1709068a5800b007c16981d062mr49900697ejc.72.1673035952563; Fri, 06 Jan 2023 12:12:32 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1673035952; cv=none; d=google.com; s=arc-20160816; b=GmaSDQWmhGUbaTr5aiof3eYw5V2dAe0s62f5mWqG/KVjO+M9vu2/Y3AkXlNZQHGeq4 r9kg29O6DPlDw5rTKV9w1CwJttRbBwSawdniCiuqE14KT4meStTeCSyanmpizBcCDgpU wu5oxTQGOrQhnRlHYRLrShJ+fVot2j8MmC3aTF1QKn3XTnNdP97icbWqF+a5sok5m7V6 N7JoqmApl9CHHeqmhGTApe/r1DINvGfhogavjAiYWdjWJ/QWVUYWRVXj0x4fssyZXUFQ jXjUA2S3xEVMkYlnGdTa4KMRXabC6WXD1/ugKMk0C+p4PXAVL96ULb0uB1ZspghvIZCF 1wOQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature:dkim-filter; bh=st0EA8HqRQn4ry/Ey+XSOXkwR07jrKA7+GlhoKjAAB4=; b=EbkpPGCcK7VwUmYignovPezl0hsn5zuZMU6kvcKpQCLab/M6XC7zt9chIJdyTA2Eii FvA38SO9p96rAzV6fCK0Qcg0C47Bmt4SKjxVLr5CpP1J/4b7adjSo8+r7k6jxsEad4CB 8pTusNrJ/YM5BTI+XWX3WCb5Hfyy5VCwbRb+/qezfBnQhlOR1QAzlcxsNKU7bhdLiwq2 lT1zjtcQLq7QW8vQQPwkfPgorE6JNGuJANCCis8enVDts3uoBHjny/8O8DG0/HpHhBtD fn+h+tRYmPFjaMgCBCynNcbTqpNs2qRjS8ZoclYbEGEE4YR7KcWcdwGp82wA5y8Jfe7S NKYQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@broadcom.com header.s=dkimrelay header.b=oopxl0l0; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=broadcom.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id sz15-20020a1709078b0f00b007ae30b550e5si1829977ejc.854.2023.01.06.12.12.08; Fri, 06 Jan 2023 12:12:32 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@broadcom.com header.s=dkimrelay header.b=oopxl0l0; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=broadcom.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236290AbjAFUK1 (ORCPT + 99 others); Fri, 6 Jan 2023 15:10:27 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48810 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236287AbjAFUKN (ORCPT ); Fri, 6 Jan 2023 15:10:13 -0500 Received: from relay.smtp-ext.broadcom.com (lpdvsmtp09.broadcom.com [192.19.166.228]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 25BBC8408B; Fri, 6 Jan 2023 12:10:12 -0800 (PST) Received: from mail-lvn-it-01.lvn.broadcom.net (mail-lvn-it-01.lvn.broadcom.net [10.75.146.107]) by relay.smtp-ext.broadcom.com (Postfix) with ESMTP id CEBA9C0000E5; Fri, 6 Jan 2023 12:10:11 -0800 (PST) DKIM-Filter: OpenDKIM Filter v2.11.0 relay.smtp-ext.broadcom.com CEBA9C0000E5 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=broadcom.com; s=dkimrelay; t=1673035811; bh=5BERIlcA8JzJwkeyjt1ucRTPCFChZtPk/WPUu85nbtk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=oopxl0l0RyXwtIlpWOxkb8UsK5cP960dZ2Hs4NnG8K3M17cJlr1hSbCMej5KX0HTI /9+kR1DxAd5UhBqFQoKo8uS+NyoSU04fd1IPvYZnqA4Rcvu3cMr6suGv4G+10jtbEi sLYCGhf6kmPMnLfwHuyQnBGjlA8oX1+/ZG7EVmtg= Received: from bcacpedev-irv-3.lvn.broadcom.net (bcacpedev-irv-3.lvn.broadcom.net [10.75.138.105]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail-lvn-it-01.lvn.broadcom.net (Postfix) with ESMTPS id CCC5818041CAC6; Fri, 6 Jan 2023 12:10:11 -0800 (PST) Received: by bcacpedev-irv-3.lvn.broadcom.net (Postfix, from userid 28376) id 184DB101B3C; Fri, 6 Jan 2023 12:10:05 -0800 (PST) From: William Zhang To: Linux SPI List , Broadcom Kernel List Cc: anand.gore@broadcom.com, tomer.yacoby@broadcom.com, dan.beygelman@broadcom.com, joel.peshkin@broadcom.com, f.fainelli@gmail.com, jonas.gorski@gmail.com, kursad.oney@broadcom.com, dregan@mail.com, William Zhang , Mark Brown , linux-kernel@vger.kernel.org Subject: [PATCH 09/16] spi: bcm63xx-hsspi: Fix multi-bit mode setting Date: Fri, 6 Jan 2023 12:08:01 -0800 Message-Id: <20230106200809.330769-10-william.zhang@broadcom.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20230106200809.330769-1-william.zhang@broadcom.com> References: <20230106200809.330769-1-william.zhang@broadcom.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE, SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1754305346931941976?= X-GMAIL-MSGID: =?utf-8?q?1754305346931941976?= Currently the driver always sets the controller to dual data bit mode for both tx and rx data in the profile mode control register even for single data bit transfer. Luckily the opcode is set correctly according to SPI transfer data bit width so it does not actually cause issues. This change fixes the problem by setting tx and rx data bit mode field correctly according to the actual SPI transfer tx and rx data bit width. Fixes: 142168eba9dc ("spi: bcm63xx-hsspi: add bcm63xx HSSPI driver") Signed-off-by: William Zhang --- drivers/spi/spi-bcm63xx-hsspi.c | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/drivers/spi/spi-bcm63xx-hsspi.c b/drivers/spi/spi-bcm63xx-hsspi.c index f2b1b83bd6d4..398c412dcc3e 100644 --- a/drivers/spi/spi-bcm63xx-hsspi.c +++ b/drivers/spi/spi-bcm63xx-hsspi.c @@ -166,7 +166,7 @@ static int bcm63xx_hsspi_do_txrx(struct spi_device *spi, struct spi_transfer *t) int step_size = HSSPI_BUFFER_LEN; const u8 *tx = t->tx_buf; u8 *rx = t->rx_buf; - u32 val; + u32 val = 0; unsigned long limit; bcm63xx_hsspi_set_clk(bs, spi, t->speed_hz); @@ -183,11 +183,16 @@ static int bcm63xx_hsspi_do_txrx(struct spi_device *spi, struct spi_transfer *t) step_size -= HSSPI_OPCODE_LEN; if ((opcode == HSSPI_OP_READ && t->rx_nbits == SPI_NBITS_DUAL) || - (opcode == HSSPI_OP_WRITE && t->tx_nbits == SPI_NBITS_DUAL)) + (opcode == HSSPI_OP_WRITE && t->tx_nbits == SPI_NBITS_DUAL)) { opcode |= HSSPI_OP_MULTIBIT; - __raw_writel(1 << MODE_CTRL_MULTIDATA_WR_SIZE_SHIFT | - 1 << MODE_CTRL_MULTIDATA_RD_SIZE_SHIFT | 0xff, + if (t->rx_nbits == SPI_NBITS_DUAL) + val |= 1 << MODE_CTRL_MULTIDATA_RD_SIZE_SHIFT; + if (t->tx_nbits == SPI_NBITS_DUAL) + val |= 1 << MODE_CTRL_MULTIDATA_WR_SIZE_SHIFT; + } + + __raw_writel(val | 0xff, bs->regs + HSSPI_PROFILE_MODE_CTRL_REG(chip_select)); while (pending > 0) { From patchwork Fri Jan 6 20:08:02 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: William Zhang X-Patchwork-Id: 40241 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4e01:0:0:0:0:0 with SMTP id p1csp1006521wrt; Fri, 6 Jan 2023 12:12:32 -0800 (PST) X-Google-Smtp-Source: AMrXdXvYug2VD1nkgF0Hhr77ynphXip07HaoXWloZfESGsDBDEJhUGswub9D4+Cu/egarPSPzpIa X-Received: by 2002:a17:906:aec3:b0:7c0:f719:838d with SMTP id me3-20020a170906aec300b007c0f719838dmr54757639ejb.36.1673035952630; Fri, 06 Jan 2023 12:12:32 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1673035952; cv=none; d=google.com; s=arc-20160816; b=w54OdSFYNWuogAp2gU0SeSAgazN1v7o24NzckuORskspbUkd1G2iT5Dox0jROYuYpN XL2b4lWUHUrAhUaWFhU71dTSjZYnn4w44RJ1UitfVcQk1qa/Ss3VpYHBQpfjN5o2veuo 8LrGX6doH0s9+pTLVuu7GFj8XdPvF4+l8Cerd7Ges78D/eoEbhL/Is86kKEzzoTiqjwG E0i3q6Y+lmQgWELU/XvFOjYZltMuyqWFBXBrFKS8BV36/8aNT0+3nZWapiTBVw8tKx2M SEEE3jPnORrr6ZqaY8B7lHWKlh1y4zS1dJLyryafdS9CMmTZ2hDWKRn4XG54dViuCtO3 borg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature:dkim-filter; bh=vhVeNLVYgqTVFjEDGp6Ik4PvXVjZZqYgVRzBfznbSjI=; b=Tvi64KWFZUcMN3NHiwvjJJxc0tdhUOlf3IMUPDH/jAUKx+p+a99EUZ8Xv/7AmB1wO0 Mf4kWbfkbuvCGtcg5XQoOqw3azRcPO/yFjAwyPYQia+7gFKDgdKZH1Z8IThQRq+A0uMN iEMX9/XkcQ57DGKhjRwd2gkVm42+KE9FUduwZ++cA7eB+ilzx1vGdmihsqRT3xTI4B3e nF4BY/HW/71qgMDtWvviNGMk4g52/LxLBH5rB7HkK821e/nBU7acW4wk4mdACPckfvpG QvB3Q5eCO39AEGzb5KjdUjpfFCY2fE59hS9o6YxPPM4LMwBfewNEULSff11hvcNmMzZD NF6A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@broadcom.com header.s=dkimrelay header.b=QGQP7Xdy; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=broadcom.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id dd18-20020a1709069b9200b0084cb8449ec3si2629641ejc.397.2023.01.06.12.12.08; Fri, 06 Jan 2023 12:12:32 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@broadcom.com header.s=dkimrelay header.b=QGQP7Xdy; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=broadcom.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236308AbjAFUKb (ORCPT + 99 others); Fri, 6 Jan 2023 15:10:31 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48854 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236293AbjAFUKO (ORCPT ); Fri, 6 Jan 2023 15:10:14 -0500 Received: from relay.smtp-ext.broadcom.com (lpdvsmtp11.broadcom.com [192.19.166.231]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 731B38408B; Fri, 6 Jan 2023 12:10:13 -0800 (PST) Received: from mail-lvn-it-01.lvn.broadcom.net (mail-lvn-it-01.lvn.broadcom.net [10.75.146.107]) by relay.smtp-ext.broadcom.com (Postfix) with ESMTP id 2712CC0000F3; Fri, 6 Jan 2023 12:10:13 -0800 (PST) DKIM-Filter: OpenDKIM Filter v2.11.0 relay.smtp-ext.broadcom.com 2712CC0000F3 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=broadcom.com; s=dkimrelay; t=1673035813; bh=ozSkN0f8jvndbN+kSJY2e89x7m1Mt90y0tVuB9JkQIs=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=QGQP7XdyE4qHmMs9NebEfOoBP8nFhPVua9PyEK+QrScvoyG4mEy2xGmOJ/Qx/eEHX r/vEgEBeW4W25cAxOA2pyKhS4JESbf6OwusZHk2W3BqTqKdiuFlpGVp7qnzKgd9y8P muwAYLhJujEU3h4XlpUppIaVEorZByV5RDoztTJc= Received: from bcacpedev-irv-3.lvn.broadcom.net (bcacpedev-irv-3.lvn.broadcom.net [10.75.138.105]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail-lvn-it-01.lvn.broadcom.net (Postfix) with ESMTPS id 253A018041CAC6; Fri, 6 Jan 2023 12:10:13 -0800 (PST) Received: by bcacpedev-irv-3.lvn.broadcom.net (Postfix, from userid 28376) id 663BB101B5D; Fri, 6 Jan 2023 12:10:06 -0800 (PST) From: William Zhang To: Linux SPI List , Broadcom Kernel List Cc: anand.gore@broadcom.com, tomer.yacoby@broadcom.com, dan.beygelman@broadcom.com, joel.peshkin@broadcom.com, f.fainelli@gmail.com, jonas.gorski@gmail.com, kursad.oney@broadcom.com, dregan@mail.com, William Zhang , Mark Brown , linux-kernel@vger.kernel.org Subject: [PATCH 10/16] spi: bcm63xx-hsspi: Make dummy cs workaround as an option Date: Fri, 6 Jan 2023 12:08:02 -0800 Message-Id: <20230106200809.330769-11-william.zhang@broadcom.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20230106200809.330769-1-william.zhang@broadcom.com> References: <20230106200809.330769-1-william.zhang@broadcom.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE, SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1754305346904604581?= X-GMAIL-MSGID: =?utf-8?q?1754305346904604581?= Due to the controller limitation to keep the chip select low during the bus idle time between the transfer, a dummy cs workaround was used when this driver was first upstreamed to the kernel. The workaround picks dummy_cs as !actual_cs and usually cs is 0 and dummy cs is 1. But this does not work out in all the situations as customer reported issues for their board design. Due to SPI block design constrain, the controller works in different mode internally depending on the clock. When clock is 30MHz or above, controller works in faster mode and cs 1 signal is used internally as feedback from the pad. So cs 1 pin must be brought out and configured as chip select function in pinmux. When clock is below 30MHz, only cs 0 pin is used. In summary when clock is below 30MHz, the workaround always works as only cs 0 is involved. For clock faster than 30MHz, it require cs1 pin used in the board design and configured as chip selection function. In a typical usage of SPI flash on cs 0 that normally runs at 100MHz, cs 1 pin must be used in the board design but this is not always the case for many customer boards. For voice daughtercard usage, the SoC alway uses internal cs 7 for voice card SPI control. Then it requires cs 0 pin as the dummy cs but board with voice design may not use cs 0 pin at all. The controller actually has a prepend feature that can combine multiple SPI transfers in a SPI message into one single transfer when the transfers meet certain requirements. So there is no need for keeping cs low when the message only has one transfer. Most of the SPI devices including SPI NOR, SPI NAND flash, Broadcom voice card and etc can use this feature without the dummy cs workaround. This patch makes the dummy cs workaround as an option based on the dts flag brcm,use-cs-workaround. By default dummy cs workaround is hard coded to enable. We will use the prepend feature and disable this workaround as default in the next patch of this series unless this flag is set in dts. Signed-off-by: William Zhang --- drivers/spi/spi-bcm63xx-hsspi.c | 55 +++++++++++++++++++++------------ 1 file changed, 36 insertions(+), 19 deletions(-) diff --git a/drivers/spi/spi-bcm63xx-hsspi.c b/drivers/spi/spi-bcm63xx-hsspi.c index 398c412dcc3e..b5043251edec 100644 --- a/drivers/spi/spi-bcm63xx-hsspi.c +++ b/drivers/spi/spi-bcm63xx-hsspi.c @@ -111,6 +111,7 @@ struct bcm63xx_hsspi { u32 speed_hz; u8 cs_polarity; + bool use_cs_workaround; int irq; }; @@ -161,16 +162,18 @@ static int bcm63xx_hsspi_do_txrx(struct spi_device *spi, struct spi_transfer *t) { struct bcm63xx_hsspi *bs = spi_master_get_devdata(spi->master); unsigned int chip_select = spi->chip_select; + unsigned int hw_cs; u16 opcode = 0; int pending = t->len; int step_size = HSSPI_BUFFER_LEN; const u8 *tx = t->tx_buf; u8 *rx = t->rx_buf; - u32 val = 0; unsigned long limit; + u32 reg = 0; bcm63xx_hsspi_set_clk(bs, spi, t->speed_hz); - bcm63xx_hsspi_set_cs(bs, spi->chip_select, true); + if (bs->use_cs_workaround) + bcm63xx_hsspi_set_cs(bs, spi->chip_select, true); if (tx && rx) opcode = HSSPI_OP_READ_WRITE; @@ -187,14 +190,15 @@ static int bcm63xx_hsspi_do_txrx(struct spi_device *spi, struct spi_transfer *t) opcode |= HSSPI_OP_MULTIBIT; if (t->rx_nbits == SPI_NBITS_DUAL) - val |= 1 << MODE_CTRL_MULTIDATA_RD_SIZE_SHIFT; + reg |= 1 << MODE_CTRL_MULTIDATA_RD_SIZE_SHIFT; if (t->tx_nbits == SPI_NBITS_DUAL) - val |= 1 << MODE_CTRL_MULTIDATA_WR_SIZE_SHIFT; + reg |= 1 << MODE_CTRL_MULTIDATA_WR_SIZE_SHIFT; } - __raw_writel(val | 0xff, + __raw_writel(reg | 0xff, bs->regs + HSSPI_PROFILE_MODE_CTRL_REG(chip_select)); + hw_cs = bs->use_cs_workaround ? !chip_select : chip_select; while (pending > 0) { int curr_step = min_t(int, step_size, pending); @@ -211,11 +215,10 @@ static int bcm63xx_hsspi_do_txrx(struct spi_device *spi, struct spi_transfer *t) __raw_writel(HSSPI_PINGx_CMD_DONE(0), bs->regs + HSSPI_INT_MASK_REG); - /* start the transfer */ - __raw_writel(!chip_select << PINGPONG_CMD_SS_SHIFT | - chip_select << PINGPONG_CMD_PROFILE_SHIFT | - PINGPONG_COMMAND_START_NOW, - bs->regs + HSSPI_PINGPONG_COMMAND_REG(0)); + reg = hw_cs << PINGPONG_CMD_SS_SHIFT | + chip_select << PINGPONG_CMD_PROFILE_SHIFT | + PINGPONG_COMMAND_START_NOW; + __raw_writel(reg, bs->regs + HSSPI_PINGPONG_COMMAND_REG(0)); if (bs->irq > 0) { if (wait_for_completion_timeout(&bs->done, HZ) == 0) @@ -223,14 +226,15 @@ static int bcm63xx_hsspi_do_txrx(struct spi_device *spi, struct spi_transfer *t) } else { /* polling mode checks for status busy bit */ limit = jiffies + msecs_to_jiffies(HSSPI_POLL_STATUS_TIMEOUT_MS); + while (!time_after(jiffies, limit)) { - val = __raw_readl(bs->regs + HSSPI_PINGPONG_STATUS_REG(0)); - if (val & HSSPI_PINGPONG_STATUS_SRC_BUSY) + reg = __raw_readl(bs->regs + HSSPI_PINGPONG_STATUS_REG(0)); + if (reg & HSSPI_PINGPONG_STATUS_SRC_BUSY) cpu_relax(); else break; } - if (val & HSSPI_PINGPONG_STATUS_SRC_BUSY) + if (reg & HSSPI_PINGPONG_STATUS_SRC_BUSY) goto err_timeout; } @@ -311,8 +315,10 @@ static int bcm63xx_hsspi_transfer_one(struct spi_master *master, * e. At the end restore the polarities again to their default values. */ - dummy_cs = !spi->chip_select; - bcm63xx_hsspi_set_cs(bs, dummy_cs, true); + if (bs->use_cs_workaround) { + dummy_cs = !spi->chip_select; + bcm63xx_hsspi_set_cs(bs, dummy_cs, true); + } list_for_each_entry(t, &msg->transfers, transfer_list) { status = bcm63xx_hsspi_do_txrx(spi, t); @@ -343,9 +349,11 @@ static int bcm63xx_hsspi_transfer_one(struct spi_master *master, restore_polarity = !t->cs_change; } - bcm63xx_hsspi_set_cs(bs, dummy_cs, false); - if (restore_polarity) - bcm63xx_hsspi_set_cs(bs, spi->chip_select, false); + if (bs->use_cs_workaround) { + bcm63xx_hsspi_set_cs(bs, dummy_cs, false); + if (restore_polarity) + bcm63xx_hsspi_set_cs(bs, spi->chip_select, false); + } msg->status = status; spi_finalize_current_message(master); @@ -445,8 +453,17 @@ static int bcm63xx_hsspi_probe(struct platform_device *pdev) init_completion(&bs->done); master->dev.of_node = dev->of_node; - if (!dev->of_node) + if (!dev->of_node) { master->bus_num = HSSPI_BUS_NUM; + /* use dummy cs workaround on old mips dev with no dts support */ + bs->use_cs_workaround = true; + } else { + /* check if dummy cs workaround is needed from device tree */ + bs->use_cs_workaround = of_property_read_bool( + dev->of_node, "brcm,use-cs-workaround"); + } + /* tmp hack. hard code to use cs workaround before prepend mode is added */ + bs->use_cs_workaround = true; of_property_read_u32(dev->of_node, "num-cs", &num_cs); if (num_cs > 8) { From patchwork Fri Jan 6 20:08:03 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: William Zhang X-Patchwork-Id: 40259 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4e01:0:0:0:0:0 with SMTP id p1csp1010025wrt; Fri, 6 Jan 2023 12:21:54 -0800 (PST) X-Google-Smtp-Source: AMrXdXs0yL8DZi37AytXO+aZcBkCQxwyLQxa5O9LuK1ZVQv5qhEmB+zQ31EAJmyGYLdyhx0lPvpg X-Received: by 2002:a17:906:11d9:b0:7ae:7c4e:195b with SMTP id o25-20020a17090611d900b007ae7c4e195bmr47808629eja.22.1673036514545; Fri, 06 Jan 2023 12:21:54 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1673036514; cv=none; d=google.com; s=arc-20160816; b=MAW+mMF3nLL/VqiZEWR2AQtxnVoERjAovwfpCu4Sk2jlEdw/bwA/W9aVfbnWZaqZCT xsB/JFhUJaMCPsIludHX6in1AODAC/j5aD3JNR2msiTt+qDhRK6Y7XFkD4xJPlASZx48 HlTpXZYaYZjV/x3IvBJi2TMACpKTZyrNlO1+nhJTa2fxkpJ2yjYpjt621h9aeFuFqMQs admNES3SVNfmcQRDEtGoIoRBxHuQvhXZEmMLYyNw7sgyKMD9nCMu0N/PwqzKe7qCm7qj B9yBVx8YYuiBhNuZ7Crcq+XtLK+SROeFD4/CtD7GBPEx+dT5DBSsZpEziyMprqSIyUah D97A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature:dkim-filter; bh=00X8gT2qA2J37km7tBN3Tpncnor9t++2YI6Ujp2HnR0=; b=Acni0TLuA589PtQKfrjeE+HVfblSWWWK0vFAUmuoiPFD3B4seqAa9yBC8pzaLEdhqg IPtC5ZRLQa06Dg0YuiI2Rb+2Utk2kHzSzf1TGjVJ2Qju6ErJyDPH2i2OOBk1LD0c7UmC /VjCCdlgM07xZAfezyc1lt7etm4BEA8iQEQhfZHw6BVrXhxXd9cB3a9M3hFn2amEyHmr ILjSfAbgZiRTDg+RDx5A5dl0hc2/ef2Z088AnJP4JG1LQQ8op4qC0/E/Q/GyHMbcsl4b xLz+WJcVYgnZUaMfwKqUCUr2Z2F3/iXK6Bw1NRqPz2AIDNix9KObcCWm4tEIpxtLW7M8 1n1g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@broadcom.com header.s=dkimrelay header.b=oop0CaGf; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=broadcom.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id dr6-20020a170907720600b0084d197a89e2si2042721ejc.957.2023.01.06.12.21.30; Fri, 06 Jan 2023 12:21:54 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@broadcom.com header.s=dkimrelay header.b=oop0CaGf; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=broadcom.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235904AbjAFUT2 (ORCPT + 99 others); Fri, 6 Jan 2023 15:19:28 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56550 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236190AbjAFUS7 (ORCPT ); Fri, 6 Jan 2023 15:18:59 -0500 X-Greylist: delayed 547 seconds by postgrey-1.37 at lindbergh.monkeyblade.net; Fri, 06 Jan 2023 12:18:26 PST Received: from relay.smtp-ext.broadcom.com (saphodev.broadcom.com [192.19.144.205]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DB5933C703; Fri, 6 Jan 2023 12:18:26 -0800 (PST) Received: from mail-lvn-it-01.lvn.broadcom.net (mail-lvn-it-01.lvn.broadcom.net [10.75.146.107]) by relay.smtp-ext.broadcom.com (Postfix) with ESMTP id 01CD8C0000F3; Fri, 6 Jan 2023 12:10:08 -0800 (PST) DKIM-Filter: OpenDKIM Filter v2.11.0 relay.smtp-ext.broadcom.com 01CD8C0000F3 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=broadcom.com; s=dkimrelay; t=1673035808; bh=4+QaWMX/RdX5N5eXa+dYncIa2WJfkQ1n8sBRvbRvhKo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=oop0CaGfTnDH6irNfURuZIwOxH34Z2FSP7W8zZlDLCQ+oKrknMUkavcarcLIkvhT/ PNyfzqr13eiQFb+zEj3vugv2hsrMs8ApOYE14ZX9hCZ5u2ED3AE+mR+fTHBC/ca4Lg UaaB8sZ7F4b0l5a8D7rLgZ+Vvu8N4MmoPuJiRQzw= Received: from bcacpedev-irv-3.lvn.broadcom.net (bcacpedev-irv-3.lvn.broadcom.net [10.75.138.105]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail-lvn-it-01.lvn.broadcom.net (Postfix) with ESMTPS id BDCA318041CAC6; Fri, 6 Jan 2023 12:10:07 -0800 (PST) Received: by bcacpedev-irv-3.lvn.broadcom.net (Postfix, from userid 28376) id B2D48101B5E; Fri, 6 Jan 2023 12:10:07 -0800 (PST) From: William Zhang To: Linux SPI List , Broadcom Kernel List Cc: anand.gore@broadcom.com, tomer.yacoby@broadcom.com, dan.beygelman@broadcom.com, joel.peshkin@broadcom.com, f.fainelli@gmail.com, jonas.gorski@gmail.com, kursad.oney@broadcom.com, dregan@mail.com, William Zhang , Mark Brown , linux-kernel@vger.kernel.org Subject: [PATCH 11/16] spi: bcm63xx-hsspi: Add prepend feature support Date: Fri, 6 Jan 2023 12:08:03 -0800 Message-Id: <20230106200809.330769-12-william.zhang@broadcom.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20230106200809.330769-1-william.zhang@broadcom.com> References: <20230106200809.330769-1-william.zhang@broadcom.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE, SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1754305936218780585?= X-GMAIL-MSGID: =?utf-8?q?1754305936218780585?= Multiple transfers within a SPI message may be combined into one transfer to the controller using its prepend feature. A SPI message is prependable only if the following are all true: * One or more half duplex write transfer * Optional full duplex read/write at the end * No delay and cs_change between transfers Most of the SPI device meets this requirements such as SPI NOR, SPI NAND flash, Broadcom SPI voice card and etc. So this patch makes use of the prepend feature as the default mode as it has no board design requirement as the dummy cs workaround needs. For any SPI device that does not meet the above requirement, dummy cs mode can be used as long as the board design meets its cs pin usage requirement or runs below 30MHz clock speed. Signed-off-by: William Zhang --- drivers/spi/spi-bcm63xx-hsspi.c | 246 ++++++++++++++++++++++++++++---- 1 file changed, 221 insertions(+), 25 deletions(-) diff --git a/drivers/spi/spi-bcm63xx-hsspi.c b/drivers/spi/spi-bcm63xx-hsspi.c index b5043251edec..58f2b495c13c 100644 --- a/drivers/spi/spi-bcm63xx-hsspi.c +++ b/drivers/spi/spi-bcm63xx-hsspi.c @@ -113,8 +113,208 @@ struct bcm63xx_hsspi { u8 cs_polarity; bool use_cs_workaround; int irq; + u32 prepend_cnt; + u8 *prepend_buf; }; +static void bcm63xx_hsspi_set_clk(struct bcm63xx_hsspi *bs, + struct spi_device *spi, int hz); + +static size_t bcm63xx_hsspi_max_message_size(struct spi_device *spi) +{ + return HSSPI_BUFFER_LEN - HSSPI_OPCODE_LEN; +} + +static int bcm63xx_hsspi_wait_cmd(struct bcm63xx_hsspi *bs) +{ + unsigned long limit; + u32 reg = 0; + int rc = 0; + + if (bs->irq > 0) { + if (wait_for_completion_timeout(&bs->done, HZ) == 0) + rc = 1; + } else { + /* polling mode checks for status busy bit */ + limit = jiffies + msecs_to_jiffies(HSSPI_POLL_STATUS_TIMEOUT_MS); + + while (!time_after(jiffies, limit)) { + reg = __raw_readl(bs->regs + HSSPI_PINGPONG_STATUS_REG(0)); + if (reg & HSSPI_PINGPONG_STATUS_SRC_BUSY) + cpu_relax(); + else + break; + } + if (reg & HSSPI_PINGPONG_STATUS_SRC_BUSY) + rc = 1; + } + + if (rc) + dev_err(&bs->pdev->dev, "transfer timed out!\n"); + + return rc; +} + +static bool bcm63xx_check_msg_prependable(struct spi_master *master, + struct spi_message *msg, + struct spi_transfer *t_prepend) +{ + + struct bcm63xx_hsspi *bs = spi_master_get_devdata(master); + bool prepend = false, tx_only = false; + struct spi_transfer *t; + + /* If cs dummy workaround used, no need to prepend message */ + if (bs->use_cs_workaround) + goto check_done; + + /* + * Multiple transfers within a message may be combined into one transfer + * to the controller using its prepend feature. A SPI message is prependable + * only if the following are all true: + * 1. One or more half duplex write transfer + * 2. Optional full duplex read/write at the end + * 3. No delay and cs_change between transfers + */ + bs->prepend_cnt = 0; + list_for_each_entry(t, &msg->transfers, transfer_list) { + if ((spi_delay_to_ns(&t->delay, t) > 0) || t->cs_change) { + dev_warn(&bs->pdev->dev, + "Delay or cs change not supported in prepend mode!\n"); + break; + } + + tx_only = false; + if (t->tx_buf && !t->rx_buf) { + tx_only = true; + if (bs->prepend_cnt + t->len > + (HSSPI_BUFFER_LEN - HSSPI_OPCODE_LEN)) { + dev_warn(&bs->pdev->dev, + "exceed max buf len, abort prepending transfers!\n"); + break; + } + memcpy(bs->prepend_buf + bs->prepend_cnt, t->tx_buf, + t->len); + bs->prepend_cnt += t->len; + } else { + if (!list_is_last(&t->transfer_list, &msg->transfers)) { + dev_warn(&bs->pdev->dev, + "rx/tx_rx transfer not supported when it is not last one!\n"); + break; + } + } + + if (list_is_last(&t->transfer_list, &msg->transfers)) { + memcpy(t_prepend, t, sizeof(struct spi_transfer)); + + if (tx_only) { + /* + * if the last one is also a tx only transfer, merge all + * them into one single tx transfer + */ + t_prepend->len = bs->prepend_cnt; + t_prepend->tx_buf = bs->prepend_buf; + bs->prepend_cnt = 0; + } else { + /* + * if the last one is not a tx only transfer, all the previous + * transfers are sent through prepend bytes and make sure it does + * not exceed the max prepend len + */ + if (bs->prepend_cnt > HSSPI_MAX_PREPEND_LEN) { + dev_warn(&bs->pdev->dev, + "exceed max prepend len, abort prepending transfers!\n"); + break; + } + } + prepend = true; + } + } + +check_done: + if (!bs->use_cs_workaround && !prepend) + dev_warn(&bs->pdev->dev, + "Msg not prependable and cs war not used. Transfer may fail!\n"); + + return prepend; +} + +static int bcm63xx_hsspi_do_prepend_txrx(struct spi_device *spi, + struct spi_transfer *t) +{ + struct bcm63xx_hsspi *bs = spi_master_get_devdata(spi->master); + unsigned int chip_select = spi->chip_select; + u16 opcode = 0; + const u8 *tx = t->tx_buf; + u8 *rx = t->rx_buf; + u32 reg = 0; + + /* + * shouldn't happen as we set the max_message_size in the probe. + * but check it again in case some driver does not honor the max size + */ + if (t->len + bs->prepend_cnt > (HSSPI_BUFFER_LEN - HSSPI_OPCODE_LEN)) { + dev_warn(&bs->pdev->dev, + "Prepend message large than fifo size len %d prepend %d\n", + t->len, bs->prepend_cnt); + return -EINVAL; + } + + bcm63xx_hsspi_set_clk(bs, spi, t->speed_hz); + + if (tx && rx) + opcode = HSSPI_OP_READ_WRITE; + else if (tx) + opcode = HSSPI_OP_WRITE; + else if (rx) + opcode = HSSPI_OP_READ; + + if ((opcode == HSSPI_OP_READ && t->rx_nbits == SPI_NBITS_DUAL) || + (opcode == HSSPI_OP_WRITE && t->tx_nbits == SPI_NBITS_DUAL)) { + opcode |= HSSPI_OP_MULTIBIT; + + if (t->rx_nbits == SPI_NBITS_DUAL) { + reg |= 1 << MODE_CTRL_MULTIDATA_RD_SIZE_SHIFT; + reg |= bs->prepend_cnt << MODE_CTRL_MULTIDATA_RD_STRT_SHIFT; + } + if (t->tx_nbits == SPI_NBITS_DUAL) { + reg |= 1 << MODE_CTRL_MULTIDATA_WR_SIZE_SHIFT; + reg |= bs->prepend_cnt << MODE_CTRL_MULTIDATA_WR_STRT_SHIFT; + } + } + + reg |= bs->prepend_cnt << MODE_CTRL_PREPENDBYTE_CNT_SHIFT; + __raw_writel(reg | 0xff, + bs->regs + HSSPI_PROFILE_MODE_CTRL_REG(chip_select)); + + reinit_completion(&bs->done); + if (bs->prepend_cnt) + memcpy_toio(bs->fifo + HSSPI_OPCODE_LEN, bs->prepend_buf, + bs->prepend_cnt); + if (tx) + memcpy_toio(bs->fifo + HSSPI_OPCODE_LEN + bs->prepend_cnt, tx, + t->len); + + __raw_writew(cpu_to_be16(opcode | t->len), bs->fifo); + /* enable interrupt */ + if (bs->irq > 0) + __raw_writel(HSSPI_PINGx_CMD_DONE(0), bs->regs + HSSPI_INT_MASK_REG); + + /* start the transfer */ + reg = chip_select << PINGPONG_CMD_SS_SHIFT | + chip_select << PINGPONG_CMD_PROFILE_SHIFT | + PINGPONG_COMMAND_START_NOW; + __raw_writel(reg, bs->regs + HSSPI_PINGPONG_COMMAND_REG(0)); + + if (bcm63xx_hsspi_wait_cmd(bs)) + return -ETIMEDOUT; + + if (rx) + memcpy_fromio(rx, bs->fifo, t->len); + + return 0; +} + static void bcm63xx_hsspi_set_cs(struct bcm63xx_hsspi *bs, unsigned int cs, bool active) { @@ -168,7 +368,6 @@ static int bcm63xx_hsspi_do_txrx(struct spi_device *spi, struct spi_transfer *t) int step_size = HSSPI_BUFFER_LEN; const u8 *tx = t->tx_buf; u8 *rx = t->rx_buf; - unsigned long limit; u32 reg = 0; bcm63xx_hsspi_set_clk(bs, spi, t->speed_hz); @@ -220,23 +419,8 @@ static int bcm63xx_hsspi_do_txrx(struct spi_device *spi, struct spi_transfer *t) PINGPONG_COMMAND_START_NOW; __raw_writel(reg, bs->regs + HSSPI_PINGPONG_COMMAND_REG(0)); - if (bs->irq > 0) { - if (wait_for_completion_timeout(&bs->done, HZ) == 0) - goto err_timeout; - } else { - /* polling mode checks for status busy bit */ - limit = jiffies + msecs_to_jiffies(HSSPI_POLL_STATUS_TIMEOUT_MS); - - while (!time_after(jiffies, limit)) { - reg = __raw_readl(bs->regs + HSSPI_PINGPONG_STATUS_REG(0)); - if (reg & HSSPI_PINGPONG_STATUS_SRC_BUSY) - cpu_relax(); - else - break; - } - if (reg & HSSPI_PINGPONG_STATUS_SRC_BUSY) - goto err_timeout; - } + if (bcm63xx_hsspi_wait_cmd(bs)) + return -ETIMEDOUT; if (rx) { memcpy_fromio(rx, bs->fifo, curr_step); @@ -247,10 +431,6 @@ static int bcm63xx_hsspi_do_txrx(struct spi_device *spi, struct spi_transfer *t) } return 0; - -err_timeout: - dev_err(&bs->pdev->dev, "transfer timed out!\n"); - return -ETIMEDOUT; } static int bcm63xx_hsspi_setup(struct spi_device *spi) @@ -300,8 +480,16 @@ static int bcm63xx_hsspi_transfer_one(struct spi_master *master, int dummy_cs; u32 reg; bool restore_polarity = true; + struct spi_transfer t_prepend; + + if (bcm63xx_check_msg_prependable(master, msg, &t_prepend)) { + status = bcm63xx_hsspi_do_prepend_txrx(spi, &t_prepend); + msg->actual_length += (t_prepend.len + bs->prepend_cnt); + goto msg_done; + } - /* This controller does not support keeping CS active during idle. + /* + * This controller does not support keeping CS active during idle. * To work around this, we use the following ugly hack: * * a. Invert the target chip select's polarity so it will be active. @@ -355,6 +543,7 @@ static int bcm63xx_hsspi_transfer_one(struct spi_master *master, bcm63xx_hsspi_set_cs(bs, spi->chip_select, false); } +msg_done: msg->status = status; spi_finalize_current_message(master); @@ -448,6 +637,11 @@ static int bcm63xx_hsspi_probe(struct platform_device *pdev) bs->speed_hz = rate; bs->fifo = (u8 __iomem *)(bs->regs + HSSPI_FIFO_REG(0)); bs->irq = irq; + bs->prepend_buf = devm_kzalloc(dev, HSSPI_BUFFER_LEN, GFP_KERNEL); + if (!bs->prepend_buf) { + ret = -ENOMEM; + goto out_put_master; + } mutex_init(&bs->bus_mutex); init_completion(&bs->done); @@ -462,8 +656,6 @@ static int bcm63xx_hsspi_probe(struct platform_device *pdev) bs->use_cs_workaround = of_property_read_bool( dev->of_node, "brcm,use-cs-workaround"); } - /* tmp hack. hard code to use cs workaround before prepend mode is added */ - bs->use_cs_workaround = true; of_property_read_u32(dev->of_node, "num-cs", &num_cs); if (num_cs > 8) { @@ -474,6 +666,10 @@ static int bcm63xx_hsspi_probe(struct platform_device *pdev) master->num_chipselect = num_cs; master->setup = bcm63xx_hsspi_setup; master->transfer_one_message = bcm63xx_hsspi_transfer_one; + if (!bs->use_cs_workaround) { + master->max_transfer_size = bcm63xx_hsspi_max_message_size; + master->max_message_size = bcm63xx_hsspi_max_message_size; + } master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_RX_DUAL | SPI_TX_DUAL; master->bits_per_word_mask = SPI_BPW_MASK(8); From patchwork Fri Jan 6 20:08:04 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: William Zhang X-Patchwork-Id: 40239 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4e01:0:0:0:0:0 with SMTP id p1csp1006497wrt; Fri, 6 Jan 2023 12:12:28 -0800 (PST) X-Google-Smtp-Source: AMrXdXubcjaRYBtpDLWiWyISezqSxVSjC1l/6XhpRo7cjr1szvE0pkDQCn7mGWJ+y5cIjq54ayCd X-Received: by 2002:a05:6402:449a:b0:47d:88f3:1165 with SMTP id er26-20020a056402449a00b0047d88f31165mr54824267edb.12.1673035948843; Fri, 06 Jan 2023 12:12:28 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1673035948; cv=none; d=google.com; s=arc-20160816; b=u/94zwi0Nm0LNwJ7k1j2cxGxZ5sYvgUuthJyIYlLYNrT4XNm/7ibkW+7AZnMU8VVVP /p5UYLfLYSHvMXCJeMyTno58QHm8f0lSv8IsIJTSbS4o5ZtLFIM2VkHRXpyarpL7vEj0 jZ9PhPnFeJoRZpwS9u/D2MAcifci0R2YlZLvRAOvDGhHh6w1auI62qP/s4o2+7swoAID SBauGQxy+wZeBp2PP8xYQ/jL1CM0jYt1hn25wFvQD33Uz7QZyrWH0xDST943wUuuSSa/ 08lBW2LEndZ5ts56+YMEqbJmpCQt32UfoAgfL5wgod7AJaWYEtnH23eoM0JB3shBYP6a fRlA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature:dkim-filter; bh=tATAvPz7X93jUNnhHgHVcJk3F1gh420xzBAbBm8xvtg=; b=MtjnpnczBCEknC2QTUQdetNYDAmKQs95JSyfhVrxrZBA66dfXaYC2b/7AEssrbjBV+ dQ6DJEMf6EIQzlSN6gBHqNXeWTVetMMUFCYK5ylW0h0dtN3ObdNNV/M/4aHch2wBisP9 tv2APL3kiOfNIUg5SBf0cbZ1N9V+vgtqc/Q2mumT8XOOU9IVXAv9i2YW0b8+T/+WSPir x8tdTvjlNatRmXJE6z2WBDmSFymnWsSkVvRq3L7m6MRHQU8zYomjiRsSYhCGgz9BptVR MzceoeqBzlDOnr1YLPYhS5IrLvyI0efMGAte7kWifZIbp9v3+REiShed8X3kY5mggejN b6XA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@broadcom.com header.s=dkimrelay header.b=UIkHd96c; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=broadcom.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id h2-20020a056402280200b0047f9f11dab3si2757521ede.25.2023.01.06.12.12.04; Fri, 06 Jan 2023 12:12:28 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@broadcom.com header.s=dkimrelay header.b=UIkHd96c; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=broadcom.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236208AbjAFUKV (ORCPT + 99 others); Fri, 6 Jan 2023 15:10:21 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48800 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236276AbjAFUKK (ORCPT ); Fri, 6 Jan 2023 15:10:10 -0500 Received: from relay.smtp-ext.broadcom.com (lpdvsmtp09.broadcom.com [192.19.166.228]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F0E6784091; Fri, 6 Jan 2023 12:10:09 -0800 (PST) Received: from mail-lvn-it-01.lvn.broadcom.net (mail-lvn-it-01.lvn.broadcom.net [10.75.146.107]) by relay.smtp-ext.broadcom.com (Postfix) with ESMTP id 7AFA1C0000E5; Fri, 6 Jan 2023 12:10:09 -0800 (PST) DKIM-Filter: OpenDKIM Filter v2.11.0 relay.smtp-ext.broadcom.com 7AFA1C0000E5 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=broadcom.com; s=dkimrelay; t=1673035809; bh=Je0b6vbxzSyApfV57XdMzbBAJ1OOxv2L5PniIWRhOb4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=UIkHd96clSQEmxDCYtME2IZM4/bQh4OVa9WI5jipic9lQxUqn89pKNRCFUhsCFaa7 9ge+SieN2xiWGdy9s3thRUlVRvJO56llhxvTZany8GVlJjwSZKjxk+2K/me88D0CJu bqambiYVxLut4VLalRL3o3NLaF3N7yopSmN67o8k= Received: from bcacpedev-irv-3.lvn.broadcom.net (bcacpedev-irv-3.lvn.broadcom.net [10.75.138.105]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail-lvn-it-01.lvn.broadcom.net (Postfix) with ESMTPS id 7916F18041CAC6; Fri, 6 Jan 2023 12:10:09 -0800 (PST) Received: by bcacpedev-irv-3.lvn.broadcom.net (Postfix, from userid 28376) id 74787101B33; Fri, 6 Jan 2023 12:10:09 -0800 (PST) From: William Zhang To: Linux SPI List , Broadcom Kernel List Cc: anand.gore@broadcom.com, tomer.yacoby@broadcom.com, dan.beygelman@broadcom.com, joel.peshkin@broadcom.com, f.fainelli@gmail.com, jonas.gorski@gmail.com, kursad.oney@broadcom.com, dregan@mail.com, William Zhang , Mark Brown , linux-kernel@vger.kernel.org Subject: [PATCH 12/16] spi: bcm63xx-hsspi: Add clock gate disable option support Date: Fri, 6 Jan 2023 12:08:04 -0800 Message-Id: <20230106200809.330769-13-william.zhang@broadcom.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20230106200809.330769-1-william.zhang@broadcom.com> References: <20230106200809.330769-1-william.zhang@broadcom.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE, SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1754305342875715419?= X-GMAIL-MSGID: =?utf-8?q?1754305342875715419?= Some SPI device such as Broadcom ISI based voice daughtercard requires SPI clock running even when chip select is deasserted. By default the controller turn off or gate the clock when cs is not active to save power. This change adds an option to support such device and keep the clock running when flag brcm,no-clk-gate is present in the SPI device node or when the SPI device driver clear the GATE_CLK_SSOFF flag in the device controller data field. Signed-off-by: William Zhang --- drivers/spi/spi-bcm63xx-hsspi.c | 46 +++++++++++++++++++++++++++++++++ 1 file changed, 46 insertions(+) diff --git a/drivers/spi/spi-bcm63xx-hsspi.c b/drivers/spi/spi-bcm63xx-hsspi.c index 58f2b495c13c..be4ca01f332a 100644 --- a/drivers/spi/spi-bcm63xx-hsspi.c +++ b/drivers/spi/spi-bcm63xx-hsspi.c @@ -23,6 +23,13 @@ #include #include +/* Broadcom Legacy SPI device driver flags */ +#define SPIDEV_CONTROLLER_STATE_SET BIT(31) +#define SPIDEV_CONTROLLER_STATE_GATE_CLK_SSOFF BIT(29) + +#define spidev_ctrl_data(spi) \ + ((u32)((uintptr_t)(spi)->controller_data)) + #define HSSPI_GLOBAL_CTRL_REG 0x0 #define GLOBAL_CTRL_CS_POLARITY_SHIFT 0 #define GLOBAL_CTRL_CS_POLARITY_MASK 0x000000ff @@ -120,11 +127,40 @@ struct bcm63xx_hsspi { static void bcm63xx_hsspi_set_clk(struct bcm63xx_hsspi *bs, struct spi_device *spi, int hz); +static inline int bcm63xx_hsspi_dev_no_clk_gate(struct spi_device *spi) +{ + u32 ctrl_data = 0; + + /* check spi device dn first */ + if (of_property_read_bool(spi->dev.of_node, "brcm,no-clk-gate")) + return 1; + + /* check spi dev controller data for legacy device support */ + ctrl_data = spidev_ctrl_data(spi); + return ((ctrl_data & SPIDEV_CONTROLLER_STATE_SET) && + !(ctrl_data & SPIDEV_CONTROLLER_STATE_GATE_CLK_SSOFF)); +} + static size_t bcm63xx_hsspi_max_message_size(struct spi_device *spi) { return HSSPI_BUFFER_LEN - HSSPI_OPCODE_LEN; } +static void bcm63xx_hsspi_restore_clk_gate(struct bcm63xx_hsspi *bs, + struct spi_device *spi) +{ + u32 reg = 0; + + /* check if clk gate setting was previously turned off */ + if (bcm63xx_hsspi_dev_no_clk_gate(spi)) { + mutex_lock(&bs->bus_mutex); + reg = __raw_readl(bs->regs + HSSPI_GLOBAL_CTRL_REG); + reg |= GLOBAL_CTRL_CLK_GATE_SSOFF; + __raw_writel(reg, bs->regs + HSSPI_GLOBAL_CTRL_REG); + mutex_unlock(&bs->bus_mutex); + } +} + static int bcm63xx_hsspi_wait_cmd(struct bcm63xx_hsspi *bs) { unsigned long limit; @@ -354,6 +390,12 @@ static void bcm63xx_hsspi_set_clk(struct bcm63xx_hsspi *bs, reg &= ~GLOBAL_CTRL_CLK_POLARITY; if (spi->mode & SPI_CPOL) reg |= GLOBAL_CTRL_CLK_POLARITY; + + if (bcm63xx_hsspi_dev_no_clk_gate(spi)) + reg &= ~GLOBAL_CTRL_CLK_GATE_SSOFF; + else + reg |= GLOBAL_CTRL_CLK_GATE_SSOFF; + __raw_writel(reg, bs->regs + HSSPI_GLOBAL_CTRL_REG); mutex_unlock(&bs->bus_mutex); } @@ -485,6 +527,7 @@ static int bcm63xx_hsspi_transfer_one(struct spi_master *master, if (bcm63xx_check_msg_prependable(master, msg, &t_prepend)) { status = bcm63xx_hsspi_do_prepend_txrx(spi, &t_prepend); msg->actual_length += (t_prepend.len + bs->prepend_cnt); + bcm63xx_hsspi_restore_clk_gate(bs, spi); goto msg_done; } @@ -543,6 +586,9 @@ static int bcm63xx_hsspi_transfer_one(struct spi_master *master, bcm63xx_hsspi_set_cs(bs, spi->chip_select, false); } + /* restore the default clk gate setting in case spidev turn it off */ + bcm63xx_hsspi_restore_clk_gate(bs, spi); + msg_done: msg->status = status; spi_finalize_current_message(master); From patchwork Fri Jan 6 20:08:05 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: William Zhang X-Patchwork-Id: 40251 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4e01:0:0:0:0:0 with SMTP id p1csp1007242wrt; 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[2620:137:e000::1:20]) by mx.google.com with ESMTP id ef8-20020a05640228c800b00486ac69b9f3si2282156edb.327.2023.01.06.12.13.54; Fri, 06 Jan 2023 12:14:18 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@broadcom.com header.s=dkimrelay header.b=bTSOz+zo; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=broadcom.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236461AbjAFUKi (ORCPT + 99 others); Fri, 6 Jan 2023 15:10:38 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48882 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236200AbjAFUKV (ORCPT ); Fri, 6 Jan 2023 15:10:21 -0500 Received: from relay.smtp-ext.broadcom.com (lpdvacalvio01.broadcom.com [192.19.166.228]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4253B84084; Fri, 6 Jan 2023 12:10:20 -0800 (PST) Received: from mail-lvn-it-01.lvn.broadcom.net (mail-lvn-it-01.lvn.broadcom.net [10.75.146.107]) by relay.smtp-ext.broadcom.com (Postfix) with ESMTP id F12ABC0000E5; Fri, 6 Jan 2023 12:10:19 -0800 (PST) DKIM-Filter: OpenDKIM Filter v2.11.0 relay.smtp-ext.broadcom.com F12ABC0000E5 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=broadcom.com; s=dkimrelay; t=1673035820; bh=KiC8m8hbRUbZZ8J7JMyhYa4Wy5NUsmvaw9AEXPtTsRE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=bTSOz+zoi32DSZV8vKmJe7+27+ywJpVtFdRfmWW5XIdTSdmlYrYOjGC5PpkGKxY6Y wjRrMNJWv5IhBIfGtJcS6hKvKDCjCxYHhs0TIKjDEKLz7TA2ljI4xojmenAAdQw553 zt0n6YZ2eG4y/bKZd6abewsX4dzR98QWY2bRKh9E= Received: from bcacpedev-irv-3.lvn.broadcom.net (bcacpedev-irv-3.lvn.broadcom.net [10.75.138.105]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail-lvn-it-01.lvn.broadcom.net (Postfix) with ESMTPS id EF4BE18041CAC6; Fri, 6 Jan 2023 12:10:19 -0800 (PST) Received: by bcacpedev-irv-3.lvn.broadcom.net (Postfix, from userid 28376) id 48D13101B33; Fri, 6 Jan 2023 12:10:13 -0800 (PST) From: William Zhang To: Linux SPI List , Broadcom Kernel List Cc: anand.gore@broadcom.com, tomer.yacoby@broadcom.com, dan.beygelman@broadcom.com, joel.peshkin@broadcom.com, f.fainelli@gmail.com, jonas.gorski@gmail.com, kursad.oney@broadcom.com, dregan@mail.com, William Zhang , Mark Brown , linux-kernel@vger.kernel.org Subject: [PATCH 13/16] spi: spi-mem: Allow controller supporting mem_ops without exec_op Date: Fri, 6 Jan 2023 12:08:05 -0800 Message-Id: <20230106200809.330769-14-william.zhang@broadcom.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20230106200809.330769-1-william.zhang@broadcom.com> References: <20230106200809.330769-1-william.zhang@broadcom.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE, SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1754305458031214021?= X-GMAIL-MSGID: =?utf-8?q?1754305458031214021?= Currently exec_op is always required if controller driver provides mem_ops. But some controller such as bcm63xx-hsspi may only need to implement other operation like supports_op and use the default execution operation. This patch removes this restriction. Signed-off-by: William Zhang --- drivers/spi/spi-mem.c | 2 +- drivers/spi/spi.c | 13 ++++++------- 2 files changed, 7 insertions(+), 8 deletions(-) diff --git a/drivers/spi/spi-mem.c b/drivers/spi/spi-mem.c index 0c79193d9697..701838b6f0c4 100644 --- a/drivers/spi/spi-mem.c +++ b/drivers/spi/spi-mem.c @@ -325,7 +325,7 @@ int spi_mem_exec_op(struct spi_mem *mem, const struct spi_mem_op *op) if (!spi_mem_internal_supports_op(mem, op)) return -ENOTSUPP; - if (ctlr->mem_ops && !mem->spi->cs_gpiod) { + if (ctlr->mem_ops && ctlr->mem_ops->exec_op && !mem->spi->cs_gpiod) { ret = spi_mem_access_start(mem); if (ret) return ret; diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c index 3cc7bb4d03de..6faa77592e93 100644 --- a/drivers/spi/spi.c +++ b/drivers/spi/spi.c @@ -3051,15 +3051,14 @@ static int spi_controller_check_ops(struct spi_controller *ctlr) * The controller may implement only the high-level SPI-memory like * operations if it does not support regular SPI transfers, and this is * valid use case. - * If ->mem_ops is NULL, we request that at least one of the - * ->transfer_xxx() method be implemented. + * If ->mem_ops or ->mem_ops->exec_op is NULL, we request that at least + * one of the ->transfer_xxx() method be implemented. */ - if (ctlr->mem_ops) { - if (!ctlr->mem_ops->exec_op) - return -EINVAL; - } else if (!ctlr->transfer && !ctlr->transfer_one && + if (!ctlr->mem_ops || (ctlr->mem_ops && !ctlr->mem_ops->exec_op)) { + if (!ctlr->transfer && !ctlr->transfer_one && !ctlr->transfer_one_message) { - return -EINVAL; + return -EINVAL; + } } return 0; From patchwork Fri Jan 6 20:08:06 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: William Zhang X-Patchwork-Id: 40242 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4e01:0:0:0:0:0 with SMTP id p1csp1006526wrt; Fri, 6 Jan 2023 12:12:33 -0800 (PST) X-Google-Smtp-Source: AMrXdXviMWhZ0AJnOXvdx9OtW7PnI+p2VqhwYnJN8S18+DeY+0mKrKkBo7bw890wwapzC8c+EDXV X-Received: by 2002:a17:906:5dad:b0:7c0:dfba:54d3 with SMTP id n13-20020a1709065dad00b007c0dfba54d3mr9023649ejv.20.1673035953674; Fri, 06 Jan 2023 12:12:33 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1673035953; cv=none; d=google.com; s=arc-20160816; b=faG06XUyvdC+CtLwAJ43qwkVtlcXpctioqABal1KGe3HZ+SyvwCRNDsoX7q6fap2Zl FnoA9iMt99aauzBwpgUnG/7vub0JhmWkmnjp7bKKW+5FxalItSC1U/XMs2fsQ9Troihx aWyRZVUYsBkXChKvZV33pzP4xZmXmMQxTXk8bAWfS9Iq+FaaK1sXWP6rYgYEnzlCr88e Cb38Hxtt9W4eqm7UGGgdqhFost9sjKhY+0mMWAsnI96hFyA7kLjV5nVR7J9dMfvWutsB KdGMlhbOmy+08d+asX9AugniAF0pq/h6IxlF+vlBQSdHy1/f7kKhGXxKWP86u7sa9+d9 3p8g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature:dkim-filter; bh=CIxtXVLXHbIkdvY0q8kWHS0WTLY1RTpc54DLksBM/q0=; b=l+jS0XZod2gfBz/yfmSVS5plKOzt8HfjStQEI3eSIe/PRGEcKfOjz+Gk7TB27yBWay JxAr5++qr9myFIR/KijyBEp3qUHQJJQCY4Usq4+nOzLr3Ws+19uSNxRe2NCeGd3e6/02 gCJ7V6X5rEB1fxRdnVuMzmlujycPzol/2HWRH5G2mPIswsc7r5dTEkUR4xkx+xbZyvY9 Qqy0HF5pfzUs5eefKCWssWpM1SemzOf8+XFrPuPqMee0yIHW3tHr979tEz5pl+XXzdPv wY+l6jmjlBOW4SgWd9krLRqBkby0R5TM+TkCsBmxsakz72ch95bWgECjAjEtHps+c/IB sviQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@broadcom.com header.s=dkimrelay header.b=n+9M+jMp; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=broadcom.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id ds4-20020a170907724400b0081a9c3ca4bcsi2427480ejc.379.2023.01.06.12.12.09; Fri, 06 Jan 2023 12:12:33 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@broadcom.com header.s=dkimrelay header.b=n+9M+jMp; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=broadcom.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236379AbjAFUKe (ORCPT + 99 others); Fri, 6 Jan 2023 15:10:34 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48882 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236305AbjAFUKR (ORCPT ); Fri, 6 Jan 2023 15:10:17 -0500 Received: from relay.smtp-ext.broadcom.com (lpdvacalvio01.broadcom.com [192.19.166.228]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0EFB28408F; Fri, 6 Jan 2023 12:10:17 -0800 (PST) Received: from mail-lvn-it-01.lvn.broadcom.net (mail-lvn-it-01.lvn.broadcom.net [10.75.146.107]) by relay.smtp-ext.broadcom.com (Postfix) with ESMTP id BC54AC0000E5; Fri, 6 Jan 2023 12:10:16 -0800 (PST) DKIM-Filter: OpenDKIM Filter v2.11.0 relay.smtp-ext.broadcom.com BC54AC0000E5 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=broadcom.com; s=dkimrelay; t=1673035816; bh=+uD5a54icoUzLx5d+NsDh5T2zoEiPm+PP/DVulvOk6M=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=n+9M+jMpQjjfxocTaKLvIc6d8q5QAICaG6Wcmk8aAoFA4r14syS0Vi8oQkhutuCnl DxKE3a7B1vdJ5+uH2epxyHsxhtV5T475h26o6uOC/r80wWBi20EjxX9+QoO8Ymwt8g Iw17eLWw3Bw9C5GXhQ/3kmZLIM0Ashg23dgf1jTA= Received: from bcacpedev-irv-3.lvn.broadcom.net (bcacpedev-irv-3.lvn.broadcom.net [10.75.138.105]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail-lvn-it-01.lvn.broadcom.net (Postfix) with ESMTPS id BA66A18041CAC6; Fri, 6 Jan 2023 12:10:16 -0800 (PST) Received: by bcacpedev-irv-3.lvn.broadcom.net (Postfix, from userid 28376) id B86B1101B3C; Fri, 6 Jan 2023 12:10:16 -0800 (PST) From: William Zhang To: Linux SPI List , Broadcom Kernel List Cc: anand.gore@broadcom.com, tomer.yacoby@broadcom.com, dan.beygelman@broadcom.com, joel.peshkin@broadcom.com, f.fainelli@gmail.com, jonas.gorski@gmail.com, kursad.oney@broadcom.com, dregan@mail.com, William Zhang , Mark Brown , linux-kernel@vger.kernel.org Subject: [PATCH 14/16] spi: bcm63xx-hsspi: prepend: Disable spi mem dual io read op support Date: Fri, 6 Jan 2023 12:08:06 -0800 Message-Id: <20230106200809.330769-15-william.zhang@broadcom.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20230106200809.330769-1-william.zhang@broadcom.com> References: <20230106200809.330769-1-william.zhang@broadcom.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE, SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1754305347670585543?= X-GMAIL-MSGID: =?utf-8?q?1754305347670585543?= In general the controller supports SPI dual mode operation but the particular SPI flash dual io read op switches from single mode in cmd phase to dual mode in address and data phase. This is not compatible with prepend operation where cmd and address are sent out through the prepend buffer and they must use same the number of io pins. This patch disables these SPI flash dual io read ops through the mem_ops supports_op interface when prepend mode is used. This makes sure the SPI flash driver selects the compatible read ops at run time. Signed-off-by: William Zhang --- drivers/spi/spi-bcm63xx-hsspi.c | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/drivers/spi/spi-bcm63xx-hsspi.c b/drivers/spi/spi-bcm63xx-hsspi.c index be4ca01f332a..7ede7f02ba2c 100644 --- a/drivers/spi/spi-bcm63xx-hsspi.c +++ b/drivers/spi/spi-bcm63xx-hsspi.c @@ -20,6 +20,7 @@ #include #include #include +#include #include #include @@ -596,6 +597,26 @@ static int bcm63xx_hsspi_transfer_one(struct spi_master *master, return 0; } +static bool bcm63xx_hsspi_mem_supports_op(struct spi_mem *mem, + const struct spi_mem_op *op) +{ + struct bcm63xx_hsspi *bs = spi_master_get_devdata(mem->spi->master); + + if (!spi_mem_default_supports_op(mem, op)) + return false; + + /* Controller doesn't support spi mem dual/quad read cmd in prepend mode */ + if (!bs->use_cs_workaround && + ((op->cmd.opcode == 0xbb) || (op->cmd.opcode == 0xeb))) + return false; + + return true; +} + +static const struct spi_controller_mem_ops bcm63xx_hsspi_mem_ops = { + .supports_op = bcm63xx_hsspi_mem_supports_op, +}; + static irqreturn_t bcm63xx_hsspi_interrupt(int irq, void *dev_id) { struct bcm63xx_hsspi *bs = (struct bcm63xx_hsspi *)dev_id; @@ -692,6 +713,7 @@ static int bcm63xx_hsspi_probe(struct platform_device *pdev) mutex_init(&bs->bus_mutex); init_completion(&bs->done); + master->mem_ops = &bcm63xx_hsspi_mem_ops; master->dev.of_node = dev->of_node; if (!dev->of_node) { master->bus_num = HSSPI_BUS_NUM; From patchwork Fri Jan 6 20:08:07 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: William Zhang X-Patchwork-Id: 40252 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4e01:0:0:0:0:0 with SMTP id p1csp1007301wrt; Fri, 6 Jan 2023 12:14:29 -0800 (PST) X-Google-Smtp-Source: AMrXdXsjGgoGSre6UnKr9TMx6v373CJBqXuzI3TuIt2a314+peYNDDzQAQbDr6HxsWmhZXU6RFxc X-Received: by 2002:a17:906:d205:b0:7c1:51ee:a2ec with SMTP id w5-20020a170906d20500b007c151eea2ecmr48279826ejz.46.1673036068954; Fri, 06 Jan 2023 12:14:28 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1673036068; cv=none; d=google.com; s=arc-20160816; b=BbEMaQAoy+gzMMxJ2GR5lRXoAEalTjxdvjKydTNXlTQd8iV5ZAmgheqqtayOMz9CgC 0PwWETTzKQRZtGhXNvGD+ER+s3F42v1MTNod/a/NyFbDp1VWG31c9smUNWmG98souosF UMgVoHjN593hsZF1m23UBuNzwJDD/rxqVx0OmCSkXhi2ocfUJRcGKO+/L/FpmeVpJK/q xZVHpSWfDXUQbCwyqrIbNA/dpV9XeMH7ER9QopeSXMm83/4IZ6tTT5pyGB3O9q0h5+7m TPiyHUjZ/DhGoAR6B4xbrVxINdb6lqraTvRIxdmTpek7RhLfke17viBDo+nmAfr+d5Eb mEjw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature:dkim-filter; bh=0EuKAthTgDCffDHq/LiLtM5CX/lnsZ5gKv8j1wqoke0=; b=daPRfGKo8YBDCS5v1q6iiTq3t+C/X5WjZnSHj/c1+3Lx5F0F/2Ubpg1h3F9KVEucwd NsPLk0l+R+4RL6BewduQrrpJvqrS4yw3HdEF7ObSbNwUv7bOLkSckz4/mHoE6Iz/8WdD SS0iP5xnYv5IwKG17qq2uGjUpqL3Ei73meWYDKHdgfnyhUBX3EnuVV2c6Q9gqzEy3aqo jzHAPm34XG1P+cg8j69nkjAn2dvILCX/AsEoFRawE1x6GD2QbubrsUdHoUKNgk1mB8eM usIIxUkk09Mdk50UbQ0hYnZUihrzYJVpWJJIIslChw0LyrcW0Az3VoGNwc3EcEhXoCsm WMlA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@broadcom.com header.s=dkimrelay header.b=CpVAUixb; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=broadcom.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id t18-20020a1709063e5200b007c0b61436efsi1629566eji.1008.2023.01.06.12.14.04; Fri, 06 Jan 2023 12:14:28 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@broadcom.com header.s=dkimrelay header.b=CpVAUixb; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=broadcom.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236704AbjAFULV (ORCPT + 99 others); Fri, 6 Jan 2023 15:11:21 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49028 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236370AbjAFUKe (ORCPT ); Fri, 6 Jan 2023 15:10:34 -0500 Received: from relay.smtp-ext.broadcom.com (lpdvacalvio01.broadcom.com [192.19.166.228]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8C20184084; Fri, 6 Jan 2023 12:10:31 -0800 (PST) Received: from mail-lvn-it-01.lvn.broadcom.net (mail-lvn-it-01.lvn.broadcom.net [10.75.146.107]) by relay.smtp-ext.broadcom.com (Postfix) with ESMTP id 21E3AC0000E5; Fri, 6 Jan 2023 12:10:31 -0800 (PST) DKIM-Filter: OpenDKIM Filter v2.11.0 relay.smtp-ext.broadcom.com 21E3AC0000E5 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=broadcom.com; s=dkimrelay; t=1673035831; bh=6KLVi9hfPI+kVtPlJFSRZrqV2su+C48MsEfp3kUcLZ0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=CpVAUixbgTugIIjFiaX4cp25cEWG84vlHm9ihySb+lQO/OmjxryvYCcbFuOUoog8o JG0TCcRHWDrdKIJM9JxBRW2FtRNHdxGGxX5WOxTfAAyY9wsa7QmcbfgY2XTqzUmXwW VOWGMqv2UmLr8tINC7Aj+avIMbeT1EgyAAaw50nI= Received: from bcacpedev-irv-3.lvn.broadcom.net (bcacpedev-irv-3.lvn.broadcom.net [10.75.138.105]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail-lvn-it-01.lvn.broadcom.net (Postfix) with ESMTPS id 1FE4118041CAC6; Fri, 6 Jan 2023 12:10:31 -0800 (PST) Received: by bcacpedev-irv-3.lvn.broadcom.net (Postfix, from userid 28376) id 6892D101B33; Fri, 6 Jan 2023 12:10:22 -0800 (PST) From: William Zhang To: Linux SPI List , Broadcom Kernel List Cc: anand.gore@broadcom.com, tomer.yacoby@broadcom.com, dan.beygelman@broadcom.com, joel.peshkin@broadcom.com, f.fainelli@gmail.com, jonas.gorski@gmail.com, kursad.oney@broadcom.com, dregan@mail.com, William Zhang , Mark Brown , =?utf-8?b?UmFmYcWCIE1pxYJlY2tp?= , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 15/16] spi: bcmbca-hsspi: Add driver for newer HSSPI controller Date: Fri, 6 Jan 2023 12:08:07 -0800 Message-Id: <20230106200809.330769-16-william.zhang@broadcom.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20230106200809.330769-1-william.zhang@broadcom.com> References: <20230106200809.330769-1-william.zhang@broadcom.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE, SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1754305468992928129?= X-GMAIL-MSGID: =?utf-8?q?1754305468992928129?= The newer BCMBCA SoCs such as BCM6756, BCM4912 and BCM6855 include an updated SPI controller that add the capability to allow the driver to control chip select explicitly. Driver can control and keep cs low between the transfers natively. Hence the dummy cs workaround or prepend mode found in the bcm63xx-hsspi driver are no longer needed and this new driver is much cleaner. The BCMBCA chips containing this controller use a new compatible string brcm,bcmbca-hsspi and are set accordingly in the chip dtsi file in dts patch from this series. Signed-off-by: William Zhang --- drivers/spi/Kconfig | 9 + drivers/spi/Makefile | 1 + drivers/spi/spi-bcmbca-hsspi.c | 629 +++++++++++++++++++++++++++++++++ 3 files changed, 639 insertions(+) create mode 100644 drivers/spi/spi-bcmbca-hsspi.c diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 3b1c0878bb85..771244582d03 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -199,6 +199,15 @@ config SPI_BCM_QSPI based platforms. This driver works for both SPI master for SPI NOR flash device as well as MSPI device. +config SPI_BCMBCA_HSSPI + tristate "Broadcom BCMBCA HS SPI controller driver" + depends on ARCH_BCMBCA || COMPILE_TEST + help + This enables support for the High Speed SPI controller present on + newer Broadcom BCMBCA SoCs. These SoCs include an updated SPI controller + that adds the capability to allow the driver to control chip select + explicitly. + config SPI_BITBANG tristate "Utilities for Bitbanging SPI masters" help diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index be9ba40ef8d0..fe92106447c3 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -30,6 +30,7 @@ obj-$(CONFIG_SPI_BCM2835) += spi-bcm2835.o obj-$(CONFIG_SPI_BCM2835AUX) += spi-bcm2835aux.o obj-$(CONFIG_SPI_BCM63XX) += spi-bcm63xx.o obj-$(CONFIG_SPI_BCM63XX_HSSPI) += spi-bcm63xx-hsspi.o +obj-$(CONFIG_SPI_BCMBCA_HSSPI) += spi-bcmbca-hsspi.o obj-$(CONFIG_SPI_BCM_QSPI) += spi-iproc-qspi.o spi-brcmstb-qspi.o spi-bcm-qspi.o obj-$(CONFIG_SPI_BITBANG) += spi-bitbang.o obj-$(CONFIG_SPI_BUTTERFLY) += spi-butterfly.o diff --git a/drivers/spi/spi-bcmbca-hsspi.c b/drivers/spi/spi-bcmbca-hsspi.c new file mode 100644 index 000000000000..7523f0e9513c --- /dev/null +++ b/drivers/spi/spi-bcmbca-hsspi.c @@ -0,0 +1,629 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Broadcom BCMBCA High Speed SPI Controller driver + * + * Copyright 2000-2010 Broadcom Corporation + * Copyright 2012-2013 Jonas Gorski + * Copyright 2019-2022 Broadcom Ltd + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* Broadcom Legacy SPI device driver flags */ +#define SPIDEV_CONTROLLER_STATE_SET BIT(31) +#define SPIDEV_CONTROLLER_STATE_GATE_CLK_SSOFF BIT(29) + +#define spidev_ctrl_data(spi) \ + ((u32)((uintptr_t)(spi)->controller_data)) + +#define HSSPI_GLOBAL_CTRL_REG 0x0 +#define GLOBAL_CTRL_CS_POLARITY_SHIFT 0 +#define GLOBAL_CTRL_CS_POLARITY_MASK 0x000000ff +#define GLOBAL_CTRL_PLL_CLK_CTRL_SHIFT 8 +#define GLOBAL_CTRL_PLL_CLK_CTRL_MASK 0x0000ff00 +#define GLOBAL_CTRL_CLK_GATE_SSOFF BIT(16) +#define GLOBAL_CTRL_CLK_POLARITY BIT(17) +#define GLOBAL_CTRL_MOSI_IDLE BIT(18) + +#define HSSPI_GLOBAL_EXT_TRIGGER_REG 0x4 + +#define HSSPI_INT_STATUS_REG 0x8 +#define HSSPI_INT_STATUS_MASKED_REG 0xc +#define HSSPI_INT_MASK_REG 0x10 + +#define HSSPI_PINGx_CMD_DONE(i) BIT((i * 8) + 0) +#define HSSPI_PINGx_RX_OVER(i) BIT((i * 8) + 1) +#define HSSPI_PINGx_TX_UNDER(i) BIT((i * 8) + 2) +#define HSSPI_PINGx_POLL_TIMEOUT(i) BIT((i * 8) + 3) +#define HSSPI_PINGx_CTRL_INVAL(i) BIT((i * 8) + 4) + +#define HSSPI_INT_CLEAR_ALL 0xff001f1f + +#define HSSPI_PINGPONG_COMMAND_REG(x) (0x80 + (x) * 0x40) +#define PINGPONG_CMD_COMMAND_MASK 0xf +#define PINGPONG_COMMAND_NOOP 0 +#define PINGPONG_COMMAND_START_NOW 1 +#define PINGPONG_COMMAND_START_TRIGGER 2 +#define PINGPONG_COMMAND_HALT 3 +#define PINGPONG_COMMAND_FLUSH 4 +#define PINGPONG_CMD_PROFILE_SHIFT 8 +#define PINGPONG_CMD_SS_SHIFT 12 + +#define HSSPI_PINGPONG_STATUS_REG(x) (0x84 + (x) * 0x40) +#define HSSPI_PINGPONG_STATUS_SRC_BUSY BIT(1) + +#define HSSPI_PROFILE_CLK_CTRL_REG(x) (0x100 + (x) * 0x20) +#define CLK_CTRL_FREQ_CTRL_MASK 0x0000ffff +#define CLK_CTRL_SPI_CLK_2X_SEL BIT(14) +#define CLK_CTRL_ACCUM_RST_ON_LOOP BIT(15) +#define CLK_CTRL_CLK_POLARITY BIT(16) + +#define HSSPI_PROFILE_SIGNAL_CTRL_REG(x) (0x104 + (x) * 0x20) +#define SIGNAL_CTRL_LATCH_RISING BIT(12) +#define SIGNAL_CTRL_LAUNCH_RISING BIT(13) +#define SIGNAL_CTRL_ASYNC_INPUT_PATH BIT(16) + +#define HSSPI_PROFILE_MODE_CTRL_REG(x) (0x108 + (x) * 0x20) +#define MODE_CTRL_MULTIDATA_RD_STRT_SHIFT 8 +#define MODE_CTRL_MULTIDATA_WR_STRT_SHIFT 12 +#define MODE_CTRL_MULTIDATA_RD_SIZE_SHIFT 16 +#define MODE_CTRL_MULTIDATA_WR_SIZE_SHIFT 18 +#define MODE_CTRL_MODE_3WIRE BIT(20) +#define MODE_CTRL_PREPENDBYTE_CNT_SHIFT 24 + +#define HSSPI_FIFO_REG(x) (0x200 + (x) * 0x200) + +#define HSSPI_OP_MULTIBIT BIT(11) +#define HSSPI_OP_CODE_SHIFT 13 +#define HSSPI_OP_SLEEP (0 << HSSPI_OP_CODE_SHIFT) +#define HSSPI_OP_READ_WRITE (1 << HSSPI_OP_CODE_SHIFT) +#define HSSPI_OP_WRITE (2 << HSSPI_OP_CODE_SHIFT) +#define HSSPI_OP_READ (3 << HSSPI_OP_CODE_SHIFT) +#define HSSPI_OP_SETIRQ (4 << HSSPI_OP_CODE_SHIFT) + +#define HSSPI_BUFFER_LEN 512 +#define HSSPI_OPCODE_LEN 2 + +#define HSSPI_MAX_PREPEND_LEN 15 + +#define HSSPI_MAX_SYNC_CLOCK 30000000 + +#define HSSPI_SPI_MAX_CS 8 +#define HSSPI_BUS_NUM 1 /* 0 is legacy SPI */ +#define HSSPI_POLL_STATUS_TIMEOUT_MS 100 + +#define SPIM_CTRL_CS_OVERRIDE_SEL_SHIFT 0 +#define SPIM_CTRL_CS_OVERRIDE_SEL_MASK 0xff +#define SPIM_CTRL_CS_OVERRIDE_VAL_SHIFT 8 +#define SPIM_CTRL_CS_OVERRIDE_VAL_MASK 0xff + +struct bcmbca_hsspi { + struct completion done; + struct mutex bus_mutex; + struct platform_device *pdev; + struct clk *clk; + struct clk *pll_clk; + void __iomem *regs; + void __iomem *spim_ctrl; + u8 __iomem *fifo; + u32 speed_hz; + u8 cs_polarity; + int irq; +}; + + +static void bcmbca_hsspi_set_clk(struct bcmbca_hsspi *bs, + struct spi_device *spi, int hz); + +static inline int bcmbca_hsspi_dev_no_clk_gate(struct spi_device *spi) +{ + u32 ctrl_data = 0; + + /* check spi device dn first */ + if (of_property_read_bool(spi->dev.of_node, "brcm,no-clk-gate")) + return 1; + + /* check spi dev controller data for legacy device support */ + ctrl_data = spidev_ctrl_data(spi); + return ((ctrl_data & SPIDEV_CONTROLLER_STATE_SET) && + !(ctrl_data & SPIDEV_CONTROLLER_STATE_GATE_CLK_SSOFF)); +} + +static void bcmbca_hsspi_restore_clk_gate(struct bcmbca_hsspi *bs, + struct spi_device *spi) +{ + u32 reg = 0; + + /* check if clk gate setting was previously turned off */ + if (bcmbca_hsspi_dev_no_clk_gate(spi)) { + mutex_lock(&bs->bus_mutex); + reg = __raw_readl(bs->regs + HSSPI_GLOBAL_CTRL_REG); + reg |= GLOBAL_CTRL_CLK_GATE_SSOFF; + __raw_writel(reg, bs->regs + HSSPI_GLOBAL_CTRL_REG); + mutex_unlock(&bs->bus_mutex); + } +} + +static void bcmbca_hsspi_set_cs(struct bcmbca_hsspi *bs, unsigned int cs, + bool active) +{ + u32 reg; + + /* No cs orerriden needed for SS7 internal cs on pcm based voice dev */ + if (cs == 7) + return; + + mutex_lock(&bs->bus_mutex); + + if (active) { + /* activate cs by setting the override bit and active value bit*/ + reg = __raw_readl(bs->spim_ctrl); + reg |= BIT(cs+SPIM_CTRL_CS_OVERRIDE_SEL_SHIFT); + reg &= ~BIT(cs+SPIM_CTRL_CS_OVERRIDE_VAL_SHIFT); + if (bs->cs_polarity & BIT(cs)) + reg |= BIT(cs+SPIM_CTRL_CS_OVERRIDE_VAL_SHIFT); + __raw_writel(reg, bs->spim_ctrl); + } else { + /* clear the cs override bit */ + reg = __raw_readl(bs->spim_ctrl); + reg &= ~BIT(cs+SPIM_CTRL_CS_OVERRIDE_SEL_SHIFT); + __raw_writel(reg, bs->spim_ctrl); + } + + mutex_unlock(&bs->bus_mutex); +} + +static void bcmbca_hsspi_set_clk(struct bcmbca_hsspi *bs, + struct spi_device *spi, int hz) +{ + unsigned int profile = spi->chip_select; + u32 reg; + + reg = DIV_ROUND_UP(2048, DIV_ROUND_UP(bs->speed_hz, hz)); + __raw_writel(CLK_CTRL_ACCUM_RST_ON_LOOP | reg, + bs->regs + HSSPI_PROFILE_CLK_CTRL_REG(profile)); + + reg = __raw_readl(bs->regs + HSSPI_PROFILE_SIGNAL_CTRL_REG(profile)); + if (hz > HSSPI_MAX_SYNC_CLOCK) + reg |= SIGNAL_CTRL_ASYNC_INPUT_PATH; + else + reg &= ~SIGNAL_CTRL_ASYNC_INPUT_PATH; + __raw_writel(reg, bs->regs + HSSPI_PROFILE_SIGNAL_CTRL_REG(profile)); + + mutex_lock(&bs->bus_mutex); + /* setup clock polarity */ + reg = __raw_readl(bs->regs + HSSPI_GLOBAL_CTRL_REG); + reg &= ~GLOBAL_CTRL_CLK_POLARITY; + if (spi->mode & SPI_CPOL) + reg |= GLOBAL_CTRL_CLK_POLARITY; + + if (bcmbca_hsspi_dev_no_clk_gate(spi)) + reg &= ~GLOBAL_CTRL_CLK_GATE_SSOFF; + else + reg |= GLOBAL_CTRL_CLK_GATE_SSOFF; + + __raw_writel(reg, bs->regs + HSSPI_GLOBAL_CTRL_REG); + + mutex_unlock(&bs->bus_mutex); +} + +static int bcmbca_hsspi_wait_cmd(struct bcmbca_hsspi *bs, unsigned int cs) +{ + unsigned long limit; + u32 reg = 0; + int rc = 0; + + if (bs->irq > 0) { + if (wait_for_completion_timeout(&bs->done, HZ) == 0) + rc = 1; + } else { + limit = jiffies + msecs_to_jiffies(HSSPI_POLL_STATUS_TIMEOUT_MS); + + while (!time_after(jiffies, limit)) { + reg = __raw_readl(bs->regs + HSSPI_PINGPONG_STATUS_REG(0)); + if (reg & HSSPI_PINGPONG_STATUS_SRC_BUSY) + cpu_relax(); + else + break; + } + if (reg & HSSPI_PINGPONG_STATUS_SRC_BUSY) + rc = 1; + } + + if (rc) { + dev_err(&bs->pdev->dev, "transfer timed out!\n"); + bcmbca_hsspi_set_cs(bs, cs, false); + } + + return rc; +} + +static int bcmbca_hsspi_do_txrx(struct spi_device *spi, struct spi_transfer *t, + struct spi_message *msg) +{ + struct bcmbca_hsspi *bs = spi_master_get_devdata(spi->master); + unsigned int chip_select = spi->chip_select; + u16 opcode = 0; + int pending = t->len; + int step_size = HSSPI_BUFFER_LEN; + const u8 *tx = t->tx_buf; + u8 *rx = t->rx_buf; + u32 reg = 0, cs_act = 0; + + bcmbca_hsspi_set_clk(bs, spi, t->speed_hz); + + if (tx && rx) + opcode = HSSPI_OP_READ_WRITE; + else if (tx) + opcode = HSSPI_OP_WRITE; + else if (rx) + opcode = HSSPI_OP_READ; + + if (opcode != HSSPI_OP_READ) + step_size -= HSSPI_OPCODE_LEN; + + if ((opcode == HSSPI_OP_READ && t->rx_nbits == SPI_NBITS_DUAL) || + (opcode == HSSPI_OP_WRITE && t->tx_nbits == SPI_NBITS_DUAL)) { + opcode |= HSSPI_OP_MULTIBIT; + + if (t->rx_nbits == SPI_NBITS_DUAL) + reg |= 1 << MODE_CTRL_MULTIDATA_RD_SIZE_SHIFT; + if (t->tx_nbits == SPI_NBITS_DUAL) + reg |= 1 << MODE_CTRL_MULTIDATA_WR_SIZE_SHIFT; + } + + __raw_writel(reg | 0xff, + bs->regs + HSSPI_PROFILE_MODE_CTRL_REG(chip_select)); + + while (pending > 0) { + int curr_step = min_t(int, step_size, pending); + + reinit_completion(&bs->done); + if (tx) { + memcpy_toio(bs->fifo + HSSPI_OPCODE_LEN, tx, curr_step); + tx += curr_step; + } + __raw_writew(cpu_to_be16(opcode | curr_step), bs->fifo); + + /* enable interrupt */ + if (bs->irq > 0) + __raw_writel(HSSPI_PINGx_CMD_DONE(0), + bs->regs + HSSPI_INT_MASK_REG); + + if (!cs_act) { + bcmbca_hsspi_set_cs(bs, chip_select, true); + cs_act = 1; + } + reg = chip_select << PINGPONG_CMD_SS_SHIFT | + chip_select << PINGPONG_CMD_PROFILE_SHIFT | + PINGPONG_COMMAND_START_NOW; + __raw_writel(reg, bs->regs + HSSPI_PINGPONG_COMMAND_REG(0)); + + if (bcmbca_hsspi_wait_cmd(bs, spi->chip_select)) + return -ETIMEDOUT; + + pending -= curr_step; + if (pending == 0) { + if (list_is_last(&t->transfer_list, &msg->transfers)) { + if (!t->cs_change) + bcmbca_hsspi_set_cs(bs, spi->chip_select, false); + } else { + if (t->cs_change) { + bcmbca_hsspi_set_cs(bs, spi->chip_select, false); + udelay(10); + bcmbca_hsspi_set_cs(bs, spi->chip_select, true); + } + } + } + if (rx) { + memcpy_fromio(rx, bs->fifo, curr_step); + rx += curr_step; + } + } + + return 0; +} + +static int bcmbca_hsspi_setup(struct spi_device *spi) +{ + struct bcmbca_hsspi *bs = spi_master_get_devdata(spi->master); + u32 reg; + + reg = __raw_readl(bs->regs + + HSSPI_PROFILE_SIGNAL_CTRL_REG(spi->chip_select)); + reg &= ~(SIGNAL_CTRL_LAUNCH_RISING | SIGNAL_CTRL_LATCH_RISING); + if (spi->mode & SPI_CPHA) + reg |= SIGNAL_CTRL_LAUNCH_RISING; + else + reg |= SIGNAL_CTRL_LATCH_RISING; + __raw_writel(reg, bs->regs + + HSSPI_PROFILE_SIGNAL_CTRL_REG(spi->chip_select)); + + mutex_lock(&bs->bus_mutex); + reg = __raw_readl(bs->regs + HSSPI_GLOBAL_CTRL_REG); + + if (spi->mode & SPI_CS_HIGH) + reg |= BIT(spi->chip_select); + else + reg &= ~BIT(spi->chip_select); + __raw_writel(reg, bs->regs + HSSPI_GLOBAL_CTRL_REG); + + if (spi->mode & SPI_CS_HIGH) + bs->cs_polarity |= BIT(spi->chip_select); + else + bs->cs_polarity &= ~BIT(spi->chip_select); + + mutex_unlock(&bs->bus_mutex); + + return 0; +} + +static int bcmbca_hsspi_transfer_one(struct spi_master *master, + struct spi_message *msg) +{ + struct bcmbca_hsspi *bs = spi_master_get_devdata(master); + struct spi_transfer *t; + struct spi_device *spi = msg->spi; + int status = -EINVAL; + + list_for_each_entry(t, &msg->transfers, transfer_list) { + status = bcmbca_hsspi_do_txrx(spi, t, msg); + if (status) + break; + + msg->actual_length += t->len; + + spi_transfer_delay_exec(t); + } + + /* restore the default clk gate setting in case spidev turn it off */ + bcmbca_hsspi_restore_clk_gate(bs, spi); + + msg->status = status; + spi_finalize_current_message(master); + + return 0; +} + +static irqreturn_t bcmbca_hsspi_interrupt(int irq, void *dev_id) +{ + struct bcmbca_hsspi *bs = (struct bcmbca_hsspi *)dev_id; + + if (__raw_readl(bs->regs + HSSPI_INT_STATUS_MASKED_REG) == 0) + return IRQ_NONE; + + __raw_writel(HSSPI_INT_CLEAR_ALL, bs->regs + HSSPI_INT_STATUS_REG); + __raw_writel(0, bs->regs + HSSPI_INT_MASK_REG); + + complete(&bs->done); + + return IRQ_HANDLED; +} + +static int bcmbca_hsspi_probe(struct platform_device *pdev) +{ + struct spi_master *master; + struct bcmbca_hsspi *bs; + struct resource *res_mem; + void __iomem *spim_ctrl; + void __iomem *regs; + struct device *dev = &pdev->dev; + struct clk *clk, *pll_clk = NULL; + int irq, ret; + u32 reg, rate, num_cs = HSSPI_SPI_MAX_CS; + + irq = platform_get_irq_optional(pdev, 0); + if (irq < 0 && irq != -ENXIO) + return irq; + + res_mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hsspi"); + if (!res_mem) + return -EINVAL; + regs = devm_ioremap_resource(dev, res_mem); + if (IS_ERR(regs)) + return PTR_ERR(regs); + + res_mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, "spim-ctrl"); + if (!res_mem) + return -EINVAL; + spim_ctrl = devm_ioremap_resource(dev, res_mem); + if (IS_ERR(spim_ctrl)) + return PTR_ERR(spim_ctrl); + + clk = devm_clk_get(dev, "hsspi"); + if (IS_ERR(clk)) + return PTR_ERR(clk); + + ret = clk_prepare_enable(clk); + if (ret) + return ret; + + rate = clk_get_rate(clk); + if (!rate) { + pll_clk = devm_clk_get(dev, "pll"); + + if (IS_ERR(pll_clk)) { + ret = PTR_ERR(pll_clk); + goto out_disable_clk; + } + + ret = clk_prepare_enable(pll_clk); + if (ret) + goto out_disable_clk; + + rate = clk_get_rate(pll_clk); + if (!rate) { + ret = -EINVAL; + goto out_disable_pll_clk; + } + } + + master = spi_alloc_master(&pdev->dev, sizeof(*bs)); + if (!master) { + ret = -ENOMEM; + goto out_disable_pll_clk; + } + + bs = spi_master_get_devdata(master); + bs->pdev = pdev; + bs->clk = clk; + bs->pll_clk = pll_clk; + bs->regs = regs; + bs->spim_ctrl = spim_ctrl; + bs->speed_hz = rate; + bs->fifo = (u8 __iomem *) (bs->regs + HSSPI_FIFO_REG(0)); + bs->irq = irq; + + mutex_init(&bs->bus_mutex); + init_completion(&bs->done); + + master->dev.of_node = dev->of_node; + if (!dev->of_node) + master->bus_num = HSSPI_BUS_NUM; + + of_property_read_u32(dev->of_node, "num-cs", &num_cs); + if (num_cs > 8) { + dev_warn(dev, "unsupported number of cs (%i), reducing to 8\n", + num_cs); + num_cs = HSSPI_SPI_MAX_CS; + } + master->num_chipselect = num_cs; + master->setup = bcmbca_hsspi_setup; + master->transfer_one_message = bcmbca_hsspi_transfer_one; + master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | + SPI_RX_DUAL | SPI_TX_DUAL; + master->bits_per_word_mask = SPI_BPW_MASK(8); + master->auto_runtime_pm = true; + + platform_set_drvdata(pdev, master); + + /* Initialize the hardware */ + __raw_writel(0, bs->regs + HSSPI_INT_MASK_REG); + + /* clean up any pending interrupts */ + __raw_writel(HSSPI_INT_CLEAR_ALL, bs->regs + HSSPI_INT_STATUS_REG); + + /* read out default CS polarities */ + reg = __raw_readl(bs->regs + HSSPI_GLOBAL_CTRL_REG); + bs->cs_polarity = reg & GLOBAL_CTRL_CS_POLARITY_MASK; + __raw_writel(reg | GLOBAL_CTRL_CLK_GATE_SSOFF, + bs->regs + HSSPI_GLOBAL_CTRL_REG); + + if (bs->irq > 0) { + ret = devm_request_irq(dev, irq, bcmbca_hsspi_interrupt, IRQF_SHARED, + pdev->name, bs); + if (ret) + goto out_put_master; + } + + pm_runtime_enable(&pdev->dev); + + /* register and we are done */ + ret = devm_spi_register_master(dev, master); + if (ret) + goto out_pm_disable; + + dev_info(dev, "Broadcom BCMBCA High Speed SPI Controller driver"); + + return 0; + +out_pm_disable: + pm_runtime_disable(&pdev->dev); +out_put_master: + spi_master_put(master); +out_disable_pll_clk: + clk_disable_unprepare(pll_clk); +out_disable_clk: + clk_disable_unprepare(clk); + return ret; +} + +static int bcmbca_hsspi_remove(struct platform_device *pdev) +{ + struct spi_master *master = platform_get_drvdata(pdev); + struct bcmbca_hsspi *bs = spi_master_get_devdata(master); + + /* reset the hardware and block queue progress */ + __raw_writel(0, bs->regs + HSSPI_INT_MASK_REG); + clk_disable_unprepare(bs->pll_clk); + clk_disable_unprepare(bs->clk); + + return 0; +} + +#ifdef CONFIG_PM_SLEEP +static int bcmbca_hsspi_suspend(struct device *dev) +{ + struct spi_master *master = dev_get_drvdata(dev); + struct bcmbca_hsspi *bs = spi_master_get_devdata(master); + + spi_master_suspend(master); + clk_disable_unprepare(bs->pll_clk); + clk_disable_unprepare(bs->clk); + + return 0; +} + +static int bcmbca_hsspi_resume(struct device *dev) +{ + struct spi_master *master = dev_get_drvdata(dev); + struct bcmbca_hsspi *bs = spi_master_get_devdata(master); + int ret; + + ret = clk_prepare_enable(bs->clk); + if (ret) + return ret; + + if (bs->pll_clk) { + ret = clk_prepare_enable(bs->pll_clk); + if (ret) { + clk_disable_unprepare(bs->clk); + return ret; + } + } + + spi_master_resume(master); + + return 0; +} +#endif + +static SIMPLE_DEV_PM_OPS(bcmbca_hsspi_pm_ops, bcmbca_hsspi_suspend, + bcmbca_hsspi_resume); + +static const struct of_device_id bcmbca_hsspi_of_match[] = { + {.compatible = "brcm,bcmbca-hsspi",}, + {}, +}; + +MODULE_DEVICE_TABLE(of, bcmbca_hsspi_of_match); + +static struct platform_driver bcmbca_hsspi_driver = { + .driver = { + .name = "bcmbca-hsspi", + .pm = &bcmbca_hsspi_pm_ops, + .of_match_table = bcmbca_hsspi_of_match, + }, + .probe = bcmbca_hsspi_probe, + .remove = bcmbca_hsspi_remove, +}; + +module_platform_driver(bcmbca_hsspi_driver); + +MODULE_ALIAS("platform:bcmbca_hsspi"); +MODULE_DESCRIPTION("Broadcom BCMBCA High Speed SPI Controller driver"); +MODULE_LICENSE("GPL"); From patchwork Fri Jan 6 20:08:08 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: William Zhang X-Patchwork-Id: 40243 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4e01:0:0:0:0:0 with SMTP id p1csp1006688wrt; Fri, 6 Jan 2023 12:13:01 -0800 (PST) X-Google-Smtp-Source: AMrXdXvoVK1uOLiu21gvBGXo21RfTOOUElZsaGUw+ei6P+55jY3cZL6Jb9bCM6OaEL6EfcQ8tw3y X-Received: by 2002:a17:907:8d17:b0:7c1:1ada:5e1e with SMTP id tc23-20020a1709078d1700b007c11ada5e1emr46495394ejc.26.1673035981616; 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[2620:137:e000::1:20]) by mx.google.com with ESMTP id t18-20020a1709063e5200b007c0b61436efsi1629566eji.1008.2023.01.06.12.12.36; Fri, 06 Jan 2023 12:13:01 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@broadcom.com header.s=dkimrelay header.b=rHSrIX+d; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=broadcom.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236686AbjAFULS (ORCPT + 99 others); Fri, 6 Jan 2023 15:11:18 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49114 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236465AbjAFUKj (ORCPT ); Fri, 6 Jan 2023 15:10:39 -0500 Received: from relay.smtp-ext.broadcom.com (lpdvsmtp09.broadcom.com [192.19.166.228]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 29E388408C; Fri, 6 Jan 2023 12:10:37 -0800 (PST) Received: from mail-lvn-it-01.lvn.broadcom.net (mail-lvn-it-01.lvn.broadcom.net [10.75.146.107]) by relay.smtp-ext.broadcom.com (Postfix) with ESMTP id C5EBCC0000E6; Fri, 6 Jan 2023 12:10:36 -0800 (PST) DKIM-Filter: OpenDKIM Filter v2.11.0 relay.smtp-ext.broadcom.com C5EBCC0000E6 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=broadcom.com; s=dkimrelay; t=1673035836; bh=frlTbcU6hpG61dJDfFSIHuuKmcrXAgLgJ5MGkCYlL0M=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=rHSrIX+d4KZB3KJnVo6JGxDZ/xdzqr0QFpxqe0U7kz+9pVT2LPg1guTWSbGWoRvTB cDGQX0R3X9Vko8C2V38bS9KkT5V7EfuhDmtQHOK1TBTDnkuIFrlXOSEYE8ahj/L54q 78UWhKKejsKFI38B3n9MnMYmsSKR8Umu/o2eqbhI= Received: from bcacpedev-irv-3.lvn.broadcom.net (bcacpedev-irv-3.lvn.broadcom.net [10.75.138.105]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail-lvn-it-01.lvn.broadcom.net (Postfix) with ESMTPS id C403C18041CAC6; Fri, 6 Jan 2023 12:10:36 -0800 (PST) Received: by bcacpedev-irv-3.lvn.broadcom.net (Postfix, from userid 28376) id 1C50A101B3C; Fri, 6 Jan 2023 12:10:31 -0800 (PST) From: William Zhang To: Linux SPI List , Broadcom Kernel List Cc: anand.gore@broadcom.com, tomer.yacoby@broadcom.com, dan.beygelman@broadcom.com, joel.peshkin@broadcom.com, f.fainelli@gmail.com, jonas.gorski@gmail.com, kursad.oney@broadcom.com, dregan@mail.com, William Zhang , linux-kernel@vger.kernel.org Subject: [PATCH 16/16] MAINTAINERS: Add entry for Broadcom Broadband SoC HS SPI drivers Date: Fri, 6 Jan 2023 12:08:08 -0800 Message-Id: <20230106200809.330769-17-william.zhang@broadcom.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20230106200809.330769-1-william.zhang@broadcom.com> References: <20230106200809.330769-1-william.zhang@broadcom.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE, SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1754305377217498927?= X-GMAIL-MSGID: =?utf-8?q?1754305377217498927?= The driver and device tree doc were originally authored by Jonas Gorski and it has been updated from Broadcom recently including the dts yaml file and a new driver for the updated controller. Add Jonas Gorski and Broadcom engineers William Zhang and Kursad Oney as the maintainers. Signed-off-by: William Zhang --- MAINTAINERS | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 7f0b7181e60a..c7b1d4046940 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -4299,6 +4299,18 @@ L: linux-kernel@vger.kernel.org S: Maintained F: drivers/phy/broadcom/phy-brcm-usb* +BROADCOM Broadband SoC High Speed SPI Controller DRIVER +M: William Zhang +M: Kursad Oney +M: Jonas Gorski +R: Broadcom internal kernel review list +L: linux-spi@vger.kernel.org +S: Maintained +F: Documentation/devicetree/bindings/spi/brcm,bcm63xx-hsspi-peripheral-props.yaml +F: Documentation/devicetree/bindings/spi/brcm,bcm63xx-hsspi.yaml +F: drivers/spi/spi-bcm63xx-hsspi.c +F: drivers/spi/spi-bcmbca-hsspi.c + BROADCOM ETHERNET PHY DRIVERS M: Florian Fainelli R: Broadcom internal kernel review list