From patchwork Fri Jan 6 12:58:15 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabrizio Castro X-Patchwork-Id: 40121 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4e01:0:0:0:0:0 with SMTP id p1csp809780wrt; Fri, 6 Jan 2023 04:59:49 -0800 (PST) X-Google-Smtp-Source: AMrXdXsWKr1dFqH/guare5+N9ZnzY1kjdQk4SkL7KeyIhbrMx1SWxpzWwamfEYiURKrzyXKJv634 X-Received: by 2002:a17:907:d109:b0:818:3f54:8df7 with SMTP id uy9-20020a170907d10900b008183f548df7mr60856673ejc.2.1673009989389; Fri, 06 Jan 2023 04:59:49 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1673009989; cv=none; d=google.com; s=arc-20160816; b=ziNdikdYge73cPS3ITnJS/lUG4nhDAhszgHIHGJfX1Ms0e8xllUi7tJ7DsYWJuL0pf cf0qr3REcWT434C+ymwzUJCFkwqspuptaDPMIaBzSs/UwYMbUOm/0X43fS38Xj/SLWi4 2V/zuzSX7ATQDE/F7LhsZVAhV/dR4FlnffifGE/dnTjWqI+x7V1i//RbCHB/oc6fl01U 4rWbMA0oN2xSKkuV3+QtkLzAD1WgR61ztmXSHm+J2pxVKGnRipd155uIGdbDAYnrxtE/ A+1tLER6HCQjLRqwhG5oqfSOvBzNoFK0SMQPLIs7rpawcINIXUjdIRQyj7t4rl4Ior6+ uppg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=BsItFcAcXiqwWWk6YiNTAopnJ3PZUCzfIqIn3saJQTc=; b=hTxs5gjNmmKoh2ofoA4or2COTOdbwECy1e395dVdobQ0aLNM303JANzXf0SvaNVkcA IUTcQHhwOwmCues03Ur1R/M+bXMgBaQe9NS8hI0o5NMW+FnIL0IEYWM3h2f5QtxifGyu OY3+r5rQChFPvCAHMEF+GcUzsPHw4tOGUpzY19hBSzC0wMtFzBbBpk4uWWB+ydfMQZ/4 q9Z13qoNpAsFmsqIMHK2CrTOAArJ3ooQG1iwwVuSc+iriwdJXHcmh6FUhuEO3OTt7T3M lIwo+IeA2x9CQkeBGzcYDwezl+vbD8Hq0EnH5uFWEf2fjUfuVSDGlZ1VFZbQByR9ye79 7fEA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=renesas.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id qf11-20020a1709077f0b00b007bd6264c2dbsi1444289ejc.28.2023.01.06.04.59.24; Fri, 06 Jan 2023 04:59:49 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=renesas.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234327AbjAFM6s (ORCPT + 99 others); Fri, 6 Jan 2023 07:58:48 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46696 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234573AbjAFM6d (ORCPT ); Fri, 6 Jan 2023 07:58:33 -0500 Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id BAA056B19D; Fri, 6 Jan 2023 04:58:31 -0800 (PST) X-IronPort-AV: E=Sophos;i="5.96,305,1665414000"; d="scan'208";a="145413764" Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie5.idc.renesas.com with ESMTP; 06 Jan 2023 21:58:31 +0900 Received: from mulinux.example.org (unknown [10.226.92.206]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 1C67B4254DA6; Fri, 6 Jan 2023 21:58:25 +0900 (JST) From: Fabrizio Castro To: Linus Walleij , Bartosz Golaszewski , Rob Herring , Krzysztof Kozlowski , Sebastian Reichel , Geert Uytterhoeven Cc: Fabrizio Castro , Lee Jones , linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, Chris Paterson , Biju Das , linux-renesas-soc@vger.kernel.org, Laurent Pinchart , Jacopo Mondi , Rob Herring Subject: [PATCH v5 1/2] dt-bindings: soc: renesas: Add RZ/V2M PWC Date: Fri, 6 Jan 2023 12:58:15 +0000 Message-Id: <20230106125816.10600-2-fabrizio.castro.jz@renesas.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230106125816.10600-1-fabrizio.castro.jz@renesas.com> References: <20230106125816.10600-1-fabrizio.castro.jz@renesas.com> MIME-Version: 1.0 X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1754278122768640208?= X-GMAIL-MSGID: =?utf-8?q?1754278122768640208?= The Renesas RZ/V2M External Power Sequence Controller (PWC) IP is capable of: * external power supply on/off sequence generation * on/off signal generation for the LPDDR4 core power supply (LPVDD) * key input signals processing * general-purpose output pins Add the corresponding dt-bindings. Signed-off-by: Fabrizio Castro Reviewed-by: Rob Herring Reviewed-by: Geert Uytterhoeven --- v1->v2: I have dropped syscon, simple-mfd, regmap, offset, and the child nodes. v2->v3: No change. v3->v4: Moved file under Documentation/devicetree/bindings/soc/renesas, and changed $id accordingly. v4->v5: Fixed subject line and changelog. Rob, I have kept your Reviewed-by tag assuming you are still happy, please do jump in if you think that's not appropriate anymore. .../soc/renesas/renesas,rzv2m-pwc.yaml | 56 +++++++++++++++++++ 1 file changed, 56 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/renesas/renesas,rzv2m-pwc.yaml diff --git a/Documentation/devicetree/bindings/soc/renesas/renesas,rzv2m-pwc.yaml b/Documentation/devicetree/bindings/soc/renesas/renesas,rzv2m-pwc.yaml new file mode 100644 index 000000000000..12df33f58484 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/renesas/renesas,rzv2m-pwc.yaml @@ -0,0 +1,56 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/renesas/renesas,rzv2m-pwc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas RZ/V2M External Power Sequence Controller (PWC) + +description: |+ + The PWC IP found in the RZ/V2M family of chips comes with the below + capabilities + - external power supply on/off sequence generation + - on/off signal generation for the LPDDR4 core power supply (LPVDD) + - key input signals processing + - general-purpose output pins + +maintainers: + - Fabrizio Castro + +properties: + compatible: + items: + - enum: + - renesas,r9a09g011-pwc # RZ/V2M + - renesas,r9a09g055-pwc # RZ/V2MA + - const: renesas,rzv2m-pwc + + reg: + maxItems: 1 + + gpio-controller: true + + '#gpio-cells': + const: 2 + + renesas,rzv2m-pwc-power: + description: The PWC is used to control the system power supplies. + type: boolean + +required: + - compatible + - reg + - gpio-controller + - '#gpio-cells' + +additionalProperties: false + +examples: + - | + pwc: pwc@a3700000 { + compatible = "renesas,r9a09g011-pwc", "renesas,rzv2m-pwc"; + reg = <0xa3700000 0x800>; + gpio-controller; + #gpio-cells = <2>; + renesas,rzv2m-pwc-power; + }; From patchwork Fri Jan 6 12:58:16 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabrizio Castro X-Patchwork-Id: 40122 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4e01:0:0:0:0:0 with SMTP id p1csp809783wrt; Fri, 6 Jan 2023 04:59:50 -0800 (PST) X-Google-Smtp-Source: AMrXdXuXvcXSnb2VTAl9mnQ5CoNrGklKh/0Aflg/eYSM84ee5c5KcfMEhmfaynb7FGwE4HRGndRR X-Received: by 2002:a05:6402:d9:b0:48e:c83d:a935 with SMTP id i25-20020a05640200d900b0048ec83da935mr11202790edu.29.1673009989949; Fri, 06 Jan 2023 04:59:49 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1673009989; cv=none; d=google.com; s=arc-20160816; b=cttZ6y/gI9ncgoWCI5I1WcelGrlnoVx9mJmX3U9VHO4Qxt6eA5XgzoCOVEg9T5akzc GVtwooxLKQBx5Ni3fe+iTpehP1B9MjziPDB1JZPz0Kp+j74BMUQ3EF27uN7yIexVyyvz 4PdtaSqQlLjjQEw7U0k1C4K1zbGqCxqyh/30qtS/jUD40AWwg0nW7POHDJdPwnrZQZ/6 HSihrrmzNLyfsDW4arib5kb4GLPjx/HALxaQYKAUm/JQtaLWGu7BUxwYmFf26j40V/6F hVtIhhnNTaGm7KJESW1lrbpf19dDw7Kk4yr5xxq6na0sNZVlu5rWQWW1Syf2EsgHsHbK vGIA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=H4wP5HKe0TLT/PNZX3Spmk7jSGe0cnZJW3VS2b0f5ro=; b=au/jTYsbbfwnW7ljyopZpYZFvJSndIoUdOWElXNX3s6BJ996tATUBUEDZDkZtfUOlA EY8hm1f8suo/O9fYw/q0cQtLNd3zvEMlDfrqO/nD6Ib6qzmU9QhKDbghAHy5J31fidSo lazsLufPiHW6sAjcjMiDffhnQdGQ7ESof5vrzjXwmP72LwoQMTZe2rb53b+yx9pYCgEb jsJam0kdGPHllG8ueL/RJQ6XfjB6WnHwiFNKjbvGEhIIkxhBEWfpex7x5Lj+ra9dWsnS aYT6mTbsXFAAZTFGDQiV0Uf/KC5BPmsc8B4xqJfKJKWHIWZDsEcFL13cp7pW06gXDv7Y aUPA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=renesas.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id jg29-20020a170907971d00b007c0d428795dsi1411645ejc.191.2023.01.06.04.59.26; Fri, 06 Jan 2023 04:59:49 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=renesas.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234387AbjAFM6v (ORCPT + 99 others); Fri, 6 Jan 2023 07:58:51 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46730 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234616AbjAFM6j (ORCPT ); Fri, 6 Jan 2023 07:58:39 -0500 Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id D67AB6B59C; Fri, 6 Jan 2023 04:58:37 -0800 (PST) X-IronPort-AV: E=Sophos;i="5.96,305,1665414000"; d="scan'208";a="148398389" Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie6.idc.renesas.com with ESMTP; 06 Jan 2023 21:58:37 +0900 Received: from mulinux.example.org (unknown [10.226.92.206]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 0D0264254DA7; Fri, 6 Jan 2023 21:58:31 +0900 (JST) From: Fabrizio Castro To: Linus Walleij , Bartosz Golaszewski , Rob Herring , Krzysztof Kozlowski , Sebastian Reichel , Geert Uytterhoeven Cc: Fabrizio Castro , Lee Jones , linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, Chris Paterson , Biju Das , linux-renesas-soc@vger.kernel.org, Laurent Pinchart , Jacopo Mondi Subject: [PATCH v5 2/2] soc: renesas: Add PWC support for RZ/V2M Date: Fri, 6 Jan 2023 12:58:16 +0000 Message-Id: <20230106125816.10600-3-fabrizio.castro.jz@renesas.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230106125816.10600-1-fabrizio.castro.jz@renesas.com> References: <20230106125816.10600-1-fabrizio.castro.jz@renesas.com> MIME-Version: 1.0 X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1754278123274172694?= X-GMAIL-MSGID: =?utf-8?q?1754278123274172694?= The Renesas RZ/V2M External Power Sequence Controller (PWC) IP is capable of: * external power supply on/off sequence generation * on/off signal generation for the LPDDR4 core power supply (LPVDD) * key input signals processing * general-purpose output pins Add the corresponding device driver. Signed-off-by: Fabrizio Castro Reviewed-by: Geert Uytterhoeven --- v1: In the first version, I had 1 driver for GPIO handling, and 1 driver for poweroff handling, both based on syscon to share the mapped memory region. v2: One more driver added to act as MFD core driver. Dropped syscon, and dropped the OF compatible string for the GPIO and poweroff drivers. v3: This new patch merges all the PWC code in 1 new driver. It also takes into account the comments received from Bartosz and Geert. Since this is a new driver, I have dropped all the Reviewed-by tags received on the separated drivers. v4: No change. v5: No change. drivers/soc/renesas/Kconfig | 4 + drivers/soc/renesas/Makefile | 1 + drivers/soc/renesas/pwc-rzv2m.c | 141 ++++++++++++++++++++++++++++++++ 3 files changed, 146 insertions(+) create mode 100644 drivers/soc/renesas/pwc-rzv2m.c diff --git a/drivers/soc/renesas/Kconfig b/drivers/soc/renesas/Kconfig index 660498252ec5..4e8b51ba2266 100644 --- a/drivers/soc/renesas/Kconfig +++ b/drivers/soc/renesas/Kconfig @@ -330,6 +330,7 @@ config ARCH_R9A09G011 bool "ARM64 Platform support for RZ/V2M" select PM select PM_GENERIC_DOMAINS + select PWC_RZV2M help This enables support for the Renesas RZ/V2M SoC. @@ -345,6 +346,9 @@ config ARCH_R9A07G043 endif # RISCV +config PWC_RZV2M + bool "Renesas RZ/V2M PWC support" if COMPILE_TEST + config RST_RCAR bool "Reset Controller support for R-Car" if COMPILE_TEST diff --git a/drivers/soc/renesas/Makefile b/drivers/soc/renesas/Makefile index 535868c9c7e4..6e4e77b0afff 100644 --- a/drivers/soc/renesas/Makefile +++ b/drivers/soc/renesas/Makefile @@ -32,6 +32,7 @@ obj-$(CONFIG_ARCH_R9A06G032) += r9a06g032-smp.o endif # Family +obj-$(CONFIG_PWC_RZV2M) += pwc-rzv2m.o obj-$(CONFIG_RST_RCAR) += rcar-rst.o obj-$(CONFIG_SYSC_RCAR) += rcar-sysc.o obj-$(CONFIG_SYSC_RCAR_GEN4) += rcar-gen4-sysc.o diff --git a/drivers/soc/renesas/pwc-rzv2m.c b/drivers/soc/renesas/pwc-rzv2m.c new file mode 100644 index 000000000000..c83bdbdabb64 --- /dev/null +++ b/drivers/soc/renesas/pwc-rzv2m.c @@ -0,0 +1,141 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2023 Renesas Electronics Corporation + */ + +#include +#include +#include +#include + +#define PWC_PWCRST 0x00 +#define PWC_PWCCKEN 0x04 +#define PWC_PWCCTL 0x50 +#define PWC_GPIO 0x80 + +#define PWC_PWCRST_RSTSOFTAX 0x1 +#define PWC_PWCCKEN_ENGCKMAIN 0x1 +#define PWC_PWCCTL_PWOFF 0x1 + +struct rzv2m_pwc_priv { + void __iomem *base; + struct device *dev; + struct gpio_chip gp; + DECLARE_BITMAP(ch_en_bits, 2); +}; + +static void rzv2m_pwc_gpio_set(struct gpio_chip *chip, unsigned int offset, + int value) +{ + struct rzv2m_pwc_priv *priv = gpiochip_get_data(chip); + u32 reg; + + /* BIT 16 enables write to BIT 0, and BIT 17 enables write to BIT 1 */ + reg = BIT(offset + 16); + if (value) + reg |= BIT(offset); + + writel(reg, priv->base + PWC_GPIO); + + assign_bit(offset, priv->ch_en_bits, value); +} + +static int rzv2m_pwc_gpio_get(struct gpio_chip *chip, unsigned int offset) +{ + struct rzv2m_pwc_priv *priv = gpiochip_get_data(chip); + + return test_bit(offset, priv->ch_en_bits); +} + +static int rzv2m_pwc_gpio_direction_output(struct gpio_chip *gc, + unsigned int nr, int value) +{ + if (nr > 1) + return -EINVAL; + + rzv2m_pwc_gpio_set(gc, nr, value); + + return 0; +} + +static const struct gpio_chip rzv2m_pwc_gc = { + .label = "gpio_rzv2m_pwc", + .owner = THIS_MODULE, + .get = rzv2m_pwc_gpio_get, + .set = rzv2m_pwc_gpio_set, + .direction_output = rzv2m_pwc_gpio_direction_output, + .can_sleep = false, + .ngpio = 2, + .base = -1, +}; + +static int rzv2m_pwc_poweroff(struct sys_off_data *data) +{ + struct rzv2m_pwc_priv *priv = data->cb_data; + + writel(PWC_PWCRST_RSTSOFTAX, priv->base + PWC_PWCRST); + writel(PWC_PWCCKEN_ENGCKMAIN, priv->base + PWC_PWCCKEN); + writel(PWC_PWCCTL_PWOFF, priv->base + PWC_PWCCTL); + + mdelay(150); + + dev_err(priv->dev, "Failed to power off the system"); + + return NOTIFY_DONE; +} + +static int rzv2m_pwc_probe(struct platform_device *pdev) +{ + struct rzv2m_pwc_priv *priv; + int ret; + + priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(priv->base)) + return PTR_ERR(priv->base); + + /* + * The register used by this driver cannot be read, therefore set the + * outputs to their default values and initialize priv->ch_en_bits + * accordingly. BIT 16 enables write to BIT 0, BIT 17 enables write to + * BIT 1, and the default value of both BIT 0 and BIT 1 is 0. + */ + writel(BIT(17) | BIT(16), priv->base + PWC_GPIO); + bitmap_zero(priv->ch_en_bits, 2); + + priv->gp = rzv2m_pwc_gc; + priv->gp.parent = pdev->dev.parent; + priv->gp.fwnode = dev_fwnode(&pdev->dev); + + ret = devm_gpiochip_add_data(&pdev->dev, &priv->gp, priv); + if (ret) + return ret; + + if (device_property_read_bool(&pdev->dev, "renesas,rzv2m-pwc-power")) + ret = devm_register_power_off_handler(&pdev->dev, + rzv2m_pwc_poweroff, priv); + + return ret; +} + +static const struct of_device_id rzv2m_pwc_of_match[] = { + { .compatible = "renesas,rzv2m-pwc" }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, rzv2m_pwc_of_match); + +static struct platform_driver rzv2m_pwc_driver = { + .probe = rzv2m_pwc_probe, + .driver = { + .name = "rzv2m_pwc", + .of_match_table = of_match_ptr(rzv2m_pwc_of_match), + }, +}; +module_platform_driver(rzv2m_pwc_driver); + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Fabrizio Castro "); +MODULE_DESCRIPTION("Renesas RZ/V2M PWC driver");