From patchwork Thu Jan 5 18:24:37 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John David Anglin X-Patchwork-Id: 39731 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4e01:0:0:0:0:0 with SMTP id p1csp437464wrt; Thu, 5 Jan 2023 10:25:11 -0800 (PST) X-Google-Smtp-Source: AMrXdXs+7snTZcfYL9Qx5rbzhsTpJDRSM4yBRyPCdaBSCfLe3t+E/VSChjWK2fatoKKqInPkp60T X-Received: by 2002:a05:6402:e83:b0:467:75c6:4565 with SMTP id h3-20020a0564020e8300b0046775c64565mr48267702eda.9.1672943110829; Thu, 05 Jan 2023 10:25:10 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1672943110; cv=none; d=google.com; s=arc-20160816; b=IPysQw7pan5axX4nB4wso7hra7PnK0QyDALhs/I095nK5J78MUgh6OKh5XRiLFpOxo gh4Xsjn19F7DynpJKMW73GpE/9kg4XuhNGfzhSKCeyrx1Gesa80zI7osFoX/l5ITwr12 042BRAbk+7zL+WmskMeUesfbTBrBBVxGZAhqbD0dLSUNyN7N/G1/XearijukUE1yiQ0f ayA1NyeLlREnnUJgCrcJLV8hXakNp0eOUZ+sghThvZjG4SyCtid510bHzzKtFrg2gZe0 GWuMjfs09+KFfUbM1DGQpz4hYmCIGzmdaX9NCNczkwMkfpiVN5H73MsucWIbn5IWsBwT HdCw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-disposition :mime-version:message-id:subject:cc:to:from:date:dmarc-filter :delivered-to; bh=+/coaDDys3Z43KsWKfPH8JEBt8TD4vqtfg2n3lZQ6Zw=; b=JiIER87GYXMNOgDMfWKOrhNIr+umRQS+kfHjnBced2OZOlY6rQao4STzbEfoTSMDbO BunnTMSN0akxovvG7ktIrnS1lzPgFY8eBeq3M2ZQpYxiwo2pUy+08kbDy58DmQP8X8A5 HiIj6A7EQjzBWccciAri0q8CcZbA73odsTmpOT+K4uCdkmB+3kc4giuNiAlsY6qxhnvb N5BIe5uxq0Q/IiHpb7WqJaobIM7xkaDycjGqmrpzPn/mlo/YX30XDHTVNta9pDMTwOpq j5u7M5a66pH8APquwsa0gO1ACexhmDfll387TlaEJWVpFuWoSs/AEhtRWDAG7Q57uLUH L4/w== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from sourceware.org (ip-8-43-85-97.sourceware.org. [8.43.85.97]) by mx.google.com with ESMTPS id v7-20020a056402174700b0048bffdbb775si13301252edx.202.2023.01.05.10.25.10 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 Jan 2023 10:25:10 -0800 (PST) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 6CDA538582A1 for ; Thu, 5 Jan 2023 18:25:06 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from dellerweb.de (unknown [IPv6:2a02:c207:3003:236::1]) by sourceware.org (Postfix) with ESMTPS id 5CDC83858D28 for ; Thu, 5 Jan 2023 18:24:41 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 5CDC83858D28 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=bell.net Authentication-Results: sourceware.org; spf=fail smtp.mailfrom=bell.net Received: from mx3210.localdomain (bras-base-otwaon0925w-grc-03-216-208-213-126.dsl.bell.ca [216.208.213.126]) by dellerweb.de (Postfix) with ESMTPSA id 805B01600053; Thu, 5 Jan 2023 19:24:39 +0100 (CET) Received: by mx3210.localdomain (Postfix, from userid 1000) id D23C922011B; Thu, 5 Jan 2023 18:24:37 +0000 (UTC) Date: Thu, 5 Jan 2023 18:24:37 +0000 From: John David Anglin To: GCC Patches Cc: libstdc++-v3@gcc.gnu.org Subject: [committed] hppa: Fix atomic operations on PA-RISC 2.0 processors Message-ID: MIME-Version: 1.0 Content-Disposition: inline X-Spam-Status: No, score=-10.1 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KHOP_HELO_FCRDNS, MAY_BE_FORGED, SPF_HELO_NONE, SPF_SOFTFAIL, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1754207995460657820?= X-GMAIL-MSGID: =?utf-8?q?1754207995460657820?= This changes fixes the atomic operations defined for hppa processors in libstdc++-v3. It appears they were originally written with only PA 1.x processors in mind. Tested on hppa64-hp-hpux11.11. Committed to trunk. Dave --- Fix atomic operations on PA-RISC 2.0 processors. PA-RISC 2.0 supports out-of-order execution for loads and stores. Thus, we need to synchonize memory accesses. This change revises the lock releases in __exchange_and_add and __atomic_add to use an ordered store with release semantics. We also use an ordered load in the inner spin loop. We use the "ldcw,co" instruction instead of "ldcw" when compiled for PA 2.0. Most PA 2.0 processors are coherent and can execute the ldcw instruction in cache for improved performance. Finally, the inner spin loop is revised to immediately branch to the ldcw instruction when it detects the lock is free. 2023-01-05 John David Anglin libstdc++-v3/ChangeLog: * config/cpu/hppa/atomicity.h (_PA_LDCW_INSN): Define. (__exchange_and_add): Use _PA_LDCW_INSN. Use ordered store for lock release. Revise loop. (__atomic_add): Likewise. diff --git a/libstdc++-v3/config/cpu/hppa/atomicity.h b/libstdc++-v3/config/cpu/hppa/atomicity.h index bb997e70c1d..658073537a4 100644 --- a/libstdc++-v3/config/cpu/hppa/atomicity.h +++ b/libstdc++-v3/config/cpu/hppa/atomicity.h @@ -25,6 +25,15 @@ #include #include +/* Perform ldcw operation in cache when possible. */ +#ifndef _PA_LDCW_INSN +# ifdef _PA_RISC2_0 +# define _PA_LDCW_INSN "ldcw,co" +# else +# define _PA_LDCW_INSN "ldcw" +# endif +#endif + namespace __gnu_cxx _GLIBCXX_VISIBILITY(default) { _GLIBCXX_BEGIN_NAMESPACE_VERSION @@ -51,19 +60,19 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION int tmp; volatile int& lock = _Atomicity_lock<0>::_S_atomicity_lock; - __asm__ __volatile__ ("ldcw 0(%1),%0\n\t" + __asm__ __volatile__ (_PA_LDCW_INSN " 0(%1),%0\n\t" "cmpib,<>,n 0,%0,.+20\n\t" - "ldw 0(%1),%0\n\t" - "cmpib,= 0,%0,.-4\n\t" + "ldw,ma 0(%1),%0\n\t" + "cmpib,<> 0,%0,.-12\n\t" "nop\n\t" - "b,n .-20" + "b,n .-12" : "=&r" (tmp) : "r" (&lock) : "memory"); result = *__mem; *__mem = result + __val; - __asm__ __volatile__ ("stw %1,0(%0)" + __asm__ __volatile__ ("stw,ma %1,0(%0)" : : "r" (&lock), "r" (tmp) : "memory"); return result; } @@ -75,18 +84,18 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION int tmp; volatile int& lock = _Atomicity_lock<0>::_S_atomicity_lock; - __asm__ __volatile__ ("ldcw 0(%1),%0\n\t" + __asm__ __volatile__ (_PA_LDCW_INSN " 0(%1),%0\n\t" "cmpib,<>,n 0,%0,.+20\n\t" - "ldw 0(%1),%0\n\t" - "cmpib,= 0,%0,.-4\n\t" + "ldw,ma 0(%1),%0\n\t" + "cmpib,<> 0,%0,.-12\n\t" "nop\n\t" - "b,n .-20" + "b,n .-12" : "=&r" (tmp) : "r" (&lock) : "memory"); *__mem += __val; - __asm__ __volatile__ ("stw %1,0(%0)" + __asm__ __volatile__ ("stw,ma %1,0(%0)" : : "r" (&lock), "r" (tmp) : "memory"); }