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[2620:137:e000::1:20]) by mx.google.com with ESMTP id l70-20020a639149000000b004985a58d4f1si33542815pge.732.2023.01.05.09.23.56; Thu, 05 Jan 2023 09:24:09 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@baylibre-com.20210112.gappssmtp.com header.s=20210112 header.b=DFV2Bk7p; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235425AbjAEROy (ORCPT + 99 others); Thu, 5 Jan 2023 12:14:54 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34576 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233734AbjAEROW (ORCPT ); Thu, 5 Jan 2023 12:14:22 -0500 Received: from mail-wr1-x429.google.com (mail-wr1-x429.google.com [IPv6:2a00:1450:4864:20::429]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 75D6067BD7 for ; Thu, 5 Jan 2023 09:08:42 -0800 (PST) Received: by mail-wr1-x429.google.com with SMTP id t15so27899420wro.9 for ; Thu, 05 Jan 2023 09:08:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=BGyNZMSELVhIYsmh8IQ0cClyJQ3/Pu1dOTSavukgh6c=; b=DFV2Bk7pE1z4nPsGE5YQsNh5/MwQhELQBIwLpGoUt5Kr9gGjWSCWaFcpmx/AiWgzTM CeJmBndmStn53lw/APB9JGUuZ75hK168BLWCI/aimccr/+KgtnF2uyggiH/FpeScDRZ9 +Yl4VULKayXF9MQk0OaIC5ksglOZuaQtzTLCqmwMD/1z4GQbtzQL3k7lIkYbHCrOMtow OtLWWmEESfhoGWyamVruOyv2ut8FI+UEPxH2mD3AOfjNKwJHDRXDin5IrcMvaC0GLALj YbliiPCOSz8pGhwtNyXH32N8CUQXHE6sJcSAizkGHLBmITscU38JNk17TMPNYeNMrW1I pQ+w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=BGyNZMSELVhIYsmh8IQ0cClyJQ3/Pu1dOTSavukgh6c=; b=e/xDxeXAuDeHHZsOuahBNBAn/4z0br2fWFocSFSdR0CuwuciGFVN1AX9obZ4h3IFrz UzFPs1v3gNTLVH0FjDr0h0ZzQzDSxMqflyOPv+jHiwbCDzrH7tg60X95fgk5ryzsk+/A 0XgXl1akLLuuUxx59Sl04YHWWK5wWTmzRu3eZd5m7+xO5qly/WyfknyqZxutwaaJtefM cMr8nYMACRXEShvxl4arNgzdeWC/ruhDSmx4OljvyP0zIPEp4M62BZuJqbgARuQesyhr XB0i/P71bF/O0SmTct623VOC5Nxg8UgYjeklDquBmgRSm8kZebdzA0Fm3bniVY+1TpZ2 tn5w== X-Gm-Message-State: AFqh2krClZN8DtJQB6hLphiaQg/6Mz/uJEyXw4roWSwc+tR9IYAZeu9n FqYUAGqlw+4xWGBWBnzTzwvL9Q== X-Received: by 2002:a5d:4e4c:0:b0:2b8:bcd8:1808 with SMTP id r12-20020a5d4e4c000000b002b8bcd81808mr215071wrt.44.1672938467798; Thu, 05 Jan 2023 09:07:47 -0800 (PST) Received: from blmsp.fritz.box ([2001:4091:a245:805c:9cf4:fdb8:bb61:5f4e]) by smtp.gmail.com with ESMTPSA id f14-20020adfe90e000000b002365730eae8sm37164853wrm.55.2023.01.05.09.07.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 Jan 2023 09:07:47 -0800 (PST) From: Markus Schneider-Pargmann To: Rob Herring , Krzysztof Kozlowski , Matthias Brugger Cc: Chun-Jie Chen , AngeloGioacchino Del Regno , Fabien Parent , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, Fabien Parent , Markus Schneider-Pargmann Subject: [PATCH 1/8] dt-bindings: power: Add MT8365 power domains Date: Thu, 5 Jan 2023 18:07:28 +0100 Message-Id: <20230105170735.1637416-2-msp@baylibre.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230105170735.1637416-1-msp@baylibre.com> References: <20230105170735.1637416-1-msp@baylibre.com> MIME-Version: 1.0 X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1754204155908594612?= X-GMAIL-MSGID: =?utf-8?q?1754204155908594612?= From: Fabien Parent Add power domains dt-bindings for MT8365. Signed-off-by: Fabien Parent Signed-off-by: Markus Schneider-Pargmann Reviewed-by: Rob Herring --- Notes: Changes in v4: - Add infracfg_nao as it is used by mt8365 Changes in v3: - Renamed mt8365-power.h to mediatek,mt8365-power.h Changes in v2: - Made include/dt-bindings/power/mt8365-power.h dual-license. .../power/mediatek,power-controller.yaml | 6 ++++++ .../dt-bindings/power/mediatek,mt8365-power.h | 19 +++++++++++++++++++ 2 files changed, 25 insertions(+) create mode 100644 include/dt-bindings/power/mediatek,mt8365-power.h diff --git a/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml b/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml index 605ec7ab5f63..a496c43cfa16 100644 --- a/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml +++ b/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml @@ -30,6 +30,7 @@ properties: - mediatek,mt8186-power-controller - mediatek,mt8192-power-controller - mediatek,mt8195-power-controller + - mediatek,mt8365-power-controller '#power-domain-cells': const: 1 @@ -86,6 +87,7 @@ $defs: "include/dt-bindings/power/mt8183-power.h" - for MT8183 type power domain. "include/dt-bindings/power/mt8192-power.h" - for MT8192 type power domain. "include/dt-bindings/power/mt8195-power.h" - for MT8195 type power domain. + "include/dt-bindings/power/mediatek,mt8365-power.h" - for MT8365 type power domain. maxItems: 1 clocks: @@ -113,6 +115,10 @@ $defs: $ref: /schemas/types.yaml#/definitions/phandle description: phandle to the device containing the INFRACFG register range. + mediatek,infracfg-nao: + $ref: /schemas/types.yaml#/definitions/phandle + description: phandle to the device containing the INFRACFG-NAO register range. + mediatek,smi: $ref: /schemas/types.yaml#/definitions/phandle description: phandle to the device containing the SMI register range. diff --git a/include/dt-bindings/power/mediatek,mt8365-power.h b/include/dt-bindings/power/mediatek,mt8365-power.h new file mode 100644 index 000000000000..e6cfd0ec7871 --- /dev/null +++ b/include/dt-bindings/power/mediatek,mt8365-power.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ +/* + * Copyright (c) 2022 MediaTek Inc. + */ + +#ifndef _DT_BINDINGS_POWER_MT8365_POWER_H +#define _DT_BINDINGS_POWER_MT8365_POWER_H + +#define MT8365_POWER_DOMAIN_MM 0 +#define MT8365_POWER_DOMAIN_CONN 1 +#define MT8365_POWER_DOMAIN_MFG 2 +#define MT8365_POWER_DOMAIN_AUDIO 3 +#define MT8365_POWER_DOMAIN_CAM 4 +#define MT8365_POWER_DOMAIN_DSP 5 +#define MT8365_POWER_DOMAIN_VDEC 6 +#define MT8365_POWER_DOMAIN_VENC 7 +#define MT8365_POWER_DOMAIN_APU 8 + +#endif /* _DT_BINDINGS_POWER_MT8365_POWER_H */ From patchwork Thu Jan 5 17:07:29 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Markus Schneider-Pargmann X-Patchwork-Id: 39720 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4e01:0:0:0:0:0 with SMTP id p1csp412163wrt; Thu, 5 Jan 2023 09:27:58 -0800 (PST) X-Google-Smtp-Source: AMrXdXscM7ZQo3x4rNsQxvtL1lB8wgdsOGM//MiTQV1TQSNreXVMbh32Mio5hcJ6Yeo+i3Rc1bIh X-Received: by 2002:aa7:d893:0:b0:47f:ab65:b3fe with SMTP id u19-20020aa7d893000000b0047fab65b3femr38479342edq.33.1672939677915; Thu, 05 Jan 2023 09:27:57 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1672939677; cv=none; d=google.com; s=arc-20160816; b=QvBqo8LIADJ22VMZ1O13607ruRAYRIxY3lFcoK8WO2rbg4Vd4N0flT4yBVPHBeXBRv mn5VywC3Ht3BxtWZbBHrGTFgEOufkgcjP2/902ySXsUJ0WK1FvHZBWKjM1zoesgQE7T8 76bx9zIyj2yGldqsSoj8Yo0AuW+hSWNUHPnqcLnH7LC7P5nVirptgunvPpLKUsUQuRma XGrbJ34zU7xO+XbKg3xt22rVziigBRe1gxjZHsi6ehEmdbd0Qy94GUmddEiEVqFw8tFX PNlJJE1h8O7wTiDYo3i/XcvlOU3XNGYTvs+YbhWgsglFTLuIAdnHxThO828gRPAziVp0 mc/A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=xvXKcEbwULcjNy/x9YB9utQCAcj11EGEkTp6VrX3MLc=; b=E/og2S1/hKkHFw7b8DBLZvyFdziFD09fNZILb8ayuLpZhCOQMS5rr9YIegETdUMj3L Zoo3TzdRV+e862jlfNRC1Gtm9A/aOCxAFgHdgsYSXMO9G5y+C10+v49Xpe1KeCcXuO0s eN5YhQvtWLf1NvlwvGHp4A+m3nBtelr4cQy21lcxj8iOiLkpzi4NnsSkfCC/6rfDDWCR b7c267Zy2q9rk5LBqngxtlZ1HngjZjcTXPXqx5nvoZB70i6FdRhOag+N6HXMbXAfHlBU LGl4cM/fqledFo2SlGLAxjhcieTEWFzsn8IH95OSjsg03cw+02OOed4TNTQW3ZLLZMAw ZLNg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@baylibre-com.20210112.gappssmtp.com header.s=20210112 header.b=TKpKVqD9; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. 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In preparation of m8365 power domain support split this one mask into two, one mask for set and clear, another one for acknowledge. Signed-off-by: Markus Schneider-Pargmann --- drivers/soc/mediatek/mtk-pm-domains.c | 24 ++++++++++++++---------- drivers/soc/mediatek/mtk-pm-domains.h | 14 ++++++++------ 2 files changed, 22 insertions(+), 16 deletions(-) diff --git a/drivers/soc/mediatek/mtk-pm-domains.c b/drivers/soc/mediatek/mtk-pm-domains.c index 474b272f9b02..4333cd297405 100644 --- a/drivers/soc/mediatek/mtk-pm-domains.c +++ b/drivers/soc/mediatek/mtk-pm-domains.c @@ -122,18 +122,20 @@ static int _scpsys_bus_protect_enable(const struct scpsys_bus_prot_data *bpd, st int i, ret; for (i = 0; i < SPM_MAX_BUS_PROT_DATA; i++) { - u32 val, mask = bpd[i].bus_prot_mask; + u32 val; + u32 set_clr_mask = bpd[i].bus_prot_set_clr_mask; + u32 sta_mask = bpd[i].bus_prot_sta_mask; - if (!mask) + if (!set_clr_mask) break; if (bpd[i].bus_prot_reg_update) - regmap_set_bits(regmap, bpd[i].bus_prot_set, mask); + regmap_set_bits(regmap, bpd[i].bus_prot_set, set_clr_mask); else - regmap_write(regmap, bpd[i].bus_prot_set, mask); + regmap_write(regmap, bpd[i].bus_prot_set, set_clr_mask); ret = regmap_read_poll_timeout(regmap, bpd[i].bus_prot_sta, - val, (val & mask) == mask, + val, (val & sta_mask) == sta_mask, MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT); if (ret) return ret; @@ -159,21 +161,23 @@ static int _scpsys_bus_protect_disable(const struct scpsys_bus_prot_data *bpd, int i, ret; for (i = SPM_MAX_BUS_PROT_DATA - 1; i >= 0; i--) { - u32 val, mask = bpd[i].bus_prot_mask; + u32 val; + u32 set_clr_mask = bpd[i].bus_prot_set_clr_mask; + u32 sta_mask = bpd[i].bus_prot_sta_mask; - if (!mask) + if (!set_clr_mask) continue; if (bpd[i].bus_prot_reg_update) - regmap_clear_bits(regmap, bpd[i].bus_prot_clr, mask); + regmap_clear_bits(regmap, bpd[i].bus_prot_clr, set_clr_mask); else - regmap_write(regmap, bpd[i].bus_prot_clr, mask); + regmap_write(regmap, bpd[i].bus_prot_clr, set_clr_mask); if (bpd[i].ignore_clr_ack) continue; ret = regmap_read_poll_timeout(regmap, bpd[i].bus_prot_sta, - val, !(val & mask), + val, !(val & sta_mask), MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT); if (ret) return ret; diff --git a/drivers/soc/mediatek/mtk-pm-domains.h b/drivers/soc/mediatek/mtk-pm-domains.h index 7d3c0c36316c..8aaed1c939d7 100644 --- a/drivers/soc/mediatek/mtk-pm-domains.h +++ b/drivers/soc/mediatek/mtk-pm-domains.h @@ -41,23 +41,24 @@ #define SPM_MAX_BUS_PROT_DATA 6 -#define _BUS_PROT(_mask, _set, _clr, _sta, _update, _ignore) { \ - .bus_prot_mask = (_mask), \ +#define _BUS_PROT(_set_clr_mask, _set, _clr, _sta_mask, _sta, _update, _ignore) { \ + .bus_prot_set_clr_mask = (_set_clr_mask), \ .bus_prot_set = _set, \ .bus_prot_clr = _clr, \ + .bus_prot_sta_mask = (_sta_mask), \ .bus_prot_sta = _sta, \ .bus_prot_reg_update = _update, \ .ignore_clr_ack = _ignore, \ } #define BUS_PROT_WR(_mask, _set, _clr, _sta) \ - _BUS_PROT(_mask, _set, _clr, _sta, false, false) + _BUS_PROT(_mask, _set, _clr, _mask, _sta, false, false) #define BUS_PROT_WR_IGN(_mask, _set, _clr, _sta) \ - _BUS_PROT(_mask, _set, _clr, _sta, false, true) + _BUS_PROT(_mask, _set, _clr, _mask, _sta, false, true) #define BUS_PROT_UPDATE(_mask, _set, _clr, _sta) \ - _BUS_PROT(_mask, _set, _clr, _sta, true, false) + _BUS_PROT(_mask, _set, _clr, _mask, _sta, true, false) #define BUS_PROT_UPDATE_TOPAXI(_mask) \ BUS_PROT_UPDATE(_mask, \ @@ -66,9 +67,10 @@ INFRA_TOPAXI_PROTECTSTA1) struct scpsys_bus_prot_data { - u32 bus_prot_mask; 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These will be used later for WAY_EN bits. Signed-off-by: Markus Schneider-Pargmann --- drivers/soc/mediatek/mtk-pm-domains.c | 68 +++++++++++++++------------ 1 file changed, 39 insertions(+), 29 deletions(-) diff --git a/drivers/soc/mediatek/mtk-pm-domains.c b/drivers/soc/mediatek/mtk-pm-domains.c index 4333cd297405..999e1f6c86b0 100644 --- a/drivers/soc/mediatek/mtk-pm-domains.c +++ b/drivers/soc/mediatek/mtk-pm-domains.c @@ -117,26 +117,50 @@ static int scpsys_sram_disable(struct scpsys_domain *pd) MTK_POLL_TIMEOUT); } +static int scpsys_bus_protect_clear(const struct scpsys_bus_prot_data *bpd, + struct regmap *regmap) +{ + u32 val; + u32 sta_mask = bpd->bus_prot_sta_mask; + + if (bpd->bus_prot_reg_update) + regmap_clear_bits(regmap, bpd->bus_prot_clr, bpd->bus_prot_set_clr_mask); + else + regmap_write(regmap, bpd->bus_prot_clr, bpd->bus_prot_set_clr_mask); + + if (bpd->ignore_clr_ack) + return 0; + + return regmap_read_poll_timeout(regmap, bpd->bus_prot_sta, + val, !(val & sta_mask), + MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT); +} + +static int scpsys_bus_protect_set(const struct scpsys_bus_prot_data *bpd, + struct regmap *regmap) +{ + u32 val; + u32 sta_mask = bpd->bus_prot_sta_mask; + + if (bpd->bus_prot_reg_update) + regmap_set_bits(regmap, bpd->bus_prot_set, bpd->bus_prot_set_clr_mask); + else + regmap_write(regmap, bpd->bus_prot_set, bpd->bus_prot_set_clr_mask); + + return regmap_read_poll_timeout(regmap, bpd->bus_prot_sta, + val, (val & sta_mask) == sta_mask, + MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT); +} + static int _scpsys_bus_protect_enable(const struct scpsys_bus_prot_data *bpd, struct regmap *regmap) { int i, ret; for (i = 0; i < SPM_MAX_BUS_PROT_DATA; i++) { - u32 val; - u32 set_clr_mask = bpd[i].bus_prot_set_clr_mask; - u32 sta_mask = bpd[i].bus_prot_sta_mask; - - if (!set_clr_mask) + if (!bpd[i].bus_prot_set_clr_mask) break; - if (bpd[i].bus_prot_reg_update) - regmap_set_bits(regmap, bpd[i].bus_prot_set, set_clr_mask); - else - regmap_write(regmap, bpd[i].bus_prot_set, set_clr_mask); - - ret = regmap_read_poll_timeout(regmap, bpd[i].bus_prot_sta, - val, (val & sta_mask) == sta_mask, - MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT); + ret = scpsys_bus_protect_set(&bpd[i], regmap); if (ret) return ret; } @@ -161,24 +185,10 @@ static int _scpsys_bus_protect_disable(const struct scpsys_bus_prot_data *bpd, int i, ret; for (i = SPM_MAX_BUS_PROT_DATA - 1; i >= 0; i--) { - u32 val; - u32 set_clr_mask = bpd[i].bus_prot_set_clr_mask; - u32 sta_mask = bpd[i].bus_prot_sta_mask; - - if (!set_clr_mask) - continue; - - if (bpd[i].bus_prot_reg_update) - regmap_clear_bits(regmap, bpd[i].bus_prot_clr, set_clr_mask); - else - regmap_write(regmap, bpd[i].bus_prot_clr, set_clr_mask); - - if (bpd[i].ignore_clr_ack) + if (!bpd[i].bus_prot_set_clr_mask) continue; - ret = regmap_read_poll_timeout(regmap, bpd[i].bus_prot_sta, - val, !(val & sta_mask), - MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT); + ret = scpsys_bus_protect_clear(&bpd[i], regmap); if (ret) return ret; } From patchwork Thu Jan 5 17:07:31 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Markus Schneider-Pargmann X-Patchwork-Id: 39715 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4e01:0:0:0:0:0 with SMTP id p1csp411288wrt; Thu, 5 Jan 2023 09:26:08 -0800 (PST) X-Google-Smtp-Source: AMrXdXuso4FtigmRhaZxDku6ZKmiBWP2F+Ld/bmPV6lmGjLCCNh41wCQLn6sJOCCrgxg1aHoNbii X-Received: by 2002:a17:90a:4e0d:b0:226:350e:1b36 with SMTP id n13-20020a17090a4e0d00b00226350e1b36mr24766127pjh.16.1672939568338; Thu, 05 Jan 2023 09:26:08 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1672939568; cv=none; d=google.com; s=arc-20160816; b=CxSf8xq8CQ6qag9w2ga5aKUChSRJ/PxaVZ3069GWL2YrEpxaWm7aWSbhVtWAktJ5DP UY/cMWHb8TfNBAW9A7U0F5kpCXz897QkmhVUYtbBruUrukk9WbjsO82RvPOoGuqefNEo h8QYISoxXcQIBdeaCKsZ1KSpAJxPkGwX9t9wmnyepMPUTZVua6oSjYiczu7hUoTd0GLO CMM3MQoCH9M8hnkb5TJbPYsYtGnBfErwTQSQ/xzBmCO5zIjflUyxh4FvJsJCwrwvGg/q LQpVB7k0Ekf0mfkgpwbvm28iG/Xw4naCqCCpuYUTNyrIC1Ty7hkcMu2wVXNb4pYIXEBz AnNg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=XQxJ8mog5ezSsMdjmsKqEBp6+hXiOvAg1jR6vm7PG+8=; b=Tchb/K/5vTRLV9RZ1ZAOsBt3qXNHKHz/L/dt6tca9dHMw1kmdBdgm1wjdC7cV+Pv/+ fYtQnwTWZxGSLeEn0h3WH7Iiwz/M04u/eu/JmnfKYCiWqfc/hsXmWKt9Rmt3jkMP+G8p hOSRBMIfp0Bj6sviIPxPIijOBGJQQoX5+qVeqI+jxE1RtfpvwqHb9LV4i4ZfOY1l6dn+ 72k3nYNLx3Uf3JLfUZT/wYRhBLnXOu5IYlWFN0F07toxdx2tNIq25yZLLbNniZOXZfFU xupKztVMOlys4nzsV+BM3NoZqnhYjyFwQbpYDVs0wBaktGv8K1U3ce6zRy4hSW32KvH2 U6nA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@baylibre-com.20210112.gappssmtp.com header.s=20210112 header.b=4kxlkctB; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Markus Schneider-Pargmann --- drivers/soc/mediatek/mtk-pm-domains.h | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/soc/mediatek/mtk-pm-domains.h b/drivers/soc/mediatek/mtk-pm-domains.h index 8aaed1c939d7..da827e91d462 100644 --- a/drivers/soc/mediatek/mtk-pm-domains.h +++ b/drivers/soc/mediatek/mtk-pm-domains.h @@ -66,6 +66,18 @@ INFRA_TOPAXI_PROTECTEN, \ INFRA_TOPAXI_PROTECTSTA1) +/** + * struct scpsys_bus_prot_data - Bus protection setting + * @bus_prot_set_clr_mask: Bitmask used for the set and clear registers. + * @bus_prot_set: infracfg set register. + * @bus_prot_clr: infracfg clear register. + * @bus_prot_sta_mask: Bitmask used for the status register. + * @bus_prot_sta: infracfg status register. + * @bus_prot_reg_update: Only update the register bits given in the mask, do not + * write the whole register. + * @ignore_clk_ack: Ignore the result in the status register for clear + * operations. + */ struct scpsys_bus_prot_data { u32 bus_prot_set_clr_mask; u32 bus_prot_set; From patchwork Thu Jan 5 17:07:32 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Markus Schneider-Pargmann X-Patchwork-Id: 39719 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4e01:0:0:0:0:0 with SMTP id p1csp411868wrt; Thu, 5 Jan 2023 09:27:17 -0800 (PST) X-Google-Smtp-Source: AMrXdXuzAB4OkQ5fJm7aSORPwhEn8h54eG0HD1v6nSijfNCaQ1IR3uJDFpdJcFqyk4CT4blttp8u X-Received: by 2002:a17:907:6f17:b0:7c1:5019:50c6 with SMTP id sy23-20020a1709076f1700b007c1501950c6mr60309951ejc.72.1672939637612; Thu, 05 Jan 2023 09:27:17 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1672939637; cv=none; d=google.com; s=arc-20160816; b=xN/SvxlzqfjXqnyswsd3wjp3p7GHPo+z6R+rqMscACQ1uf3Ih6i/tLU7dM5l3juUiL NHqG5UT9n0l+ufGO7yrRDVKWcYW4qHU469b/aCop37EoumHyjRAmmchDAZ4suT+KsZdz xl6VcGi6NnS+Z1pdmV4mgfpO3jbBHRNQ1GgvuRL5LfgXW9CKT/9IEiv5yirL1YgsYnqT eaBd7D4GRtzVIbIVOghJuoWMx08+Xz/JQdhO77/wpraJwm6C97GZ0FcesvxtMWrO4VVt b0/YZg5QQyFpBlRDgc4BcOw2vAsG7dqmKiOwd7biH7V9S/uj0I2BuIzrFH41HnaE20Wy Au4w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=+AVf+pfLkaJ1Gl2NWqezqv2bXezRKHHSaj8ghEqd14w=; b=cFfTIoSwKWR1207FgvstNSqyKcM5nN1lSQI1LrGLaBSan5lvCsq6vEZ8LzDR+9ce14 SecPw37R4R1Uku+VyrE8SP7z/hlnrX0fqwNL0mHjC53CpLmX8NOwyeiwk0Y48K2Fl2jH ooXbGobcrU2B6Q8/z1UCQaHJMmoptc4OOOcji1oIJ/UFLiocskK6c3M1IfWs1wKyymw2 vGnOcC4UjecGZkzIgl5ERynU1ZqTDqv6mBELltg7g54xF3TsL3KSABzIjNK/ri2NYssO HVXJBhgn7LtNMceo4yNW94BjPuEOgoLT8Xy9AUhbCs6c3Y48k1kwn04yohNdwwf/Jd90 f5ew== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@baylibre-com.20210112.gappssmtp.com header.s=20210112 header.b=y7jLrTG7; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. 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There are a lot of other flags defined as well. Fixes: 59b644b01cf4 ("soc: mediatek: Add MediaTek SCPSYS power domains") Signed-off-by: Markus Schneider-Pargmann --- drivers/soc/mediatek/mtk-pm-domains.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/soc/mediatek/mtk-pm-domains.h b/drivers/soc/mediatek/mtk-pm-domains.h index da827e91d462..34642a279213 100644 --- a/drivers/soc/mediatek/mtk-pm-domains.h +++ b/drivers/soc/mediatek/mtk-pm-domains.h @@ -95,7 +95,7 @@ struct scpsys_bus_prot_data { * @ctl_offs: The offset for main power control register. * @sram_pdn_bits: The mask for sram power control bits. * @sram_pdn_ack_bits: The mask for sram power control acked bits. - * @caps: The flag for active wake-up action. + * @caps: MTK_SCPD_* capability flags. * @bp_infracfg: bus protection for infracfg subsystem * @bp_smi: bus protection for smi subsystem */ From patchwork Thu Jan 5 17:07:33 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Markus Schneider-Pargmann X-Patchwork-Id: 39714 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4e01:0:0:0:0:0 with SMTP id p1csp411070wrt; Thu, 5 Jan 2023 09:25:41 -0800 (PST) X-Google-Smtp-Source: AMrXdXvzZFf/PbUD8YcWL7fx+3Ex6iTwTIuYldpNQBHvSyuDilTxyXRqmhJSmKUmnntXO8k3lRDv X-Received: by 2002:a17:907:6d12:b0:7c1:79f5:9545 with SMTP id sa18-20020a1709076d1200b007c179f59545mr63912175ejc.42.1672939541481; Thu, 05 Jan 2023 09:25:41 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1672939541; cv=none; d=google.com; s=arc-20160816; b=DLa8d1YforoEJmMgLKFPkpR5fpUTGhP3G9a3ISN2vnUb/Kv+qe10KL6pQfSzg1aRnL 3T9CVWS351H5+xyJphONV2w4+5tIjxBHlQyU5qK09DbJCymTa+mFYJEYlhDIvHW9KoQC Qqguu1+mbsr3Humi+Tv8em9OqWWScfedQnlHOuflQ7Omatf0VPZJ2LX81PfSzn/NkMaz eqnTESQ/wrZOuBcGIIyQz9LZq4k8O39a+WV5gDWgLtZKZEwcC/DQETcrpd2FTprOJ/pg /R4JNTyrRfZGA8VwzSALcpC7dGrx5xp3KXKfBLP7YC1+uEDNW4rhpBdCrofXdsE3/qVU W0Ng== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=KPJV1qfI65vcb6ofJWhCMHNO2xRqa9GjQ0e1B9CiTNQ=; b=foxjirKAhX1fgRtiKezSeO2e3/B//NF0GUjJ9wDBs2c6az+KrlkSuvKYiAooyPE6o1 CLEKmL/iMPSXcnt/Xh+5w0+9qNGl2wwvnKIRsiGPJvdd6QNO+tO0zzUVSEPJVz95dB/q lzZUYkf9qfy0yCXGzHMKIyllsi1t90FbviI/xzP9Ksl8o9AWyd9HiVWsedtnBIoj1JlD hMRkWc9RIx2eKftBjFfLK1Zt7BhLigcuWFGviQigGCeLFIwpF9oZbQfo9f+TsWCcufLy zzQkI2N5W3zpknExdizZYFI7e3E8p7xYlLmjW9tCADtxfq6SrVvcSWgCRAYDKihe40bG gRLg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@baylibre-com.20210112.gappssmtp.com header.s=20210112 header.b=yNsOPbDT; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. 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These operations enable a path between different units of the chip and are labeled as 'way_en' in the register descriptions. This operation is required by the mt8365 for the MM power domain. Signed-off-by: Alexandre Bailon Signed-off-by: Fabien Parent Signed-off-by: Markus Schneider-Pargmann --- Notes: Changes in v4: - Redesigned the patch to be better to understand and have less code duplication Changes in v3: - Separated the way_en functions for clarity - Added some checks for infracfg_nao Changes in v2: - some minor style fixes. - Renamed 'wayen' to 'way_en' to clarify the meaning - Updated commit message drivers/soc/mediatek/mtk-pm-domains.c | 57 ++++++++++++++++++++------- drivers/soc/mediatek/mtk-pm-domains.h | 16 ++++++-- 2 files changed, 54 insertions(+), 19 deletions(-) diff --git a/drivers/soc/mediatek/mtk-pm-domains.c b/drivers/soc/mediatek/mtk-pm-domains.c index 999e1f6c86b0..d53309f050ee 100644 --- a/drivers/soc/mediatek/mtk-pm-domains.c +++ b/drivers/soc/mediatek/mtk-pm-domains.c @@ -43,6 +43,7 @@ struct scpsys_domain { struct clk_bulk_data *clks; int num_subsys_clks; struct clk_bulk_data *subsys_clks; + struct regmap *infracfg_nao; struct regmap *infracfg; struct regmap *smi; struct regulator *supply; @@ -118,10 +119,13 @@ static int scpsys_sram_disable(struct scpsys_domain *pd) } static int scpsys_bus_protect_clear(const struct scpsys_bus_prot_data *bpd, - struct regmap *regmap) + struct regmap *regmap, + struct regmap *sta_regmap) { u32 val; u32 sta_mask = bpd->bus_prot_sta_mask; + /* way_en acknowledges successful clear with the bit being set */ + u32 expected_ack = (bpd->way_en ? sta_mask : 0); if (bpd->bus_prot_reg_update) regmap_clear_bits(regmap, bpd->bus_prot_clr, bpd->bus_prot_set_clr_mask); @@ -131,13 +135,14 @@ static int scpsys_bus_protect_clear(const struct scpsys_bus_prot_data *bpd, if (bpd->ignore_clr_ack) return 0; - return regmap_read_poll_timeout(regmap, bpd->bus_prot_sta, - val, !(val & sta_mask), + return regmap_read_poll_timeout(sta_regmap, bpd->bus_prot_sta, + val, (val & sta_mask) == expected_ack, MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT); } static int scpsys_bus_protect_set(const struct scpsys_bus_prot_data *bpd, - struct regmap *regmap) + struct regmap *regmap, + struct regmap *sta_regmap) { u32 val; u32 sta_mask = bpd->bus_prot_sta_mask; @@ -147,12 +152,13 @@ static int scpsys_bus_protect_set(const struct scpsys_bus_prot_data *bpd, else regmap_write(regmap, bpd->bus_prot_set, bpd->bus_prot_set_clr_mask); - return regmap_read_poll_timeout(regmap, bpd->bus_prot_sta, + return regmap_read_poll_timeout(sta_regmap, bpd->bus_prot_sta, val, (val & sta_mask) == sta_mask, MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT); } -static int _scpsys_bus_protect_enable(const struct scpsys_bus_prot_data *bpd, struct regmap *regmap) +static int _scpsys_bus_protect_enable(const struct scpsys_bus_prot_data *bpd, + struct regmap *regmap, struct regmap *infracfg_nao) { int i, ret; @@ -160,9 +166,14 @@ static int _scpsys_bus_protect_enable(const struct scpsys_bus_prot_data *bpd, st if (!bpd[i].bus_prot_set_clr_mask) break; - ret = scpsys_bus_protect_set(&bpd[i], regmap); - if (ret) + if (bpd[i].way_en) + ret = scpsys_bus_protect_clear(&bpd[i], regmap, infracfg_nao); + else + ret = scpsys_bus_protect_set(&bpd[i], regmap, regmap); + if (ret) { + pr_err("%s %d %d\n", __PRETTY_FUNCTION__, __LINE__, ret); return ret; + } } return 0; @@ -172,15 +183,17 @@ static int scpsys_bus_protect_enable(struct scpsys_domain *pd) { int ret; - ret = _scpsys_bus_protect_enable(pd->data->bp_infracfg, pd->infracfg); + ret = _scpsys_bus_protect_enable(pd->data->bp_infracfg, + pd->infracfg, pd->infracfg_nao); if (ret) return ret; - return _scpsys_bus_protect_enable(pd->data->bp_smi, pd->smi); + return _scpsys_bus_protect_enable(pd->data->bp_smi, pd->smi, NULL); } static int _scpsys_bus_protect_disable(const struct scpsys_bus_prot_data *bpd, - struct regmap *regmap) + struct regmap *regmap, + struct regmap *infracfg_nao) { int i, ret; @@ -188,9 +201,14 @@ static int _scpsys_bus_protect_disable(const struct scpsys_bus_prot_data *bpd, if (!bpd[i].bus_prot_set_clr_mask) continue; - ret = scpsys_bus_protect_clear(&bpd[i], regmap); - if (ret) + if (bpd[i].way_en) + ret = scpsys_bus_protect_set(&bpd[i], regmap, infracfg_nao); + else + ret = scpsys_bus_protect_clear(&bpd[i], regmap, regmap); + if (ret) { + pr_err("%s %d %d\n", __PRETTY_FUNCTION__, __LINE__, ret); return ret; + } } return 0; @@ -200,11 +218,12 @@ static int scpsys_bus_protect_disable(struct scpsys_domain *pd) { int ret; - ret = _scpsys_bus_protect_disable(pd->data->bp_smi, pd->smi); + ret = _scpsys_bus_protect_disable(pd->data->bp_smi, pd->smi, NULL); if (ret) return ret; - return _scpsys_bus_protect_disable(pd->data->bp_infracfg, pd->infracfg); + return _scpsys_bus_protect_disable(pd->data->bp_infracfg, + pd->infracfg, pd->infracfg_nao); } static int scpsys_regulator_enable(struct regulator *supply) @@ -378,6 +397,14 @@ generic_pm_domain *scpsys_add_one_domain(struct scpsys *scpsys, struct device_no return ERR_CAST(pd->smi); } + pd->infracfg_nao = syscon_regmap_lookup_by_phandle(node, "mediatek,infracfg-nao"); + if (IS_ERR(pd->infracfg_nao)) { + if (MTK_SCPD_CAPS(pd, MTK_SCPD_HAS_WAY_EN)) + return ERR_CAST(pd->infracfg_nao); + + pd->infracfg_nao = NULL; + } + num_clks = of_clk_get_parent_count(node); if (num_clks > 0) { /* Calculate number of subsys_clks */ diff --git a/drivers/soc/mediatek/mtk-pm-domains.h b/drivers/soc/mediatek/mtk-pm-domains.h index 34642a279213..1fa634509db1 100644 --- a/drivers/soc/mediatek/mtk-pm-domains.h +++ b/drivers/soc/mediatek/mtk-pm-domains.h @@ -10,6 +10,7 @@ #define MTK_SCPD_DOMAIN_SUPPLY BIT(4) /* can't set MTK_SCPD_KEEP_DEFAULT_OFF at the same time */ #define MTK_SCPD_ALWAYS_ON BIT(5) +#define MTK_SCPD_HAS_WAY_EN BIT(6) #define MTK_SCPD_CAPS(_scpd, _x) ((_scpd)->data->caps & (_x)) #define SPM_VDE_PWR_CON 0x0210 @@ -41,7 +42,7 @@ #define SPM_MAX_BUS_PROT_DATA 6 -#define _BUS_PROT(_set_clr_mask, _set, _clr, _sta_mask, _sta, _update, _ignore) { \ +#define _BUS_PROT(_set_clr_mask, _set, _clr, _sta_mask, _sta, _update, _ignore, _way_en) { \ .bus_prot_set_clr_mask = (_set_clr_mask), \ .bus_prot_set = _set, \ .bus_prot_clr = _clr, \ @@ -49,16 +50,20 @@ .bus_prot_sta = _sta, \ .bus_prot_reg_update = _update, \ .ignore_clr_ack = _ignore, \ + .way_en = _way_en, \ } #define BUS_PROT_WR(_mask, _set, _clr, _sta) \ - _BUS_PROT(_mask, _set, _clr, _mask, _sta, false, false) + _BUS_PROT(_mask, _set, _clr, _mask, _sta, false, false, false) #define BUS_PROT_WR_IGN(_mask, _set, _clr, _sta) \ - _BUS_PROT(_mask, _set, _clr, _mask, _sta, false, true) + _BUS_PROT(_mask, _set, _clr, _mask, _sta, false, true, false) #define BUS_PROT_UPDATE(_mask, _set, _clr, _sta) \ - _BUS_PROT(_mask, _set, _clr, _mask, _sta, true, false) + _BUS_PROT(_mask, _set, _clr, _mask, _sta, true, false, false) + +#define BUS_PROT_WAY_EN(_set_mask, _set, _sta_mask, _sta) \ + _BUS_PROT(_set_mask, _set, _set, _sta_mask, _sta, true, false, true) #define BUS_PROT_UPDATE_TOPAXI(_mask) \ BUS_PROT_UPDATE(_mask, \ @@ -77,6 +82,8 @@ * write the whole register. * @ignore_clk_ack: Ignore the result in the status register for clear * operations. + * @way_en: Enable a way in the SoC. For this type the status bit to acknowledge + * the change is always 1 on successful change. */ struct scpsys_bus_prot_data { u32 bus_prot_set_clr_mask; @@ -86,6 +93,7 @@ struct scpsys_bus_prot_data { u32 bus_prot_sta; bool bus_prot_reg_update; bool ignore_clr_ack; + bool way_en; }; /** From patchwork Thu Jan 5 17:07:34 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Markus Schneider-Pargmann X-Patchwork-Id: 39712 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4e01:0:0:0:0:0 with SMTP id p1csp410998wrt; Thu, 5 Jan 2023 09:25:32 -0800 (PST) X-Google-Smtp-Source: AMrXdXtmrKRquROXtJ65pdHli057tT0DVnVQV8qGk13yqCtz7OTvVxYesgnkzqIJsSBZLS/ou2jG X-Received: by 2002:a05:6402:685:b0:46c:e558:ce60 with SMTP id f5-20020a056402068500b0046ce558ce60mr45227143edy.22.1672939532106; Thu, 05 Jan 2023 09:25:32 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1672939532; cv=none; d=google.com; s=arc-20160816; b=rO7KLmxr86TfvP3BKu5xMvqrJ7D6PpuiB2tGKmWsuAkVv6DPeoCIBp81UGnBvv/aAi 4Lc+/inJ0UyDxAfSyN9wAMR755o2eU0i13Kt/hBFxSvqCkEcNb2Ah/VRpZLIKu4ZIYWB li15ug6Q0xObx0bkvt7Aj/I5tsDJIivVnuEZUMuvidyq4bnGhT81h/cK/5d6dOyL16as 8Yw84H7OCL9qJkD3ujiFjpnwh6sgK/kakO0UtaVXSgqrHAYK7YpwDcTTmL4kKofIn0Zf Eg31NPNcQp9C/Y8YLVQxGERzXK1YGYwVC+KBMYQiAiewzpuiavTuiaJzKofIEqiQS/x6 tndQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=sncxYiJ19EBEMYozwgCXbGEKSdQ2+11yxAIRrAVvyso=; b=MruyvavDfvqckxRikYVRXz/XRtfh2NavMasa7o7nG8ccecivEWgrxknpE3/0dw3IOm tRE8my3xYIeBifGfjzV2U9/rRXDZJd+86LDHLC/6VR2Ad7lpCO/Dt/spGoMxKEairXC5 kT06QbwvYsy4u2hJw/6qi+BTcsF7Qi+tw7VTyOxA1BM+/jIqMDuCvGOgd1K2zZT8CCRI jaAHf1bLykEXWTnAa6OOzP2LOX1qsHWnvIdfwn+8Oa2RAZujfMK5BvPusYa9wepQqBig jSxKE+IO5ZVzybOQVGE5V3uoGXIGQ28VGCITBFd2s8z13MMHWJytTLT6SnvZfBCyLYLi ba4w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@baylibre-com.20210112.gappssmtp.com header.s=20210112 header.b=L8GGi7ni; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id m19-20020a056402431300b0047b79b99e58si37149357edc.446.2023.01.05.09.25.08; Thu, 05 Jan 2023 09:25:32 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@baylibre-com.20210112.gappssmtp.com header.s=20210112 header.b=L8GGi7ni; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234932AbjAERP2 (ORCPT + 99 others); Thu, 5 Jan 2023 12:15:28 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34286 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234975AbjAERO0 (ORCPT ); Thu, 5 Jan 2023 12:14:26 -0500 Received: from mail-wm1-x332.google.com (mail-wm1-x332.google.com [IPv6:2a00:1450:4864:20::332]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 198C467BEC for ; Thu, 5 Jan 2023 09:08:45 -0800 (PST) Received: by mail-wm1-x332.google.com with SMTP id ay2-20020a05600c1e0200b003d22e3e796dso1854930wmb.0 for ; Thu, 05 Jan 2023 09:08:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=sncxYiJ19EBEMYozwgCXbGEKSdQ2+11yxAIRrAVvyso=; b=L8GGi7ni7dl6wFN8IW77qB70367v8PhZ3Sd7+oJtMLY5Ej9cNvDNLQSAsDm09a+xsP wK3c5FXsCw2fAI8nS6woEXI0BA5uhEXQAs1+yNidpxEMs39ztajNLQMH9bjXgBm615vp 3UTrsw/syO8Q2MNa9PtePGoMM7ezHfYurfTCo5Ds8UGYdF/+rmD+F7wd79Y8dZwU7VSn B14ErNIeK6oq02bUfQPt0ZEJNesP1wNbvDsX2THshhyp5+nW2Par/RJXvy52WSR2YMq1 ZFJUeYixlF/HoXntuGwSv4jBB+damvcCP4cq//5M4DNqUB6jD+nSsg5nryz18+5IskYw fWLw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=sncxYiJ19EBEMYozwgCXbGEKSdQ2+11yxAIRrAVvyso=; b=S53kgJI4ZQN1rqqNK4n/YdV5FlaWc/V9yH3w91msucvsRJ73rohba/7c5NMfkIHysz TqwKjE1bGBU4XBbTasnuCXNszyfozmyYsaV8x6rXeTrHUbpqVPA3nZ/xY76zRQTlpi+s 1Nl4/1szHUtn/LvqtFtGjTqR2soM6rSDCS4tVokJgOTdiwC7tr4VgBxrrsvZC+4yaLvm gUef+R2jr1K3h/h54S6p7D8UD8dx0IWMsu5bfOFVk/3tiTKcnHKpkpjmet+YysVHRQuK YsiRZIMoC5ahngFGD3nRmvkx4KeaQJxXcP+OCRph71EtT1w9TAWtfvbbz8PzUHssM5Er ZdiA== X-Gm-Message-State: AFqh2koxOxe6yqilv9c4aB7KH9FGhKqZCUD1ojzqSVppxLKhYaq8fcID BlrScrXJlsigkg64of5V3GH8hA== X-Received: by 2002:a1c:770b:0:b0:3cf:a18d:399c with SMTP id t11-20020a1c770b000000b003cfa18d399cmr39048182wmi.1.1672938474085; Thu, 05 Jan 2023 09:07:54 -0800 (PST) Received: from blmsp.fritz.box ([2001:4091:a245:805c:9cf4:fdb8:bb61:5f4e]) by smtp.gmail.com with ESMTPSA id f14-20020adfe90e000000b002365730eae8sm37164853wrm.55.2023.01.05.09.07.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 Jan 2023 09:07:53 -0800 (PST) From: Markus Schneider-Pargmann To: Rob Herring , Krzysztof Kozlowski , Matthias Brugger Cc: Chun-Jie Chen , AngeloGioacchino Del Regno , Fabien Parent , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, Alexandre Bailon , Fabien Parent , Markus Schneider-Pargmann Subject: [PATCH 7/8] soc: mediatek: Add support for MTK_SCPD_STRICT_BUS_PROTECTION cap Date: Thu, 5 Jan 2023 18:07:34 +0100 Message-Id: <20230105170735.1637416-8-msp@baylibre.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230105170735.1637416-1-msp@baylibre.com> References: <20230105170735.1637416-1-msp@baylibre.com> MIME-Version: 1.0 X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1754204242492891753?= X-GMAIL-MSGID: =?utf-8?q?1754204242492891753?= From: Alexandre Bailon This adds support for MTK_SCPD_STRICT_BUS_PROTECTION capability. It is a strict bus protection policy that requires the bus protection to be disabled before accessing the bus. This is required by the mt8365, for the MM power domain. Signed-off-by: Alexandre Bailon Signed-off-by: Fabien Parent Signed-off-by: Markus Schneider-Pargmann --- Notes: Changes in v4: - Change name in title and commit message Changes in v3: - Rename MTK_SCPD_STRICT_BUSP to MTK_SCPD_STRICT_BUS_PROTECTION - Remove extra bool variable reflecting the capability Changes in v2: - Fixup error handling path. drivers/soc/mediatek/mtk-pm-domains.c | 27 +++++++++++++++++++++++---- drivers/soc/mediatek/mtk-pm-domains.h | 1 + 2 files changed, 24 insertions(+), 4 deletions(-) diff --git a/drivers/soc/mediatek/mtk-pm-domains.c b/drivers/soc/mediatek/mtk-pm-domains.c index d53309f050ee..29a9028dd9b3 100644 --- a/drivers/soc/mediatek/mtk-pm-domains.c +++ b/drivers/soc/mediatek/mtk-pm-domains.c @@ -265,9 +265,17 @@ static int scpsys_power_on(struct generic_pm_domain *genpd) regmap_clear_bits(scpsys->base, pd->data->ctl_offs, PWR_ISO_BIT); regmap_set_bits(scpsys->base, pd->data->ctl_offs, PWR_RST_B_BIT); - ret = clk_bulk_prepare_enable(pd->num_subsys_clks, pd->subsys_clks); - if (ret) - goto err_pwr_ack; + /* + * In few Mediatek platforms(e.g. MT6779), the bus protect policy is + * stricter, which leads to bus protect release must be prior to bus + * access. + */ + if (!MTK_SCPD_CAPS(pd, MTK_SCPD_STRICT_BUS_PROTECTION)) { + ret = clk_bulk_prepare_enable(pd->num_subsys_clks, + pd->subsys_clks); + if (ret) + goto err_pwr_ack; + } ret = scpsys_sram_enable(pd); if (ret < 0) @@ -277,12 +285,23 @@ static int scpsys_power_on(struct generic_pm_domain *genpd) if (ret < 0) goto err_disable_sram; + if (MTK_SCPD_CAPS(pd, MTK_SCPD_STRICT_BUS_PROTECTION)) { + ret = clk_bulk_prepare_enable(pd->num_subsys_clks, + pd->subsys_clks); + if (ret) + goto err_enable_bus_protect; + } + return 0; +err_enable_bus_protect: + scpsys_bus_protect_enable(pd); err_disable_sram: scpsys_sram_disable(pd); err_disable_subsys_clks: - clk_bulk_disable_unprepare(pd->num_subsys_clks, pd->subsys_clks); + if (!MTK_SCPD_CAPS(pd, MTK_SCPD_STRICT_BUS_PROTECTION)) + clk_bulk_disable_unprepare(pd->num_subsys_clks, + pd->subsys_clks); err_pwr_ack: clk_bulk_disable_unprepare(pd->num_clks, pd->clks); err_reg: diff --git a/drivers/soc/mediatek/mtk-pm-domains.h b/drivers/soc/mediatek/mtk-pm-domains.h index 1fa634509db1..e5aa2348a9db 100644 --- a/drivers/soc/mediatek/mtk-pm-domains.h +++ b/drivers/soc/mediatek/mtk-pm-domains.h @@ -11,6 +11,7 @@ /* can't set MTK_SCPD_KEEP_DEFAULT_OFF at the same time */ #define MTK_SCPD_ALWAYS_ON BIT(5) #define MTK_SCPD_HAS_WAY_EN BIT(6) +#define MTK_SCPD_STRICT_BUS_PROTECTION BIT(7) #define MTK_SCPD_CAPS(_scpd, _x) ((_scpd)->data->caps & (_x)) #define SPM_VDE_PWR_CON 0x0210 From patchwork Thu Jan 5 17:07:35 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Markus Schneider-Pargmann X-Patchwork-Id: 39713 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4e01:0:0:0:0:0 with SMTP id p1csp411003wrt; Thu, 5 Jan 2023 09:25:32 -0800 (PST) X-Google-Smtp-Source: AMrXdXvS0wbpk8Nlfp+XlZO34rzSqQ9DXMF2zfdlfsZ59UId5tyXW6yJFtWdLAAPDvIDd39Tb5Xe X-Received: by 2002:a05:6402:6c7:b0:492:609a:f144 with SMTP id n7-20020a05640206c700b00492609af144mr2695318edy.6.1672939532624; Thu, 05 Jan 2023 09:25:32 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1672939532; cv=none; d=google.com; s=arc-20160816; b=LDmUEMo1XpDEud715b07z/AEscFzbTqH64Kcu1NE9MJcNr/LrQOBZpyzY2lkLibLXA rPd1VaSlJZOGvVkiGjiltJuBuboRA+2p4RFg+LCf3VxOJppkb/9kML8tQjMVZqOIXkGn uHZEWNakVUu98zg3KkUWV2Zrw+/VrQ1llzwjfzw1yLvot/9DEwvGjo65HS2qnjfegCG0 +L2oSGrCYXCuTgZjU1gGpXElbBRLB/kB4thf+gi7ZTmf0sX+BxZknyzMTY5b2DBWqPpv my6rltp6AxFXQtanJm4QxZ/Ckfa8JQGfYg8TlyUAyBvalj7sZWVCh6XxdlSWB7TuRiSh 9VbA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=vP64e5b9ohPWmtQISJdT6ZMeITPgHiIqXiaeBFbmRb0=; b=AvT6ToGhf66B5lzP8vmox1hqOLc+QpYoP4U58GrP+x1LpJBz2QZvxpCiA8l0lhsJDf 7JuIKFZUqGkq07UZiDysaUHc65m4jGiNFm+bWnjoKWL1FLNuW8ufichmkcFxWQumQPh2 xooyDEHOO0Ul00hbQ89Sxd5GYYuuau5sMxFtle5bw3wZOjN5NNmWJmgo8866OUB+oIxf FopU5RjU7M0UA0DTxF3w9rGPpGvgqt1GbNW+Ph+NUhozVtkD3FdJafTQWukI1tCvMdWE NBn2K3MeR/+bpzbI9C5c6rxV6DSfgt5M1IMicnAJNUexzzXJ1ZMT7A86nYU6OFgUiFk/ hjGQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@baylibre-com.20210112.gappssmtp.com header.s=20210112 header.b=eCNMHDOa; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id g5-20020a056402428500b0048e1008c744si10691843edc.147.2023.01.05.09.25.09; Thu, 05 Jan 2023 09:25:32 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@baylibre-com.20210112.gappssmtp.com header.s=20210112 header.b=eCNMHDOa; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235058AbjAERPf (ORCPT + 99 others); Thu, 5 Jan 2023 12:15:35 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34414 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235277AbjAEROb (ORCPT ); Thu, 5 Jan 2023 12:14:31 -0500 Received: from mail-wr1-x436.google.com (mail-wr1-x436.google.com [IPv6:2a00:1450:4864:20::436]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7641463D04 for ; Thu, 5 Jan 2023 09:08:52 -0800 (PST) Received: by mail-wr1-x436.google.com with SMTP id r2so1949523wrv.7 for ; Thu, 05 Jan 2023 09:08:52 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=vP64e5b9ohPWmtQISJdT6ZMeITPgHiIqXiaeBFbmRb0=; b=eCNMHDOaWZVSQxYE+JmQV8tG4HWDvxojEViLcY7wJRhQzMqsxDtzFgrjlujeERKhEJ K0R+BPVOcnmZJN/RtFEVPnktuxHBcDaWQFKZjnQc9SiYGXl050ITes6RIuDXKQvovVsx cQLSaMVucd2bHrRVTvYJXc51FFdbtJjUMmUBO5enk1YjPGB41+VRZeiayZVAjQN4P7MV 4vXCOG2iTMFbLNZwUX6bethu+JxTW4TqemawA2IosX5KXyVrFxR+/KDGM5hbpwXU8iFt RUdriaIDnqvhqMXPjviX6VExdGwnWGyJKKpnrXqdALfTL8unN3/nibCPRyzkxe7qbeI1 ns7Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=vP64e5b9ohPWmtQISJdT6ZMeITPgHiIqXiaeBFbmRb0=; b=KkWHv7aC6uM3CNvo6jF8ANnnQerqCZw8ZQy9q76SGhWg72xLpytsxd9qLafKDOCDjG cBzXGnxyd9yafWQxeTFnFBDCxJf3QyretTCRFaoWioPwXmNnl+pAoeUECPf+EQ+ghVci EiyeOC8ASdKC+KEugcPNng1bC0GsWqsW8eraTLz5/i7oiHyh3E0sriceZzzbbbp5iFvH SBFQXEFwAO8/HiVwoQ8ryVcOSZGKL+bWHnF8r1J19GEk6atdvktC2S7hvUHV7ql1duGc tomofxEG8QCcmaQbaDFwObBcwxuA46Dzykkfh7TG5AXEnd8P7d+L0I8v/wfBDJLIUQgj pv+A== X-Gm-Message-State: AFqh2kriRFBMM19ZXP4lRmJho/3CuXYXOJ5T1cRszTdwsI38OkvdvWEH paaUTyLtH8g15QyDDI8jJJe+8A== X-Received: by 2002:a05:6000:242:b0:27f:aa94:a9f2 with SMTP id m2-20020a056000024200b0027faa94a9f2mr23955810wrz.68.1672938475251; Thu, 05 Jan 2023 09:07:55 -0800 (PST) Received: from blmsp.fritz.box ([2001:4091:a245:805c:9cf4:fdb8:bb61:5f4e]) by smtp.gmail.com with ESMTPSA id f14-20020adfe90e000000b002365730eae8sm37164853wrm.55.2023.01.05.09.07.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 Jan 2023 09:07:54 -0800 (PST) From: Markus Schneider-Pargmann To: Rob Herring , Krzysztof Kozlowski , Matthias Brugger Cc: Chun-Jie Chen , AngeloGioacchino Del Regno , Fabien Parent , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, Fabien Parent , Markus Schneider-Pargmann Subject: [PATCH 8/8] soc: mediatek: pm-domains: Add support for MT8365 Date: Thu, 5 Jan 2023 18:07:35 +0100 Message-Id: <20230105170735.1637416-9-msp@baylibre.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230105170735.1637416-1-msp@baylibre.com> References: <20230105170735.1637416-1-msp@baylibre.com> MIME-Version: 1.0 X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1754204243139111786?= X-GMAIL-MSGID: =?utf-8?q?1754204243139111786?= From: Fabien Parent Add the needed board data to support MT8365 SoC. Signed-off-by: Fabien Parent Signed-off-by: Markus Schneider-Pargmann --- drivers/soc/mediatek/mt8365-pm-domains.h | 147 +++++++++++++++++++++++ drivers/soc/mediatek/mtk-pm-domains.c | 5 + 2 files changed, 152 insertions(+) create mode 100644 drivers/soc/mediatek/mt8365-pm-domains.h diff --git a/drivers/soc/mediatek/mt8365-pm-domains.h b/drivers/soc/mediatek/mt8365-pm-domains.h new file mode 100644 index 000000000000..8735e833b15b --- /dev/null +++ b/drivers/soc/mediatek/mt8365-pm-domains.h @@ -0,0 +1,147 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __SOC_MEDIATEK_MT8365_PM_DOMAINS_H +#define __SOC_MEDIATEK_MT8365_PM_DOMAINS_H + +#include "mtk-pm-domains.h" +#include + +/* + * MT8365 power domain support + */ + +static const struct scpsys_domain_data scpsys_domain_data_mt8365[] = { + [MT8365_POWER_DOMAIN_MM] = { + .name = "mm", + .sta_mask = PWR_STATUS_DISP, + .ctl_offs = 0x30c, + .pwr_sta_offs = 0x0180, + .pwr_sta2nd_offs = 0x0184, + .sram_pdn_bits = GENMASK(8, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + .caps = MTK_SCPD_STRICT_BUS_PROTECTION | MTK_SCPD_HAS_WAY_EN, + .bp_infracfg = { + BUS_PROT_WR(BIT(16) | BIT(17), 0x2a8, 0x2ac, 0x258), + BUS_PROT_WR(BIT(1) | BIT(2) | BIT(10) | BIT(11), 0x2a0, 0x2a4, 0x228), + BUS_PROT_WAY_EN(BIT(6), 0x200, BIT(24), 0x0), + BUS_PROT_WAY_EN(BIT(5), 0x234, BIT(14), 0x28), + BUS_PROT_WR(BIT(6), 0x2a0, 0x2a4, 0x228), + }, + }, + [MT8365_POWER_DOMAIN_VENC] = { + .name = "venc", + .sta_mask = PWR_STATUS_VENC, + .ctl_offs = 0x0304, + .pwr_sta_offs = 0x0180, + .pwr_sta2nd_offs = 0x0184, + .sram_pdn_bits = GENMASK(8, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + .bp_smi = { + BUS_PROT_WR(BIT(1), 0x3c4, 0x3c8, 0x3c0), + }, + }, + [MT8365_POWER_DOMAIN_AUDIO] = { + .name = "audio", + .sta_mask = PWR_STATUS_AUDIO, + .ctl_offs = 0x0314, + .pwr_sta_offs = 0x0180, + .pwr_sta2nd_offs = 0x0184, + .sram_pdn_bits = GENMASK(12, 8), + .sram_pdn_ack_bits = GENMASK(17, 13), + .bp_infracfg = { + BUS_PROT_WR(BIT(27) | BIT(28), 0x2a8, 0x2ac, 0x258), + }, + .caps = MTK_SCPD_ACTIVE_WAKEUP, + }, + [MT8365_POWER_DOMAIN_CONN] = { + .name = "conn", + .sta_mask = PWR_STATUS_CONN, + .ctl_offs = 0x032c, + .pwr_sta_offs = 0x0180, + .pwr_sta2nd_offs = 0x0184, + .sram_pdn_bits = 0, + .sram_pdn_ack_bits = 0, + .bp_infracfg = { + BUS_PROT_WR(BIT(13), 0x2a0, 0x2a4, 0x228), + BUS_PROT_WR(BIT(18), 0x2a8, 0x2ac, 0x258), + BUS_PROT_WR(BIT(14), 0x2a0, 0x2a4, 0x228), + BUS_PROT_WR(BIT(21), 0x2a8, 0x2ac, 0x258), + }, + .caps = MTK_SCPD_ACTIVE_WAKEUP | MTK_SCPD_KEEP_DEFAULT_OFF, + }, + [MT8365_POWER_DOMAIN_MFG] = { + .name = "mfg", + .sta_mask = PWR_STATUS_MFG, + .ctl_offs = 0x0338, + .pwr_sta_offs = 0x0180, + .pwr_sta2nd_offs = 0x0184, + .sram_pdn_bits = GENMASK(9, 8), + .sram_pdn_ack_bits = GENMASK(13, 12), + .bp_infracfg = { + BUS_PROT_WR(BIT(25), 0x2a0, 0x2a4, 0x228), + BUS_PROT_WR(BIT(21) | BIT(22), 0x2a0, 0x2a4, 0x228), + }, + }, + [MT8365_POWER_DOMAIN_CAM] = { + .name = "cam", + .sta_mask = BIT(25), + .ctl_offs = 0x0344, + .pwr_sta_offs = 0x0180, + .pwr_sta2nd_offs = 0x0184, + .sram_pdn_bits = GENMASK(9, 8), + .sram_pdn_ack_bits = GENMASK(13, 12), + .bp_infracfg = { + BUS_PROT_WR(BIT(19), 0x2a8, 0x2ac, 0x258), + }, + .bp_smi = { + BUS_PROT_WR(BIT(2), 0x3c4, 0x3c8, 0x3c0), + }, + }, + [MT8365_POWER_DOMAIN_VDEC] = { + .name = "vdec", + .sta_mask = BIT(31), + .ctl_offs = 0x0370, + .pwr_sta_offs = 0x0180, + .pwr_sta2nd_offs = 0x0184, + .sram_pdn_bits = GENMASK(8, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + .bp_smi = { + BUS_PROT_WR(BIT(3), 0x3c4, 0x3c8, 0x3c0), + }, + }, + [MT8365_POWER_DOMAIN_APU] = { + .name = "apu", + .sta_mask = BIT(16), + .ctl_offs = 0x0378, + .pwr_sta_offs = 0x0180, + .pwr_sta2nd_offs = 0x0184, + .sram_pdn_bits = GENMASK(14, 8), + .sram_pdn_ack_bits = GENMASK(21, 15), + .bp_infracfg = { + BUS_PROT_WR(BIT(2) | BIT(20), 0x2a8, 0x2ac, 0x258), + }, + .bp_smi = { + BUS_PROT_WR(BIT(4), 0x3c4, 0x3c8, 0x3c0), + }, + }, + [MT8365_POWER_DOMAIN_DSP] = { + .name = "dsp", + .sta_mask = BIT(17), + .ctl_offs = 0x037C, + .pwr_sta_offs = 0x0180, + .pwr_sta2nd_offs = 0x0184, + .sram_pdn_bits = GENMASK(11, 8), + .sram_pdn_ack_bits = GENMASK(15, 12), + .bp_infracfg = { + BUS_PROT_WR(BIT(24) | BIT(30) | BIT(31), 0x2a8, 0x2ac, 0x258), + }, + .caps = MTK_SCPD_ACTIVE_WAKEUP, + }, +}; + +static const struct scpsys_soc_data mt8365_scpsys_data = { + .domains_data = scpsys_domain_data_mt8365, + .num_domains = ARRAY_SIZE(scpsys_domain_data_mt8365), +}; + +#endif /* __SOC_MEDIATEK_MT8365_PM_DOMAINS_H */ diff --git a/drivers/soc/mediatek/mtk-pm-domains.c b/drivers/soc/mediatek/mtk-pm-domains.c index 29a9028dd9b3..adb7716df0a8 100644 --- a/drivers/soc/mediatek/mtk-pm-domains.c +++ b/drivers/soc/mediatek/mtk-pm-domains.c @@ -23,6 +23,7 @@ #include "mt8186-pm-domains.h" #include "mt8192-pm-domains.h" #include "mt8195-pm-domains.h" +#include "mt8365-pm-domains.h" #define MTK_POLL_DELAY_US 10 #define MTK_POLL_TIMEOUT USEC_PER_SEC @@ -647,6 +648,10 @@ static const struct of_device_id scpsys_of_match[] = { .compatible = "mediatek,mt8195-power-controller", .data = &mt8195_scpsys_data, }, + { + .compatible = "mediatek,mt8365-power-controller", + .data = &mt8365_scpsys_data, + }, { } };