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[2620:137:e000::1:20]) by mx.google.com with ESMTP id b9-20020a63d809000000b004785d1e2b7bsi35004230pgh.514.2023.01.04.12.15.07; Wed, 04 Jan 2023 12:15:20 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=GYvz7XOA; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239905AbjADUOJ (ORCPT + 99 others); Wed, 4 Jan 2023 15:14:09 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59696 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231197AbjADUOH (ORCPT ); Wed, 4 Jan 2023 15:14:07 -0500 Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 868461A818 for ; Wed, 4 Jan 2023 12:14:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1672863246; x=1704399246; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=O+nU4p5hgQUT3M7z+rZZ2tFIqvoh8BbKb8EMQ4dLjNU=; b=GYvz7XOAPCMtKTrQM2sZfSs2XBdo2EMqIj0+zua8lx+CQXnn5Fw5Fu8O P1i+CiH3fbeliYHLKuErNlu4axZqqu7RGcvzZOhfeq50DI30nx8QZ2gkd 1Zps0B3F5cNHkPYDbvHTQ/P+LK/JPT+yzbJdsUw33MZVYFaDp1WLYYRjV 4PuAF8byq7CuB9Lu8aE0LGra32Hsm+eiBK/ZAvCAR3YZi5MamC+67lWpG FDqnb9NlCpnsAaQqMK70AojNEuFUFIYV+LHEkHeAN0VLhtEXwiLZnRcDr 2jq+jXMy+TJgAwgAbNy6N/mGwmJ0fFxkyg/ahTGMqdN8zZr9hs3vRlEWw w==; X-IronPort-AV: E=McAfee;i="6500,9779,10580"; a="322105437" X-IronPort-AV: E=Sophos;i="5.96,300,1665471600"; d="scan'208";a="322105437" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Jan 2023 12:14:06 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10580"; a="779323969" X-IronPort-AV: E=Sophos;i="5.96,300,1665471600"; d="scan'208";a="779323969" Received: from kanliang-dev.jf.intel.com ([10.165.154.102]) by orsmga004.jf.intel.com with ESMTP; 04 Jan 2023 12:14:05 -0800 From: kan.liang@linux.intel.com To: peterz@infradead.org, mingo@redhat.com, acme@kernel.org, linux-kernel@vger.kernel.org Cc: ak@linux.intel.com, eranian@google.com, irogers@google.com, Kan Liang Subject: [PATCH V2 1/9] perf: Add PMU_FORMAT_ATTR_SHOW Date: Wed, 4 Jan 2023 12:13:41 -0800 Message-Id: <20230104201349.1451191-1-kan.liang@linux.intel.com> X-Mailer: git-send-email 2.35.1 MIME-Version: 1.0 X-Spam-Status: No, score=-4.3 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1754124329570707684?= X-GMAIL-MSGID: =?utf-8?q?1754124329570707684?= From: Kan Liang The macro PMU_FORMAT_ATTR facilitates the definition of both the "show" function and "format_attr". But it only works for a non-hybrid platform. For a hybrid platform, the name "format_attr_hybrid_" is used. The definition of the "show" function can be shared between a non-hybrid platform and a hybrid platform. Add a new macro PMU_FORMAT_ATTR_SHOW. No functional change. The PMU_FORMAT_ATTR_SHOW will be used in the following patch. Signed-off-by: Kan Liang --- No change since V1 include/linux/perf_event.h | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/include/linux/perf_event.h b/include/linux/perf_event.h index c6a3bac76966..ad92ad37600e 100644 --- a/include/linux/perf_event.h +++ b/include/linux/perf_event.h @@ -1724,7 +1724,7 @@ static struct perf_pmu_events_attr _var = { \ .id = _id, } \ })[0].attr.attr) -#define PMU_FORMAT_ATTR(_name, _format) \ +#define PMU_FORMAT_ATTR_SHOW(_name, _format) \ static ssize_t \ _name##_show(struct device *dev, \ struct device_attribute *attr, \ @@ -1733,6 +1733,9 @@ _name##_show(struct device *dev, \ BUILD_BUG_ON(sizeof(_format) >= PAGE_SIZE); \ return sprintf(page, _format "\n"); \ } \ + +#define PMU_FORMAT_ATTR(_name, _format) \ + PMU_FORMAT_ATTR_SHOW(_name, _format) \ \ static struct device_attribute format_attr_##_name = __ATTR_RO(_name) From patchwork Wed Jan 4 20:13:42 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Liang, Kan" X-Patchwork-Id: 39078 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4e01:0:0:0:0:0 with SMTP id p1csp5335011wrt; Wed, 4 Jan 2023 12:15:22 -0800 (PST) X-Google-Smtp-Source: AMrXdXvULGPDXRxu3EF0TDzOXKyE3oHESYZ+dSccNrvwulbrgeLNWKM7ju6dFKCNcCzYgxEC6rZZ X-Received: by 2002:a17:902:a3c7:b0:192:a1e0:260c with SMTP id q7-20020a170902a3c700b00192a1e0260cmr21651369plb.2.1672863322143; Wed, 04 Jan 2023 12:15:22 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1672863322; cv=none; d=google.com; s=arc-20160816; b=hxiXOCLSPNE+V9HTRF3yN7OlKmBsnxDfwTwUkduHj5M1EQ8yFW9JXHn994rBxbXSMK GwV0MsDs7IgVvE6ZTAAJqoEcVn9jqwGsjxxxFCVuiDccv0ZeNVEEA7Mbrz04l1GCqsH8 w8H+IPqTb7CTr04LQptRh2+oDJ3Bwz0JMdlX2E91hLYnQPQyS2MBU9tvtU+N9zrcnaEX 1BPsNrSg1VdjF5v5tKMpEQee94ir36mErvPOs3KyPF6hSVwHOcwkE6GLNaOaD/oNEJ8H fX/3OyV8P0qjgtAN/WxnRno2oP7wS87Y596V5iifWiiOMC6yp5tCWYQEA/pFp1Yz9xkS l/AA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=gHy42lqwSnCwr38+ncTLCCKyiAgLRun+L5GJBj0DyVc=; b=JEC/PtrEhh/n6H4Y+a4KQAIaqdYIsHXA+3tnFh50zg0Udd34vwAf5VhGAHFSVwABtM YI7dtkfc1Xm0St9jwDqBSA2tSzMPEm8q5FudO7Ff782fJVt6yzN12WK3oePVv2pwnmkN sYUuEEdsW6vKRlOpGxjC0b9VNvjURdVh9Ekl+cRjA351quN237wJeMmr0EhmIVpx9mU9 NMd4dQMruWtH0C8iLKOtsuFR6EpzVUQFY67HYy/w+rHl0hT3O1dnWO1R0DtXny4N33YS Vh2RH8RI1dU7L0KhRcFhRJh3ccPBvXO56ydrLVohiBuYmW/H9JnCSB+UqIjXNU13vwC2 MOBg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=oIGEpg2g; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id q21-20020a170902edd500b00192d633db20si6484933plk.366.2023.01.04.12.15.09; Wed, 04 Jan 2023 12:15:22 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=oIGEpg2g; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239952AbjADUOP (ORCPT + 99 others); Wed, 4 Jan 2023 15:14:15 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59708 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239792AbjADUOJ (ORCPT ); Wed, 4 Jan 2023 15:14:09 -0500 Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F36C71A818 for ; Wed, 4 Jan 2023 12:14:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1672863247; x=1704399247; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=ElJS8KaJ9XfGJoMZNQywYH19kBNEbWY1z/v4xQbHzNk=; b=oIGEpg2g4mn+9pASv2Qw7mhb3Jvi/3Mfpm9RNuAfobm4Y04ElDJ2pt5V zGLC1V6tHsNUFqNpJq+PD3/1fqPJ2SjLvGORgUw0KHuOMG8ZMd3HXqhyP jGHm4Tn5vMHVdgOgNawapVIv4YnUhRAp8STQUoQNwM3ryDz8chvLSx3JA J5wGzHsT2QQ6tJMPoPOmN6bZGirsQeRXKS+q+SMUIwPWfkyf9pjIAlBmD vQjFMVNUCx35XCBAA2qlfRQTNCoHknOpYkny26uE0PjdkvE862RVd7P7r BWH5AGbEjkw8UIsigxU/5uGcRtNMNG564arTJHlIZAaj+vqOUgGv9isA6 A==; X-IronPort-AV: E=McAfee;i="6500,9779,10580"; a="322105446" X-IronPort-AV: E=Sophos;i="5.96,300,1665471600"; d="scan'208";a="322105446" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Jan 2023 12:14:07 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10580"; a="779323996" X-IronPort-AV: E=Sophos;i="5.96,300,1665471600"; d="scan'208";a="779323996" Received: from kanliang-dev.jf.intel.com ([10.165.154.102]) by orsmga004.jf.intel.com with ESMTP; 04 Jan 2023 12:14:07 -0800 From: kan.liang@linux.intel.com To: peterz@infradead.org, mingo@redhat.com, acme@kernel.org, linux-kernel@vger.kernel.org Cc: ak@linux.intel.com, eranian@google.com, irogers@google.com, Kan Liang Subject: [PATCH V2 2/9] perf/x86: Add Meteor Lake support Date: Wed, 4 Jan 2023 12:13:42 -0800 Message-Id: <20230104201349.1451191-2-kan.liang@linux.intel.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20230104201349.1451191-1-kan.liang@linux.intel.com> References: <20230104201349.1451191-1-kan.liang@linux.intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.3 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1754124331227321223?= X-GMAIL-MSGID: =?utf-8?q?1754124331227321223?= From: Kan Liang From PMU's perspective, Meteor Lake is similar to Alder Lake. Both are hybrid platforms, with e-core and p-core. The key differences include: - The e-core supports 2 PDIST GP counters (GP0 & GP1) - New MSRs for the Module Snoop Response Events on the e-core. - New Data Source fields are introduced for the e-core. - There are 8 GP counters for the e-core. - The load latency AUX event is not required for the p-core anymore. - Retire Latency (Support in a separate patch) for both cores. Since most of the code in the intel_pmu_init() should be the same as Alder Lake, to avoid code duplication, share the path with Alder Lake. Add new specific functions of extra_regs, and get_event_constraints to support the OCR events, Module Snoop Response Events and 2 PDIST GP counters on e-core. Add new MTL specific mem_attrs which drops the load latency AUX event. The Data Source field is extended to 4:0, which can contains max 32 sources. The Retire Latency is implemented with a separate patch. Reviewed-by: Andi Kleen Signed-off-by: Kan Liang --- No change since V1 arch/x86/events/intel/core.c | 141 ++++++++++++++++++++++++++++--- arch/x86/events/intel/ds.c | 70 ++++++++++++--- arch/x86/events/perf_event.h | 21 +++-- arch/x86/include/asm/msr-index.h | 3 + 4 files changed, 203 insertions(+), 32 deletions(-) diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c index dfd2c124cdf8..d2030be04e4a 100644 --- a/arch/x86/events/intel/core.c +++ b/arch/x86/events/intel/core.c @@ -2119,6 +2119,16 @@ static struct extra_reg intel_grt_extra_regs[] __read_mostly = { EVENT_EXTRA_END }; +static struct extra_reg intel_cmt_extra_regs[] __read_mostly = { + /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ + INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x800ff3ffffffffffull, RSP_0), + INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0xff3ffffffffffull, RSP_1), + INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x5d0), + INTEL_UEVENT_EXTRA_REG(0x0127, MSR_SNOOP_RSP_0, 0xffffffffffffffffull, SNOOP_0), + INTEL_UEVENT_EXTRA_REG(0x0227, MSR_SNOOP_RSP_1, 0xffffffffffffffffull, SNOOP_1), + EVENT_EXTRA_END +}; + #define KNL_OT_L2_HITE BIT_ULL(19) /* Other Tile L2 Hit */ #define KNL_OT_L2_HITF BIT_ULL(20) /* Other Tile L2 Hit */ #define KNL_MCDRAM_LOCAL BIT_ULL(21) @@ -4182,6 +4192,12 @@ static int hsw_hw_config(struct perf_event *event) static struct event_constraint counter0_constraint = INTEL_ALL_EVENT_CONSTRAINT(0, 0x1); +static struct event_constraint counter1_constraint = + INTEL_ALL_EVENT_CONSTRAINT(0, 0x2); + +static struct event_constraint counter0_1_constraint = + INTEL_ALL_EVENT_CONSTRAINT(0, 0x3); + static struct event_constraint counter2_constraint = EVENT_CONSTRAINT(0, 0x4, 0); @@ -4191,6 +4207,9 @@ static struct event_constraint fixed0_constraint = static struct event_constraint fixed0_counter0_constraint = INTEL_ALL_EVENT_CONSTRAINT(0, 0x100000001ULL); +static struct event_constraint fixed0_counter0_1_constraint = + INTEL_ALL_EVENT_CONSTRAINT(0, 0x100000003ULL); + static struct event_constraint * hsw_get_event_constraints(struct cpu_hw_events *cpuc, int idx, struct perf_event *event) @@ -4322,6 +4341,54 @@ adl_get_event_constraints(struct cpu_hw_events *cpuc, int idx, return &emptyconstraint; } +static struct event_constraint * +cmt_get_event_constraints(struct cpu_hw_events *cpuc, int idx, + struct perf_event *event) +{ + struct event_constraint *c; + + c = intel_get_event_constraints(cpuc, idx, event); + + /* + * The :ppp indicates the Precise Distribution (PDist) facility, which + * is only supported on the GP counter 0 & 1 and Fixed counter 0. + * If a :ppp event which is not available on the above eligible counters, + * error out. + */ + if (event->attr.precise_ip == 3) { + /* Force instruction:ppp on PMC0, 1 and Fixed counter 0 */ + if (constraint_match(&fixed0_constraint, event->hw.config)) + return &fixed0_counter0_1_constraint; + + switch (c->idxmsk64 & 0x3ull) { + case 0x1: + return &counter0_constraint; + case 0x2: + return &counter1_constraint; + case 0x3: + return &counter0_1_constraint; + } + return &emptyconstraint; + } + + return c; +} + +static struct event_constraint * +mtl_get_event_constraints(struct cpu_hw_events *cpuc, int idx, + struct perf_event *event) +{ + struct x86_hybrid_pmu *pmu = hybrid_pmu(event->pmu); + + if (pmu->cpu_type == hybrid_big) + return spr_get_event_constraints(cpuc, idx, event); + if (pmu->cpu_type == hybrid_small) + return cmt_get_event_constraints(cpuc, idx, event); + + WARN_ON(1); + return &emptyconstraint; +} + static int adl_hw_config(struct perf_event *event) { struct x86_hybrid_pmu *pmu = hybrid_pmu(event->pmu); @@ -5463,6 +5530,12 @@ static struct attribute *adl_hybrid_mem_attrs[] = { NULL, }; +static struct attribute *mtl_hybrid_mem_attrs[] = { + EVENT_PTR(mem_ld_adl), + EVENT_PTR(mem_st_adl), + NULL +}; + EVENT_ATTR_STR_HYBRID(tx-start, tx_start_adl, "event=0xc9,umask=0x1", hybrid_big); EVENT_ATTR_STR_HYBRID(tx-commit, tx_commit_adl, "event=0xc9,umask=0x2", hybrid_big); EVENT_ATTR_STR_HYBRID(tx-abort, tx_abort_adl, "event=0xc9,umask=0x4", hybrid_big); @@ -5490,20 +5563,40 @@ FORMAT_ATTR_HYBRID(offcore_rsp, hybrid_big_small); FORMAT_ATTR_HYBRID(ldlat, hybrid_big_small); FORMAT_ATTR_HYBRID(frontend, hybrid_big); +#define ADL_HYBRID_RTM_FORMAT_ATTR \ + FORMAT_HYBRID_PTR(in_tx), \ + FORMAT_HYBRID_PTR(in_tx_cp) + +#define ADL_HYBRID_FORMAT_ATTR \ + FORMAT_HYBRID_PTR(offcore_rsp), \ + FORMAT_HYBRID_PTR(ldlat), \ + FORMAT_HYBRID_PTR(frontend) + static struct attribute *adl_hybrid_extra_attr_rtm[] = { - FORMAT_HYBRID_PTR(in_tx), - FORMAT_HYBRID_PTR(in_tx_cp), - FORMAT_HYBRID_PTR(offcore_rsp), - FORMAT_HYBRID_PTR(ldlat), - FORMAT_HYBRID_PTR(frontend), - NULL, + ADL_HYBRID_RTM_FORMAT_ATTR, + ADL_HYBRID_FORMAT_ATTR, + NULL }; static struct attribute *adl_hybrid_extra_attr[] = { - FORMAT_HYBRID_PTR(offcore_rsp), - FORMAT_HYBRID_PTR(ldlat), - FORMAT_HYBRID_PTR(frontend), - NULL, + ADL_HYBRID_FORMAT_ATTR, + NULL +}; + +PMU_FORMAT_ATTR_SHOW(snoop_rsp, "config1:0-63"); +FORMAT_ATTR_HYBRID(snoop_rsp, hybrid_small); + +static struct attribute *mtl_hybrid_extra_attr_rtm[] = { + ADL_HYBRID_RTM_FORMAT_ATTR, + ADL_HYBRID_FORMAT_ATTR, + FORMAT_HYBRID_PTR(snoop_rsp), + NULL +}; + +static struct attribute *mtl_hybrid_extra_attr[] = { + ADL_HYBRID_FORMAT_ATTR, + FORMAT_HYBRID_PTR(snoop_rsp), + NULL }; static bool is_attr_for_this_pmu(struct kobject *kobj, struct attribute *attr) @@ -5725,6 +5818,12 @@ static void intel_pmu_check_hybrid_pmus(u64 fixed_mask) } } +static __always_inline bool is_mtl(u8 x86_model) +{ + return (x86_model == INTEL_FAM6_METEORLAKE) || + (x86_model == INTEL_FAM6_METEORLAKE_L); +} + __init int intel_pmu_init(void) { struct attribute **extra_skl_attr = &empty_attrs; @@ -6381,6 +6480,8 @@ __init int intel_pmu_init(void) case INTEL_FAM6_RAPTORLAKE: case INTEL_FAM6_RAPTORLAKE_P: case INTEL_FAM6_RAPTORLAKE_S: + case INTEL_FAM6_METEORLAKE: + case INTEL_FAM6_METEORLAKE_L: /* * Alder Lake has 2 types of CPU, core and atom. * @@ -6400,9 +6501,7 @@ __init int intel_pmu_init(void) x86_pmu.flags |= PMU_FL_HAS_RSP_1; x86_pmu.flags |= PMU_FL_NO_HT_SHARING; x86_pmu.flags |= PMU_FL_INSTR_LATENCY; - x86_pmu.flags |= PMU_FL_MEM_LOADS_AUX; x86_pmu.lbr_pt_coexist = true; - intel_pmu_pebs_data_source_adl(); x86_pmu.pebs_latency_data = adl_latency_data_small; x86_pmu.num_topdown_events = 8; static_call_update(intel_pmu_update_topdown_event, @@ -6489,8 +6588,22 @@ __init int intel_pmu_init(void) pmu->event_constraints = intel_slm_event_constraints; pmu->pebs_constraints = intel_grt_pebs_event_constraints; pmu->extra_regs = intel_grt_extra_regs; - pr_cont("Alderlake Hybrid events, "); - name = "alderlake_hybrid"; + if (is_mtl(boot_cpu_data.x86_model)) { + x86_pmu.pebs_latency_data = mtl_latency_data_small; + extra_attr = boot_cpu_has(X86_FEATURE_RTM) ? + mtl_hybrid_extra_attr_rtm : mtl_hybrid_extra_attr; + mem_attr = mtl_hybrid_mem_attrs; + intel_pmu_pebs_data_source_mtl(); + x86_pmu.get_event_constraints = mtl_get_event_constraints; + pmu->extra_regs = intel_cmt_extra_regs; + pr_cont("Meteorlake Hybrid events, "); + name = "meteorlake_hybrid"; + } else { + x86_pmu.flags |= PMU_FL_MEM_LOADS_AUX; + intel_pmu_pebs_data_source_adl(); + pr_cont("Alderlake Hybrid events, "); + name = "alderlake_hybrid"; + } break; default: diff --git a/arch/x86/events/intel/ds.c b/arch/x86/events/intel/ds.c index 88e58b6ee73c..e991c54916d1 100644 --- a/arch/x86/events/intel/ds.c +++ b/arch/x86/events/intel/ds.c @@ -53,6 +53,13 @@ union intel_x86_pebs_dse { unsigned int st_lat_locked:1; unsigned int ld_reserved3:26; }; + struct { + unsigned int mtl_dse:5; + unsigned int mtl_locked:1; + unsigned int mtl_stlb_miss:1; + unsigned int mtl_fwd_blk:1; + unsigned int ld_reserved4:24; + }; }; @@ -135,6 +142,29 @@ void __init intel_pmu_pebs_data_source_adl(void) __intel_pmu_pebs_data_source_grt(data_source); } +static void __init intel_pmu_pebs_data_source_cmt(u64 *data_source) +{ + data_source[0x07] = OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOPX, FWD); + data_source[0x08] = OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, HITM); + data_source[0x0a] = OP_LH | P(LVL, LOC_RAM) | LEVEL(RAM) | P(SNOOP, NONE); + data_source[0x0b] = OP_LH | LEVEL(RAM) | REM | P(SNOOP, NONE); + data_source[0x0c] = OP_LH | LEVEL(RAM) | REM | P(SNOOPX, FWD); + data_source[0x0d] = OP_LH | LEVEL(RAM) | REM | P(SNOOP, HITM); +} + +void __init intel_pmu_pebs_data_source_mtl(void) +{ + u64 *data_source; + + data_source = x86_pmu.hybrid_pmu[X86_HYBRID_PMU_CORE_IDX].pebs_data_source; + memcpy(data_source, pebs_data_source, sizeof(pebs_data_source)); + __intel_pmu_pebs_data_source_skl(false, data_source); + + data_source = x86_pmu.hybrid_pmu[X86_HYBRID_PMU_ATOM_IDX].pebs_data_source; + memcpy(data_source, pebs_data_source, sizeof(pebs_data_source)); + intel_pmu_pebs_data_source_cmt(data_source); +} + static u64 precise_store_data(u64 status) { union intel_x86_pebs_dse dse; @@ -219,24 +249,19 @@ static inline void pebs_set_tlb_lock(u64 *val, bool tlb, bool lock) } /* Retrieve the latency data for e-core of ADL */ -u64 adl_latency_data_small(struct perf_event *event, u64 status) +static u64 __adl_latency_data_small(struct perf_event *event, u64 status, + u8 dse, bool tlb, bool lock, bool blk) { - union intel_x86_pebs_dse dse; u64 val; WARN_ON_ONCE(hybrid_pmu(event->pmu)->cpu_type == hybrid_big); - dse.val = status; - - val = hybrid_var(event->pmu, pebs_data_source)[dse.ld_dse]; + dse &= PERF_PEBS_DATA_SOURCE_MASK; + val = hybrid_var(event->pmu, pebs_data_source)[dse]; - /* - * For the atom core on ADL, - * bit 4: lock, bit 5: TLB access. - */ - pebs_set_tlb_lock(&val, dse.ld_locked, dse.ld_stlb_miss); + pebs_set_tlb_lock(&val, tlb, lock); - if (dse.ld_data_blk) + if (blk) val |= P(BLK, DATA); else val |= P(BLK, NA); @@ -244,6 +269,29 @@ u64 adl_latency_data_small(struct perf_event *event, u64 status) return val; } +u64 adl_latency_data_small(struct perf_event *event, u64 status) +{ + union intel_x86_pebs_dse dse; + + dse.val = status; + + return __adl_latency_data_small(event, status, dse.ld_dse, + dse.ld_locked, dse.ld_stlb_miss, + dse.ld_data_blk); +} + +/* Retrieve the latency data for e-core of MTL */ +u64 mtl_latency_data_small(struct perf_event *event, u64 status) +{ + union intel_x86_pebs_dse dse; + + dse.val = status; + + return __adl_latency_data_small(event, status, dse.mtl_dse, + dse.mtl_stlb_miss, dse.mtl_locked, + dse.mtl_fwd_blk); +} + static u64 load_latency_data(struct perf_event *event, u64 status) { union intel_x86_pebs_dse dse; diff --git a/arch/x86/events/perf_event.h b/arch/x86/events/perf_event.h index 0e849f28a5c1..1ac9d9e3c55c 100644 --- a/arch/x86/events/perf_event.h +++ b/arch/x86/events/perf_event.h @@ -35,15 +35,17 @@ * per-core reg tables. */ enum extra_reg_type { - EXTRA_REG_NONE = -1, /* not used */ + EXTRA_REG_NONE = -1, /* not used */ - EXTRA_REG_RSP_0 = 0, /* offcore_response_0 */ - EXTRA_REG_RSP_1 = 1, /* offcore_response_1 */ - EXTRA_REG_LBR = 2, /* lbr_select */ - EXTRA_REG_LDLAT = 3, /* ld_lat_threshold */ - EXTRA_REG_FE = 4, /* fe_* */ + EXTRA_REG_RSP_0 = 0, /* offcore_response_0 */ + EXTRA_REG_RSP_1 = 1, /* offcore_response_1 */ + EXTRA_REG_LBR = 2, /* lbr_select */ + EXTRA_REG_LDLAT = 3, /* ld_lat_threshold */ + EXTRA_REG_FE = 4, /* fe_* */ + EXTRA_REG_SNOOP_0 = 5, /* snoop response 0 */ + EXTRA_REG_SNOOP_1 = 6, /* snoop response 1 */ - EXTRA_REG_MAX /* number of entries needed */ + EXTRA_REG_MAX /* number of entries needed */ }; struct event_constraint { @@ -647,6 +649,7 @@ enum { }; #define PERF_PEBS_DATA_SOURCE_MAX 0x10 +#define PERF_PEBS_DATA_SOURCE_MASK (PERF_PEBS_DATA_SOURCE_MAX - 1) struct x86_hybrid_pmu { struct pmu pmu; @@ -1486,6 +1489,8 @@ int intel_pmu_drain_bts_buffer(void); u64 adl_latency_data_small(struct perf_event *event, u64 status); +u64 mtl_latency_data_small(struct perf_event *event, u64 status); + extern struct event_constraint intel_core2_pebs_event_constraints[]; extern struct event_constraint intel_atom_pebs_event_constraints[]; @@ -1597,6 +1602,8 @@ void intel_pmu_pebs_data_source_adl(void); void intel_pmu_pebs_data_source_grt(void); +void intel_pmu_pebs_data_source_mtl(void); + int intel_pmu_setup_lbr_filter(struct perf_event *event); void intel_pt_interrupt(void); diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index 37ff47552bcb..d55cc1dc6fb8 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -189,6 +189,9 @@ #define MSR_TURBO_RATIO_LIMIT1 0x000001ae #define MSR_TURBO_RATIO_LIMIT2 0x000001af +#define MSR_SNOOP_RSP_0 0x00001328 +#define MSR_SNOOP_RSP_1 0x00001329 + #define MSR_LBR_SELECT 0x000001c8 #define MSR_LBR_TOS 0x000001c9 From patchwork Wed Jan 4 20:13:43 2023 Content-Type: text/plain; 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[2620:137:e000::1:20]) by mx.google.com with ESMTP id e37-20020a635465000000b00476f43ccfa8si37295162pgm.849.2023.01.04.12.15.23; Wed, 04 Jan 2023 12:15:35 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=BYssGMos; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239949AbjADUOU (ORCPT + 99 others); Wed, 4 Jan 2023 15:14:20 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59710 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239891AbjADUOJ (ORCPT ); Wed, 4 Jan 2023 15:14:09 -0500 Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D92941ADAE for ; Wed, 4 Jan 2023 12:14:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1672863248; x=1704399248; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=ASV50RpTsst4D7Bu4atslCazcYGAe3W6ZUfwWfrYJW0=; b=BYssGMosB8csH9RfcQV8R2nih1tAPHRGJ0dUIf/adP893NqtNR4KZ3JP Y+I1ddcDBW6qHjvKUlx8gA7L+EkQgcCjBltClxcAycuSJjBWyO3dRSit8 gU7MOrxyutOcPqmvJHAj19/j2LuWDid43tkjmNsANmcmGR54qx17i2Sem 4TkggdF5yGUVdb8mwqZswMLO6aIKVBkm2+sAvAq36h/c3QiTl7r1vfUIk kIQhBb+rGCVUZteKhZXlwfyQS12crq0aQHB4NnJGc+AeAorAk/DRHUkFE JsATQ+i4KlboVXDl/GZd8p+r6VbuFTvMb/puTwTrDU/lP2eN3pj+7lQpo g==; X-IronPort-AV: E=McAfee;i="6500,9779,10580"; a="322105454" X-IronPort-AV: E=Sophos;i="5.96,300,1665471600"; d="scan'208";a="322105454" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Jan 2023 12:14:08 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10580"; a="779324001" X-IronPort-AV: E=Sophos;i="5.96,300,1665471600"; d="scan'208";a="779324001" Received: from kanliang-dev.jf.intel.com ([10.165.154.102]) by orsmga004.jf.intel.com with ESMTP; 04 Jan 2023 12:14:08 -0800 From: kan.liang@linux.intel.com To: peterz@infradead.org, mingo@redhat.com, acme@kernel.org, linux-kernel@vger.kernel.org Cc: ak@linux.intel.com, eranian@google.com, irogers@google.com, Kan Liang Subject: [PATCH V2 3/9] perf/x86: Support Retire Latency Date: Wed, 4 Jan 2023 12:13:43 -0800 Message-Id: <20230104201349.1451191-3-kan.liang@linux.intel.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20230104201349.1451191-1-kan.liang@linux.intel.com> References: <20230104201349.1451191-1-kan.liang@linux.intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.3 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1754124344920293085?= X-GMAIL-MSGID: =?utf-8?q?1754124344920293085?= From: Kan Liang Retire Latency reports the number of elapsed core clocks between the retirement of the instruction indicated by the Instruction Pointer field of the PEBS record and the retirement of the prior instruction. It's enumerated by the IA32_PERF_CAPABILITIES.PEBS_TIMING_INFO[17]. Add flag PMU_FL_RETIRE_LATENCY to indicate the availability of the feature. The Retire Latency is not supported by the fixed counter 0 on p-core of MTL. Reviewed-by: Andi Kleen Signed-off-by: Kan Liang --- No change since V1 arch/x86/events/intel/core.c | 32 +++++++++++++++++++++++++++++++- arch/x86/events/intel/ds.c | 4 ++++ arch/x86/events/perf_event.h | 2 ++ 3 files changed, 37 insertions(+), 1 deletion(-) diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c index d2030be04e4a..a5678ab6d3e3 100644 --- a/arch/x86/events/intel/core.c +++ b/arch/x86/events/intel/core.c @@ -4210,6 +4210,9 @@ static struct event_constraint fixed0_counter0_constraint = static struct event_constraint fixed0_counter0_1_constraint = INTEL_ALL_EVENT_CONSTRAINT(0, 0x100000003ULL); +static struct event_constraint counters_1_7_constraint = + INTEL_ALL_EVENT_CONSTRAINT(0, 0xfeULL); + static struct event_constraint * hsw_get_event_constraints(struct cpu_hw_events *cpuc, int idx, struct perf_event *event) @@ -4374,6 +4377,30 @@ cmt_get_event_constraints(struct cpu_hw_events *cpuc, int idx, return c; } +static struct event_constraint * +rwc_get_event_constraints(struct cpu_hw_events *cpuc, int idx, + struct perf_event *event) +{ + struct event_constraint *c; + + c = spr_get_event_constraints(cpuc, idx, event); + + /* The Retire Latency is not supported by the fixed counter 0. */ + if (event->attr.precise_ip && + (event->attr.sample_type & PERF_SAMPLE_WEIGHT_TYPE) && + constraint_match(&fixed0_constraint, event->hw.config)) { + /* + * The Instruction PDIR is only available + * on the fixed counter 0. Error out for this case. + */ + if (event->attr.precise_ip == 3) + return &emptyconstraint; + return &counters_1_7_constraint; + } + + return c; +} + static struct event_constraint * mtl_get_event_constraints(struct cpu_hw_events *cpuc, int idx, struct perf_event *event) @@ -4381,7 +4408,7 @@ mtl_get_event_constraints(struct cpu_hw_events *cpuc, int idx, struct x86_hybrid_pmu *pmu = hybrid_pmu(event->pmu); if (pmu->cpu_type == hybrid_big) - return spr_get_event_constraints(cpuc, idx, event); + return rwc_get_event_constraints(cpuc, idx, event); if (pmu->cpu_type == hybrid_small) return cmt_get_event_constraints(cpuc, idx, event); @@ -6718,6 +6745,9 @@ __init int intel_pmu_init(void) if (is_hybrid()) intel_pmu_check_hybrid_pmus((u64)fixed_mask); + if (x86_pmu.intel_cap.pebs_timing_info) + x86_pmu.flags |= PMU_FL_RETIRE_LATENCY; + intel_aux_output_init(); return 0; diff --git a/arch/x86/events/intel/ds.c b/arch/x86/events/intel/ds.c index e991c54916d1..6ec326b47e2e 100644 --- a/arch/x86/events/intel/ds.c +++ b/arch/x86/events/intel/ds.c @@ -1753,6 +1753,7 @@ static void adaptive_pebs_save_regs(struct pt_regs *regs, #define PEBS_LATENCY_MASK 0xffff #define PEBS_CACHE_LATENCY_OFFSET 32 +#define PEBS_RETIRE_LATENCY_OFFSET 32 /* * With adaptive PEBS the layout depends on what fields are configured. @@ -1804,6 +1805,9 @@ static void setup_pebs_adaptive_sample_data(struct perf_event *event, set_linear_ip(regs, basic->ip); regs->flags = PERF_EFLAGS_EXACT; + if ((sample_type & PERF_SAMPLE_WEIGHT_STRUCT) && (x86_pmu.flags & PMU_FL_RETIRE_LATENCY)) + data->weight.var3_w = format_size >> PEBS_RETIRE_LATENCY_OFFSET & PEBS_LATENCY_MASK; + /* * The record for MEMINFO is in front of GP * But PERF_SAMPLE_TRANSACTION needs gprs->ax. diff --git a/arch/x86/events/perf_event.h b/arch/x86/events/perf_event.h index 1ac9d9e3c55c..d6de4487348c 100644 --- a/arch/x86/events/perf_event.h +++ b/arch/x86/events/perf_event.h @@ -608,6 +608,7 @@ union perf_capabilities { u64 pebs_baseline:1; u64 perf_metrics:1; u64 pebs_output_pt_available:1; + u64 pebs_timing_info:1; u64 anythread_deprecated:1; }; u64 capabilities; @@ -1003,6 +1004,7 @@ do { \ #define PMU_FL_PAIR 0x40 /* merge counters for large incr. events */ #define PMU_FL_INSTR_LATENCY 0x80 /* Support Instruction Latency in PEBS Memory Info Record */ #define PMU_FL_MEM_LOADS_AUX 0x100 /* Require an auxiliary event for the complete memory info */ +#define PMU_FL_RETIRE_LATENCY 0x200 /* Support Retire Latency in PEBS */ #define EVENT_VAR(_id) event_attr_##_id #define EVENT_PTR(_id) &event_attr_##_id.attr.attr From patchwork Wed Jan 4 20:13:44 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Liang, Kan" X-Patchwork-Id: 39080 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4e01:0:0:0:0:0 with SMTP id p1csp5335150wrt; Wed, 4 Jan 2023 12:15:43 -0800 (PST) X-Google-Smtp-Source: AMrXdXtm6nO/WKlKc9RPHyFXXK+V9E4eaI7SYf+om+gmOYRgThiWphsMakYjqN5g3x1TaxyYzzD6 X-Received: by 2002:a17:90b:796:b0:219:5f68:586e with SMTP id l22-20020a17090b079600b002195f68586emr50617236pjz.18.1672863342713; Wed, 04 Jan 2023 12:15:42 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1672863342; cv=none; d=google.com; s=arc-20160816; b=fwfYsHgkCu4lVPb+upnzs68AetXDPRg29Z6Fpl5jK5TcFpvTCaW56YbD8OlueBEuYI MGAPYZO+Zc2j/fdoz8ylDrdgejaak6heFrdQK8CBF0W4ZPdDAySaRwmVR1vXSNYYH+Y+ IVkr0jpOUFDCoN59D/5PHfz1/QeyupjW5qasVQYCpMYl0kJuC2BPFfgQW0LRWadxmItw EUZdxwP/MmyCyAfEKXBPYL0j2PA5Q91qSDPTY1HlKJk1pVIpqB/hvWgXYVKQmVWGxpMp YpoQY8kgYk+xobs3yg3NK5LBaEXSk9E3MjCPj5s8ZxpaInO7XZHeA1avb34GNmaIcD1/ jfPw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=vlUfBXclKbvEYrepnyEvvIa+Ufze1VLoMptGwUqeUDI=; b=qaz0uoVspB/Jry6lRMwtbOfsUsh00V4T0EnL/n2ErRIAjI+sgKRyrQgWmadmfhGFMJ q2hP/ihj3RdJTeb5RoS0m/3cpDlCBVywNuUcuZRzJepIk/e5cfnO0MwFZVS/KCiIs6T5 MG80UQnCVRc+wFRmnO+bjRgvdBbcuYZhgS1I3Ufjp8FmhqDWLqxPHC64tWcvRMhNCv69 AYRa2IP83aVRCSsrG6pA9b10BfH9Z4MWplg/ZsvnIKOjIt3sT3VGOQwZo1KcK79BoKlS ibm/Upx1MY/m920juUr7seD1pRmZ2oFQMPuwD5mWAaEomMmvLUSenyo+Of7/ydjngE+Y n2zQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=NtkPnD6+; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id 144-20020a630096000000b004a08210f49fsi14909693pga.329.2023.01.04.12.15.29; Wed, 04 Jan 2023 12:15:42 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=NtkPnD6+; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240083AbjADUOZ (ORCPT + 99 others); Wed, 4 Jan 2023 15:14:25 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59720 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239277AbjADUOL (ORCPT ); Wed, 4 Jan 2023 15:14:11 -0500 Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E51D21B9FB for ; Wed, 4 Jan 2023 12:14:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1672863249; x=1704399249; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=7qAgriB4wHb+jHdCXvImsH0VxmeivK2v66/ujQm0auE=; b=NtkPnD6+P4Dql5BizSDZ9Y4PnTlsLS3h8onSPO8ngTL509Vp81d2V/Jv nTHaW6tlklSyI3vqKXD79qSf3mnAnBLLkG/YPxk8BxE1xVKxA7DTIsAwF Y73xO4tJo75weszET/I+SvHyyC9odyjieCXGXMEms0gQglmjvZi4TepJt GdvN7Tf6cIZdwrM9fIF73keEARGC84HPD7B/5UPu6KKKk73OrVKJ2Z5dM e+XUNTiB7M0Cou1Vk47dvRAfKG2zjezTKsySxRqcke4PIJXfeVMrfneKy sdTPu0owA754Xi56v9h5pxeS+4hKSYMixU5GLRnujH856B0z6lLWEPHzq g==; X-IronPort-AV: E=McAfee;i="6500,9779,10580"; a="322105461" X-IronPort-AV: E=Sophos;i="5.96,300,1665471600"; d="scan'208";a="322105461" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Jan 2023 12:14:09 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10580"; a="779324003" X-IronPort-AV: E=Sophos;i="5.96,300,1665471600"; d="scan'208";a="779324003" Received: from kanliang-dev.jf.intel.com ([10.165.154.102]) by orsmga004.jf.intel.com with ESMTP; 04 Jan 2023 12:14:09 -0800 From: kan.liang@linux.intel.com To: peterz@infradead.org, mingo@redhat.com, acme@kernel.org, linux-kernel@vger.kernel.org Cc: ak@linux.intel.com, eranian@google.com, irogers@google.com, Kan Liang Subject: [PATCH V2 4/9] x86/cpufeatures: Add Architectural PerfMon Extension bit Date: Wed, 4 Jan 2023 12:13:44 -0800 Message-Id: <20230104201349.1451191-4-kan.liang@linux.intel.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20230104201349.1451191-1-kan.liang@linux.intel.com> References: <20230104201349.1451191-1-kan.liang@linux.intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.3 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1754124352422242111?= X-GMAIL-MSGID: =?utf-8?q?1754124352422242111?= From: Kan Liang CPUID.(EAX=07H, ECX=1):EAX[8] indicates whether the Architectural PerfMon Extension leaf (CPUID leaf 23) is supported. The "X86_FEATURE_..., word 12" is already mirrored from CPUID "0x00000007:1 (EAX)". Add X86_FEATURE_ARCH_PERFMON_EXT under the "word 12" section. The new Architectural PerfMon Extension leaf (CPUID leaf 23) will be supported in the perf_events subsystem later. The feature will not appear in /proc/cpuinfo. Signed-off-by: Kan Liang --- Change since V1 - Rebase on top of 6.2-rc1 arch/x86/include/asm/cpufeatures.h | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h index 61012476d66e..b64555b68a14 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -312,6 +312,7 @@ #define X86_FEATURE_AVX_VNNI (12*32+ 4) /* AVX VNNI instructions */ #define X86_FEATURE_AVX512_BF16 (12*32+ 5) /* AVX512 BFLOAT16 instructions */ #define X86_FEATURE_CMPCCXADD (12*32+ 7) /* "" CMPccXADD instructions */ +#define X86_FEATURE_ARCH_PERFMON_EXT (12*32+ 8) /* "" Intel Architectural PerfMon Extension */ #define X86_FEATURE_AMX_FP16 (12*32+21) /* "" AMX fp16 Support */ #define X86_FEATURE_AVX_IFMA (12*32+23) /* "" Support for VPMADD52[H,L]UQ */ From patchwork Wed Jan 4 20:13:45 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Liang, Kan" X-Patchwork-Id: 39081 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4e01:0:0:0:0:0 with SMTP id p1csp5335191wrt; Wed, 4 Jan 2023 12:15:49 -0800 (PST) X-Google-Smtp-Source: AMrXdXv/NP77tmqMF0ViftNM2fJSRmXCIjuQ3saO3zsfbmiRsdjaGGPcbP1OqZwhdk5RivuBOk3x X-Received: by 2002:aa7:9147:0:b0:56c:318a:f83b with SMTP id 7-20020aa79147000000b0056c318af83bmr57112769pfi.13.1672863349391; Wed, 04 Jan 2023 12:15:49 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1672863349; cv=none; d=google.com; s=arc-20160816; b=KzvCrmdEoEzU02RGfjLBE5/m8IHD0yHEbyRx32xwV5uRRW5TuVqBkgFuJ75H12qbPF GHcpEjdM4Zp+qp70GFLt8GGE+1Tm8PSg1hUNMsshB5ZVmDJ/m3H6JisyCpFpq8Ad/mTm rAXHq14EiLkH9XWVyEs8sRB1/N6BZ9vhkbJEBlS/LDUAQ/QJS61VfU7AK3E7SPf5sat3 mHRoJljhYhz0pnFgq2rotQTATNqiotWsBI8M62sBpapQi4JSzpfzFsMyN7p1o7DfOMva kudk6ERpnHCgmyGX0OlBqpY5cTLp5V740Q2+oytsIFevKvwg8exudw+GLL8trRCQek4j FHtw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=XD7tryjvpr/OOwuIm9OaUVTzvvVr1f7eJhkEGGuQ3H8=; b=YddwfgDP8PCpzKH29To5+ZpYYE54n0fCk5jLY6HSbSrN3nIxhA8pgePxHFyllrEIDe yOeq9j+rYdNIA+CSm7h9HOnF/kdcXsDm4WHOJ9iHSURI8mctU1DfJbKl5NPcz4HXgUJB WKBUY5KjLaq4/4Z9xCOjz//hv/5KsLca9hKRBUUkL4EQeXpCXtOC4T4N8usDNooZg2f9 7pFrkvP/c4E2VSddnwVwgc7y2dnZyOVCr3j+ZNBu1ucaZOweRJ0PzfRPokhcKqtPPHAi ntffmMDF1vBYieA43Jn02uixL6M9OJ7X+LJ62+yVGubsfm9yabZVvs9I/vvMbR9Sy8R/ T7vQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=XgDVi17b; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id ay17-20020a056a00301100b005827904e343si9059567pfb.220.2023.01.04.12.15.37; Wed, 04 Jan 2023 12:15:49 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=XgDVi17b; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240006AbjADUO3 (ORCPT + 99 others); Wed, 4 Jan 2023 15:14:29 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59728 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239929AbjADUOL (ORCPT ); Wed, 4 Jan 2023 15:14:11 -0500 Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BBB991BE8E for ; Wed, 4 Jan 2023 12:14:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1672863250; x=1704399250; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=970u/0g+e4dGCNxze4E0X7C5IVyu6CmpruauqCZkzzc=; b=XgDVi17bwbpIbHxh02ToEBxXibxTAb8omb/dPzTWOoGCVt9myje9Hviv BNMk0Ch33eQ8iDvbCwQOi9Qq8Bfg3YQElOE/C45EkiWRNq46oi7a3SgXk L9UKWXTlnk6LTZAZxJfk/wyN9W6zR2zkfrVuTKwe2im3Fkba22KD/orb/ WoFXa8NB5KDbPDlQRnJ9BLWfosBPl5m6oyJ1Pi7f6yrYHaDI9qyMDX98z dt6LGwoCGmaK9XpcufVdxy7wNutmTeJlxoQW2k5ouaIGEOG/kaReJga1E YYKQcdSTI0EYK8hM9NRKPOSSg1TNbT0QGdNiFrumUJvjZdvuGsFwjvXez A==; X-IronPort-AV: E=McAfee;i="6500,9779,10580"; a="322105472" X-IronPort-AV: E=Sophos;i="5.96,300,1665471600"; d="scan'208";a="322105472" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Jan 2023 12:14:10 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10580"; a="779324005" X-IronPort-AV: E=Sophos;i="5.96,300,1665471600"; d="scan'208";a="779324005" Received: from kanliang-dev.jf.intel.com ([10.165.154.102]) by orsmga004.jf.intel.com with ESMTP; 04 Jan 2023 12:14:10 -0800 From: kan.liang@linux.intel.com To: peterz@infradead.org, mingo@redhat.com, acme@kernel.org, linux-kernel@vger.kernel.org Cc: ak@linux.intel.com, eranian@google.com, irogers@google.com, Kan Liang Subject: [PATCH V2 5/9] perf/x86/intel: Support Architectural PerfMon Extension leaf Date: Wed, 4 Jan 2023 12:13:45 -0800 Message-Id: <20230104201349.1451191-5-kan.liang@linux.intel.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20230104201349.1451191-1-kan.liang@linux.intel.com> References: <20230104201349.1451191-1-kan.liang@linux.intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.3 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1754124359782756775?= X-GMAIL-MSGID: =?utf-8?q?1754124359782756775?= From: Kan Liang The new CPUID leaf 0x23 reports the "true view" of PMU resources. The sub-leaf 1 reports the available general-purpose counters and fixed counters. Update the number of counters and fixed counters when the sub-leaf is detected. Signed-off-by: Kan Liang --- No change since V1 arch/x86/events/intel/core.c | 22 ++++++++++++++++++++++ arch/x86/include/asm/perf_event.h | 8 ++++++++ 2 files changed, 30 insertions(+) diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c index a5678ab6d3e3..29d2d0411caf 100644 --- a/arch/x86/events/intel/core.c +++ b/arch/x86/events/intel/core.c @@ -4588,6 +4588,25 @@ static void flip_smm_bit(void *data) } } +static void intel_pmu_check_num_counters(int *num_counters, + int *num_counters_fixed, + u64 *intel_ctrl, u64 fixed_mask); + +static void update_pmu_cap(struct x86_hybrid_pmu *pmu) +{ + unsigned int sub_bitmaps = cpuid_eax(ARCH_PERFMON_EXT_LEAF); + unsigned int eax, ebx, ecx, edx; + + if (sub_bitmaps & ARCH_PERFMON_NUM_COUNTER_LEAF_BIT) { + cpuid_count(ARCH_PERFMON_EXT_LEAF, ARCH_PERFMON_NUM_COUNTER_LEAF, + &eax, &ebx, &ecx, &edx); + pmu->num_counters = fls(eax); + pmu->num_counters_fixed = fls(ebx); + intel_pmu_check_num_counters(&pmu->num_counters, &pmu->num_counters_fixed, + &pmu->intel_ctrl, ebx); + } +} + static bool init_hybrid_pmu(int cpu) { struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu); @@ -4613,6 +4632,9 @@ static bool init_hybrid_pmu(int cpu) if (!cpumask_empty(&pmu->supported_cpus)) goto end; + if (this_cpu_has(X86_FEATURE_ARCH_PERFMON_EXT)) + update_pmu_cap(pmu); + if (!check_hw_exists(&pmu->pmu, pmu->num_counters, pmu->num_counters_fixed)) return false; diff --git a/arch/x86/include/asm/perf_event.h b/arch/x86/include/asm/perf_event.h index 5d0f6891ae61..6496bdbcac98 100644 --- a/arch/x86/include/asm/perf_event.h +++ b/arch/x86/include/asm/perf_event.h @@ -159,6 +159,14 @@ union cpuid10_edx { unsigned int full; }; +/* + * Intel "Architectural Performance Monitoring extension" CPUID + * detection/enumeration details: + */ +#define ARCH_PERFMON_EXT_LEAF 0x00000023 +#define ARCH_PERFMON_NUM_COUNTER_LEAF_BIT 0x1 +#define ARCH_PERFMON_NUM_COUNTER_LEAF 0x1 + /* * Intel Architectural LBR CPUID detection/enumeration details: */ From patchwork Wed Jan 4 20:13:46 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Liang, Kan" X-Patchwork-Id: 39082 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4e01:0:0:0:0:0 with SMTP id p1csp5335261wrt; Wed, 4 Jan 2023 12:15:57 -0800 (PST) X-Google-Smtp-Source: AMrXdXsRYJxRRYxmeOha117EL2tXs/a5V0GG9OYgKzRwLPYSBD8hEelhgo2+fJ4yV9/bW1rWG6Lb X-Received: by 2002:a17:902:7488:b0:189:fbe0:fe8a with SMTP id h8-20020a170902748800b00189fbe0fe8amr54662396pll.26.1672863357431; Wed, 04 Jan 2023 12:15:57 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1672863357; cv=none; d=google.com; s=arc-20160816; b=W/p/dRuVL0mOGKWx87FkCENOjw4F5xRFQXggXbeTkgbEZQ2hMNU5Qncuz51sLbUmEu yQp/JBr9TeZNnY+cXSqDe6GM2EURGu9bo5LF/OouRZojeMjcWlpEbSBhUSXonK2B7+g3 Jwi/HpyT3KpbjoGjS9qbi5zhaxldNRkmyRR//1h21Jjh3RqUeAwvsT6kNaUEWpbgFwmG sOeWg75azTYQHI9IhzVQgd5ZzI8rxxTpiJ2RSMRUCgsFgiMLji+uoae51UL2I3Hz/PTX s4eRzloNdf7xj+yqNrjlxZQe97z0iI0YBWV+v3DEXjItZwylvVZJzyGYOpMSYQ8fV8V+ G/iA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=D6hGY2v+Q70/2y5//K8lLKVtVkhN2k5KorBITxCzz48=; b=rt+O9Sbq/KmjhOyweutpZCYUf0tPmfhVSRlchE/7tW2/4mE7knJ3VVcEpSDjCyWrJ/ zVOpbvqtQlMC4x0WrEtOmXpV3+P7r166vpOiB+A//ncsdI9+lYmabuZrMH4b1qaYhag3 L/36WCoPuU4mM2vXAauHUOxoUIZdJvaif/0pLFjm7f/tcIFcJWDjqbLxz+WIgggUPSxF AY54IIZAU25nmSri8Mk+8nzXBUbLT6MGiZsQoM5uIyILBYuNIvDmVcemCd4fqy4TVIzt IKWvY8R3uMWoLIJw+xqyNxsl6nO4lu3RXaettC0Mo+ir7IhllesBAMznYUZfpQlJTR8s k3Aw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=oFzCnG8M; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id r10-20020a170902c60a00b00192569ad4f2si33143670plr.426.2023.01.04.12.15.44; Wed, 04 Jan 2023 12:15:57 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=oFzCnG8M; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240089AbjADUOd (ORCPT + 99 others); Wed, 4 Jan 2023 15:14:33 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59740 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239931AbjADUOM (ORCPT ); Wed, 4 Jan 2023 15:14:12 -0500 Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9EDE91ADAE for ; Wed, 4 Jan 2023 12:14:11 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1672863251; x=1704399251; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=ODnj0oJoGmWARgg6cHLRiOsAa7nFIWXK+OjGcPoiaW4=; b=oFzCnG8MpVtqgnYd1nSvW29bPwRbrwfTFneRSUROKwB26U1buRJELakF 9uAaBpJDR0xgmsv7y9NS4GjnDXF8oQTlqfayByk80gQFnCydlmmH+Hyum l5O6C61PvyKANug1eB+STo9f3OlMRNBHvEJQztsShL0uPmxe1hsSfMUvI AWlu2imXau/fuoMUwQnSzjcbEvXxEKL9n13MHV8pDdm6huGhX2hD+EscY RjqXUnnfw50UfwICYSMsYzFZBdnGfNQxn9cDzZ/FgGOEt/LRL8YaorOEj Wfp+L84bT9iHfm1+sGQJKoxrHRSDF44RC2ZeLKkeIMAeXBr8fyr8/GlqG A==; X-IronPort-AV: E=McAfee;i="6500,9779,10580"; a="322105478" X-IronPort-AV: E=Sophos;i="5.96,300,1665471600"; d="scan'208";a="322105478" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Jan 2023 12:14:11 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10580"; a="779324007" X-IronPort-AV: E=Sophos;i="5.96,300,1665471600"; d="scan'208";a="779324007" Received: from kanliang-dev.jf.intel.com ([10.165.154.102]) by orsmga004.jf.intel.com with ESMTP; 04 Jan 2023 12:14:11 -0800 From: kan.liang@linux.intel.com To: peterz@infradead.org, mingo@redhat.com, acme@kernel.org, linux-kernel@vger.kernel.org Cc: ak@linux.intel.com, eranian@google.com, irogers@google.com, Kan Liang Subject: [PATCH V2 6/9] perf/x86/cstate: Add Meteor Lake support Date: Wed, 4 Jan 2023 12:13:46 -0800 Message-Id: <20230104201349.1451191-6-kan.liang@linux.intel.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20230104201349.1451191-1-kan.liang@linux.intel.com> References: <20230104201349.1451191-1-kan.liang@linux.intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.3 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1754124367734441599?= X-GMAIL-MSGID: =?utf-8?q?1754124367734441599?= From: Kan Liang Meteor Lake is Intel's successor to Raptor lake. From the perspective of Intel cstate residency counters, there is nothing changed compared with Raptor lake. Share adl_cstates with Raptor lake. Update the comments for Meteor Lake. Reviewed-by: Andi Kleen Signed-off-by: Kan Liang --- No change since V1 arch/x86/events/intel/cstate.c | 21 ++++++++++++--------- 1 file changed, 12 insertions(+), 9 deletions(-) diff --git a/arch/x86/events/intel/cstate.c b/arch/x86/events/intel/cstate.c index a2834bc93149..3019fb1926e3 100644 --- a/arch/x86/events/intel/cstate.c +++ b/arch/x86/events/intel/cstate.c @@ -41,6 +41,7 @@ * MSR_CORE_C1_RES: CORE C1 Residency Counter * perf code: 0x00 * Available model: SLM,AMT,GLM,CNL,ICX,TNT,ADL,RPL + * MTL * Scope: Core (each processor core has a MSR) * MSR_CORE_C3_RESIDENCY: CORE C3 Residency Counter * perf code: 0x01 @@ -51,50 +52,50 @@ * perf code: 0x02 * Available model: SLM,AMT,NHM,WSM,SNB,IVB,HSW,BDW, * SKL,KNL,GLM,CNL,KBL,CML,ICL,ICX, - * TGL,TNT,RKL,ADL,RPL,SPR + * TGL,TNT,RKL,ADL,RPL,SPR,MTL * Scope: Core * MSR_CORE_C7_RESIDENCY: CORE C7 Residency Counter * perf code: 0x03 * Available model: SNB,IVB,HSW,BDW,SKL,CNL,KBL,CML, - * ICL,TGL,RKL,ADL,RPL + * ICL,TGL,RKL,ADL,RPL,MTL * Scope: Core * MSR_PKG_C2_RESIDENCY: Package C2 Residency Counter. * perf code: 0x00 * Available model: SNB,IVB,HSW,BDW,SKL,KNL,GLM,CNL, * KBL,CML,ICL,ICX,TGL,TNT,RKL,ADL, - * RPL,SPR + * RPL,SPR,MTL * Scope: Package (physical package) * MSR_PKG_C3_RESIDENCY: Package C3 Residency Counter. * perf code: 0x01 * Available model: NHM,WSM,SNB,IVB,HSW,BDW,SKL,KNL, * GLM,CNL,KBL,CML,ICL,TGL,TNT,RKL, - * ADL,RPL + * ADL,RPL,MTL * Scope: Package (physical package) * MSR_PKG_C6_RESIDENCY: Package C6 Residency Counter. * perf code: 0x02 * Available model: SLM,AMT,NHM,WSM,SNB,IVB,HSW,BDW, * SKL,KNL,GLM,CNL,KBL,CML,ICL,ICX, - * TGL,TNT,RKL,ADL,RPL,SPR + * TGL,TNT,RKL,ADL,RPL,SPR,MTL * Scope: Package (physical package) * MSR_PKG_C7_RESIDENCY: Package C7 Residency Counter. * perf code: 0x03 * Available model: NHM,WSM,SNB,IVB,HSW,BDW,SKL,CNL, - * KBL,CML,ICL,TGL,RKL,ADL,RPL + * KBL,CML,ICL,TGL,RKL,ADL,RPL,MTL * Scope: Package (physical package) * MSR_PKG_C8_RESIDENCY: Package C8 Residency Counter. * perf code: 0x04 * Available model: HSW ULT,KBL,CNL,CML,ICL,TGL,RKL, - * ADL,RPL + * ADL,RPL,MTL * Scope: Package (physical package) * MSR_PKG_C9_RESIDENCY: Package C9 Residency Counter. * perf code: 0x05 * Available model: HSW ULT,KBL,CNL,CML,ICL,TGL,RKL, - * ADL,RPL + * ADL,RPL,MTL * Scope: Package (physical package) * MSR_PKG_C10_RESIDENCY: Package C10 Residency Counter. * perf code: 0x06 * Available model: HSW ULT,KBL,GLM,CNL,CML,ICL,TGL, - * TNT,RKL,ADL,RPL + * TNT,RKL,ADL,RPL,MTL * Scope: Package (physical package) * */ @@ -686,6 +687,8 @@ static const struct x86_cpu_id intel_cstates_match[] __initconst = { X86_MATCH_INTEL_FAM6_MODEL(RAPTORLAKE, &adl_cstates), X86_MATCH_INTEL_FAM6_MODEL(RAPTORLAKE_P, &adl_cstates), X86_MATCH_INTEL_FAM6_MODEL(RAPTORLAKE_S, &adl_cstates), + X86_MATCH_INTEL_FAM6_MODEL(METEORLAKE, &adl_cstates), + X86_MATCH_INTEL_FAM6_MODEL(METEORLAKE_L, &adl_cstates), { }, }; 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[2620:137:e000::1:20]) by mx.google.com with ESMTP id j2-20020a17090ae60200b00212e2e1b626si34687781pjy.164.2023.01.04.12.15.46; Wed, 04 Jan 2023 12:15:58 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b="aLo/I2Yu"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240010AbjADUOh (ORCPT + 99 others); Wed, 4 Jan 2023 15:14:37 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59746 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239925AbjADUOM (ORCPT ); Wed, 4 Jan 2023 15:14:12 -0500 Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 65BAF1B9FB for ; Wed, 4 Jan 2023 12:14:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1672863252; x=1704399252; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=+ybMgws1VuLWCF0sTJYUUURfo8JwvOHjZoWJLyMlu14=; b=aLo/I2Yu4m3x0wX2tKJp/bQ4ZrDow2yxsqCAu5Ptz8pv/S4p8P79w4oy xBlxxjPmuF7W9Z0Lg1++gv8FHuhGA3ejAWwvl+DUnOWXMsUcc9SJmtdyr ejp231w0c2Jq7XztwCLcZHYyUtE2w6XxcTgRLnxlneI+FuSHaYRKSD7SN C/PqKzGMeM7dKjcLR2rLguQheTvxjXhmdaapsUCdD5WbeyDYbmozjdciH y3bvdOZavxVizZpxl/74zh/J7Mp+UeTJ6tkEfz6N+Qxs98UzNM1vSAImf Jpg6ekrz7coEqTCZTikg12opM3s63tBjZuOIq0CK+A2jUhcqIZBxG2m9q Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10580"; a="322105484" X-IronPort-AV: E=Sophos;i="5.96,300,1665471600"; d="scan'208";a="322105484" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Jan 2023 12:14:12 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10580"; a="779324015" X-IronPort-AV: E=Sophos;i="5.96,300,1665471600"; d="scan'208";a="779324015" Received: from kanliang-dev.jf.intel.com ([10.165.154.102]) by orsmga004.jf.intel.com with ESMTP; 04 Jan 2023 12:14:12 -0800 From: kan.liang@linux.intel.com To: peterz@infradead.org, mingo@redhat.com, acme@kernel.org, linux-kernel@vger.kernel.org Cc: ak@linux.intel.com, eranian@google.com, irogers@google.com, Kan Liang Subject: [PATCH V2 7/9] perf/x86/msr: Add Meteor Lake support Date: Wed, 4 Jan 2023 12:13:47 -0800 Message-Id: <20230104201349.1451191-7-kan.liang@linux.intel.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20230104201349.1451191-1-kan.liang@linux.intel.com> References: <20230104201349.1451191-1-kan.liang@linux.intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.3 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1754124368749517171?= X-GMAIL-MSGID: =?utf-8?q?1754124368749517171?= From: Kan Liang Meteor Lake is Intel's successor to Raptor lake. PPERF and SMI_COUNT MSRs are also supported. Reviewed-by: Andi Kleen Signed-off-by: Kan Liang --- No change since V1 arch/x86/events/msr.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/x86/events/msr.c b/arch/x86/events/msr.c index ecced3a52668..074150d28fa8 100644 --- a/arch/x86/events/msr.c +++ b/arch/x86/events/msr.c @@ -107,6 +107,8 @@ static bool test_intel(int idx, void *data) case INTEL_FAM6_RAPTORLAKE: case INTEL_FAM6_RAPTORLAKE_P: case INTEL_FAM6_RAPTORLAKE_S: + case INTEL_FAM6_METEORLAKE: + case INTEL_FAM6_METEORLAKE_L: if (idx == PERF_MSR_SMI || idx == PERF_MSR_PPERF) return true; break; From patchwork Wed Jan 4 20:13:48 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Liang, Kan" X-Patchwork-Id: 39084 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4e01:0:0:0:0:0 with SMTP id p1csp5335464wrt; Wed, 4 Jan 2023 12:16:27 -0800 (PST) X-Google-Smtp-Source: AMrXdXuGiz/coPa9u7GxxbZrcL+CNwtLZ2GJdbgweRyq41yaKHgXeX+hf/Z9xHCXu1/beA8Z6Gq1 X-Received: by 2002:a17:90b:4d8c:b0:223:dd6f:13af with SMTP id oj12-20020a17090b4d8c00b00223dd6f13afmr53339240pjb.36.1672863387744; Wed, 04 Jan 2023 12:16:27 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1672863387; cv=none; d=google.com; s=arc-20160816; b=wHHGJAobnOY6dSYzco9Efted0ZTETqAykC2Ep4GOdsf1lzIHYPlt4Ihsdk+wWlnKhF 60NEheCkh21RRhQK+6OuLhBiKRPNMVh02FppS3D9rsNp6hOHrsC8XFyuErxH8TKC1Pii saIR9BQQ7nPTQVTEtJFoCtg/zPvCNaCS93wD0H2cFZeyUYyQ2hbmFllGBFd/djWVYaUy 4bkUMUcXPQYRtca4e88bOdig32uyIVk49KPuh8Jny1T0VtqjTCjLloZkFdO6Ei17vZGR w4WRy4VWw0+gKIcCHz7/WcKr9IFZDT58DtzGMrm5U9QWqEj9ijXCwSZh2uP3q76DGzFi HQXQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=/HJ/AsLtnKZ7+OXdCien0MOZCvk+IfeRb+2A559OPLY=; b=YHZg2ensm0Cn6pKXkuGWRvfD1OKprwLmC/KwUfqgHOoIQXIXwPBP5oMVrmoU+Zfnbj NELOvwMMK516dmzmy56c0g4Bi3fS/LjOh/Y+bkbQGFL4lCOoQ198ZTUrcQTsCnyaAJtm tAYjfQ3F86qNKvx0m07rigOHTz7kwZqktCLmpAdJ7XbN6hke9Cme55IUp8PHkG23qEzq YoF8LGv5e2TtpWPGslvTu9j15kdJvsduRg5zSxL+JJxwDT0D1axJMCBQgnz+6pLKuDRe poZ84Oij5SeqCUhhpo0fXSpmZ5ov3Y52F0nPXnXJOZbgnrkXnpjZH/Jtb9YsAlnvoFR+ 0CtA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=n7DKaUYo; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id j6-20020a17090a7e8600b0022695223cdcsi5757198pjl.178.2023.01.04.12.16.15; Wed, 04 Jan 2023 12:16:27 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=n7DKaUYo; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240127AbjADUOn (ORCPT + 99 others); Wed, 4 Jan 2023 15:14:43 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59752 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239935AbjADUOO (ORCPT ); Wed, 4 Jan 2023 15:14:14 -0500 Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4679F11C3A for ; Wed, 4 Jan 2023 12:14:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1672863253; x=1704399253; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Ehlpv62JJoPoTAs4sBwCHanyUqPdY5VYO9Qbv8uzt+o=; b=n7DKaUYo+UkNAhzuC2lUl9N1nfs0I0VD3buMIcbtnNg3dafxsr+h14lq IcV+dnIGnpmZI1LSCWup5vSZ/nnhNvBqCgEx739CTXpj0rWoHMSUaBzYs RWRGHg99rpYB4960bRgFTUlJ73JCZm2ENBM5Oak5cfJal5JgdlPyWT5rw P/frrIqjfNwdnz805h9ObPBl/2PyMCbBaCydaMmiteFRC09BvFifrhp+s WKmSqdkE9I+W+tmvHqs8DUgblCvCCWBqQI9sEF0OLDw1N24yCmboEr5yp MpIqofMTt7N7DJi1yFkNrFFxrf/qlLKKTG1Den+iheZ4vCybgEGEpJy68 g==; X-IronPort-AV: E=McAfee;i="6500,9779,10580"; a="322105490" X-IronPort-AV: E=Sophos;i="5.96,300,1665471600"; d="scan'208";a="322105490" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Jan 2023 12:14:12 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10580"; a="779324019" X-IronPort-AV: E=Sophos;i="5.96,300,1665471600"; d="scan'208";a="779324019" Received: from kanliang-dev.jf.intel.com ([10.165.154.102]) by orsmga004.jf.intel.com with ESMTP; 04 Jan 2023 12:14:12 -0800 From: kan.liang@linux.intel.com To: peterz@infradead.org, mingo@redhat.com, acme@kernel.org, linux-kernel@vger.kernel.org Cc: ak@linux.intel.com, eranian@google.com, irogers@google.com, Kan Liang Subject: [PATCH V2 8/9] perf report: Support Retire Latency Date: Wed, 4 Jan 2023 12:13:48 -0800 Message-Id: <20230104201349.1451191-8-kan.liang@linux.intel.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20230104201349.1451191-1-kan.liang@linux.intel.com> References: <20230104201349.1451191-1-kan.liang@linux.intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.3 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1754124399705672627?= X-GMAIL-MSGID: =?utf-8?q?1754124399705672627?= From: Kan Liang The Retire Latency field is added in the var3_w of the PERF_SAMPLE_WEIGHT_STRUCT. The Retire Latency reports pipeline stall of this instruction compared to the previous instruction in cycles. That's quite useful to display the information with perf mem report. The p_stage_cyc for Power is also from the var3_w. Union the p_stage_cyc and retire_lat to share the code. Implement X86 specific codes to display the X86 specific header. Add a new sort key retire_lat for the Retire Latency. Reviewed-by: Andi Kleen Signed-off-by: Kan Liang --- Change since V1 - Rebase on top of 6.2-rc1 tools/perf/Documentation/perf-report.txt | 2 ++ tools/perf/arch/x86/util/event.c | 20 ++++++++++++++++++++ tools/perf/util/sample.h | 5 ++++- tools/perf/util/sort.c | 2 ++ tools/perf/util/sort.h | 2 ++ 5 files changed, 30 insertions(+), 1 deletion(-) diff --git a/tools/perf/Documentation/perf-report.txt b/tools/perf/Documentation/perf-report.txt index 4fa509b15948..e3971ddb666c 100644 --- a/tools/perf/Documentation/perf-report.txt +++ b/tools/perf/Documentation/perf-report.txt @@ -115,6 +115,8 @@ OPTIONS - p_stage_cyc: On powerpc, this presents the number of cycles spent in a pipeline stage. And currently supported only on powerpc. - addr: (Full) virtual address of the sampled instruction + - retire_lat: On X86, this reports pipeline stall of this instruction compared + to the previous instruction in cycles. And currently supported only on X86 By default, comm, dso and symbol keys are used. (i.e. --sort comm,dso,symbol) diff --git a/tools/perf/arch/x86/util/event.c b/tools/perf/arch/x86/util/event.c index a3acefe6d0c6..37b3feb53e8d 100644 --- a/tools/perf/arch/x86/util/event.c +++ b/tools/perf/arch/x86/util/event.c @@ -89,6 +89,7 @@ void arch_perf_parse_sample_weight(struct perf_sample *data, else { data->weight = weight.var1_dw; data->ins_lat = weight.var2_w; + data->retire_lat = weight.var3_w; } } @@ -102,3 +103,22 @@ void arch_perf_synthesize_sample_weight(const struct perf_sample *data, *array |= ((u64)data->ins_lat << 32); } } + +const char *arch_perf_header_entry(const char *se_header) +{ + if (!strcmp(se_header, "Local Pipeline Stage Cycle")) + return "Local Retire Latency"; + else if (!strcmp(se_header, "Pipeline Stage Cycle")) + return "Retire Latency"; + + return se_header; +} + +int arch_support_sort_key(const char *sort_key) +{ + if (!strcmp(sort_key, "p_stage_cyc")) + return 1; + if (!strcmp(sort_key, "local_p_stage_cyc")) + return 1; + return 0; +} diff --git a/tools/perf/util/sample.h b/tools/perf/util/sample.h index 60ec79d4eea4..33b08e0ac746 100644 --- a/tools/perf/util/sample.h +++ b/tools/perf/util/sample.h @@ -92,7 +92,10 @@ struct perf_sample { u8 cpumode; u16 misc; u16 ins_lat; - u16 p_stage_cyc; + union { + u16 p_stage_cyc; + u16 retire_lat; + }; bool no_hw_idx; /* No hw_idx collected in branch_stack */ char insn[MAX_INSN]; void *raw_data; diff --git a/tools/perf/util/sort.c b/tools/perf/util/sort.c index e188f74698dd..e2cc18cd08cd 100644 --- a/tools/perf/util/sort.c +++ b/tools/perf/util/sort.c @@ -2132,6 +2132,8 @@ static struct sort_dimension common_sort_dimensions[] = { DIM(SORT_LOCAL_PIPELINE_STAGE_CYC, "local_p_stage_cyc", sort_local_p_stage_cyc), DIM(SORT_GLOBAL_PIPELINE_STAGE_CYC, "p_stage_cyc", sort_global_p_stage_cyc), DIM(SORT_ADDR, "addr", sort_addr), + DIM(SORT_LOCAL_RETIRE_LAT, "local_retire_lat", sort_local_p_stage_cyc), + DIM(SORT_GLOBAL_RETIRE_LAT, "retire_lat", sort_global_p_stage_cyc), }; #undef DIM diff --git a/tools/perf/util/sort.h b/tools/perf/util/sort.h index 921715e6aec4..9a91d0df2833 100644 --- a/tools/perf/util/sort.h +++ b/tools/perf/util/sort.h @@ -237,6 +237,8 @@ enum sort_type { SORT_LOCAL_PIPELINE_STAGE_CYC, SORT_GLOBAL_PIPELINE_STAGE_CYC, SORT_ADDR, + SORT_LOCAL_RETIRE_LAT, + SORT_GLOBAL_RETIRE_LAT, /* branch stack specific sort keys */ __SORT_BRANCH_STACK, From patchwork Wed Jan 4 20:13:49 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Liang, Kan" X-Patchwork-Id: 39085 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4e01:0:0:0:0:0 with SMTP id p1csp5335704wrt; Wed, 4 Jan 2023 12:16:56 -0800 (PST) X-Google-Smtp-Source: AMrXdXsycD6+a9WY5pxnWFu3bfOGojQkK0WLRR1kmXY4zDAA7Knq7rVbtbL/C9DEBEusO2rfHVIB X-Received: by 2002:a17:902:7284:b0:190:d273:38a9 with SMTP id d4-20020a170902728400b00190d27338a9mr52009290pll.14.1672863415754; Wed, 04 Jan 2023 12:16:55 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1672863415; cv=none; d=google.com; s=arc-20160816; b=Rea3umOAQqXlhAFJVZ610JOesr9hi6JWYHqafxL9FhwaheUTTI6lSa7kDNZQ4mkptY WXxhA98nHUu1v+AiAieSlWVOHaw9Dcuf2Nru97DR4uWTye8uUSWyHucWj+j7tTDynnXx kRw2r7ptaFkBFoVHyyzbElxoIqrEEhiCsUgAIwdkI1qo6jtpNg6dCYaDHbOp9+AvRMoS Vo4ogv4KFaAe0nzlJWxj4LxCgO1OSMcjZ9YMxk8cO9jQV3hAPKmPjm6IeNsuHGb9/nJL mAzi/3a9xbZg8VJe0VJNnh8wZqe8SQVyuUYAbjgBYEQSv6MhUzEMs0h39dWkWJz273aG Xa5A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=nmAMPpYpFuQSMae/WiLzidZRvJAK6UJHrPgdZpl/6rs=; b=dL5Sbmnoh1fMdFeZyrUBduU/7v/RMbyny/2+QD3kDiVHucYz7jMdF6+74JJ+LlIer0 ks2Mp2INutV5A0FqtEkwVvC7Tq2rqspvdb8aSTg4CEL75QjygF6RmLQGwPOe9gJqizHq VHJyL/baVsOfP44ld+RKC9TWr8tdX9I5Zj2agdWjyPc5KjJcZMXymuOlcYgH2VERXvo8 +gB/UhyfTOravHlxuoT1bT7+8hXB1ArpBej/yfzy/zO/WqVTCLdQ5SbmkqYoBBGsLv5T d8KfkhqYrIIC62QTCL0o8jL1bFm38sv0SnP3LRrxjixzX1XbnaTAWLEjiFIUBPorcvpq SLQA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=QhG6wflr; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. 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The Retire Latency reports the number of elapsed core clocks between the retirement of the instruction indicated by the Instruction Pointer field of the PEBS record and the retirement of the prior instruction. That's quite useful to display the information with perf script. Add a new field retire_lat for the Retire Latency information. Reviewed-by: Andi Kleen Signed-off-by: Kan Liang --- Change since V1 - Rebase on top of 6.2-rc1 tools/perf/builtin-script.c | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/tools/perf/builtin-script.c b/tools/perf/builtin-script.c index 69394ac0a20d..5a783d4ab55e 100644 --- a/tools/perf/builtin-script.c +++ b/tools/perf/builtin-script.c @@ -130,6 +130,7 @@ enum perf_output_field { PERF_OUTPUT_BRSTACKINSNLEN = 1ULL << 36, PERF_OUTPUT_MACHINE_PID = 1ULL << 37, PERF_OUTPUT_VCPU = 1ULL << 38, + PERF_OUTPUT_RETIRE_LAT = 1ULL << 39, }; struct perf_script { @@ -200,6 +201,7 @@ struct output_option { {.str = "brstackinsnlen", .field = PERF_OUTPUT_BRSTACKINSNLEN}, {.str = "machine_pid", .field = PERF_OUTPUT_MACHINE_PID}, {.str = "vcpu", .field = PERF_OUTPUT_VCPU}, + {.str = "retire_lat", .field = PERF_OUTPUT_RETIRE_LAT}, }; enum { @@ -275,7 +277,7 @@ static struct { PERF_OUTPUT_ADDR | PERF_OUTPUT_DATA_SRC | PERF_OUTPUT_WEIGHT | PERF_OUTPUT_PHYS_ADDR | PERF_OUTPUT_DATA_PAGE_SIZE | PERF_OUTPUT_CODE_PAGE_SIZE | - PERF_OUTPUT_INS_LAT, + PERF_OUTPUT_INS_LAT | PERF_OUTPUT_RETIRE_LAT, .invalid_fields = PERF_OUTPUT_TRACE | PERF_OUTPUT_BPF_OUTPUT, }, @@ -542,6 +544,10 @@ static int evsel__check_attr(struct evsel *evsel, struct perf_session *session) evsel__check_stype(evsel, PERF_SAMPLE_WEIGHT_STRUCT, "WEIGHT_STRUCT", PERF_OUTPUT_INS_LAT)) return -EINVAL; + if (PRINT_FIELD(RETIRE_LAT) && + evsel__check_stype(evsel, PERF_SAMPLE_WEIGHT_STRUCT, "WEIGHT_STRUCT", PERF_OUTPUT_RETIRE_LAT)) + return -EINVAL; + return 0; } @@ -2178,6 +2184,9 @@ static void process_event(struct perf_script *script, if (PRINT_FIELD(INS_LAT)) fprintf(fp, "%16" PRIu16, sample->ins_lat); + if (PRINT_FIELD(RETIRE_LAT)) + fprintf(fp, "%16" PRIu16, sample->retire_lat); + if (PRINT_FIELD(IP)) { struct callchain_cursor *cursor = NULL; @@ -3856,7 +3865,7 @@ int cmd_script(int argc, const char **argv) "brstacksym,flags,data_src,weight,bpf-output,brstackinsn," "brstackinsnlen,brstackoff,callindent,insn,insnlen,synth," "phys_addr,metric,misc,srccode,ipc,tod,data_page_size," - "code_page_size,ins_lat", + "code_page_size,ins_lat,retire_lat", parse_output_fields), OPT_BOOLEAN('a', "all-cpus", &system_wide, "system-wide collection from all CPUs"),