From patchwork Wed Jan 4 16:21:34 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Srinivasa Rao Mandadapu X-Patchwork-Id: 38988 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4e01:0:0:0:0:0 with SMTP id p1csp5230125wrt; Wed, 4 Jan 2023 08:24:31 -0800 (PST) X-Google-Smtp-Source: AMrXdXs2g1u8aP3nTC91dxd3hPpmijbxXI6wlaI/DM52vjRRfmN6EOgpncAFiu2z3ZiF7gICkqyg X-Received: by 2002:a05:6402:3983:b0:475:c640:ddd2 with SMTP id fk3-20020a056402398300b00475c640ddd2mr44513879edb.26.1672849471495; Wed, 04 Jan 2023 08:24:31 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1672849471; cv=none; d=google.com; s=arc-20160816; b=rvm/itPXy9jCDLJP+puOVqWEPAoh6jCkbNG27DQVkCRDec8kh4CnSlxX2BR4KLNrFM lqorwjmT8l3MrNxN8yWOIl7ffbsGJwjPy3rUPeXiSltMLYzoJZTQQodshEL4TxXF/djc 7EytGkMwCQ9LezbRwm8RIVPIXOOsxSvOMV7c+m97ewv0fYvP4YcpzCFvkCGIRtEbO+4k 8nbh89yIn0Xdzmi2s9nSFmLliGLM05xR9CUf1z0elhI3l3+SfMhY916dKD9ADlTsUWYu e/t/i45C/S134sUha5Xkcgl7aEw/RzPC2YJrshmwI+ve6/lke3q4PnJ4DgyBT1aXFV7b f9pg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=qVxLVNi1vjauSf0iGsvDfnimrpo5LpqH79zwOIt7/GY=; b=TBBYJidmxsxG8wZUpm1QedCszmWBdaHjmNIeR277z5ImRnA/6vzGbyPv1OmrnjVVPH x8gFmmWhHq1kpfJ/7sO4THjD7MICQq36wox6RC5u5Xv6BZJEg/Fp3nIl62fOoL3ZODKO 5TO7v3kF5XSLqCQbWlcVLmVMmWw8uXrzau4eR2p96BRqtL83WjEgLcNRpYorYeYZ2pId VGw6ln95NH4082/0fvfVAmqiv2RwUkqvXGYtOqEQ4gtBoHGRchWGtsaTpdIokas/kdsd 2r63XOsD1zCTtbyPRpJbe7L4dlKxw6j/1VtbLvlrq1Os990DDgwNFeO/4X4IL4u7pyq3 Ky9Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=iffvpJ2u; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id f8-20020a0564021e8800b004819219f5fasi14976866edf.152.2023.01.04.08.24.07; Wed, 04 Jan 2023 08:24:31 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=iffvpJ2u; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239727AbjADQXB (ORCPT + 99 others); Wed, 4 Jan 2023 11:23:01 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45732 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235253AbjADQWQ (ORCPT ); Wed, 4 Jan 2023 11:22:16 -0500 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3552F4085C; Wed, 4 Jan 2023 08:22:15 -0800 (PST) Received: from pps.filterd (m0279868.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 304G257B031845; Wed, 4 Jan 2023 16:22:08 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=qcppdkim1; bh=qVxLVNi1vjauSf0iGsvDfnimrpo5LpqH79zwOIt7/GY=; b=iffvpJ2u8YNT5awhj1uWrUlYld6nsHfpX4UzCIBEF/HZ0NMOm9BRt7O+8uw+4/HVzxB6 dB6hlpdHDkSKoKTAeCEMbN75/W6hfj03z6XHIdwJH8j3dy1MNbcwwKr41THAQBhB/q/g XRJHnqprDyXVHNv09R/5VyaGTn5ht3YCA7AbF1wkL/+K0CDTDecBWj+ef7dkrM6eHAAR QYo2fXEXYkhCWAHOLi11lWpo0PdDRva7r7xKWg3XHhT/9Wpame1XmXk++OmgFL/H4RVw e5RD/jACxiNTE7Pf4WtEAyg06/SCeDLgD2mxz+/U/la22d6/T8aQxuS1DsMEXeTsPRUh sw== Received: from nalasppmta02.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3mvsvxta5f-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 04 Jan 2023 16:22:08 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA02.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 304GM7Iw027208 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 4 Jan 2023 16:22:07 GMT Received: from hu-srivasam-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.36; Wed, 4 Jan 2023 08:22:02 -0800 From: Srinivasa Rao Mandadapu To: , , , , , , , , , , , , , CC: Srinivasa Rao Mandadapu Subject: [RESEND v3 1/4] dt-bindings: clock: qcom,sc7280-lpasscc: Add qcom,adsp-pil-mode property Date: Wed, 4 Jan 2023 21:51:34 +0530 Message-ID: <1672849297-3116-2-git-send-email-quic_srivasam@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1672849297-3116-1-git-send-email-quic_srivasam@quicinc.com> References: <1672849297-3116-1-git-send-email-quic_srivasam@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: V9aOv9mUu05jz2SxJs-E47ocJkf71tZp X-Proofpoint-GUID: V9aOv9mUu05jz2SxJs-E47ocJkf71tZp X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.923,Hydra:6.0.545,FMLib:17.11.122.1 definitions=2023-01-04_07,2023-01-04_02,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=32 bulkscore=0 suspectscore=0 malwarescore=0 impostorscore=0 lowpriorityscore=0 clxscore=1015 priorityscore=1501 spamscore=0 mlxlogscore=999 phishscore=0 mlxscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2212070000 definitions=main-2301040136 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1754109807368067617?= X-GMAIL-MSGID: =?utf-8?q?1754109807368067617?= When this property is set, the remoteproc is used to boot the LPASS and therefore qdsp6ss clocks would be used to bring LPASS out of reset, hence they are directly controlled by the remoteproc. This is a cleanup done to handle overlap of regmap of lpasscc and adsp remoteproc blocks. Signed-off-by: Srinivasa Rao Mandadapu Tested-by: Mohammad Rafi Shaik Reviewed-by: Krzysztof Kozlowski Reviewed-by: Stephen Boyd --- Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscc.yaml | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscc.yaml b/Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscc.yaml index 6151fde..97c6bd9 100644 --- a/Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscc.yaml @@ -41,6 +41,12 @@ properties: - const: qdsp6ss - const: top_cc + qcom,adsp-pil-mode: + description: + Indicates if the LPASS would be brought out of reset using + remoteproc peripheral loader. + type: boolean + required: - compatible - reg @@ -60,6 +66,7 @@ examples: reg-names = "qdsp6ss", "top_cc"; clocks = <&gcc GCC_CFG_NOC_LPASS_CLK>; clock-names = "iface"; + qcom,adsp-pil-mode; #clock-cells = <1>; }; ... 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Signed-off-by: Srinivasa Rao Mandadapu Tested-by: Mohammad Rafi Shaik Reviewed-by: Krzysztof Kozlowski --- .../devicetree/bindings/clock/qcom,sc7280-lpasscc.yaml | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscc.yaml b/Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscc.yaml index 97c6bd9..054c496 100644 --- a/Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscc.yaml @@ -31,15 +31,20 @@ properties: '#clock-cells': const: 1 + '#reset-cells': + const: 1 + reg: items: - description: LPASS qdsp6ss register - description: LPASS top-cc register + - description: LPASS reset-cgcr register reg-names: items: - const: qdsp6ss - const: top_cc + - const: reset_cgcr qcom,adsp-pil-mode: description: @@ -62,11 +67,14 @@ examples: #include clock-controller@3000000 { compatible = "qcom,sc7280-lpasscc"; - reg = <0x03000000 0x40>, <0x03c04000 0x4>; - reg-names = "qdsp6ss", "top_cc"; + reg = <0x03000000 0x40>, + <0x03c04000 0x4>, + <0x032a9000 0x1000>; + reg-names = "qdsp6ss", "top_cc", "reset_cgcr"; clocks = <&gcc GCC_CFG_NOC_LPASS_CLK>; clock-names = "iface"; qcom,adsp-pil-mode; #clock-cells = <1>; + #reset-cells = <1>; }; ... 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As the qdsp6ss clocks are being enabled in remoteproc driver, skip qdsp6ss clock registration if "qcom,adsp-pil-mode" is enabled. Fixes: 4ab43d171181 ("clk: qcom: Add lpass clock controller driver for SC7280") Signed-off-by: Srinivasa Rao Mandadapu Tested-by: Mohammad Rafi Shaik Reviewed-by: Stephen Boyd --- drivers/clk/qcom/lpasscc-sc7280.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/drivers/clk/qcom/lpasscc-sc7280.c b/drivers/clk/qcom/lpasscc-sc7280.c index 5c1e17b..85dd5b9 100644 --- a/drivers/clk/qcom/lpasscc-sc7280.c +++ b/drivers/clk/qcom/lpasscc-sc7280.c @@ -118,12 +118,14 @@ static int lpass_cc_sc7280_probe(struct platform_device *pdev) goto destroy_pm_clk; } - lpass_regmap_config.name = "qdsp6ss"; - desc = &lpass_qdsp6ss_sc7280_desc; + if (!of_property_read_bool(pdev->dev.of_node, "qcom,adsp-pil-mode")) { + lpass_regmap_config.name = "qdsp6ss"; + desc = &lpass_qdsp6ss_sc7280_desc; - ret = qcom_cc_probe_by_index(pdev, 0, desc); - if (ret) - goto destroy_pm_clk; + ret = qcom_cc_probe_by_index(pdev, 0, desc); + if (ret) + goto destroy_pm_clk; + } lpass_regmap_config.name = "top_cc"; desc = &lpass_cc_top_sc7280_desc; From patchwork Wed Jan 4 16:21:37 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Srinivasa Rao Mandadapu X-Patchwork-Id: 38986 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4e01:0:0:0:0:0 with SMTP id p1csp5229870wrt; Wed, 4 Jan 2023 08:23:57 -0800 (PST) X-Google-Smtp-Source: AMrXdXuXPzK8Ije+0MtF1t5ryUniq1MIxCiYpJlASvmcXLfNZy+KjQ6lTWGfDnfofAFdSOZfPkw2 X-Received: by 2002:a17:907:8d17:b0:7c1:1ada:5e1e with SMTP id tc23-20020a1709078d1700b007c11ada5e1emr39179224ejc.26.1672849437102; Wed, 04 Jan 2023 08:23:57 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1672849437; cv=none; d=google.com; s=arc-20160816; b=kwwHyhWQ1FVXIwpqNxmCNZ17kPffJaqOHZywxsQEXSIFhEYSpFgJg1lORbO/ViNJ22 y+HTY0hAxvPma3wsMX6b23/8XRF+TFatXbcmu8EbHq67u3Rg9ttzYVMu0mn3NveR5BUg Fotrnr/dYmqy0BZSQ4M5HivRTBw3jvSN9ncvVfS0MkKWcuNWkusqzmAZKTnI735lcAJr iQE7ykAiuaYTznUH2JzricI9vEnTcD+cOF1Bd8G8L0+CyCHWQIF3XMGDPxrUOqblhSNR 15R1jVtjb4DHPoBMQT6rJu3EcxJs2lSoQ8LXN5u76vwvVAphM8/RPSzTm9hM8j6x0lAR 8Q/A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=3KPGEp3I4+Jctna2PAD8ox70bJxxOEzVkwc5+X1wK+Q=; b=hhXLlVUK2RWcqCwKfvSafRBdKy+qzu/W9YlGBct/O73HBTNTSJdJXTdjjHFKoBGzAw tW0NNwLD0ueh4Ym2sd0ZlNx63O6XU3/qPqzpmDOwWqv3OuhRq4xG3tjzPlXbFX2UopZl guXh3ceh4Ap+jd/zu3iX/VpLjbpmBlb5FMXwoI3tJggOsvbWCl1ZCY1py5PvGda2Yevr rN+ZgefFSXrCPAgI2UwK1W8FLV+lO4JJm2/KA0vjaST3yxDJiNsIWm8caZhgmpURfSGC KOO5jMePfUrYYjM1P/NHsxRv/rauasHa7DsBqHrQObq8miB8OF0HM1az4i90y3kvNOUm IfkQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=MmEcmYe+; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from out1.vger.email (out1.vger.email. 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Thus add the support for the reset clocks in audioreach based clock driver. Signed-off-by: Srinivasa Rao Mandadapu Tested-by: Mohammad Rafi Shaik --- drivers/clk/qcom/lpasscc-sc7280.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/drivers/clk/qcom/lpasscc-sc7280.c b/drivers/clk/qcom/lpasscc-sc7280.c index 85dd5b9..1efb72d 100644 --- a/drivers/clk/qcom/lpasscc-sc7280.c +++ b/drivers/clk/qcom/lpasscc-sc7280.c @@ -12,10 +12,12 @@ #include #include +#include #include "clk-regmap.h" #include "clk-branch.h" #include "common.h" +#include "reset.h" static struct clk_branch lpass_top_cc_lpi_q6_axim_hs_clk = { .halt_reg = 0x0, @@ -102,6 +104,18 @@ static const struct qcom_cc_desc lpass_qdsp6ss_sc7280_desc = { .num_clks = ARRAY_SIZE(lpass_qdsp6ss_sc7280_clocks), }; +static const struct qcom_reset_map lpass_cc_sc7280_resets[] = { + [LPASS_AUDIO_SWR_RX_CGCR] = { 0xa0, 1 }, + [LPASS_AUDIO_SWR_TX_CGCR] = { 0xa8, 1 }, + [LPASS_AUDIO_SWR_WSA_CGCR] = { 0xb0, 1 }, +}; + +static const struct qcom_cc_desc lpass_audio_cc_reset_sc7280_desc = { + .config = &lpass_regmap_config, + .resets = lpass_cc_sc7280_resets, + .num_resets = ARRAY_SIZE(lpass_cc_sc7280_resets), +}; + static int lpass_cc_sc7280_probe(struct platform_device *pdev) { const struct qcom_cc_desc *desc; @@ -134,6 +148,15 @@ static int lpass_cc_sc7280_probe(struct platform_device *pdev) if (ret) goto destroy_pm_clk; + if (of_property_read_bool(pdev->dev.of_node, "qcom,adsp-pil-mode")) { + lpass_regmap_config.name = "reset_cgcr"; + desc = &lpass_audio_cc_reset_sc7280_desc; + + ret = qcom_cc_probe_by_index(pdev, 2, desc); + if (ret) + goto destroy_pm_clk; + } + return 0; destroy_pm_clk: