From patchwork Mon Oct 10 08:20:38 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Srinath Parvathaneni X-Patchwork-Id: 1853 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4ac7:0:0:0:0:0 with SMTP id y7csp1465890wrs; Mon, 10 Oct 2022 01:21:55 -0700 (PDT) X-Google-Smtp-Source: AMsMyM5NNYdV7/tHxcg1R3GIX544Fl9JzTx1oyoCCOuCK84K5gCVypCCQkzihh1HRB1zLIeNNaWR X-Received: by 2002:aa7:cb18:0:b0:452:9071:aff with SMTP id s24-20020aa7cb18000000b0045290710affmr16706634edt.194.1665390115478; Mon, 10 Oct 2022 01:21:55 -0700 (PDT) Received: from sourceware.org (ip-8-43-85-97.sourceware.org. [8.43.85.97]) by mx.google.com with ESMTPS id d14-20020a50fb0e000000b004587e99bcc2si8291847edq.383.2022.10.10.01.21.55 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Oct 2022 01:21:55 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=hXqiU3c5; arc=fail (signature failed); spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 2FAD2385803D for ; Mon, 10 Oct 2022 08:21:54 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 2FAD2385803D DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1665390114; bh=V6euIDC+plmTgA5LXoFB3LakpbyFKA/Ehq/LnGAJb9w=; h=To:Subject:Date:List-Id:List-Unsubscribe:List-Archive:List-Post: List-Help:List-Subscribe:From:Reply-To:Cc:From; b=hXqiU3c5Soc0Kqqszkypj3y2fDoqq6CqDObGHT9wQhjHiJgKKWZhUiCiVp8VU8SOR Ip1KVPaXD2cIjY5G5oB4R7iz7BqombpftUY9+rbMXDeaXcOB1mioTd9wLp8YyFONfQ FXiY44cBnrszvsyXVUGq2NBgTFBedl0exgKAQLzg= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from EUR04-HE1-obe.outbound.protection.outlook.com (mail-eopbgr70074.outbound.protection.outlook.com [40.107.7.74]) by sourceware.org (Postfix) with ESMTPS id 5D7803858D37 for ; Mon, 10 Oct 2022 08:20:58 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 5D7803858D37 ARC-Seal: i=2; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=pass; b=RrRDRM8jvj/YcMCb/30MMn9cysg0Xg5dPyxhpNNO5WUDPHnKajGiqHII0bG7/xKa50lq6viNjLE50F/1LcyhKXkEhEt7VYeeSElQHPzYgZJl556P3MOCzvLeAk9pr7B49FDwvDcVhOuUrrF+K8SpEBhVin68CMcAr2XauAapx0ZEoxPBb8wN98Mr5sCAgmr6WzyZqC8bC5TCXz8Y5nxQMXE4eT0nUzmK//NakO+TK5+ZpUUo73oNMnUSyW7hKKoyUfTAjoXQXCc8hY6ihSAbh3lOgD0w22eQakjwT8GBp+leIHcfai92uhgNEFcq70k39w7KAuXTGHWvGSjH1oLHrg== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=V6euIDC+plmTgA5LXoFB3LakpbyFKA/Ehq/LnGAJb9w=; b=Q5P86L1FlJg2f2RM69CaDf+1iuIT9zNA0id4k8Y/+RLt0wHUvrss3DluYhaZp/zDsD+tQMpvFk3k4fKCZaokaUyGpC8oORjL2KPNeqV09oDQe3YXlkiElwoXwbrQBlkeEqyVMNoV+UZTZgMPu1ThCv17KOZE0ICxwOrw0O+EknHYFJgCeANOnqdabfVBny1nXwvpLYudX5XSeRkmMy5oxGkBWlAEh7AML4aFYUnBpFWWZWYss6v+Vk1aoLl96UXWlMkqS6mEC9kdgOJu+nJRspbMaNJzK3EML23pIRxWC/yWcujGnDqkWb5Tluy3yxF6pisZPUQWilBRzHlNWhXX4Q== ARC-Authentication-Results: i=2; mx.microsoft.com 1; spf=pass (sender ip is 63.35.35.123) smtp.rcpttodomain=gcc.gnu.org smtp.mailfrom=arm.com; dmarc=pass (p=none sp=none pct=100) action=none header.from=arm.com; dkim=pass (signature was verified) header.d=armh.onmicrosoft.com; arc=pass (0 oda=1 ltdi=1 spf=[1,1,smtp.mailfrom=arm.com] dmarc=[1,1,header.from=arm.com]) Received: from AS9PR06CA0472.eurprd06.prod.outlook.com (2603:10a6:20b:49a::21) by PA4PR08MB7457.eurprd08.prod.outlook.com (2603:10a6:102:2a4::8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5709.15; Mon, 10 Oct 2022 08:20:52 +0000 Received: from AM7EUR03FT062.eop-EUR03.prod.protection.outlook.com (2603:10a6:20b:49a:cafe::ec) by AS9PR06CA0472.outlook.office365.com (2603:10a6:20b:49a::21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5709.15 via Frontend Transport; Mon, 10 Oct 2022 08:20:52 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 63.35.35.123) smtp.mailfrom=arm.com; dkim=pass (signature was verified) header.d=armh.onmicrosoft.com;dmarc=pass action=none header.from=arm.com; Received-SPF: Pass (protection.outlook.com: domain of arm.com designates 63.35.35.123 as permitted sender) receiver=protection.outlook.com; client-ip=63.35.35.123; helo=64aa7808-outbound-1.mta.getcheckrecipient.com; pr=C Received: from 64aa7808-outbound-1.mta.getcheckrecipient.com (63.35.35.123) by AM7EUR03FT062.mail.protection.outlook.com (100.127.140.99) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5709.10 via Frontend Transport; Mon, 10 Oct 2022 08:20:52 +0000 Received: ("Tessian outbound c2c2da38ad67:v128"); Mon, 10 Oct 2022 08:20:52 +0000 X-CheckRecipientChecked: true X-CR-MTA-CID: 1a9fb39fb14af5f8 X-CR-MTA-TID: 64aa7808 Received: from f2682162bf96.1 by 64aa7808-outbound-1.mta.getcheckrecipient.com id 14145291-8CB8-49C3-9415-669DFD28FEED.1; Mon, 10 Oct 2022 08:20:44 +0000 Received: from EUR05-VI1-obe.outbound.protection.outlook.com by 64aa7808-outbound-1.mta.getcheckrecipient.com with ESMTPS id f2682162bf96.1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384); Mon, 10 Oct 2022 08:20:44 +0000 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=Z98t4U0svLNvq9VOWBIYuXD79j3dQ7t7bll0hsvv2R01monSC8sGH2Fi40jhX5P2XeSNRgw8chmGNE81BJSopuFxBqXze7FAbalGwwBqMjQoAc1YC0y8kAIrFdHztBK/WJ8AOV8V4OPpWJOd8eeWgBP9zBLiWw8Zm5+5oPDvHich4fiGzzamzh9m79pxb4qkvwl56Jlf5XOvXgZWCqAUIdBIzsyOFKjhhIRGZF4rmbugFvAD6UIiUTR4CRc/iYT7MBre/v3m/c6tUllD48Nz0swog2rhkUWSA913eJzK+NyXsPN7mPBiFzSltjjcxpCB4Ftd5VnPQwhar9zSA1ui1A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=V6euIDC+plmTgA5LXoFB3LakpbyFKA/Ehq/LnGAJb9w=; b=oM2KxBSXkHJOVTO+gjvtpu1JaRi/HdYvcFvISTG+hzvxo1MPeqhQAD2Z2mIrY3torsCGR+oYdQ6bJegZkRDfHEtm+cjzUOMvV6mMaEJnWZDxu1orUXbV02+4kI1aFAW6LlR3fLzuVNc/H9s4nRU/J+rYuQGlMu11Qj8WvYRadZ24O74hVYmedtALZ3HV2UvKxyZaV60vqjcEcW7h7zVAt2ZmXeDjunAyLGPH1M3euqjkE84lmnKyDHfDa1nAA8vzoQX0jWaoG4BCWv0HkD85v7H13RgpTCUvXZWC2Ar6Buj5mTJUflJsQQDAHk0gn3Qo6Q4m4o2SISo41dsl4a1dUg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 40.67.248.234) smtp.rcpttodomain=gcc.gnu.org smtp.mailfrom=arm.com; dmarc=pass (p=none sp=none pct=100) action=none header.from=arm.com; dkim=none (message not signed); arc=none Received: from AM6P191CA0053.EURP191.PROD.OUTLOOK.COM (2603:10a6:209:7f::30) by PA4PR08MB6045.eurprd08.prod.outlook.com (2603:10a6:102:ef::10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5676.28; Mon, 10 Oct 2022 08:20:40 +0000 Received: from AM7EUR03FT025.eop-EUR03.prod.protection.outlook.com (2603:10a6:209:7f:cafe::bd) by AM6P191CA0053.outlook.office365.com (2603:10a6:209:7f::30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5709.15 via Frontend Transport; Mon, 10 Oct 2022 08:20:39 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 40.67.248.234) smtp.mailfrom=arm.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=arm.com; Received-SPF: Pass (protection.outlook.com: domain of arm.com designates 40.67.248.234 as permitted sender) receiver=protection.outlook.com; client-ip=40.67.248.234; helo=nebula.arm.com; pr=C Received: from nebula.arm.com (40.67.248.234) by AM7EUR03FT025.mail.protection.outlook.com (100.127.140.199) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.5709.10 via Frontend Transport; Mon, 10 Oct 2022 08:20:39 +0000 Received: from AZ-NEU-EX04.Arm.com (10.251.24.32) by AZ-NEU-EX03.Arm.com (10.251.24.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Mon, 10 Oct 2022 08:20:39 +0000 Received: from e120703.arm.com (10.2.81.20) by mail.arm.com (10.251.24.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12 via Frontend Transport; Mon, 10 Oct 2022 08:20:39 +0000 MIME-Version: 1.0 To: Subject: [GCC][PATCH] arm: Add cde feature support for Cortex-M55 CPU. Date: Mon, 10 Oct 2022 09:20:38 +0100 Message-ID: X-EOPAttributedMessage: 1 X-MS-TrafficTypeDiagnostic: AM7EUR03FT025:EE_|PA4PR08MB6045:EE_|AM7EUR03FT062:EE_|PA4PR08MB7457:EE_ X-MS-Office365-Filtering-Correlation-Id: f7623a1d-6891-462c-beb6-08daaa9858c0 x-checkrecipientrouted: true NoDisclaimer: true X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Untrusted: BCL:0; X-Microsoft-Antispam-Message-Info-Original: TZY8VlDs5QsfcbZqZqie9GVldKVoqljbLC0/e/SAh0P+sAOtmrXK5nqRbet7rm/v31av5Q8V3V43inPqjyXoO4Ah3rRp4yhZMSUX8Y4x3r1mBQLLHtmFzQhFtLCXgPsDy5hCeC++olrhXDS35zNlNFdDDbHJD2dwpCoeNMi8kYaEJWHPH3ge2CtNxf8OQ/9HvcSLux85UwcVzvkmIxagMifwgVbd2JHSb8ynQ3J37bLHYxEmKtM11gPWlcR+iqLANbyAzqJkq63hrta0PESOdx9vC5JHOzMsqw0l34f/2cl0Mh/1pjY6UpDwE7l8vdbHE59eKwwluklDns6Hoxd+Qrm7dXbLWSngAMtzuAArzZlS8p/HSCkT6nCBzQ2oIm2Fo6AxO8ARoIaGW9oslHzstocq77uo+OsQBUCA16nEwNtEEOSIBql0YfOG0+yq27YcBWimhodOoyjLEz8AbDr4BOqiwPOGxG4cMpcg9GY4JaFBNHBObrwILNx8foresf/3ksFOco4xSK+uLxNTHSWsYh0Am9SHPLz/HMeDgX40Psw5k1USMdXaLsz8T8o6dog92ZB1WnGtDHSvu7n4bp3EPvh7wBisas1QmLWA8ESxtVRIjl5xmGi9cCsz2r7ffz5/tp5+lIEwU3Ixz6PhCF5vQfzMB/6U2wQCXW8vHzUjs/Vy2dqPd10zP2Bq0k5Xm5ti0/Q0tr4A4sob3Qnl/izcVQjUdakzC/VicVFpCmrnCjnm1egaTInCfrpvsTyEf1B11j/mKB4AezIMCbUMsj4N/nUhPuCzjaXfkwhDNxJzvBLylybYDtWBKNpAlKJ5Q1DJawvJPjuiAtRI4tlI3kN3mctVplHG+wWfDsnUWLTSeqUuN99BgGwtAsKYEKxKM6qu X-Forefront-Antispam-Report-Untrusted: CIP:40.67.248.234; CTRY:IE; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:nebula.arm.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230022)(4636009)(376002)(136003)(39860400002)(346002)(396003)(451199015)(36840700001)(40470700004)(46966006)(31686004)(186003)(336012)(26005)(82310400005)(70206006)(70586007)(2906002)(31696002)(86362001)(8676002)(4326008)(5660300002)(235185007)(33964004)(316002)(40480700001)(36860700001)(966005)(478600001)(84970400001)(356005)(44832011)(54906003)(47076005)(426003)(41300700001)(8936002)(6916009)(82740400003)(40460700003)(81166007)(36900700001); DIR:OUT; SFP:1101; X-MS-Exchange-Transport-CrossTenantHeadersStamped: PA4PR08MB6045 X-MS-Exchange-Transport-CrossTenantHeadersStripped: AM7EUR03FT062.eop-EUR03.prod.protection.outlook.com X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id-Prvs: 473d3458-cc6b-45f1-50aa-08daaa98510d X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: W+byQVGikh7h9eXmnrUbzgJxcnhdxITHGfO51OMQMOOeZgcNGdIp22Yc+T4lu8sQ7344tw1I+7uVkfDUqWMa9/YgBauCvDIK5OoPCsWeZmmWiIfcT+h8v9Pch1cxaTHiDsIIwz2ZTkX5faMhyAXhTn8aUHIr1iw9qKn30UZXubNfxWK/DQdK3e7+56G9VAbz51qyVKOZk+wr13T1AO7IH+N8LHg3c0beHEUhe0D4WLcOwAqBvmug6GMH0iHJWzEG8QzWzULyXEkjd8pkSsPHXKk6AUIwzgIloGszoajtR+zAMYNa5zGovQEvpH1yOfLBvzUdWIYDFbzhL+7i+PDzj1iDnUObTkiTfzMFuquADTScI6YXESahLRAOIlRzo+OdEN434AxQGAXq5pei5aE2nW1xWhF7jyEV9866+jgmmKvcPZBX+UsN/D6nmwYEQT3MwGhGtdT8wZDft6t02HdhSlTObdgCYrPJh5l+S9VSSd+dCKgT9JHmJquMJ6lUVSgK+JkfPFVEUQM0N71aztm3xalSyhJ9Y0kQBGgWUGQWld2YcdBYyp5+8G0kf7rimLUrdqOPLd6z/FJKv1bvNXDDUTbUp3fhTSRgUcErdcusAY7QbQSBZ7PeHX/JLXHMQMDAixT30bfT1KZA3u/hQMvFMYXOgGKqHO+dfO1SzeRLGz/83koqsuTSwFE3UuoRPOA0QmXU5ftmBe/t+/cOcvwPpXba8WFOq/PIWfM68tR00HbUV+6UvmHHsBW/p4g4wpDvQdzMlTko7lDyszNyEEkkCjBbM5c30NQqMN2IJGgbFtrsGHiYU4fA/U/6e+w4gimi8P4HSbLaS/6F1bHI6fABtQ== X-Forefront-Antispam-Report: CIP:63.35.35.123; CTRY:IE; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:64aa7808-outbound-1.mta.getcheckrecipient.com; PTR:ec2-63-35-35-123.eu-west-1.compute.amazonaws.com; CAT:NONE; SFS:(13230022)(4636009)(136003)(376002)(346002)(396003)(39860400002)(451199015)(46966006)(36840700001)(40470700004)(316002)(86362001)(82310400005)(31696002)(70586007)(36860700001)(44832011)(6916009)(54906003)(70206006)(2906002)(8936002)(47076005)(235185007)(4326008)(41300700001)(40480700001)(5660300002)(40460700003)(426003)(336012)(186003)(82740400003)(478600001)(966005)(8676002)(81166007)(33964004)(26005)(31686004)(84970400001); DIR:OUT; SFP:1101; X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Oct 2022 08:20:52.6342 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f7623a1d-6891-462c-beb6-08daaa9858c0 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d; Ip=[63.35.35.123]; Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: AM7EUR03FT062.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PA4PR08MB7457 X-Spam-Status: No, score=-13.1 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, FORGED_SPF_HELO, GIT_PATCH_0, KAM_DMARC_NONE, KAM_LOTSOFHASH, KAM_SHORT, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_NONE, TXREP, UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Srinath Parvathaneni via Gcc-patches From: Srinath Parvathaneni Reply-To: Srinath Parvathaneni Cc: richard.earnshaw@arm.com Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1746288105983861166?= X-GMAIL-MSGID: =?utf-8?q?1746288105983861166?= Hi, This patch adds cde feature (optional) support for Cortex-M55 CPU, please refer [1] for more details. To use this feature we need to specify +cdecpN (e.g. -mcpu=cortex-m55+cdecp), where N is the coprocessor number 0 to 7. Bootstrapped for arm-none-linux-gnueabihf target, regression tested on arm-none-eabi target and found no regressions. [1] https://developer.arm.com/documentation/101051/0101/?lang=en (version: r1p1). Ok for master? Regards, Srinath. gcc/ChangeLog: 2022-10-07 Srinath Parvathaneni * common/config/arm/arm-common.cc (arm_canon_arch_option_1): Ignore cde options for mlibarch. * config/arm/arm-cpus.in (begin cpu cortex-m55): Add cde options. * doc/invoke.texi (CDE): Document options for Cortex-M55 CPU. gcc/testsuite/ChangeLog: 2022-10-07 Srinath Parvathaneni * gcc.target/arm/multilib.exp: Add multilib tests for Cortex-M55 CPU. ############### Attachment also inlined for ease of reply ############### diff --git a/gcc/common/config/arm/arm-common.cc b/gcc/common/config/arm/arm-common.cc index c38812f1ea6a690cd19b0dc74d963c4f5ae155ca..b6f955b3c012475f398382e72c9a3966412991ec 100644 --- a/gcc/common/config/arm/arm-common.cc +++ b/gcc/common/config/arm/arm-common.cc @@ -753,6 +753,15 @@ arm_canon_arch_option_1 (int argc, const char **argv, bool arch_for_multilib) arm_initialize_isa (target_isa, selected_cpu->common.isa_bits); arm_parse_option_features (target_isa, &selected_cpu->common, strchr (cpu, '+')); + if (arch_for_multilib) + { + const enum isa_feature removable_bits[] = {ISA_IGNORE_FOR_MULTILIB, + isa_nobit}; + sbitmap isa_bits = sbitmap_alloc (isa_num_bits); + arm_initialize_isa (isa_bits, removable_bits); + bitmap_and_compl (target_isa, target_isa, isa_bits); + } + if (fpu && strcmp (fpu, "auto") != 0) { /* The easiest and safest way to remove the default fpu diff --git a/gcc/config/arm/arm-cpus.in b/gcc/config/arm/arm-cpus.in index 5a63bc548e54dbfdce5d1df425bd615d81895d80..aa02c04c4924662f3ddd58e6967392ba3f4b4a87 100644 --- a/gcc/config/arm/arm-cpus.in +++ b/gcc/config/arm/arm-cpus.in @@ -1633,6 +1633,14 @@ begin cpu cortex-m55 option nomve remove mve mve_float option nofp remove ALL_FP mve_float option nodsp remove MVE mve_float + option cdecp0 add cdecp0 + option cdecp1 add cdecp1 + option cdecp2 add cdecp2 + option cdecp3 add cdecp3 + option cdecp4 add cdecp4 + option cdecp5 add cdecp5 + option cdecp6 add cdecp6 + option cdecp7 add cdecp7 isa quirk_no_asmcpu quirk_vlldm costs v7m vendor 41 diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index aa5655764a0360959f9c1061749d2cc9ebd23489..26857f7a90e42d925bc6908686ac78138a53c4ad 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -21698,6 +21698,10 @@ floating-point instructions on @samp{cortex-m55}. Disable the M-Profile Vector Extension (MVE) single precision floating-point instructions on @samp{cortex-m55}. +@item +cdecp0, +cdecp1, ... , +cdecp7 +Enable the Custom Datapath Extension (CDE) on selected coprocessors according +to the numbers given in the options in the range 0 to 7 on @samp{cortex-m55}. + @item +nofp Disables the floating-point instructions on @samp{arm9e}, @samp{arm946e-s}, @samp{arm966e-s}, @samp{arm968e-s}, @samp{arm10e}, diff --git a/gcc/testsuite/gcc.target/arm/multilib.exp b/gcc/testsuite/gcc.target/arm/multilib.exp index 2fa648c61dafebb663969198bf7849400a7547f6..7a977bff58b7b68bfe9e49d7602989a39caa6534 100644 --- a/gcc/testsuite/gcc.target/arm/multilib.exp +++ b/gcc/testsuite/gcc.target/arm/multilib.exp @@ -851,6 +851,18 @@ if {[multilib_config "rmprofile"] } { {-mcpu=cortex-m55+nomve+nofp -mfpu=auto -mfloat-abi=softfp} "thumb/v8-m.main/nofp" {-mcpu=cortex-m55+nodsp+nofp -mfpu=auto -mfloat-abi=soft} "thumb/v8-m.main/nofp" {-mcpu=cortex-m55+nodsp+nofp -mfpu=auto -mfloat-abi=softfp} "thumb/v8-m.main/nofp" + {-mcpu=cortex-m55 -mfloat-abi=hard -mfpu=auto} "thumb/v8-m.main+dp/hard" + {-mcpu=cortex-m55+cdecp0 -mfloat-abi=hard -mfpu=auto} "thumb/v8-m.main+dp/hard" + {-mcpu=cortex-m55+nomve+cdecp0 -mfloat-abi=hard -mfpu=auto} "thumb/v8-m.main+dp/hard" + {-mcpu=cortex-m55+cdecp0+cdecp1+cdecp2+cdecp3+cdecp4+cdecp5+cdecp6+cdecp7 -mfloat-abi=hard -mfpu=auto} "thumb/v8-m.main+dp/hard" + {-mcpu=cortex-m55 -mfloat-abi=softfp -mfpu=auto} "thumb/v8-m.main+dp/softfp" + {-mcpu=cortex-m55+cdecp0 -mfloat-abi=softfp -mfpu=auto} "thumb/v8-m.main+dp/softfp" + {-mcpu=cortex-m55+nomve+cdecp0 -mfloat-abi=softfp -mfpu=auto} "thumb/v8-m.main+dp/softfp" + {-mcpu=cortex-m55+cdecp0+cdecp1+cdecp2+cdecp3+cdecp4+cdecp5+cdecp6+cdecp7 -mfloat-abi=softfp -mfpu=auto} "thumb/v8-m.main+dp/softfp" + {-mcpu=cortex-m55 -mfloat-abi=soft -mfpu=auto} "thumb/v8-m.main/nofp" + {-mcpu=cortex-m55+cdecp0 -mfloat-abi=soft -mfpu=auto} "thumb/v8-m.main/nofp" + {-mcpu=cortex-m55+nomve+cdecp0 -mfloat-abi=soft -mfpu=auto} "thumb/v8-m.main/nofp" + {-mcpu=cortex-m55+cdecp0+cdecp1+cdecp2+cdecp3+cdecp4+cdecp5+cdecp6+cdecp7 -mfloat-abi=soft -mfpu=auto} "thumb/v8-m.main/nofp" {-march=armv8-m.main+cdecp0 -mfpu=auto -mfloat-abi=soft} "thumb/v8-m.main/nofp" {-march=armv8-m.main+fp+cdecp0 -mfpu=auto -mfloat-abi=soft} "thumb/v8-m.main/nofp" {-march=armv8-m.main+fp.dp+cdecp0 -mfpu=auto -mfloat-abi=soft} "thumb/v8-m.main/nofp" diff --git a/gcc/common/config/arm/arm-common.cc b/gcc/common/config/arm/arm-common.cc index c38812f1ea6a690cd19b0dc74d963c4f5ae155ca..b6f955b3c012475f398382e72c9a3966412991ec 100644 --- a/gcc/common/config/arm/arm-common.cc +++ b/gcc/common/config/arm/arm-common.cc @@ -753,6 +753,15 @@ arm_canon_arch_option_1 (int argc, const char **argv, bool arch_for_multilib) arm_initialize_isa (target_isa, selected_cpu->common.isa_bits); arm_parse_option_features (target_isa, &selected_cpu->common, strchr (cpu, '+')); + if (arch_for_multilib) + { + const enum isa_feature removable_bits[] = {ISA_IGNORE_FOR_MULTILIB, + isa_nobit}; + sbitmap isa_bits = sbitmap_alloc (isa_num_bits); + arm_initialize_isa (isa_bits, removable_bits); + bitmap_and_compl (target_isa, target_isa, isa_bits); + } + if (fpu && strcmp (fpu, "auto") != 0) { /* The easiest and safest way to remove the default fpu diff --git a/gcc/config/arm/arm-cpus.in b/gcc/config/arm/arm-cpus.in index 5a63bc548e54dbfdce5d1df425bd615d81895d80..aa02c04c4924662f3ddd58e6967392ba3f4b4a87 100644 --- a/gcc/config/arm/arm-cpus.in +++ b/gcc/config/arm/arm-cpus.in @@ -1633,6 +1633,14 @@ begin cpu cortex-m55 option nomve remove mve mve_float option nofp remove ALL_FP mve_float option nodsp remove MVE mve_float + option cdecp0 add cdecp0 + option cdecp1 add cdecp1 + option cdecp2 add cdecp2 + option cdecp3 add cdecp3 + option cdecp4 add cdecp4 + option cdecp5 add cdecp5 + option cdecp6 add cdecp6 + option cdecp7 add cdecp7 isa quirk_no_asmcpu quirk_vlldm costs v7m vendor 41 diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index aa5655764a0360959f9c1061749d2cc9ebd23489..26857f7a90e42d925bc6908686ac78138a53c4ad 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -21698,6 +21698,10 @@ floating-point instructions on @samp{cortex-m55}. Disable the M-Profile Vector Extension (MVE) single precision floating-point instructions on @samp{cortex-m55}. +@item +cdecp0, +cdecp1, ... , +cdecp7 +Enable the Custom Datapath Extension (CDE) on selected coprocessors according +to the numbers given in the options in the range 0 to 7 on @samp{cortex-m55}. + @item +nofp Disables the floating-point instructions on @samp{arm9e}, @samp{arm946e-s}, @samp{arm966e-s}, @samp{arm968e-s}, @samp{arm10e}, diff --git a/gcc/testsuite/gcc.target/arm/multilib.exp b/gcc/testsuite/gcc.target/arm/multilib.exp index 2fa648c61dafebb663969198bf7849400a7547f6..7a977bff58b7b68bfe9e49d7602989a39caa6534 100644 --- a/gcc/testsuite/gcc.target/arm/multilib.exp +++ b/gcc/testsuite/gcc.target/arm/multilib.exp @@ -851,6 +851,18 @@ if {[multilib_config "rmprofile"] } { {-mcpu=cortex-m55+nomve+nofp -mfpu=auto -mfloat-abi=softfp} "thumb/v8-m.main/nofp" {-mcpu=cortex-m55+nodsp+nofp -mfpu=auto -mfloat-abi=soft} "thumb/v8-m.main/nofp" {-mcpu=cortex-m55+nodsp+nofp -mfpu=auto -mfloat-abi=softfp} "thumb/v8-m.main/nofp" + {-mcpu=cortex-m55 -mfloat-abi=hard -mfpu=auto} "thumb/v8-m.main+dp/hard" + {-mcpu=cortex-m55+cdecp0 -mfloat-abi=hard -mfpu=auto} "thumb/v8-m.main+dp/hard" + {-mcpu=cortex-m55+nomve+cdecp0 -mfloat-abi=hard -mfpu=auto} "thumb/v8-m.main+dp/hard" + {-mcpu=cortex-m55+cdecp0+cdecp1+cdecp2+cdecp3+cdecp4+cdecp5+cdecp6+cdecp7 -mfloat-abi=hard -mfpu=auto} "thumb/v8-m.main+dp/hard" + {-mcpu=cortex-m55 -mfloat-abi=softfp -mfpu=auto} "thumb/v8-m.main+dp/softfp" + {-mcpu=cortex-m55+cdecp0 -mfloat-abi=softfp -mfpu=auto} "thumb/v8-m.main+dp/softfp" + {-mcpu=cortex-m55+nomve+cdecp0 -mfloat-abi=softfp -mfpu=auto} "thumb/v8-m.main+dp/softfp" + {-mcpu=cortex-m55+cdecp0+cdecp1+cdecp2+cdecp3+cdecp4+cdecp5+cdecp6+cdecp7 -mfloat-abi=softfp -mfpu=auto} "thumb/v8-m.main+dp/softfp" + {-mcpu=cortex-m55 -mfloat-abi=soft -mfpu=auto} "thumb/v8-m.main/nofp" + {-mcpu=cortex-m55+cdecp0 -mfloat-abi=soft -mfpu=auto} "thumb/v8-m.main/nofp" + {-mcpu=cortex-m55+nomve+cdecp0 -mfloat-abi=soft -mfpu=auto} "thumb/v8-m.main/nofp" + {-mcpu=cortex-m55+cdecp0+cdecp1+cdecp2+cdecp3+cdecp4+cdecp5+cdecp6+cdecp7 -mfloat-abi=soft -mfpu=auto} "thumb/v8-m.main/nofp" {-march=armv8-m.main+cdecp0 -mfpu=auto -mfloat-abi=soft} "thumb/v8-m.main/nofp" {-march=armv8-m.main+fp+cdecp0 -mfpu=auto -mfloat-abi=soft} "thumb/v8-m.main/nofp" {-march=armv8-m.main+fp.dp+cdecp0 -mfpu=auto -mfloat-abi=soft} "thumb/v8-m.main/nofp"