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Wed, 4 Jan 2023 09:20:27 GMT Received: from smtpav02.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 5C77A20040; Wed, 4 Jan 2023 09:20:27 +0000 (GMT) Received: from smtpav02.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 93FC520049; Wed, 4 Jan 2023 09:20:25 +0000 (GMT) Received: from [9.200.36.187] (unknown [9.200.36.187]) by smtpav02.fra02v.mail.ibm.com (Postfix) with ESMTP; Wed, 4 Jan 2023 09:20:25 +0000 (GMT) Message-ID: <9defdca0-1cf3-82a3-d04a-2eb4f3daf106@linux.ibm.com> Date: Wed, 4 Jan 2023 17:20:23 +0800 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:91.0) Gecko/20100101 Thunderbird/91.6.1 Content-Language: en-US Subject: [PATCH] rs6000: Make P10_FUSION honour tuning setting To: GCC Patches Cc: Segher Boessenkool , David Edelsohn , Peter Bergner X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: m1jBD4lhL_jeTvxJvDeNFPJ8HExGxoba X-Proofpoint-GUID: QgT1_SVAoRSfKA2sEhVaeYFFq6tUbzKZ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.923,Hydra:6.0.545,FMLib:17.11.122.1 definitions=2023-01-04_04,2023-01-03_02,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 mlxlogscore=738 clxscore=1015 impostorscore=0 lowpriorityscore=0 spamscore=0 adultscore=0 phishscore=0 priorityscore=1501 mlxscore=0 suspectscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2212070000 definitions=main-2301040076 X-Spam-Status: No, score=-11.9 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: "Kewen.Lin via Gcc-patches" From: "Kewen.Lin" Reply-To: "Kewen.Lin" Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1754083228355695483?= X-GMAIL-MSGID: =?utf-8?q?1754083228355695483?= Hi, We noticed this issue when Segher reviewed the patch for PR104024. When there is no explicit setting for option -mpower10-fusion, we enable OPTION_MASK_P10_FUSION for TARGET_POWER10. But it's not right, it should honour tuning setting instead. This patch is to fix it accordingly, it's bootstrapped and regtested on powerpc64-linux-gnu P8 and powerpc64le-linux-gnu P9, but on powerpc64le-linux-gnu P10 it had one regression failure against the test case gcc.target/powerpc/pr105586.c. I looked into it and confirmed a latent bug was exposed and filed one separated bug PR108273 instead. I'm going to push this soon if no objections. BR, Kewen ----- gcc/ChangeLog: * config/rs6000/rs6000.cc (rs6000_option_override_internal): Make OPTION_MASK_P10_FUSION implicit setting honour Power10 tuning setting. * config/rs6000/rs6000-cpus.def (ISA_3_1_MASKS_SERVER): Remove OPTION_MASK_P10_FUSION. --- gcc/config/rs6000/rs6000-cpus.def | 3 +-- gcc/config/rs6000/rs6000.cc | 12 +++++++++--- 2 files changed, 10 insertions(+), 5 deletions(-) -- 2.27.0 diff --git a/gcc/config/rs6000/rs6000-cpus.def b/gcc/config/rs6000/rs6000-cpus.def index c3825bcccd8..4d5544e927a 100644 --- a/gcc/config/rs6000/rs6000-cpus.def +++ b/gcc/config/rs6000/rs6000-cpus.def @@ -84,8 +84,7 @@ #define ISA_3_1_MASKS_SERVER (ISA_3_0_MASKS_SERVER \ | OPTION_MASK_POWER10 \ - | OTHER_POWER10_MASKS \ - | OPTION_MASK_P10_FUSION) + | OTHER_POWER10_MASKS) /* Flags that need to be turned off if -mno-power9-vector. */ #define OTHER_P9_VECTOR_MASKS (OPTION_MASK_FLOAT128_HW \ diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc index 88c865b6b4b..6fa084c0807 100644 --- a/gcc/config/rs6000/rs6000.cc +++ b/gcc/config/rs6000/rs6000.cc @@ -4378,9 +4378,15 @@ rs6000_option_override_internal (bool global_init_p) rs6000_isa_flags &= ~OPTION_MASK_MMA; } - if (TARGET_POWER10 - && (rs6000_isa_flags_explicit & OPTION_MASK_P10_FUSION) == 0) - rs6000_isa_flags |= OPTION_MASK_P10_FUSION; + /* Enable power10 fusion if we are tuning for power10, even if we aren't + generating power10 instructions. */ + if (!(rs6000_isa_flags_explicit & OPTION_MASK_P10_FUSION)) + { + if (processor_target_table[tune_index].processor == PROCESSOR_POWER10) + rs6000_isa_flags |= OPTION_MASK_P10_FUSION; + else + rs6000_isa_flags &= ~OPTION_MASK_P10_FUSION; + } /* MMA requires SIMD support as ISA 3.1 claims and our implementation such as "*movoo" uses vector pair access which use VSX registers.