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Wed, 4 Jan 2023 08:28:20 +0000 (GMT) Message-ID: Date: Wed, 4 Jan 2023 13:58:19 +0530 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:102.0) Gecko/20100101 Thunderbird/102.5.0 Content-Language: en-US To: GCC Patches Cc: Peter Bergner , Segher Boessenkool , meissner@linux.ibm.com Subject: [PATCH] swap: Fix incorrect lane extraction by vec_extract() [PR106770] X-TM-AS-GCONF: 00 X-Proofpoint-GUID: zSa-W_66dJpvjmR7ziOKoobWEGK8XhO4 X-Proofpoint-ORIG-GUID: zSa-W_66dJpvjmR7ziOKoobWEGK8XhO4 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.923,Hydra:6.0.545,FMLib:17.11.122.1 definitions=2023-01-04_04,2023-01-03_02,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 mlxlogscore=927 suspectscore=0 impostorscore=0 phishscore=0 mlxscore=0 clxscore=1011 malwarescore=0 adultscore=0 priorityscore=1501 lowpriorityscore=0 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2212070000 definitions=main-2301040067 X-Spam-Status: No, score=-11.5 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Surya Kumari Jangala via Gcc-patches From: Surya Kumari Jangala Reply-To: Surya Kumari Jangala Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1754079913046883678?= X-GMAIL-MSGID: =?utf-8?q?1754079913046883678?= swap: Fix incorrect lane extraction by vec_extract() [PR106770] In the routine rs6000_analyze_swaps(), special handling of swappable instructions is done even if the webs that contain the swappable instructions are not optimized, i.e., the webs do not contain any permuting load/store instructions along with the associated register swap instructions. Doing special handling in such webs will result in the extracted lane being adjusted unnecessarily for vec_extract. Modifying swappable instructions is also incorrect in webs where loads/stores on quad word aligned addresses are changed to lvx/stvx. Similarly, in webs where swap(load(vector constant)) instructions are replaced with load(swapped vector constant), the swappable instructions should not be modified. 2023-01-04 Surya Kumari Jangala gcc/ PR rtl-optimization/106770 * rs6000-p8swap.cc (rs6000_analyze_swaps): . gcc/testsuite/ PR rtl-optimization/106770 * gcc.target/powerpc/pr106770.c: New test. diff --git a/gcc/config/rs6000/rs6000-p8swap.cc b/gcc/config/rs6000/rs6000-p8swap.cc index 19fbbfb67dc..7ed39251df9 100644 --- a/gcc/config/rs6000/rs6000-p8swap.cc +++ b/gcc/config/rs6000/rs6000-p8swap.cc @@ -179,6 +179,9 @@ class swap_web_entry : public web_entry_base unsigned int special_handling : 4; /* Set if the web represented by this entry cannot be optimized. */ unsigned int web_not_optimizable : 1; + /* Set if the web represented by this entry has been optimized, ie, + register swaps of permuting loads/stores have been removed. */ + unsigned int web_is_optimized : 1; /* Set if this insn should be deleted. */ unsigned int will_delete : 1; }; @@ -2627,22 +2630,43 @@ rs6000_analyze_swaps (function *fun) /* For each load and store in an optimizable web (which implies the loads and stores are permuting), find the associated register swaps and mark them for removal. Due to various - optimizations we may mark the same swap more than once. Also - perform special handling for swappable insns that require it. */ + optimizations we may mark the same swap more than once. Fix up + the non-permuting loads and stores by converting them into + permuting ones. */ for (i = 0; i < e; ++i) if ((insn_entry[i].is_load || insn_entry[i].is_store) && insn_entry[i].is_swap) { swap_web_entry* root_entry = (swap_web_entry*)((&insn_entry[i])->unionfind_root ()); - if (!root_entry->web_not_optimizable) + if (!root_entry->web_not_optimizable) { mark_swaps_for_removal (insn_entry, i); + root_entry->web_is_optimized = true; + } } - else if (insn_entry[i].is_swappable && insn_entry[i].special_handling) + else if (insn_entry[i].is_swappable + && (insn_entry[i].special_handling == SH_NOSWAP_LD || + insn_entry[i].special_handling == SH_NOSWAP_ST)) + { + swap_web_entry* root_entry + = (swap_web_entry*)((&insn_entry[i])->unionfind_root ()); + if (!root_entry->web_not_optimizable) { + handle_special_swappables (insn_entry, i); + root_entry->web_is_optimized = true; + } + } + + /* Perform special handling for swappable insns that require it. + Note that special handling should be done only for those + swappable insns that are present in webs optimized above. */ + for (i = 0; i < e; ++i) + if (insn_entry[i].is_swappable && insn_entry[i].special_handling && + !(insn_entry[i].special_handling == SH_NOSWAP_LD || + insn_entry[i].special_handling == SH_NOSWAP_ST)) { swap_web_entry* root_entry = (swap_web_entry*)((&insn_entry[i])->unionfind_root ()); - if (!root_entry->web_not_optimizable) + if (root_entry->web_is_optimized) handle_special_swappables (insn_entry, i); } diff --git a/gcc/testsuite/gcc.target/powerpc/pr106770.c b/gcc/testsuite/gcc.target/powerpc/pr106770.c new file mode 100644 index 00000000000..84e9aead975 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr106770.c @@ -0,0 +1,20 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target powerpc_p8vector_ok } */ +/* { dg-options "-mdejagnu-cpu=power8 -O3 " } */ +/* { dg-final { scan-assembler-times "xxpermdi" 2 } } */ + +/* Test case to resolve PR106770 */ + +#include + +int cmp2(double a, double b) +{ + vector double va = vec_promote(a, 1); + vector double vb = vec_promote(b, 1); + vector long long vlt = (vector long long)vec_cmplt(va, vb); + vector long long vgt = (vector long long)vec_cmplt(vb, va); + vector signed long long vr = vec_sub(vlt, vgt); + + return vec_extract(vr, 1); +} +