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[2620:137:e000::1:20]) by mx.google.com with ESMTP id gn29-20020a1709070d1d00b007c0dcc62e49si32339381ejc.56.2023.01.03.22.29.40; Tue, 03 Jan 2023 22:30:03 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=Stq26XXZ; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233635AbjADG2B (ORCPT + 99 others); Wed, 4 Jan 2023 01:28:01 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42102 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233239AbjADG1f (ORCPT ); Wed, 4 Jan 2023 01:27:35 -0500 Received: from lelv0143.ext.ti.com (lelv0143.ext.ti.com [198.47.23.248]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id ABD4218E2B; Tue, 3 Jan 2023 22:26:46 -0800 (PST) Received: from lelv0266.itg.ti.com ([10.180.67.225]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id 3046QOIH054824; Wed, 4 Jan 2023 00:26:24 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1672813584; bh=JH3+7om56Hn+Os1YAI02Uac/iNLa0MUdUR9qw1LiMaE=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=Stq26XXZB7DzzkC24qob+ewfNrA/y9zB5IfuzGmBxtxohNFg19VX0qXXgHZGvTbPZ HB6Yg7KJQkiMThxQvn+QynvtxcQhEFHLxTaLTYy9hKYwBNAWWK659EzFUpBID2AA26 sdqKVgU671FKd04mp2iwadtHOD7lqdVqJXyY9OXk= Received: from DFLE111.ent.ti.com (dfle111.ent.ti.com [10.64.6.32]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 3046QOs0104566 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 4 Jan 2023 00:26:24 -0600 Received: from DFLE115.ent.ti.com (10.64.6.36) by DFLE111.ent.ti.com (10.64.6.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16; Wed, 4 Jan 2023 00:26:24 -0600 Received: from fllv0039.itg.ti.com (10.64.41.19) by DFLE115.ent.ti.com (10.64.6.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16 via Frontend Transport; Wed, 4 Jan 2023 00:26:24 -0600 Received: from localhost (ileaxei01-snat.itg.ti.com [10.180.69.5]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 3046QNO0095871; Wed, 4 Jan 2023 00:26:23 -0600 From: Dhruva Gole To: CC: Dhruva Gole , , , Vignesh , Pratyush Yadav , Vaishnav Achath Subject: [PATCH 1/2] spi: cadence-quadspi: setup ADDR Bits in cmd reads Date: Wed, 4 Jan 2023 11:56:03 +0530 Message-ID: <20230104062604.1556763-2-d-gole@ti.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230104062604.1556763-1-d-gole@ti.com> References: <20230104062604.1556763-1-d-gole@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1754072407068119551?= X-GMAIL-MSGID: =?utf-8?q?1754072407068119551?= Setup the Addr bit field while issuing register reads in STIG mode. This is needed for example flashes like cypress define in their transaction table that to read any register there is 1 cmd byte and a few more address bytes trailing the cmd byte. Absence of addr bytes will obviously fail to read correct data from flash register that maybe requested by flash driver because the controller doesn't even specify which address of the flash register the read is being requested from. Signed-off-by: Dhruva Gole --- drivers/spi/spi-cadence-quadspi.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-quadspi.c index 676313e1bdad..8c7938776cfc 100644 --- a/drivers/spi/spi-cadence-quadspi.c +++ b/drivers/spi/spi-cadence-quadspi.c @@ -531,6 +531,17 @@ static int cqspi_command_read(struct cqspi_flash_pdata *f_pdata, /* 0 means 1 byte. */ reg |= (((n_rx - 1) & CQSPI_REG_CMDCTRL_RD_BYTES_MASK) << CQSPI_REG_CMDCTRL_RD_BYTES_LSB); + + /* setup ADDR BIT field */ + if (op->addr.nbytes) { + reg |= (0x1 << CQSPI_REG_CMDCTRL_ADDR_EN_LSB); + reg |= ((op->addr.nbytes - 1) & + CQSPI_REG_CMDCTRL_ADD_BYTES_MASK) + << CQSPI_REG_CMDCTRL_ADD_BYTES_LSB; + + writel(op->addr.val, reg_base + CQSPI_REG_CMDADDRESS); + } + status = cqspi_exec_flash_cmd(cqspi, reg); if (status) return status; From patchwork Wed Jan 4 06:26:04 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dhruva Gole X-Patchwork-Id: 38767 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4e01:0:0:0:0:0 with SMTP id p1csp4998107wrt; Tue, 3 Jan 2023 22:39:05 -0800 (PST) X-Google-Smtp-Source: AMrXdXvBckqIFUc39Yo4bkeYT7d5xXdnYSgS85BmydIz22hQEf4/OeNIplmz7TXhCF8+DTLNJq1R X-Received: by 2002:a17:906:8447:b0:7c4:fa17:7203 with SMTP id e7-20020a170906844700b007c4fa177203mr35794797ejy.63.1672814345610; Tue, 03 Jan 2023 22:39:05 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1672814345; cv=none; d=google.com; s=arc-20160816; b=SmVH7KNUvoLNGv4HayOU99RaCS/PbDsrFgK0E2rricHuy/Zmr+ggnp5eXcKmmhfSkL uYPas0TVe5x0ZbbcHsWk/UXjdFKXEHvO5oGFOSw9XUB5lq2y+MSON8esJ/fY9ijp/vAN zeubhTHF/zaXE04Hyllfs6rhVOH23IVJC7HrgKRfxRwCXkILW9X6LomAQE41Vn6DxorF Vhx09WdL5qGxqF+5hlnlYWBCxcpIP3d6i3hkL9f6dvF+U0AGBpDoPhEplJ21P3A5Y5Cx lnyEOKbggYfoCV0GgQdRvWI1tM0ZvIfhZNrXvAFiijFaLPdQFapUAbGC5UvkKqZfY3le xJpA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=NliV50lmKoUKDsRuaYCtjajFhmQGOUAjwjZaOIj01AY=; b=nUMdmVuAjsQktuQaVDytBr7e04biS09Wauds7F2E98G+17OgJoamBobl8xmYY7A2bf lqbQ1ydH0NaGFPJO8MoM2X6ld0xOj+r/pQr+K3pWZl+LcjgZeqK+P9Xz/sVDDpaE/kM2 IYpWSvGlgVW8KLKvSXB1EC+BVbQghgLNY5IpuMBWicsnuyTckn/jZKM4bmpt0cJtZoK/ c/48a2kdSrfDHrxxyDVdYKe7hd+vrgNFtasjefxI9Ek6gdB/s7heOUwSQ+L/+TSVqjKD b1el+wNuvLiFH7Q9U7pwiFANy31Igkwj0+0M93e8UBjUpdBYWP3cSjW3tnb83Qxc1qDm CtMw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=KtEB5PTl; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: from out1.vger.email (out1.vger.email. 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For example in the TI K3-AM62x Processors refer [0] Technical Reference Manual there is a layer of digital logic in front of the QSPI/OSPI Drive when used in DAC mode. This is part of the Flash Subsystem (FSS) which provides access to external Flash devices. The FSS0_0_SYSCONFIG Register (Offset = 4h) has a BIT Field for OSPI_32B_DISABLE_MODE which has a Reset value = 0. This means, OSPI 32bit mode enabled by default. Thus, by default controller operates in 32 bit mode causing it to always align all data to 4 bytes from a 4byte aligned address. In some flash chips like cypress for example if we try to read some regs in DAC mode then it keeps sending the value of the first register that was requested and inorder to read the next reg, we have to stop and re-initiate a new transaction. This causes wrong register values to be read than what is desired when registers are read in DAC mode. Hence if the data.nbytes is very less then prefer STIG mode for such small reads. [0] https://www.ti.com/lit/ug/spruiv7a/spruiv7a.pdf Signed-off-by: Dhruva Gole --- drivers/spi/spi-cadence-quadspi.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-quadspi.c index 8c7938776cfc..f5188dc52db6 100644 --- a/drivers/spi/spi-cadence-quadspi.c +++ b/drivers/spi/spi-cadence-quadspi.c @@ -1344,7 +1344,13 @@ static int cqspi_mem_process(struct spi_mem *mem, const struct spi_mem_op *op) cqspi_configure(f_pdata, mem->spi->max_speed_hz); if (op->data.dir == SPI_MEM_DATA_IN && op->data.buf.in) { - if (!op->addr.nbytes) + /* + * Performing reads in DAC mode forces to read minimum 4 bytes + * which is unsupported on some flash devices during register + * reads, prefer STIG mode for such small reads. + */ + if (!op->addr.nbytes || + op->data.nbytes <= CQSPI_STIG_DATA_LEN_MAX) return cqspi_command_read(f_pdata, op); return cqspi_read(f_pdata, op);