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[2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id hs12-20020a1709073e8c00b007c10638840asi29171606ejc.75.2023.01.03.21.59.55 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Jan 2023 21:59:55 -0800 (PST) Received-SPF: pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; dkim=pass header.i=@aurel32.net header.s=202004.hall header.b=xW9elJyy; spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id C59A73858C62 for ; Wed, 4 Jan 2023 05:59:53 +0000 (GMT) X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from hall.aurel32.net (hall.aurel32.net [IPv6:2001:bc8:30d7:100::1]) by sourceware.org (Postfix) with ESMTPS id CB13B3858D1E for ; Wed, 4 Jan 2023 05:59:47 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org CB13B3858D1E Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=aurel32.net Authentication-Results: sourceware.org; spf=none smtp.mailfrom=aurel32.net DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=aurel32.net ; s=202004.hall; h=Content-Transfer-Encoding:MIME-Version:Message-Id:Date: Subject:Cc:To:From:Content-Type:From:Reply-To:Subject:Content-ID: Content-Description:In-Reply-To:References:X-Debbugs-Cc; bh=k9ew4Iw5rNKjp1Tc4oRS8b31YjpSJoLj2D20UJM6US0=; b=xW9elJyyAj2qftJLPuzQOlplnS 9jZWSLDwr03/vigkyCyohvvm4wx2gQiRx3in4DUXXdsou7/HVieNWkOIYKPGWDd0hxBj6lbg73jKX asyMHJoKVFcbZ33MTjg1xDmof8/rvT/frTAsOxa2iFBVWuFZf9LxPVdz+dtFRF+1rZyt3TW4GzaWL XPNwltnxWSkPIjIDTtK9Ak3rUPXSmKvrmYsUR4BoJDOHOBN/u1AufQyBtHEKaOwzcNKwPb/C+jpJB +72lPygig/3k2gEXIHuhPMyqBAdpkJwOIiGPN/0vFXGCzxHMJJ1W4Ajfrlw1ljnfQ84Nc+FZ3VdmI MX77rBBw==; Received: from [2a01:e34:ec5d:a741:8a4c:7c4e:dc4c:1787] (helo=ohm.rr44.fr) by hall.aurel32.net with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1pCwoT-00FMqm-J0; Wed, 04 Jan 2023 06:59:45 +0100 Received: from aurel32 by ohm.rr44.fr with local (Exim 4.96) (envelope-from ) id 1pCwoT-004k9F-0a; Wed, 04 Jan 2023 06:59:45 +0100 From: Aurelien Jarno To: binutils@sourceware.org Cc: Jan Beulich , Aurelien Jarno Subject: [PATCH] RISC-V: fix JAL aliases ordering in opcode table Date: Wed, 4 Jan 2023 06:59:36 +0100 Message-Id: <20230104055936.1130680-1-aurelien@aurel32.net> X-Mailer: git-send-email 2.35.1 MIME-Version: 1.0 X-Spam-Status: No, score=-13.4 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, SPF_HELO_PASS, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: binutils-bounces+ouuuleilei=gmail.com@sourceware.org Sender: "Binutils" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1754070510966787661?= X-GMAIL-MSGID: =?utf-8?q?1754070510966787661?= Commit 839189bc932e ("RISC-V: re-arrange opcode table for consistent alias handling") reorder the instructions in the opcode tables, including the various JAL aliases. In particular they are not ordered anymore from the most specific to the less specific one. This causes the form "JAL reg, imm" to emit a relocation with the register name. This breaks various things like building Linux kernel modules. This patch fixes the issue by restoring the original ordering of the JAL aliases. Tested on riscv64-linux PR gas/29940 Bug: https://sourceware.org/bugzilla/show_bug.cgi?id=29940 --- opcodes/riscv-opc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c index 6b65296a3f2..89c6572519e 100644 --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -340,9 +340,9 @@ const struct riscv_opcode riscv_opcodes[] = {"jalr", 0, INSN_CLASS_I, "d,s,j", MATCH_JALR, MASK_JALR, match_opcode, INSN_JSR }, {"j", 0, INSN_CLASS_C, "Ca", MATCH_C_J, MASK_C_J, match_opcode, INSN_ALIAS|INSN_BRANCH }, {"j", 0, INSN_CLASS_I, "a", MATCH_JAL, MASK_JAL|MASK_RD, match_opcode, INSN_ALIAS|INSN_BRANCH }, -{"jal", 0, INSN_CLASS_I, "a", MATCH_JAL|(X_RA << OP_SH_RD), MASK_JAL|MASK_RD, match_opcode, INSN_ALIAS|INSN_JSR }, {"jal", 0, INSN_CLASS_I, "d,a", MATCH_JAL, MASK_JAL, match_opcode, INSN_JSR }, {"jal", 32, INSN_CLASS_C, "Ca", MATCH_C_JAL, MASK_C_JAL, match_opcode, INSN_ALIAS|INSN_JSR }, +{"jal", 0, INSN_CLASS_I, "a", MATCH_JAL|(X_RA << OP_SH_RD), MASK_JAL|MASK_RD, match_opcode, INSN_ALIAS|INSN_JSR }, {"call", 0, INSN_CLASS_I, "d,c", (X_T1 << OP_SH_RS1), (int) M_CALL, match_never, INSN_MACRO }, {"call", 0, INSN_CLASS_I, "c", (X_RA << OP_SH_RS1)|(X_RA << OP_SH_RD), (int) M_CALL, match_never, INSN_MACRO }, {"tail", 0, INSN_CLASS_I, "c", (X_T1 << OP_SH_RS1), (int) M_CALL, match_never, INSN_MACRO },