From patchwork Tue Jan 3 18:02:07 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ashok Raj X-Patchwork-Id: 38573 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4e01:0:0:0:0:0 with SMTP id p1csp4747481wrt; Tue, 3 Jan 2023 10:03:22 -0800 (PST) X-Google-Smtp-Source: AMrXdXsg4HpKsIUOf3nlaCjYppD8Gb8rtiT502YsdAPuOuCAogJHpav3pleElXnXfRKNIZ+G02L/ X-Received: by 2002:a17:906:b7c4:b0:7c0:dac7:36dc with SMTP id fy4-20020a170906b7c400b007c0dac736dcmr43745628ejb.46.1672769002631; Tue, 03 Jan 2023 10:03:22 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1672769002; cv=none; d=google.com; s=arc-20160816; b=fctaulHRnppn9NV1PjGCjpngKgly6RlE7/1jdcgdYOz1e8W2Ncnr+HzKCg7J/bu1nA 1Lgj3wxhWrBOMn92BrDBS1LfEujTwPejEuXY6DdcnXfsupgHl5Kt5oQeCYXLUwHad128 FOrtsj4ZJDLlX/e+a0BPwLiqDB58Tm+aUSwxaYcWn49YMBj4pLAiR6galuR3+lzOcp9I 8kE6osFfT1H2alz8AskPoFl3Udsobd2WJEmwHlg4MR78PIBi7Rdq2TFQoXd275O3SbEV o/LDPWuhKx2kY2Cm4Eq+FJQn/C2DCyEJMZRLdUdWqXSzkc4sNN9A+A+UwrEmWpRWAYFK uAmQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=ZJM19aXzJtMTK9rlZ38A0q9sfEAOAfkNT82A0bdY8wk=; b=t9XQF0OvCd780wrQI28FIzgizxzf00svKw/8WCGQ9U2mh1N6+fZBgzlQYWuPCcBZHP msQgCoEEgZos3ep805L8vIAdS3ddO/KeUGuk74SQdMUFuQRkVE7I/b4oCAmkQ+D2eBTR exErXLwDgL2ei/3wCYD+qo/hcoENPqUIF/byDPrABykwEiRx50IvvCQkx9a8W5KFYhYo avW1WCg/2WQ3uEyRHlkKCKurCLLyf2mj4m1mWBj7EDZRWz7zKVp3KWxkKZcvjauFmoKa IRQlQxp7LuSkCfFvN3uJlPlxI/GBYQgKLl1xT+imrhvtjNbdYA/ukQ0PePLzvp9ZAIfb qBSw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=gS1mBIFd; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id m20-20020a056402431400b0047026e8bb8bsi30015639edc.233.2023.01.03.10.02.57; Tue, 03 Jan 2023 10:03:22 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=gS1mBIFd; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238621AbjACSCj (ORCPT + 99 others); Tue, 3 Jan 2023 13:02:39 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55388 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238421AbjACSC1 (ORCPT ); Tue, 3 Jan 2023 13:02:27 -0500 Received: from mga06.intel.com (mga06b.intel.com [134.134.136.31]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 442C311A27 for ; Tue, 3 Jan 2023 10:02:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1672768944; x=1704304944; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=zSTaTcLJbOegMxQuinD52HPOguvdV7463+YMjh/di6M=; b=gS1mBIFdV+iLsRUbZkPigoJC98vubC4xmYwuZ2LAZqDeEmgKyaKXL+tA jD3ncXCxsVQeEa6F3GSTieLcJMuO52XCjnLk543bi1usHN0qXqeOBtlMZ Fyzu9F2GLpxw8JgRKPArQS+csxo7qBYOXA2jNmsQwcauMAoumASARNs97 2wkTvmETDTjKxa8dm4xFGMdemXzDSuC+9ley+RwixTLdDNyYk9RdKzgb5 CnTTmsbyv7B5d0ou4QyJeImzmiCD9zt5qWE/OSyKmbYX6U1EdHO/cg1Bb FOetxIIU3UHj5rg4a7jx+cFZwhl4Nzgb5dv+U5zIw2F14EQlwZqAsxbEq A==; X-IronPort-AV: E=McAfee;i="6500,9779,10579"; a="384010636" X-IronPort-AV: E=Sophos;i="5.96,297,1665471600"; d="scan'208";a="384010636" Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Jan 2023 10:02:22 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10579"; a="654876879" X-IronPort-AV: E=Sophos;i="5.96,297,1665471600"; d="scan'208";a="654876879" Received: from araj-ucode.jf.intel.com ([10.23.0.19]) by orsmga002-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Jan 2023 10:02:24 -0800 From: Ashok Raj To: Borislav Petkov , Thomas Gleixner Cc: X86-kernel , LKML Mailing List , Ashok Raj , Dave Hansen , Tony Luck , Alison Schofield , Reinette Chatre , Tom Lendacky Subject: [PATCH v3 1/6] x86/microcode: Add a parameter to microcode_check() to store CPU capabilities Date: Tue, 3 Jan 2023 10:02:07 -0800 Message-Id: <20230103180212.333496-2-ashok.raj@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230103180212.333496-1-ashok.raj@intel.com> References: <20230103180212.333496-1-ashok.raj@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1754025429693272936?= X-GMAIL-MSGID: =?utf-8?q?1754025429693272936?= This is a preparation before the next patch uses this to compare CPU capabilities after performing an update. Add a parameter to store CPU capabilities before performing a microcode update. Signed-off-by: Ashok Raj Cc: LKML Cc: x86 Cc: Tony Luck Cc: Dave Hansen Cc: Alison Schofield Cc: Reinette Chatre Cc: Thomas Gleixner Cc: Tom Lendacky --- arch/x86/include/asm/processor.h | 2 +- arch/x86/kernel/cpu/common.c | 12 +++++------- arch/x86/kernel/cpu/microcode/core.c | 3 ++- 3 files changed, 8 insertions(+), 9 deletions(-) diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/processor.h index 4e35c66edeb7..387578049de0 100644 --- a/arch/x86/include/asm/processor.h +++ b/arch/x86/include/asm/processor.h @@ -697,7 +697,7 @@ bool xen_set_default_idle(void); #endif void __noreturn stop_this_cpu(void *dummy); -void microcode_check(void); +void microcode_check(struct cpuinfo_x86 *info); enum l1tf_mitigations { L1TF_MITIGATION_OFF, diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c index 9cfca3d7d0e2..b9c7529c920e 100644 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -2302,25 +2302,23 @@ void cpu_init_secondary(void) * only when microcode has been updated. Caller holds microcode_mutex and CPU * hotplug lock. */ -void microcode_check(void) +void microcode_check(struct cpuinfo_x86 *info) { - struct cpuinfo_x86 info; - perf_check_microcode(); /* Reload CPUID max function as it might've changed. */ - info.cpuid_level = cpuid_eax(0); + info->cpuid_level = cpuid_eax(0); /* * Copy all capability leafs to pick up the synthetic ones so that * memcmp() below doesn't fail on that. The ones coming from CPUID will * get overwritten in get_cpu_cap(). */ - memcpy(&info.x86_capability, &boot_cpu_data.x86_capability, sizeof(info.x86_capability)); + memcpy(&info->x86_capability, &boot_cpu_data.x86_capability, sizeof(info->x86_capability)); - get_cpu_cap(&info); + get_cpu_cap(info); - if (!memcmp(&info.x86_capability, &boot_cpu_data.x86_capability, sizeof(info.x86_capability))) + if (!memcmp(&info->x86_capability, &boot_cpu_data.x86_capability, sizeof(info->x86_capability))) return; pr_warn("x86/CPU: CPU features have changed after loading microcode, but might not take effect.\n"); diff --git a/arch/x86/kernel/cpu/microcode/core.c b/arch/x86/kernel/cpu/microcode/core.c index c4cd7328177b..d86a4f910a6b 100644 --- a/arch/x86/kernel/cpu/microcode/core.c +++ b/arch/x86/kernel/cpu/microcode/core.c @@ -439,6 +439,7 @@ static int __reload_late(void *info) static int microcode_reload_late(void) { int old = boot_cpu_data.microcode, ret; + struct cpuinfo_x86 info; pr_err("Attempting late microcode loading - it is dangerous and taints the kernel.\n"); pr_err("You should switch to early loading, if possible.\n"); @@ -448,7 +449,7 @@ static int microcode_reload_late(void) ret = stop_machine_cpuslocked(__reload_late, NULL, cpu_online_mask); if (ret == 0) - microcode_check(); + microcode_check(&info); pr_info("Reload completed, microcode revision: 0x%x -> 0x%x\n", old, boot_cpu_data.microcode); From patchwork Tue Jan 3 18:02:08 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ashok Raj X-Patchwork-Id: 38577 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4e01:0:0:0:0:0 with SMTP id p1csp4748047wrt; Tue, 3 Jan 2023 10:04:20 -0800 (PST) X-Google-Smtp-Source: AMrXdXs27GUq/pQKwgl20Y+xSk6I9SJ19BtwqDKvxe2tv7ugAqAUFgE9qJdBy4T1PJF4i/dK+PRI X-Received: by 2002:a17:906:688f:b0:7ae:31a0:571c with SMTP id n15-20020a170906688f00b007ae31a0571cmr39161427ejr.57.1672769060423; Tue, 03 Jan 2023 10:04:20 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1672769060; cv=none; d=google.com; s=arc-20160816; b=dn/XzY+EyQwlVDOI38pXW2fdsSgnE61Z+/1rOS7f3Z9NEEp0XvaqP2YWygrn/87pxs l3rwzGLNhilVwZipE7sWEzmdmBhEbgmFH3O/Ra5mvJM+7lYX1q/Cp5apbba+t14hP/nP 0h7gxlFVNp2uoN9SBlSReH3MamFR7E1f5Qhlee3VjKVGL0vPK60FyY2p/Vju/gC57UZQ lgABCX/aMDr1N/wyHl3SdCSSvRIaohKRm+Zwn6hhjpv9e1SSpTPllvGM2EBgMkRAltfM mMZFhqZzWwmAr+Kgsja55GuARu0EwqanQFB+9QPOswKPS5gqf1LnNjaZRUkan1AmdX0h 3FmQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=qkSIpZnAELFslvd3BJfOEaPsRW9Q0jEHIwfZtZFGwNs=; b=X++T1rbb33dd3fiwl3XHofO+CeZspLC4sYKcfZXpdZsORINZ7r6UDzyHGw8rrzQi1W VGHPMNZqUIqLlggWXFUyVNnHJM6pYhzARiXrRsrEltJVksjF2raWdSS8a3GS1Urus5fP JpqR19HdSmtshACWZEabzttM5kKDDawyTaEAa9l7muLIlnF+cpY15P3/Kr+tQVwd0OZc oQLNs86whHZQ2o37vSmL9jlukaYDwapuJ1vo4pXKyqKg5wObStU5TVokFWUtokT6ft5P /qbC/+Mw33s+F24BvA5kIlB6hygG1dPpjhibtt06OJfiQzsyAq5IpoWdhIJYHQneXo4c VBQA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=KUutnocC; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id xj3-20020a170906db0300b0078789399a48si29066985ejb.870.2023.01.03.10.03.57; Tue, 03 Jan 2023 10:04:20 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=KUutnocC; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238641AbjACSC4 (ORCPT + 99 others); Tue, 3 Jan 2023 13:02:56 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55464 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238611AbjACSCc (ORCPT ); Tue, 3 Jan 2023 13:02:32 -0500 Received: from mga06.intel.com (mga06b.intel.com [134.134.136.31]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7C6C812758 for ; Tue, 3 Jan 2023 10:02:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1672768949; x=1704304949; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=q0x8csfN7wsoyn+pz3gFYTMKHtMvDkQiL+H6SEMMaV0=; b=KUutnocCm0kC6JwAwaC6WB3XDoILk/3b1KxeYl/DWHVSoLpp0jmV+X00 drKh3ejOl+xqtEJucjyo35S6OP2RTnRiA8fzh737p4fqgJTTcb7Oo6Puw KKoGD0GLlxuMkgrGn2u5mrKMHVyvPsmWwx0+dEDGmmvcytCsn4tzhh8Pa rxyWjy2nLUfFKceviNHeCHsr8+j0PrFdPUKAmzx9/xHDRCwkQ8rWBAwoE OVSiR9Raf1H1g3Ln+sdFA4ziF/fJ4Hp2RxnNZp3kSMMoYGHhfIes3m2EY KiwC/lq2wX5ebBAke+5DY5oLUdrMenNPFslCLDFJPSKTriPejR15KKugk A==; X-IronPort-AV: E=McAfee;i="6500,9779,10579"; a="384010641" X-IronPort-AV: E=Sophos;i="5.96,297,1665471600"; d="scan'208";a="384010641" Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Jan 2023 10:02:22 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10579"; a="654876882" X-IronPort-AV: E=Sophos;i="5.96,297,1665471600"; d="scan'208";a="654876882" Received: from araj-ucode.jf.intel.com ([10.23.0.19]) by orsmga002-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Jan 2023 10:02:24 -0800 From: Ashok Raj To: Borislav Petkov , Thomas Gleixner Cc: X86-kernel , LKML Mailing List , Ashok Raj , Dave Hansen , Tony Luck , Alison Schofield , Reinette Chatre , Tom Lendacky Subject: [PATCH v3 2/6] x86/microcode/core: Take a snapshot before and after applying microcode Date: Tue, 3 Jan 2023 10:02:08 -0800 Message-Id: <20230103180212.333496-3-ashok.raj@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230103180212.333496-1-ashok.raj@intel.com> References: <20230103180212.333496-1-ashok.raj@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1754025490751011285?= X-GMAIL-MSGID: =?utf-8?q?1754025490751011285?= The kernel caches features about each CPU's features at boot in an x86_capability[] structure. The microcode update takes one snapshot and compares it with the saved copy at boot. However, the capabilities in the boot copy can be turned off as a result of certain command line parameters or configuration restrictions. This can cause a mismatch when comparing the values before and after the microcode update. microcode_check() is called after an update to report any previously cached CPUID bits might have changed due to the update. microcode_store_cpu_caps() basically stores the original CPU reported values and not the OS modified values. This will avoid giving a false warning even if no capabilities have changed. Ignore the capabilities recorded at boot. Take a new snapshot before the update and compare with a snapshot after the update to eliminate the false warning. Fixes: 1008c52c09dc ("x86/CPU: Add a microcode loader callback") Signed-off-by: Ashok Raj Cc: LKML Cc: x86 Cc: Tony Luck Cc: Dave Hansen Cc: Alison Schofield Cc: Reinette Chatre Cc: Thomas Gleixner Cc: Tom Lendacky --- Changes since last post - Boris - Change function from copy_cpu_caps() -> store_cpu_caps() - Keep microcode_check() inside cpu/common.c and not bleed get_cpu_caps() outside of core code. - Thomas : Commit log changes. --- arch/x86/include/asm/processor.h | 1 + arch/x86/kernel/cpu/common.c | 31 +++++++++++++++++++++------- arch/x86/kernel/cpu/microcode/core.c | 7 +++++++ 3 files changed, 31 insertions(+), 8 deletions(-) diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/processor.h index 387578049de0..ac2e67156b9b 100644 --- a/arch/x86/include/asm/processor.h +++ b/arch/x86/include/asm/processor.h @@ -697,6 +697,7 @@ bool xen_set_default_idle(void); #endif void __noreturn stop_this_cpu(void *dummy); +void microcode_store_cpu_caps(struct cpuinfo_x86 *info); void microcode_check(struct cpuinfo_x86 *info); enum l1tf_mitigations { diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c index b9c7529c920e..7c86c6fd07ae 100644 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -2297,28 +2297,43 @@ void cpu_init_secondary(void) #endif #ifdef CONFIG_MICROCODE_LATE_LOADING + +void microcode_store_cpu_caps(struct cpuinfo_x86 *info) +{ + /* Reload CPUID max function as it might've changed. */ + info->cpuid_level = cpuid_eax(0); + + /* + * Copy all capability leafs to pick up the synthetic ones so that + * memcmp() below doesn't fail on that. The ones coming from CPUID will + * get overwritten in get_cpu_cap(). + */ + memcpy(info->x86_capability, &boot_cpu_data.x86_capability, + sizeof(info->x86_capability)); + + get_cpu_cap(info); +} + /* * The microcode loader calls this upon late microcode load to recheck features, * only when microcode has been updated. Caller holds microcode_mutex and CPU * hotplug lock. */ -void microcode_check(struct cpuinfo_x86 *info) +void microcode_check(struct cpuinfo_x86 *orig) { - perf_check_microcode(); + struct cpuinfo_x86 info; - /* Reload CPUID max function as it might've changed. */ - info->cpuid_level = cpuid_eax(0); + perf_check_microcode(); /* * Copy all capability leafs to pick up the synthetic ones so that * memcmp() below doesn't fail on that. The ones coming from CPUID will * get overwritten in get_cpu_cap(). */ - memcpy(&info->x86_capability, &boot_cpu_data.x86_capability, sizeof(info->x86_capability)); - - get_cpu_cap(info); + microcode_store_cpu_caps(&info); - if (!memcmp(&info->x86_capability, &boot_cpu_data.x86_capability, sizeof(info->x86_capability))) + if (!memcmp(&info.x86_capability, &orig->x86_capability, + sizeof(info.x86_capability))) return; pr_warn("x86/CPU: CPU features have changed after loading microcode, but might not take effect.\n"); diff --git a/arch/x86/kernel/cpu/microcode/core.c b/arch/x86/kernel/cpu/microcode/core.c index d86a4f910a6b..14d9031ed68a 100644 --- a/arch/x86/kernel/cpu/microcode/core.c +++ b/arch/x86/kernel/cpu/microcode/core.c @@ -447,6 +447,13 @@ static int microcode_reload_late(void) atomic_set(&late_cpus_in, 0); atomic_set(&late_cpus_out, 0); + /* + * Take a snapshot before the microcode update, so we can compare + * them after the update is successful to check for any bits + * changed. + */ + microcode_store_cpu_caps(&info); + ret = stop_machine_cpuslocked(__reload_late, NULL, cpu_online_mask); if (ret == 0) microcode_check(&info); From patchwork Tue Jan 3 18:02:09 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ashok Raj X-Patchwork-Id: 38572 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4e01:0:0:0:0:0 with SMTP id p1csp4747453wrt; Tue, 3 Jan 2023 10:03:19 -0800 (PST) X-Google-Smtp-Source: AMrXdXuPRbkd9mIzOex3PTma/o5ATw9G3ug6/Gg2LexO8GKPNfXLZM81IL1tF7n2t3nYtHGdFigR X-Received: by 2002:a05:6402:528e:b0:481:420e:206d with SMTP id en14-20020a056402528e00b00481420e206dmr33929547edb.42.1672768999249; Tue, 03 Jan 2023 10:03:19 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1672768999; cv=none; d=google.com; s=arc-20160816; b=iPoq+yPWF94e8nIjuQoomePys9jG3o1ljBGw9Dj0pyYIU0iFI/m5YwNwMG+AqtVtdl DJQa8JANt+iJAYgkwLQgdnisw0nHjV7DxclyXSmEEg7lPctTCcd/FDcbB88aeqfE9pF/ uPflG8uFqMng/lWuELrB77P0QyXKmw4/TEIv6RpCLw0S8i2uREvikAHRQ94jSkUqxWiX PIdEgvSbICRUBv8zNOVKUPoYnRx0HaPuEmqmJkfWKLsbma0gt3AGnuWwGf5I4qIWJ1Mp ZjFvlU+lrzIzLfsy8oibznjDDLn2fWaQS8jRbODVjoR2xMUpq81EjZd/XFBq7JHkHkom TxPA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=FX1033HgNG5U9BgqSogetv30AcC4J0cS1LbQekYGHZ8=; b=dF3YeDm9lGF5wer/F6W0Gf6mYnv3cULnRDezx2EP7Df7blJ2Auad3sHODJDbG+sPEi DvB0HMpRivd1ghRCahRYHGMoGe3hJA0AAbXiwRcKtBg6zLSr1Nc/TbsWP/K43Jg2UBxc wgFRahdy2cOAjOHB/T8x4LxyHnCqERlX8yQ9IthUf1oiRdcuTFeBmnvIdKFuOT6z847G VnPVs4h0X0U7L8OB5F4w4oY2t4gev6rdczXn0q13vSVM27x+G3DuCbkPSZdNM/wu+YIA Vb+PxJlNJ7LYK9Gd//YkFtnJL95MDQ2nKKa0UJaYid+Zq0EkXabjM+ndC1w4UuJGiTFk xPhg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=U47aOgG9; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id l23-20020a056402029700b0045938ab7129si24751901edv.330.2023.01.03.10.02.55; Tue, 03 Jan 2023 10:03:19 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=U47aOgG9; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238568AbjACSCa (ORCPT + 99 others); Tue, 3 Jan 2023 13:02:30 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55390 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238527AbjACSC1 (ORCPT ); Tue, 3 Jan 2023 13:02:27 -0500 Received: from mga06.intel.com (mga06b.intel.com [134.134.136.31]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6A72A11A2A for ; Tue, 3 Jan 2023 10:02:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1672768944; x=1704304944; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Ksdr92gH6DZ8dyITiXCe+MBzgbUi62N2nRt+rCqGjeE=; b=U47aOgG99MHa+KoPh5oq37PvW/zwKn/8w2g/HoY1b/2kOqYLWB+nBY21 NgGKLb57YQCAaKMxhTQWSe7ed6uGkIkmE0ccT+85RMBFQHgw/J5h2xT9f t1N4WqUXgqnhBEJMl/zl0rQOWUTcXMusZcdQ3N+AdGVnGu563NBkoDHNf qUEA7LgXahVoMjy1Gsg1zdXQOYt8GSx5fV131RZfzCtwRgdHDLyqonoe1 L6bQLIFT3WLF5VM06ajQC+EFyQn4oekejpHGMkIzP1jcqx1XXk8XpNnja yBX6Z8H9+SJhXCrvTuDM6oPFgXc19nrt3h+m60WD7DrLWOpWcPLXS7vSp g==; X-IronPort-AV: E=McAfee;i="6500,9779,10579"; a="384010646" X-IronPort-AV: E=Sophos;i="5.96,297,1665471600"; d="scan'208";a="384010646" Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Jan 2023 10:02:22 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10579"; a="654876885" X-IronPort-AV: E=Sophos;i="5.96,297,1665471600"; d="scan'208";a="654876885" Received: from araj-ucode.jf.intel.com ([10.23.0.19]) by orsmga002-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Jan 2023 10:02:24 -0800 From: Ashok Raj To: Borislav Petkov , Thomas Gleixner Cc: X86-kernel , LKML Mailing List , Ashok Raj , Dave Hansen , Tony Luck , Alison Schofield , Reinette Chatre , Tom Lendacky Subject: [PATCH v3 3/6] x86/microcode: Display revisions only when update is successful Date: Tue, 3 Jan 2023 10:02:09 -0800 Message-Id: <20230103180212.333496-4-ashok.raj@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230103180212.333496-1-ashok.raj@intel.com> References: <20230103180212.333496-1-ashok.raj@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1754025426302390247?= X-GMAIL-MSGID: =?utf-8?q?1754025426302390247?= Right now, microcode loading failures and successes print the same message "Reloading completed". This is misleading to users. Display the updated revision number only if an update was successful. Suggested-by: Thomas Gleixner Signed-off-by: Ashok Raj Reviewed-by: Tony Luck Link: https://lore.kernel.org/lkml/874judpqqd.ffs@tglx/ Cc: LKML Cc: x86 Cc: Tony Luck Cc: Dave Hansen Cc: Alison Schofield Cc: Reinette Chatre Cc: Thomas Gleixner Cc: Tom Lendacky --- arch/x86/kernel/cpu/microcode/core.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/arch/x86/kernel/cpu/microcode/core.c b/arch/x86/kernel/cpu/microcode/core.c index 14d9031ed68a..e67f8923f119 100644 --- a/arch/x86/kernel/cpu/microcode/core.c +++ b/arch/x86/kernel/cpu/microcode/core.c @@ -455,11 +455,12 @@ static int microcode_reload_late(void) microcode_store_cpu_caps(&info); ret = stop_machine_cpuslocked(__reload_late, NULL, cpu_online_mask); - if (ret == 0) - microcode_check(&info); - pr_info("Reload completed, microcode revision: 0x%x -> 0x%x\n", - old, boot_cpu_data.microcode); + if (ret == 0) { + pr_info("Reload completed, microcode revision: 0x%x -> 0x%x\n", + old, boot_cpu_data.microcode); + microcode_check(&info); + } return ret; } From patchwork Tue Jan 3 18:02:10 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ashok Raj X-Patchwork-Id: 38575 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4e01:0:0:0:0:0 with SMTP id p1csp4747763wrt; Tue, 3 Jan 2023 10:03:48 -0800 (PST) X-Google-Smtp-Source: AMrXdXulvoap9m38KjCUtvQpJ30De0kGtmI+4lNC/AbaPOj3xCyOsJTSHlFM2Cy09kqRBJ1QSgid X-Received: by 2002:a17:906:49cd:b0:7c0:f684:9092 with SMTP id w13-20020a17090649cd00b007c0f6849092mr38214539ejv.37.1672769028420; Tue, 03 Jan 2023 10:03:48 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1672769028; cv=none; d=google.com; s=arc-20160816; b=jwmlVd8WBanehzaAH7/02h3MKtkKwukW3eLNNA3qt4RqJIlPL4kOLaF9npNAAG8iq5 lhWSbJS/xCi5H5WiSYfjevZULogLR5bGwHHZ0zjLlPTFJjLokTdz701OwRn9DIq+RlEt eSemae86s+GI0hY2dEQdW+PnivbB3j70dWSGe/GbxE63ZcYCPxZ4HmeudutnIlIBeMzy Jov7IBHEhusWR6+eqsYROBGqmvNlbcr3x3D1Qs2cAKMZ5cj3Yj7ySinHbaDM2uuf4tfI tKzld2Akwsf8BK6Ftu1VZJ79i5kIRKBwstHRDpwpGM1icoeg7MKvqoUO2Zv1SqiFGDG3 4EHA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=Wj9SnnoW3+QUsrElLaCSEx+KtaocMDLeXkG5A6cBpZI=; b=Ja+wAeq887yaWsGJpnJ7rF8aKpeEOaW2KpudUO3j7tpyQIyXnWV+oEz1gIiKdJZW9s yYMzM4tiG0r6T1zujojKjqfaTN+Uti05Auu80PZIZnuANMgQ2SRpGbCOAV0rSVp4RwBH K8b2hVlpJAI1JlsFbqNxUXkSZsZj8aD/BQqQ6dGXCRw3L/v8k7dG9KaCXmB8NIJN4/EI rSiTFilZPis2Fntl8zbUQETGw3lkO9BQHsoiTohTB3q/EbGE3AWVUoSkWtVCyNUz0Ja3 f5CjO6HPJsycObULCch3KZaIWLlcCGr+DULZ3M5/ThfoATc49n4KKqIhvwKBAD6hN8Nn V8xw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b="XHA/9oB6"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id cr18-20020a170906d55200b0078d805901b1si28081661ejc.489.2023.01.03.10.03.25; Tue, 03 Jan 2023 10:03:48 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b="XHA/9oB6"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238626AbjACSCm (ORCPT + 99 others); Tue, 3 Jan 2023 13:02:42 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55422 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238552AbjACSC2 (ORCPT ); Tue, 3 Jan 2023 13:02:28 -0500 Received: from mga06.intel.com (mga06b.intel.com [134.134.136.31]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D4A9511A27 for ; Tue, 3 Jan 2023 10:02:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1672768945; x=1704304945; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=lzIse4ZWwsUKwU2q15GNya0zg7eYgzn0naky1H7IqGc=; b=XHA/9oB618gKmvBx60b4494Zj9KfRJbKcHAhn3oH8gfivSDYrSvFGxzl 2CMa3U72aH7Pp1yn6HxLMQ9HpeCMufrP6yXD7CkmfYJP56RbkzAE71FVr H2Olc6eeIRRqWe3WcMKvB0AB+rCjquibgYOejI/Y9tdWIYdW7MVcc00l/ pv/Uh4jE4DBE+1xxxCrfui8XyIVt0Z7aB3lV6lk3bkTLdo5qNM1QJc0o0 oOIjdBISWsJ4BglBP85rkNm6MKoGg0UiIlJGwSAnQqAAFqe61IFcDRwWp zXx08o58neZwHEURNQbm8pvhyTh6soHTP3EQloF4OOPj9bMx8gFpr5wHP g==; X-IronPort-AV: E=McAfee;i="6500,9779,10579"; a="384010652" X-IronPort-AV: E=Sophos;i="5.96,297,1665471600"; d="scan'208";a="384010652" Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Jan 2023 10:02:22 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10579"; a="654876888" X-IronPort-AV: E=Sophos;i="5.96,297,1665471600"; d="scan'208";a="654876888" Received: from araj-ucode.jf.intel.com ([10.23.0.19]) by orsmga002-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Jan 2023 10:02:24 -0800 From: Ashok Raj To: Borislav Petkov , Thomas Gleixner Cc: X86-kernel , LKML Mailing List , Ashok Raj , Dave Hansen , Tony Luck , Alison Schofield , Reinette Chatre , Tom Lendacky Subject: [PATCH v3 4/6] x86/microcode/intel: Use a plain revision argument for print_ucode_rev() Date: Tue, 3 Jan 2023 10:02:10 -0800 Message-Id: <20230103180212.333496-5-ashok.raj@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230103180212.333496-1-ashok.raj@intel.com> References: <20230103180212.333496-1-ashok.raj@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1754025456418654428?= X-GMAIL-MSGID: =?utf-8?q?1754025456418654428?= print_ucode_rev() takes a struct ucode_cpu_info argument. The sole purpose of it is to print the microcode revision. The only available ucode_cpu_info always describes the currently loaded microcode revision. After a microcode update is successful, this is the new revision, or on failure it is the original revision. Subsequent changes need to print both the original and new revision, but the original version will be cached in a plain integer, which makes the code inconsistent. Replace the struct ucode_cpu_info argument with a plain integer which contains the revision number and adjust the call sites accordingly. No functional change. Signed-off-by: Ashok Raj Reviewed-by: Thomas Gleixner Cc: LKML Cc: x86 Cc: Tony Luck Cc: Dave Hansen Cc: Alison Schofield Cc: Reinette Chatre Cc: Thomas Gleixner Cc: Tom Lendacky --- Changes since earlier post. Thomas: - Updated commit log as suggested - Remove the line break after static void before print_ucode_info --- arch/x86/kernel/cpu/microcode/intel.c | 31 ++++++++------------------- 1 file changed, 9 insertions(+), 22 deletions(-) diff --git a/arch/x86/kernel/cpu/microcode/intel.c b/arch/x86/kernel/cpu/microcode/intel.c index 6bebc46ad8b1..1d709b72cfd0 100644 --- a/arch/x86/kernel/cpu/microcode/intel.c +++ b/arch/x86/kernel/cpu/microcode/intel.c @@ -310,13 +310,10 @@ static bool load_builtin_intel_microcode(struct cpio_data *cp) /* * Print ucode update info. */ -static void -print_ucode_info(struct ucode_cpu_info *uci, unsigned int date) +static void print_ucode_info(unsigned int new_rev, unsigned int date) { pr_info_once("microcode updated early to revision 0x%x, date = %04x-%02x-%02x\n", - uci->cpu_sig.rev, - date & 0xffff, - date >> 24, + new_rev, date & 0xffff, date >> 24, (date >> 16) & 0xff); } @@ -334,7 +331,7 @@ void show_ucode_info_early(void) if (delay_ucode_info) { intel_cpu_collect_info(&uci); - print_ucode_info(&uci, current_mc_date); + print_ucode_info(uci.cpu_sig.rev. current_mc_date); delay_ucode_info = 0; } } @@ -343,33 +340,23 @@ void show_ucode_info_early(void) * At this point, we can not call printk() yet. Delay printing microcode info in * show_ucode_info_early() until printk() works. */ -static void print_ucode(struct ucode_cpu_info *uci) +static void print_ucode(int new_rev, int date) { struct microcode_intel *mc; int *delay_ucode_info_p; int *current_mc_date_p; - mc = uci->mc; - if (!mc) - return; - delay_ucode_info_p = (int *)__pa_nodebug(&delay_ucode_info); current_mc_date_p = (int *)__pa_nodebug(¤t_mc_date); *delay_ucode_info_p = 1; - *current_mc_date_p = mc->hdr.date; + *current_mc_date_p = date; } #else -static inline void print_ucode(struct ucode_cpu_info *uci) +static inline void print_ucode(int new_rev, int date) { - struct microcode_intel *mc; - - mc = uci->mc; - if (!mc) - return; - - print_ucode_info(uci, mc->hdr.date); + print_ucode_info(new_rev, date); } #endif @@ -409,9 +396,9 @@ static int apply_microcode_early(struct ucode_cpu_info *uci, bool early) uci->cpu_sig.rev = rev; if (early) - print_ucode(uci); + print_ucode(uci->cpu_sig.rev, mc->hdr.date); else - print_ucode_info(uci, mc->hdr.date); + print_ucode_info(uci->cpu_sig.rev, mc->hdr.date); return 0; } From patchwork Tue Jan 3 18:02:11 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ashok Raj X-Patchwork-Id: 38574 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4e01:0:0:0:0:0 with SMTP id p1csp4747536wrt; Tue, 3 Jan 2023 10:03:27 -0800 (PST) X-Google-Smtp-Source: AMrXdXuk7rNpL2VGzE0jyr68fkjTLiNZPeBi0mcJdil5FSO0M3mR9wRJHo7LvKEEk2U0oEQJLKj7 X-Received: by 2002:a05:6402:f28:b0:46d:cf78:8c62 with SMTP id i40-20020a0564020f2800b0046dcf788c62mr39614298eda.27.1672769007343; Tue, 03 Jan 2023 10:03:27 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1672769007; cv=none; d=google.com; s=arc-20160816; b=udc/Vs9bmPUmY6CBfiPcMv1z1JIeei827FImUqc8+v2zm0Nfs7Ev044LDP2FWY+URW ucYAmynliMGzEdOnSoqTo4fw6wXAE+AAvl7oW1X6vb4/bH/z6mqTPERXn0Tzm0GF7xtf DmfdQlRzIqd+SPRXkTPUwZLpVMvMvqpudOYCE5CfyUcog0ehFc1IB87O1Qp9ofptrEfX Y95swrHcRaLWhP49A/TsNEvf4CSzUAA9pIT7xj5tKu0EzWRgFHYyimX0mTiVyR1B4Lwd F0Fk+ExxNhmCPz2PxgzMYcihL9jTnBcHzKd7Y7ojCpS6xiQDQyUIYw6QVQimyOERxwyO qBWA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=QoRj3DXPVUPlNmVpcPhUeVeCQtZgBqi3bNB9/9XzVbI=; b=TqoofjYu/uJkxcwxRz4lcidCfla0C7pFCIWE2xm9NFh0SVdRj2nvWfRIHsMwWITt6f 5bqeVNaczpiS0togb9RDEabFoy7sHrLLETRcSmOZevFoPKT88mlNXiD2rUPxDU+7I7wc X5vrOiW35w40dHC4PBIzPbn9IgowzuHXoO5IqQDLc9wZGesTaKHcZg2gT2yFDpdMqy0G RyrsEgLOjjeBGH0MTWExnN5OQYnAD/9r8RJ2v2yPXVLsnBe/p2kNW6b8qHmKlCL4jr04 Ai8fu/ZPVRAe0/4arRmI1GLfQD1qjiylEfZIj8B08YJ/KAZ7PoAvxi6iLtxpxP8zMGjc Ewxg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=DMD5Mzan; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id fe12-20020a056402390c00b0048b2c1d1621si10629859edb.83.2023.01.03.10.03.02; Tue, 03 Jan 2023 10:03:27 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=DMD5Mzan; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238635AbjACSCp (ORCPT + 99 others); Tue, 3 Jan 2023 13:02:45 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55420 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238546AbjACSC2 (ORCPT ); Tue, 3 Jan 2023 13:02:28 -0500 Received: from mga06.intel.com (mga06b.intel.com [134.134.136.31]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A3ED812AE7 for ; Tue, 3 Jan 2023 10:02:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1672768945; x=1704304945; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=iKTyz4kG5wNghmRCTt8/fCMlWiOtY5ulPwSrncqRr5Q=; b=DMD5Mzan91NHy2NxpbH9JjhC7yrDtAfm3zKrGPRy0qe4fX7mLVmf+Tbw bPAR+VttrmpQuCJ7G8qyf8WZ1JmgeSWaWgZt+KKSYV2Nd1fcmpsi55ydr 9f5MYF0BGtnrj6fU2WJyA0fctEs6OxIMoweoYgB31DfQnBAIq17eRWqyH IRpFx6PqoGf7uZbWTshJNuFXyJIKopxQoo0pHfXn0o/1zimoLEfZh7q6g xRRBsyFLA2HOoiZ7qHiXlkN4XJHCP11KQm3z13BueY5kAfW/w6Km2XDhp EEgqF9p3z4zjSJt73LA4wQ/6SM++JICgJToeryc/5T43SW23wdMGFlxyY A==; X-IronPort-AV: E=McAfee;i="6500,9779,10579"; a="384010659" X-IronPort-AV: E=Sophos;i="5.96,297,1665471600"; d="scan'208";a="384010659" Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Jan 2023 10:02:22 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10579"; a="654876890" X-IronPort-AV: E=Sophos;i="5.96,297,1665471600"; d="scan'208";a="654876890" Received: from araj-ucode.jf.intel.com ([10.23.0.19]) by orsmga002-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Jan 2023 10:02:24 -0800 From: Ashok Raj To: Borislav Petkov , Thomas Gleixner Cc: X86-kernel , LKML Mailing List , Ashok Raj , Dave Hansen , Tony Luck , Alison Schofield , Reinette Chatre , Tom Lendacky Subject: [PATCH v3 5/6] x86/microcode/intel: Print old and new rev during early boot Date: Tue, 3 Jan 2023 10:02:11 -0800 Message-Id: <20230103180212.333496-6-ashok.raj@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230103180212.333496-1-ashok.raj@intel.com> References: <20230103180212.333496-1-ashok.raj@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1754025434685260202?= X-GMAIL-MSGID: =?utf-8?q?1754025434685260202?= Make early loading message to match late loading messages. Print both old and new revisions. This is helpful to know what the BIOS loaded revision is before an early update. New dmesg log is shown below. microcode: early update: 0x2b000041 -> 0x2b000070 date = 2000-01-01 Cache the early BIOS revision before the microcode update and change the print_ucode_info() so it prints both the old and new revision in the same format as microcode_reload_late(). Signed-off-by: Ashok Raj Reviewed-by: Thomas Gleixner Cc: LKML Cc: x86 Cc: Tony Luck Cc: Dave Hansen Cc: Alison Schofield Cc: Reinette Chatre Cc: Thomas Gleixner Cc: Tom Lendacky --- Updates since previous post. Thomas: Commit log updates as suggested. --- arch/x86/kernel/cpu/microcode/intel.c | 25 +++++++++++++++---------- 1 file changed, 15 insertions(+), 10 deletions(-) diff --git a/arch/x86/kernel/cpu/microcode/intel.c b/arch/x86/kernel/cpu/microcode/intel.c index 1d709b72cfd0..f24300830ed7 100644 --- a/arch/x86/kernel/cpu/microcode/intel.c +++ b/arch/x86/kernel/cpu/microcode/intel.c @@ -310,10 +310,10 @@ static bool load_builtin_intel_microcode(struct cpio_data *cp) /* * Print ucode update info. */ -static void print_ucode_info(unsigned int new_rev, unsigned int date) +static void print_ucode_info(int old_rev, int new_rev, unsigned int date) { - pr_info_once("microcode updated early to revision 0x%x, date = %04x-%02x-%02x\n", - new_rev, date & 0xffff, date >> 24, + pr_info_once("early update: 0x%x -> 0x%x, date = %04x-%02x-%02x\n", + old_rev, new_rev, date & 0xffff, date >> 24, (date >> 16) & 0xff); } @@ -321,6 +321,7 @@ static void print_ucode_info(unsigned int new_rev, unsigned int date) static int delay_ucode_info; static int current_mc_date; +static int early_old_rev; /* * Print early updated ucode info after printk works. This is delayed info dump. @@ -331,7 +332,7 @@ void show_ucode_info_early(void) if (delay_ucode_info) { intel_cpu_collect_info(&uci); - print_ucode_info(uci.cpu_sig.rev. current_mc_date); + print_ucode_info(early_old_rev, uci.cpu_sig.rev, current_mc_date); delay_ucode_info = 0; } } @@ -340,30 +341,33 @@ void show_ucode_info_early(void) * At this point, we can not call printk() yet. Delay printing microcode info in * show_ucode_info_early() until printk() works. */ -static void print_ucode(int new_rev, int date) +static void print_ucode(int old_rev, int new_rev, int date) { struct microcode_intel *mc; int *delay_ucode_info_p; int *current_mc_date_p; + int *early_old_rev_p; delay_ucode_info_p = (int *)__pa_nodebug(&delay_ucode_info); current_mc_date_p = (int *)__pa_nodebug(¤t_mc_date); + early_old_rev_p = (int *)__pa_nodebug(&early_old_rev); *delay_ucode_info_p = 1; *current_mc_date_p = date; + *early_old_rev_p = old_rev; } #else -static inline void print_ucode(int new_rev, int date) +static inline void print_ucode(int old_rev, int new_rev, int date) { - print_ucode_info(new_rev, date); + print_ucode_info(old_rev, new_rev, date); } #endif static int apply_microcode_early(struct ucode_cpu_info *uci, bool early) { struct microcode_intel *mc; - u32 rev; + u32 rev, old_rev; mc = uci->mc; if (!mc) @@ -389,6 +393,7 @@ static int apply_microcode_early(struct ucode_cpu_info *uci, bool early) /* write microcode via MSR 0x79 */ native_wrmsrl(MSR_IA32_UCODE_WRITE, (unsigned long)mc->bits); + old_rev = rev; rev = intel_get_microcode_revision(); if (rev != mc->hdr.rev) return -1; @@ -396,9 +401,9 @@ static int apply_microcode_early(struct ucode_cpu_info *uci, bool early) uci->cpu_sig.rev = rev; if (early) - print_ucode(uci->cpu_sig.rev, mc->hdr.date); + print_ucode(old_rev, uci->cpu_sig.rev, mc->hdr.date); else - print_ucode_info(uci->cpu_sig.rev, mc->hdr.date); + print_ucode_info(old_rev, uci->cpu_sig.rev, mc->hdr.date); return 0; } From patchwork Tue Jan 3 18:02:12 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ashok Raj X-Patchwork-Id: 38576 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4e01:0:0:0:0:0 with SMTP id p1csp4748045wrt; Tue, 3 Jan 2023 10:04:20 -0800 (PST) X-Google-Smtp-Source: AMrXdXvZIXoujhePc4KtE34jzLDCEPwzshfEi9I74Qelx7Xy4MTYt7OG49mpBxh2zSEVe+vfxoxT X-Received: by 2002:a17:906:280d:b0:7c1:65f5:7b95 with SMTP id r13-20020a170906280d00b007c165f57b95mr41205959ejc.26.1672769060217; Tue, 03 Jan 2023 10:04:20 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1672769060; cv=none; d=google.com; s=arc-20160816; b=icaf1JgHjCgv6qL1NIG/9+pQxNAwwmXAeshIjqrA4sL8PhBMH2fZoIpmOhvyorZvK7 rCNmINfggT5h9xd/pUA1rRczysjnYbtNlfC37leRr8IzTPVcjgM6NY9VbKV+VI6hVJMo 5v57VQCLhVAs+rPPUibv2qPWuWwpfOyhXMgM4Z1hMUY48T4/4LEqIhQYl7tYn2EgljuR VwdDGGlNuYPPPv2eOFBHv7itP5Aqkq1o3xsjj4UWbVClRnKERl5LCLRpbWFItzOas7Vq mCPGP6M5xooNN9a6acIYtW7gh2aN65eCjDAQX7fU5uQXnMd5eEbJ/DSdY3siThkzXvro ip0A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=l5pxbQTYC0zbTTffNJDuInwIYZlUb2PNvtrq46V44mw=; b=GQ0VXl9YUd7SiKS9+YjuOyWHUz6eaVOaP3nHiECn7Fn6CvNU9Bks5M550TM/LkCn/R ayF7xo/oOL6/n19CXcdYJ9dpwkK06vpR0PdRG/d7GUCCV390XQVY0KnQ3jcA6roe6RQq MBjiSTSkCi/yJpFRPG8rUeRTOqIgh+CCyIE2yZRg/Z9cKP4ciW31uts0cu2PJyYFTYzo UpwZC5bQTOKqD8AqMzWgLr6bJyP9+ZoT6hwKIJ1LFEe1V51VGyfeYZj5A6nvo5AT78yA DCFA6J1YfyRdMsdlyBwUsMnpvW8m4/6/8DRJqIw1GS1Q+NOkmJA5E2F4eBR7b1VHtPjK fd2Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=n05lAqKZ; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id nd21-20020a170907629500b0084c9f6cbe3asi12839332ejc.843.2023.01.03.10.03.56; Tue, 03 Jan 2023 10:04:20 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=n05lAqKZ; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238661AbjACSCs (ORCPT + 99 others); Tue, 3 Jan 2023 13:02:48 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55424 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238553AbjACSC3 (ORCPT ); Tue, 3 Jan 2023 13:02:29 -0500 Received: from mga06.intel.com (mga06b.intel.com [134.134.136.31]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D4A62E09E for ; Tue, 3 Jan 2023 10:02:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1672768945; x=1704304945; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Rpu7Ee31xVGs/Ge1cmadMTPDkLVc3s122FBVNn8fO8I=; b=n05lAqKZu7EPrKQJQ/eSXB/bIKwWqNDGhLpkodkzZCO2cTrvvVWUWgpS ylhdACdjaX76sv4FSwLnHbcI6mxxHFky0IY79WJcaviJ7EsdicQA7+Xmj Gj7Iprs78aa+Bx1k7Xx9TDWruZWzpImtb50I9Rk76Zncv6xvLIvufCgXh T/aJaInEHriIQnFH/todK1B1v75xIvi7Da7EtEbEP1o+4uIxweBHW4KSF 2iaC7o8fEPR2Wojl/VI3kh9NxTLFoxQojPHz0FY9eWXjJvFbik2oA7zkQ PHukj8bq//HFSgR+bxFX9Lzzsy6hreURYosTdi17bogB9GiGF/8LOfiBt g==; X-IronPort-AV: E=McAfee;i="6500,9779,10579"; a="384010661" X-IronPort-AV: E=Sophos;i="5.96,297,1665471600"; d="scan'208";a="384010661" Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Jan 2023 10:02:22 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10579"; a="654876893" X-IronPort-AV: E=Sophos;i="5.96,297,1665471600"; d="scan'208";a="654876893" Received: from araj-ucode.jf.intel.com ([10.23.0.19]) by orsmga002-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Jan 2023 10:02:24 -0800 From: Ashok Raj To: Borislav Petkov , Thomas Gleixner Cc: X86-kernel , LKML Mailing List , Ashok Raj , Dave Hansen , Tony Luck , Alison Schofield , Reinette Chatre , Tom Lendacky Subject: [PATCH v3 6/6] x86/microcode/intel: Print when early microcode loading fails Date: Tue, 3 Jan 2023 10:02:12 -0800 Message-Id: <20230103180212.333496-7-ashok.raj@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230103180212.333496-1-ashok.raj@intel.com> References: <20230103180212.333496-1-ashok.raj@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1754025490086989840?= X-GMAIL-MSGID: =?utf-8?q?1754025490086989840?= Currently when early microcode loading fails there is no way for the user to know that the update failed. Store the failed status and pass it to print_ucode_info() so that early loading failures are captured in dmesg. Signed-off-by: Ashok Raj Cc: LKML Cc: x86 Cc: Tony Luck Cc: Dave Hansen Cc: Alison Schofield Cc: Reinette Chatre Cc: Thomas Gleixner Cc: Tom Lendacky --- Changes since last post. Thomas: Fix commit log as suggested. --- arch/x86/kernel/cpu/microcode/intel.c | 28 +++++++++++++++------------ 1 file changed, 16 insertions(+), 12 deletions(-) diff --git a/arch/x86/kernel/cpu/microcode/intel.c b/arch/x86/kernel/cpu/microcode/intel.c index f24300830ed7..0cdff9ed2a4e 100644 --- a/arch/x86/kernel/cpu/microcode/intel.c +++ b/arch/x86/kernel/cpu/microcode/intel.c @@ -310,11 +310,11 @@ static bool load_builtin_intel_microcode(struct cpio_data *cp) /* * Print ucode update info. */ -static void print_ucode_info(int old_rev, int new_rev, unsigned int date) +static void print_ucode_info(bool failed, int old_rev, int new_rev, unsigned int date) { - pr_info_once("early update: 0x%x -> 0x%x, date = %04x-%02x-%02x\n", + pr_info_once("early update: 0x%x -> 0x%x, date = %04x-%02x-%02x %s\n", old_rev, new_rev, date & 0xffff, date >> 24, - (date >> 16) & 0xff); + (date >> 16) & 0xff, failed ? "FAILED" : ""); } #ifdef CONFIG_X86_32 @@ -322,6 +322,7 @@ static void print_ucode_info(int old_rev, int new_rev, unsigned int date) static int delay_ucode_info; static int current_mc_date; static int early_old_rev; +static bool early_failed; /* * Print early updated ucode info after printk works. This is delayed info dump. @@ -332,7 +333,7 @@ void show_ucode_info_early(void) if (delay_ucode_info) { intel_cpu_collect_info(&uci); - print_ucode_info(early_old_rev, uci.cpu_sig.rev, current_mc_date); + print_ucode_info(early_failed, early_old_rev, uci.cpu_sig.rev, current_mc_date); delay_ucode_info = 0; } } @@ -341,26 +342,28 @@ void show_ucode_info_early(void) * At this point, we can not call printk() yet. Delay printing microcode info in * show_ucode_info_early() until printk() works. */ -static void print_ucode(int old_rev, int new_rev, int date) +static void print_ucode(bool failed, int old_rev, int new_rev, int date) { - struct microcode_intel *mc; int *delay_ucode_info_p; int *current_mc_date_p; int *early_old_rev_p; + bool *early_failed_p; delay_ucode_info_p = (int *)__pa_nodebug(&delay_ucode_info); current_mc_date_p = (int *)__pa_nodebug(¤t_mc_date); early_old_rev_p = (int *)__pa_nodebug(&early_old_rev); + early_failed_p = (bool *)__pa_nodebug(&early_failed); *delay_ucode_info_p = 1; *current_mc_date_p = date; *early_old_rev_p = old_rev; + *early_failed_p = failed; } #else -static inline void print_ucode(int old_rev, int new_rev, int date) +static inline void print_ucode(bool failed, int old_rev, int new_rev, int date) { - print_ucode_info(old_rev, new_rev, date); + print_ucode_info(failed, old_rev, new_rev, date); } #endif @@ -368,6 +371,7 @@ static int apply_microcode_early(struct ucode_cpu_info *uci, bool early) { struct microcode_intel *mc; u32 rev, old_rev; + int retval = 0; mc = uci->mc; if (!mc) @@ -396,16 +400,16 @@ static int apply_microcode_early(struct ucode_cpu_info *uci, bool early) old_rev = rev; rev = intel_get_microcode_revision(); if (rev != mc->hdr.rev) - return -1; + retval = -1; uci->cpu_sig.rev = rev; if (early) - print_ucode(old_rev, uci->cpu_sig.rev, mc->hdr.date); + print_ucode(retval, old_rev, mc->hdr.rev, mc->hdr.date); else - print_ucode_info(old_rev, uci->cpu_sig.rev, mc->hdr.date); + print_ucode_info(retval, old_rev, uci->cpu_sig.rev, mc->hdr.date); - return 0; + return retval; } int __init save_microcode_in_initrd_intel(void)