From patchwork Tue Jan 3 14:22:27 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 38456 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4e01:0:0:0:0:0 with SMTP id p1csp4645491wrt; Tue, 3 Jan 2023 06:23:36 -0800 (PST) X-Google-Smtp-Source: AMrXdXuOPjmYuq/u9S9zf/0vueDY1jJ+Oux8+5aUMfuj70HqDc260rxMp+Qff2LAzF8sGv5NEhWA X-Received: by 2002:a17:90a:a28:b0:223:f78c:15d with SMTP id o37-20020a17090a0a2800b00223f78c015dmr48452387pjo.41.1672755816015; Tue, 03 Jan 2023 06:23:36 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1672755815; cv=none; d=google.com; s=arc-20160816; b=JPGTvnRQ3ZGkGvGcYy//UadRvpulZX2q29qI6dghLlRaM5dE0FvAssVEOo24w5l+0f rCbwVW6ASVNn3ZfJPQ6RTL+zpeBCg2yGgEOHMMyYawA/XTwWWB/c5bz44LFpNOvtE8nI 58/9ge+YHG/+1quJKvtGc5seM8KHcWGnPYK86uK/MiwP3Oo7osIBo2xe0lzqaC4PsgMA pni0UWe+3ujMm69J4auLf3ftFYnvrzH4hzm795RPT+OuCEAVSw19eXftRbu6RFNRlc/o 6/01nOCjwL6Iq2zg9Z7ULeNjcjhF832mHe92euxrOkd5eRDzBF/ttyQZ7wAr9Pe0+dmt amtQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:cc:to:in-reply-to:references:message-id :content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=BrQTlFtoTu8he9ydQRdvctc8hmi7ieuddKkLwr03Ix0=; b=vla1YnQi/FsUVk0wksCbyoT83dXLdTmPxYHDbje+jz8u2l53+Hb99CoyCW4FOO45EI gfk/GYxNyjSUQ4ddK/cMJkzdB3MC3pssjGfRjJO/lGpAZuTI0U3WlY4Ppwtm+cDaRDgW zpNn7ipb8bX4TEjhHTnpdZkI7ENqtQwuILRrRYMvqYWYMAU/Qy4NaQX9eC+03Mu4aP8O DHtFBG4ElthnULvuoMdUgdIvZScwDgGO3fTrKxbYwcOVGBmiG51f4pPKdPHO52G9n16d yb4kd1dQXvx/t2z80EOBxW9wSoPk3dJGY5vlqdGKOYlV+RTpZDwAdLyE5ynpu6eTroKV OECg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=xHYxZ0jD; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id lx1-20020a17090b4b0100b00223770a1235si35428889pjb.138.2023.01.03.06.23.23; Tue, 03 Jan 2023 06:23:35 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=xHYxZ0jD; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237894AbjACOWi (ORCPT + 99 others); Tue, 3 Jan 2023 09:22:38 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39096 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237778AbjACOWd (ORCPT ); Tue, 3 Jan 2023 09:22:33 -0500 Received: from mail-wr1-x42a.google.com (mail-wr1-x42a.google.com [IPv6:2a00:1450:4864:20::42a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 735512714 for ; Tue, 3 Jan 2023 06:22:32 -0800 (PST) Received: by mail-wr1-x42a.google.com with SMTP id d17so9850367wrs.2 for ; Tue, 03 Jan 2023 06:22:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=BrQTlFtoTu8he9ydQRdvctc8hmi7ieuddKkLwr03Ix0=; b=xHYxZ0jDW2+TBmQ5IAf+o48+WdHcrpuYIJpkEKuoa8Hvb/BQHziGbWUph2B1hstbEU uOyZAreWTU3SynAXgs/KUVW609XGxXbjE8SsFSYwTSxphKlGUqg45z2jv+ip4PNysIhJ wLWNeS5qSAFdzN+2Z0T6EqzqQ9FX3YK4UKmLI76hIez8PmYQUq1WhrC8nv/0nqFQ/1LF PCUBCuC4YGW5VHu3UoRcGpJG8YR3gqXl/ieW1R1rMvOIBWb3ugsRIo02L/g6ewizQvWq wZ7p2jYJTssUMdyu0jckxKPj6/vtUUc3Wz+cmmQ/69Fy/D/7ZK2CNhweVpsmgFUl9bvD NejA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=BrQTlFtoTu8he9ydQRdvctc8hmi7ieuddKkLwr03Ix0=; b=j/2fBeovJnj9NB0V7S3s3T8z5p8PRijd+cx5QsO/zfj2zk6BxG+d6dvhHg0otuBsym oJnkY/KWpnBZTkY+td6evztz4uMDkP14nLpwiAIPzAT2lnjjwuJ6VFebopqL5GHHOuva i5uwcQ5zxZ/g+OdxVqXgbHo92NccvU0Lj0hzYRZjkMA7RaH7Z0Ai5uAr7oHEWAcXbTfv d00FL/4V2IuG78CUqggB0X3UbFKt6hfknxFsbE4qy/blWPmNDP6l9+oGy07viu2stQEG h838AQLAuIfzN6uzkLMJ8DEkYDf2PS2u0vW2y8sojOYBrFkkH0ja/mT0tGzQzsVqIix3 sRJA== X-Gm-Message-State: AFqh2krEE0kIyd+04PoNQNgtZP+/9zjq95fJd/qwhgT9zANlGmFWW9QK QuVVwxUftjRpwjN+drTEZ5qq/A== X-Received: by 2002:adf:cc81:0:b0:275:ae5c:d448 with SMTP id p1-20020adfcc81000000b00275ae5cd448mr26043702wrj.13.1672755751009; Tue, 03 Jan 2023 06:22:31 -0800 (PST) Received: from arrakeen.starnux.net ([2a01:e0a:982:cbb0:52eb:f6ff:feb3:451a]) by smtp.gmail.com with ESMTPSA id i6-20020a5d55c6000000b00283c7b5ee3bsm20182163wrw.101.2023.01.03.06.22.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Jan 2023 06:22:30 -0800 (PST) From: Neil Armstrong Date: Tue, 03 Jan 2023 15:22:27 +0100 Subject: [PATCH 1/2] dt-bindings: display: panel: document the Visionox VTDR6130 AMOLED DSI Panel bindings MIME-Version: 1.0 Message-Id: <20230103-topic-sm8550-upstream-vtdr6130-panel-v1-1-9b746b858378@linaro.org> References: <20230103-topic-sm8550-upstream-vtdr6130-panel-v1-0-9b746b858378@linaro.org> In-Reply-To: <20230103-topic-sm8550-upstream-vtdr6130-panel-v1-0-9b746b858378@linaro.org> To: Thierry Reding , Sam Ravnborg , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski Cc: dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, Neil Armstrong X-Mailer: b4 0.11.1 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1754011602710952812?= X-GMAIL-MSGID: =?utf-8?q?1754011602710952812?= Document the 1080x2400 Visionox VTDR6130 AMOLED DSI Panel bindings. Signed-off-by: Neil Armstrong Reviewed-by: Krzysztof Kozlowski Reviewed-by: Sam Ravnborg --- .../bindings/display/panel/visionox,vtdr6130.yaml | 53 ++++++++++++++++++++++ 1 file changed, 53 insertions(+) diff --git a/Documentation/devicetree/bindings/display/panel/visionox,vtdr6130.yaml b/Documentation/devicetree/bindings/display/panel/visionox,vtdr6130.yaml new file mode 100644 index 000000000000..49e2fd4b4e99 --- /dev/null +++ b/Documentation/devicetree/bindings/display/panel/visionox,vtdr6130.yaml @@ -0,0 +1,53 @@ +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/panel/visionox,vtdr6130.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Visionox VTDR6130 AMOLED DSI Panel + +maintainers: + - Neil Armstrong + +allOf: + - $ref: panel-common.yaml# + +properties: + compatible: + const: visionox,vtdr6130 + + vddio-supply: true + vci-supply: true + vdd-supply: true + port: true + reset-gpios: true + +additionalProperties: false + +required: + - compatible + - vddio-supply + - vci-supply + - vdd-supply + - reset-gpios + - port + +examples: + - | + #include + panel { + compatible = "visionox,vtdr6130"; + + vddio-supply = <&vreg_l12b_1p8>; + vci-supply = <&vreg_l13b_3p0>; + vdd-supply = <&vreg_l11b_1p2>; + + reset-gpios = <&tlmm 133 GPIO_ACTIVE_LOW>; + + port { + panel0_in: endpoint { + remote-endpoint = <&dsi0_out>; + }; + }; + }; +... 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By default the the panel is configured to work with DSI compressed streams, but can work in uncompressed video mode since 1080x2400 in RGB888 fits in the 4 DSI lanes bandwidth. While display compression is preferred for performance and power reasons, let's start with the uncompressed video mode support and add the DSC support later on. Signed-off-by: Neil Armstrong --- drivers/gpu/drm/panel/Kconfig | 8 + drivers/gpu/drm/panel/Makefile | 1 + drivers/gpu/drm/panel/panel-visionox-vtdr6130.c | 366 ++++++++++++++++++++++++ 3 files changed, 375 insertions(+) diff --git a/drivers/gpu/drm/panel/Kconfig b/drivers/gpu/drm/panel/Kconfig index 737edcdf9eef..fd1d7e6f536b 100644 --- a/drivers/gpu/drm/panel/Kconfig +++ b/drivers/gpu/drm/panel/Kconfig @@ -717,6 +717,14 @@ config DRM_PANEL_VISIONOX_RM69299 Say Y here if you want to enable support for Visionox RM69299 DSI Video Mode panel. +config DRM_PANEL_VISIONOX_VTDR6130 + tristate "Visionox VTDR6130" + depends on OF + depends on DRM_MIPI_DSI + help + Say Y here if you want to enable support for Visionox + VTDR6130 1080x2400 AMOLED DSI panel. + config DRM_PANEL_WIDECHIPS_WS2401 tristate "Widechips WS2401 DPI panel driver" depends on SPI && GPIOLIB diff --git a/drivers/gpu/drm/panel/Makefile b/drivers/gpu/drm/panel/Makefile index f8f9d9f6a307..1966404fcf7a 100644 --- a/drivers/gpu/drm/panel/Makefile +++ b/drivers/gpu/drm/panel/Makefile @@ -73,5 +73,6 @@ obj-$(CONFIG_DRM_PANEL_TPO_TD043MTEA1) += panel-tpo-td043mtea1.o obj-$(CONFIG_DRM_PANEL_TPO_TPG110) += panel-tpo-tpg110.o obj-$(CONFIG_DRM_PANEL_TRULY_NT35597_WQXGA) += panel-truly-nt35597.o obj-$(CONFIG_DRM_PANEL_VISIONOX_RM69299) += panel-visionox-rm69299.o +obj-$(CONFIG_DRM_PANEL_VISIONOX_VTDR6130) += panel-visionox-vtdr6130.o obj-$(CONFIG_DRM_PANEL_WIDECHIPS_WS2401) += panel-widechips-ws2401.o obj-$(CONFIG_DRM_PANEL_XINPENG_XPP055C272) += panel-xinpeng-xpp055c272.o diff --git a/drivers/gpu/drm/panel/panel-visionox-vtdr6130.c b/drivers/gpu/drm/panel/panel-visionox-vtdr6130.c new file mode 100644 index 000000000000..94ad2a32efc9 --- /dev/null +++ b/drivers/gpu/drm/panel/panel-visionox-vtdr6130.c @@ -0,0 +1,366 @@ +// SPDX-License-Identifier: GPL-2.0-only +// Copyright (c) 2023, Linaro Limited + +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +struct visionox_vtdr6130 { + struct drm_panel panel; + struct mipi_dsi_device *dsi; + struct gpio_desc *reset_gpio; + struct regulator_bulk_data supplies[3]; + bool prepared; +}; + +static inline struct visionox_vtdr6130 *to_visionox_vtdr6130(struct drm_panel *panel) +{ + return container_of(panel, struct visionox_vtdr6130, panel); +} + +static inline int visionox_vtdr6130_dsi_write(struct mipi_dsi_device *dsi, const void *seq, + size_t len) +{ + return mipi_dsi_dcs_write_buffer(dsi, seq, len); +} + +#define dsi_dcs_write_seq(dsi, seq...) \ + { \ + const u8 d[] = { seq }; \ + visionox_vtdr6130_dsi_write(dsi, d, ARRAY_SIZE(d)); \ + } + +static void visionox_vtdr6130_reset(struct visionox_vtdr6130 *ctx) +{ + gpiod_set_value_cansleep(ctx->reset_gpio, 0); + usleep_range(10000, 11000); + gpiod_set_value_cansleep(ctx->reset_gpio, 1); + usleep_range(10000, 11000); + gpiod_set_value_cansleep(ctx->reset_gpio, 0); + usleep_range(10000, 11000); +} + +static int visionox_vtdr6130_on(struct visionox_vtdr6130 *ctx) +{ + struct mipi_dsi_device *dsi = ctx->dsi; + struct device *dev = &dsi->dev; + int ret; + + dsi->mode_flags |= MIPI_DSI_MODE_LPM; + + dsi_dcs_write_seq(dsi, 0x03, 0x01); + dsi_dcs_write_seq(dsi, 0x35, 0x00); + dsi_dcs_write_seq(dsi, 0x53, 0x20); + dsi_dcs_write_seq(dsi, 0x51, 0x00, 0x00); + dsi_dcs_write_seq(dsi, 0x59, 0x09); + dsi_dcs_write_seq(dsi, 0x6c, 0x01); + dsi_dcs_write_seq(dsi, 0x6d, 0x00); + dsi_dcs_write_seq(dsi, 0x6f, 0x01); + dsi_dcs_write_seq(dsi, 0x70, + 0x12, 0x00, 0x00, 0xab, 0x30, 0x80, 0x09, 0x60, 0x04, + 0x38, 0x00, 0x28, 0x02, 0x1c, 0x02, 0x1c, 0x02, 0x00, + 0x02, 0x0e, 0x00, 0x20, 0x03, 0xdd, 0x00, 0x07, 0x00, + 0x0c, 0x02, 0x77, 0x02, 0x8b, 0x18, 0x00, 0x10, 0xf0, + 0x07, 0x10, 0x20, 0x00, 0x06, 0x0f, 0x0f, 0x33, 0x0e, + 0x1c, 0x2a, 0x38, 0x46, 0x54, 0x62, 0x69, 0x70, 0x77, + 0x79, 0x7b, 0x7d, 0x7e, 0x02, 0x02, 0x22, 0x00, 0x2a, + 0x40, 0x2a, 0xbe, 0x3a, 0xfc, 0x3a, 0xfa, 0x3a, 0xf8, + 0x3b, 0x38, 0x3b, 0x78, 0x3b, 0xb6, 0x4b, 0xb6, 0x4b, + 0xf4, 0x4b, 0xf4, 0x6c, 0x34, 0x84, 0x74, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00); + dsi_dcs_write_seq(dsi, 0xf0, 0xaa, 0x10); + dsi_dcs_write_seq(dsi, 0xb1, + 0x01, 0x38, 0x00, 0x14, 0x00, 0x1c, 0x00, 0x01, 0x66, + 0x00, 0x14, 0x00, 0x14, 0x00, 0x01, 0x66, 0x00, 0x14, + 0x05, 0xcc, 0x00); + dsi_dcs_write_seq(dsi, 0xf0, 0xaa, 0x13); + dsi_dcs_write_seq(dsi, 0xce, + 0x09, 0x11, 0x09, 0x11, 0x08, 0xc1, 0x07, 0xfa, 0x05, + 0xa4, 0x00, 0x3c, 0x00, 0x34, 0x00, 0x24, 0x00, 0x0c, + 0x00, 0x0c, 0x04, 0x00, 0x35); + dsi_dcs_write_seq(dsi, 0xf0, 0xaa, 0x14); + dsi_dcs_write_seq(dsi, 0xb2, 0x03, 0x33); + dsi_dcs_write_seq(dsi, 0xb4, + 0x00, 0x33, 0x00, 0x00, 0x00, 0x3e, 0x00, 0x00, 0x00, + 0x3e, 0x00, 0x00); + dsi_dcs_write_seq(dsi, 0xb5, + 0x00, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x06, 0x01); + dsi_dcs_write_seq(dsi, 0xb9, 0x00, 0x00, 0x08, 0x09, 0x09, 0x09); + dsi_dcs_write_seq(dsi, 0xbc, + 0x10, 0x00, 0x00, 0x06, 0x11, 0x09, 0x3b, 0x09, 0x47, + 0x09, 0x47, 0x00); + dsi_dcs_write_seq(dsi, 0xbe, + 0x10, 0x10, 0x00, 0x08, 0x22, 0x09, 0x19, 0x09, 0x25, + 0x09, 0x25, 0x00); + dsi_dcs_write_seq(dsi, 0xff, 0x5a, 0x80); + dsi_dcs_write_seq(dsi, 0x65, 0x14); + dsi_dcs_write_seq(dsi, 0xfa, 0x08, 0x08, 0x08); + dsi_dcs_write_seq(dsi, 0xff, 0x5a, 0x81); + dsi_dcs_write_seq(dsi, 0x65, 0x05); + dsi_dcs_write_seq(dsi, 0xf3, 0x0f); + dsi_dcs_write_seq(dsi, 0xf0, 0xaa, 0x00); + dsi_dcs_write_seq(dsi, 0xff, 0x5a, 0x82); + dsi_dcs_write_seq(dsi, 0xf9, 0x00); + dsi_dcs_write_seq(dsi, 0xff, 0x51, 0x83); + dsi_dcs_write_seq(dsi, 0x65, 0x04); + dsi_dcs_write_seq(dsi, 0xf8, 0x00); + dsi_dcs_write_seq(dsi, 0xff, 0x5a, 0x00); + dsi_dcs_write_seq(dsi, 0x65, 0x01); + dsi_dcs_write_seq(dsi, 0xf4, 0x9a); + dsi_dcs_write_seq(dsi, 0xff, 0x5a, 0x00); + + ret = mipi_dsi_dcs_exit_sleep_mode(dsi); + if (ret < 0) { + dev_err(dev, "Failed to exit sleep mode: %d\n", ret); + return ret; + } + msleep(120); + + ret = mipi_dsi_dcs_set_display_on(dsi); + if (ret < 0) { + dev_err(dev, "Failed to set display on: %d\n", ret); + return ret; + } + msleep(20); + + return 0; +} + +static int visionox_vtdr6130_off(struct visionox_vtdr6130 *ctx) +{ + struct mipi_dsi_device *dsi = ctx->dsi; + struct device *dev = &dsi->dev; + int ret; + + dsi->mode_flags &= ~MIPI_DSI_MODE_LPM; + + ret = mipi_dsi_dcs_set_display_off(dsi); + if (ret < 0) { + dev_err(dev, "Failed to set display off: %d\n", ret); + return ret; + } + msleep(20); + + ret = mipi_dsi_dcs_enter_sleep_mode(dsi); + if (ret < 0) { + dev_err(dev, "Failed to enter sleep mode: %d\n", ret); + return ret; + } + msleep(120); + + return 0; +} + +static int visionox_vtdr6130_prepare(struct drm_panel *panel) +{ + struct visionox_vtdr6130 *ctx = to_visionox_vtdr6130(panel); + struct device *dev = &ctx->dsi->dev; + int ret; + + if (ctx->prepared) + return 0; + + ret = regulator_bulk_enable(ARRAY_SIZE(ctx->supplies), + ctx->supplies); + if (ret < 0) + return ret; + + visionox_vtdr6130_reset(ctx); + + ret = visionox_vtdr6130_on(ctx); + if (ret < 0) { + dev_err(dev, "Failed to initialize panel: %d\n", ret); + gpiod_set_value_cansleep(ctx->reset_gpio, 1); + regulator_bulk_disable(ARRAY_SIZE(ctx->supplies), ctx->supplies); + return ret; + } + + /* Explicitly disable DSC since compression is on by default on the panel */ + mipi_dsi_compression_mode(ctx->dsi, false); + + ctx->prepared = true; + return 0; +} + +static int visionox_vtdr6130_unprepare(struct drm_panel *panel) +{ + struct visionox_vtdr6130 *ctx = to_visionox_vtdr6130(panel); + struct device *dev = &ctx->dsi->dev; + int ret; + + if (!ctx->prepared) + return 0; + + ret = visionox_vtdr6130_off(ctx); + if (ret < 0) + dev_err(dev, "Failed to un-initialize panel: %d\n", ret); + + gpiod_set_value_cansleep(ctx->reset_gpio, 1); + + regulator_bulk_disable(ARRAY_SIZE(ctx->supplies), ctx->supplies); + + ctx->prepared = false; + return 0; +} + +static const struct drm_display_mode visionox_vtdr6130_mode = { + .clock = (1080 + 20 + 2 + 20) * (2400 + 20 + 2 + 18) * 144 / 1000, + .hdisplay = 1080, + .hsync_start = 1080 + 20, + .hsync_end = 1080 + 20 + 2, + .htotal = 1080 + 20 + 2 + 20, + .vdisplay = 2400, + .vsync_start = 2400 + 20, + .vsync_end = 2400 + 20 + 2, + .vtotal = 2400 + 20 + 2 + 18, + .width_mm = 0, + .height_mm = 0, +}; + +static int visionox_vtdr6130_get_modes(struct drm_panel *panel, + struct drm_connector *connector) +{ + struct drm_display_mode *mode; + + mode = drm_mode_duplicate(connector->dev, &visionox_vtdr6130_mode); + if (!mode) + return -ENOMEM; + + drm_mode_set_name(mode); + + mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED; + connector->display_info.width_mm = mode->width_mm; + connector->display_info.height_mm = mode->height_mm; + drm_mode_probed_add(connector, mode); + + return 1; +} + +static const struct drm_panel_funcs visionox_vtdr6130_panel_funcs = { + .prepare = visionox_vtdr6130_prepare, + .unprepare = visionox_vtdr6130_unprepare, + .get_modes = visionox_vtdr6130_get_modes, +}; + +static int visionox_vtdr6130_bl_update_status(struct backlight_device *bl) +{ + struct mipi_dsi_device *dsi = bl_get_data(bl); + u16 brightness = backlight_get_brightness(bl); + int ret; + + ret = mipi_dsi_dcs_set_display_brightness(dsi, cpu_to_le16(brightness)); + if (ret < 0) + return ret; + + return 0; +} + +static const struct backlight_ops visionox_vtdr6130_bl_ops = { + .update_status = visionox_vtdr6130_bl_update_status, +}; + +static struct backlight_device * +visionox_vtdr6130_create_backlight(struct mipi_dsi_device *dsi) +{ + struct device *dev = &dsi->dev; + const struct backlight_properties props = { + .type = BACKLIGHT_RAW, + .brightness = 4095, + .max_brightness = 4095, + }; + + return devm_backlight_device_register(dev, dev_name(dev), dev, dsi, + &visionox_vtdr6130_bl_ops, &props); +} + +static int visionox_vtdr6130_probe(struct mipi_dsi_device *dsi) +{ + struct device *dev = &dsi->dev; + struct visionox_vtdr6130 *ctx; + int ret; + + ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL); + if (!ctx) + return -ENOMEM; + + ctx->supplies[0].supply = "vddio"; + ctx->supplies[1].supply = "vci"; + ctx->supplies[2].supply = "vdd"; + + ret = devm_regulator_bulk_get(&dsi->dev, ARRAY_SIZE(ctx->supplies), + ctx->supplies); + if (ret < 0) + return ret; + + ctx->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW); + if (IS_ERR(ctx->reset_gpio)) + return dev_err_probe(dev, PTR_ERR(ctx->reset_gpio), + "Failed to get reset-gpios\n"); + + ctx->dsi = dsi; + mipi_dsi_set_drvdata(dsi, ctx); + + dsi->lanes = 4; + dsi->format = MIPI_DSI_FMT_RGB888; + dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_NO_EOT_PACKET | + MIPI_DSI_CLOCK_NON_CONTINUOUS; + + drm_panel_init(&ctx->panel, dev, &visionox_vtdr6130_panel_funcs, + DRM_MODE_CONNECTOR_DSI); + + ctx->panel.backlight = visionox_vtdr6130_create_backlight(dsi); + if (IS_ERR(ctx->panel.backlight)) + return dev_err_probe(dev, PTR_ERR(ctx->panel.backlight), + "Failed to create backlight\n"); + + drm_panel_add(&ctx->panel); + + ret = mipi_dsi_attach(dsi); + if (ret < 0) { + dev_err(dev, "Failed to attach to DSI host: %d\n", ret); + drm_panel_remove(&ctx->panel); + return ret; + } + + return 0; +} + +static void visionox_vtdr6130_remove(struct mipi_dsi_device *dsi) +{ + struct visionox_vtdr6130 *ctx = mipi_dsi_get_drvdata(dsi); + int ret; + + ret = mipi_dsi_detach(dsi); + if (ret < 0) + dev_err(&dsi->dev, "Failed to detach from DSI host: %d\n", ret); + + drm_panel_remove(&ctx->panel); +} + +static const struct of_device_id visionox_vtdr6130_of_match[] = { + { .compatible = "visionox,vtdr6130" }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, visionox_vtdr6130_of_match); + +static struct mipi_dsi_driver visionox_vtdr6130_driver = { + .probe = visionox_vtdr6130_probe, + .remove = visionox_vtdr6130_remove, + .driver = { + .name = "panel-visionox-vtdr6130", + .of_match_table = visionox_vtdr6130_of_match, + }, +}; +module_mipi_dsi_driver(visionox_vtdr6130_driver); + +MODULE_AUTHOR("Neil Armstron "); +MODULE_DESCRIPTION("Panel driver for the visionox VTDR6130 AMOLED DSI panel"); +MODULE_LICENSE("GPL");