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[2620:137:e000::1:20]) by mx.google.com with ESMTP id y20-20020a056402271400b0046a84b922a2si20439692edd.499.2022.12.31.05.08.25; Sat, 31 Dec 2022 05:08:50 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=NsR2jtqs; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235676AbiLaNIC (ORCPT + 99 others); Sat, 31 Dec 2022 08:08:02 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45960 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235648AbiLaNH7 (ORCPT ); Sat, 31 Dec 2022 08:07:59 -0500 Received: from mail-pj1-x102d.google.com (mail-pj1-x102d.google.com [IPv6:2607:f8b0:4864:20::102d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2E3A56261 for ; Sat, 31 Dec 2022 05:07:59 -0800 (PST) Received: by mail-pj1-x102d.google.com with SMTP id c8-20020a17090a4d0800b00225c3614161so21076935pjg.5 for ; Sat, 31 Dec 2022 05:07:59 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=03EcVfcgn594UPANtn877VRHUEcrNy316gwc2wdWerc=; b=NsR2jtqsrt3qzyDQmMkY9hX72wNshQRRtijNRgntkmZwYcvtH2uXkilcK36csmmuTx DnWpJXMX80s1FW/xzo9KtsRtpNz4bmUjVtie4frFR/h3/wXLiXQcOK9BRxsoe8SVcuYX ZlG2GOcH1zTc9RgOkFiQ7xNESfwSt0MEUzF2Udolh7Ml7/QPFSp7z2u6vs3n3+Uc4dAW RAu58jYejFvZKdww7Z9dPr1I8f25YDA86XuFK5QK4mGIrbPdQHC6Z2CL+KhsMyta8nW6 +SRhktdiRs/ax3aTwgpmiy7F+S3b+Ijl+w27DWVsHq8k7e8vTA6it2MycQluQN1t4esY yU7Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=03EcVfcgn594UPANtn877VRHUEcrNy316gwc2wdWerc=; b=M0MDmIN4xW58icj9Fh7OiA0G6rn16EeGxfMyD5Kxw+PZhJ8acIEG8ZHkWFf5yXPzn9 sP3zpYbBTAFsHpKxRC4luZymecbLUgWfCKoxj1K4nyWvSgPIxQyRVKPgsB+g9CURdFU8 LLf3zeiGvvSnN3t+I16W3URaJteKrF8cAmXtEegSdyeASD5iKSmZdBxvjaslFduVZGt8 WCP5Bc65nltwgU9p/2AIBAGdvNM2PqvpuvO8ZFGtZwOgBN4qOC14EFaEVOg9vre4DTgk ofrArDEFERk73ftzFQQULqLFRzcEmCrCmZozU1aP8ojQJssNIMWPAMBJeEijxxmIE4Yw AmXg== X-Gm-Message-State: AFqh2kpMqExdNJ4rzfJtij9pI0Yr4YIERzn/G4bxswMSg2pGQZ48wPvg ON7dyWgrx4kn5wEeDbTzSq9OYRyCCenAEFnttBU= X-Received: by 2002:a05:6a20:b297:b0:9d:efbf:7880 with SMTP id ei23-20020a056a20b29700b0009defbf7880mr37131383pzb.53.1672492078593; Sat, 31 Dec 2022 05:07:58 -0800 (PST) Received: from localhost.localdomain ([2401:4900:1c5e:e3b5:c341:16de:ce17:b857]) by smtp.gmail.com with ESMTPSA id d7-20020a17090ab30700b0021904307a53sm14568161pjr.19.2022.12.31.05.07.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 31 Dec 2022 05:07:58 -0800 (PST) From: Bhupesh Sharma To: linux-arm-msm@vger.kernel.org, linux-usb@vger.kernel.org, devicetree@vger.kernel.org Cc: quic_schowdhu@quicinc.com, agross@kernel.org, andersson@kernel.org, konrad.dybcio@linaro.org, gregkh@linuxfoundation.org, linux-kernel@vger.kernel.org, bhupesh.linux@gmail.com, bhupesh.sharma@linaro.org, robh+dt@kernel.org Subject: [PATCH 1/2] dt-bindings: soc: qcom: eud: Add SM6115 / SM4250 binding Date: Sat, 31 Dec 2022 18:37:42 +0530 Message-Id: <20221231130743.3285664-2-bhupesh.sharma@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221231130743.3285664-1-bhupesh.sharma@linaro.org> References: <20221231130743.3285664-1-bhupesh.sharma@linaro.org> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1753735107978714087?= X-GMAIL-MSGID: =?utf-8?q?1753735107978714087?= Add dt-bindings for EUD found on Qualcomm SM6115 / SM4250 SoC. On this SoC (and derivatives) the enable bit inside 'tcsr_check_reg' needs to be set first to 'enable' the eud module. So, update the dt-bindings to accommodate the third register property required by the driver on these SoCs. Cc: Souradeep Chowdhury Signed-off-by: Bhupesh Sharma --- .../devicetree/bindings/soc/qcom/qcom,eud.yaml | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,eud.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,eud.yaml index c98aab209bc5d..1dffe14868735 100644 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,eud.yaml +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,eud.yaml @@ -18,12 +18,22 @@ properties: items: - enum: - qcom,sc7280-eud + - qcom,sm6115-eud - const: qcom,eud reg: + minItems: 2 items: - description: EUD Base Register Region - description: EUD Mode Manager Register + - description: TCSR Check Register + + reg-names: + minItems: 2 + items: + - const: eud-base + - const: eud-mode-mgr + - const: tcsr-check-base interrupts: description: EUD interrupt From patchwork Sat Dec 31 13:07:43 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bhupesh Sharma X-Patchwork-Id: 37862 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4e01:0:0:0:0:0 with SMTP id p1csp3335028wrt; Sat, 31 Dec 2022 05:09:40 -0800 (PST) X-Google-Smtp-Source: AMrXdXuUc1VAtxKefDPkibDszegDjL7kVLxLRFq0vwEbkzaEXObFaISv7QMBFu3RaFjh5SfG+Lum X-Received: by 2002:a05:6402:1249:b0:48a:84da:538a with SMTP id l9-20020a056402124900b0048a84da538amr6151619edw.34.1672492180123; Sat, 31 Dec 2022 05:09:40 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1672492180; cv=none; d=google.com; s=arc-20160816; b=B/U3Rdapb1fY4hFGbGol76TqriGiSzcYLh+964bKhuBD7jONUsyA0vvkifKsopb5RX r61fXkCiZ4c4a7ffSD7Ia82iN6x7OZo9HSDoifJvnsIgMjv837MTkhw7yw+9rOPzv/rC amda6q9xxNmNxzcsfNkkPHiv+6ebtLO/DA0hwXJ+rmGsIe/PxuzpZnkLY0wiCF7sKAaT K+zIp6FnZ/neZT6TWF7RT26J95O8sh8/YbivKZPgmE8wnpY7TGquTIqej+FvfJeM2kof 2BM9c82BeMVlI1LFzImMXynNuCcmp1iAceYsy2D08cdVpTTL2KCCdLMVwB7Gp+9Bj8Yg vGDw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=X0IXPVtq9K1twOTm6NDDEYDtsm5gy6I4CxkJN0usls4=; b=kvIyAbw+HOJe9XQIJL4qTXq1quswg/joFa7XxhYi3xMafG0/7EglnvuNrqMpPCYfyP KtJ6xKGrx6SshztxNaMymvzkPdQhtE9E2UYzIH9nQh90SdvPdxfcatpYzHJ7WmWX2H2t /3ehVcJTrRKmDycQrYUMVLwVtWgPu0n0z1PrM0rn7Hvpi1TlOKVl2aLtt87cqKZ0IlCi u3+2t1hKsImr9ta8G6tF0768bYr9M2l7nSU9otR9N89V+URhfYn5cJkgWJvziLErJJyv K67NmmO3kfe/Rtgu2gRsqHPdrhLkcJfgOrGD+aGXUm3bMSRIrTxOLBBL0wvimSrhTKx3 iwZg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=NPUExoCX; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. 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On some SoCs (like the SM6115 / SM4250 SoC), the mode manager needs to be accessed only via the secure world (through 'scm' calls). Also, the enable bit inside 'tcsr_check_reg' needs to be set first to set the eud in 'enable' mode on these SoCs. Cc: Souradeep Chowdhury Signed-off-by: Bhupesh Sharma --- drivers/usb/misc/qcom_eud.c | 49 ++++++++++++++++++++++++++++++++++--- 1 file changed, 46 insertions(+), 3 deletions(-) diff --git a/drivers/usb/misc/qcom_eud.c b/drivers/usb/misc/qcom_eud.c index b7f13df007646..a96ca28a4899b 100644 --- a/drivers/usb/misc/qcom_eud.c +++ b/drivers/usb/misc/qcom_eud.c @@ -11,7 +11,9 @@ #include #include #include +#include #include +#include #include #include #include @@ -30,15 +32,24 @@ #define EUD_INT_SAFE_MODE BIT(4) #define EUD_INT_ALL (EUD_INT_VBUS | EUD_INT_SAFE_MODE) +struct eud_soc_data { + bool secure_eud_en; + bool tcsr_check_enable; +}; + struct eud_chip { struct device *dev; struct usb_role_switch *role_sw; + const struct eud_soc_data *eud_data; void __iomem *base; void __iomem *mode_mgr; unsigned int int_status; int irq; bool enabled; bool usb_attached; + phys_addr_t mode_mgr_phys_base; + phys_addr_t tcsr_check_phys_base; + }; static int enable_eud(struct eud_chip *priv) @@ -46,7 +57,11 @@ static int enable_eud(struct eud_chip *priv) writel(EUD_ENABLE, priv->base + EUD_REG_CSR_EUD_EN); writel(EUD_INT_VBUS | EUD_INT_SAFE_MODE, priv->base + EUD_REG_INT1_EN_MASK); - writel(1, priv->mode_mgr + EUD_REG_EUD_EN2); + + if (priv->eud_data->secure_eud_en) + qcom_scm_io_writel(priv->mode_mgr_phys_base + EUD_REG_EUD_EN2, BIT(0)); + else + writel(1, priv->mode_mgr + EUD_REG_EUD_EN2); return usb_role_switch_set_role(priv->role_sw, USB_ROLE_DEVICE); } @@ -54,7 +69,11 @@ static int enable_eud(struct eud_chip *priv) static void disable_eud(struct eud_chip *priv) { writel(0, priv->base + EUD_REG_CSR_EUD_EN); - writel(0, priv->mode_mgr + EUD_REG_EUD_EN2); + + if (priv->eud_data->secure_eud_en) + qcom_scm_io_writel(priv->mode_mgr_phys_base + EUD_REG_EUD_EN2, 0); + else + writel(0, priv->mode_mgr + EUD_REG_EUD_EN2); } static ssize_t enable_show(struct device *dev, @@ -178,12 +197,15 @@ static void eud_role_switch_release(void *data) static int eud_probe(struct platform_device *pdev) { struct eud_chip *chip; + struct resource *res; int ret; chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL); if (!chip) return -ENOMEM; + chip->eud_data = of_device_get_match_data(&pdev->dev); + chip->dev = &pdev->dev; chip->role_sw = usb_role_switch_get(&pdev->dev); @@ -200,10 +222,25 @@ static int eud_probe(struct platform_device *pdev) if (IS_ERR(chip->base)) return PTR_ERR(chip->base); - chip->mode_mgr = devm_platform_ioremap_resource(pdev, 1); + chip->mode_mgr = devm_platform_get_and_ioremap_resource(pdev, 1, &res); if (IS_ERR(chip->mode_mgr)) return PTR_ERR(chip->mode_mgr); + if (chip->eud_data->secure_eud_en) + chip->mode_mgr_phys_base = res->start; + + if (chip->eud_data->tcsr_check_enable) { + res = platform_get_resource(pdev, IORESOURCE_MEM, 2); + if (!res) + return dev_err_probe(chip->dev, -ENODEV, "failed to get tcsr reg base\n"); + + chip->tcsr_check_phys_base = res->start; + + ret = qcom_scm_io_writel(chip->tcsr_check_phys_base, BIT(0)); + if (ret) + return dev_err_probe(chip->dev, ret, "failed to write tcsr check reg\n"); + } + chip->irq = platform_get_irq(pdev, 0); ret = devm_request_threaded_irq(&pdev->dev, chip->irq, handle_eud_irq, handle_eud_irq_thread, IRQF_ONESHOT, NULL, chip); @@ -230,8 +267,14 @@ static int eud_remove(struct platform_device *pdev) return 0; } +static const struct eud_soc_data sm6115_eud_data = { + .secure_eud_en = true, + .tcsr_check_enable = true, +}; + static const struct of_device_id eud_dt_match[] = { { .compatible = "qcom,sc7280-eud" }, + { .compatible = "qcom,sm6115-eud", .data = &sm6115_eud_data }, { } }; MODULE_DEVICE_TABLE(of, eud_dt_match);