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[2a01:c22:cd9d:4b00:ef17:3c78:1696:7315]) by smtp.gmail.com with ESMTPSA id c10-20020a056402158a00b00482c1f1a039sm8350500edv.30.2022.12.30.12.35.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Dec 2022 12:35:43 -0800 (PST) From: =?utf-8?q?Bernhard_Rosenkr=C3=A4nzer?= To: linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-usb@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, matthias.bgg@gmail.com, krzysztof.kozlowski+dt@linaro.org, robh+dt@kernel.org, gregkh@linuxfoundation.org, chunfeng.yun@mediatek.com, linus.walleij@linaro.org, lee@kernel.org, maz@kernel.org, tglx@linutronix.de, angelogioacchino.delregno@collabora.com Subject: [PATCH v6 1/7] dt-bindings: arm64: dts: mediatek: Add mt8365-evk board Date: Fri, 30 Dec 2022 21:35:35 +0100 Message-Id: <20221230203541.146807-2-bero@baylibre.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20221230203541.146807-1-bero@baylibre.com> References: <20221230203541.146807-1-bero@baylibre.com> MIME-Version: 1.0 X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1753672792326569533?= X-GMAIL-MSGID: =?utf-8?q?1753672792326569533?= Add bindings for the Mediatek mt8365-evk board. Signed-off-by: Bernhard Rosenkränzer Acked-by: Krzysztof Kozlowski Reviewed-by: AngeloGioacchino Del Regno --- Documentation/devicetree/bindings/arm/mediatek.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/mediatek.yaml b/Documentation/devicetree/bindings/arm/mediatek.yaml index 2275e5d93721b..ae12b1cab9fbd 100644 --- a/Documentation/devicetree/bindings/arm/mediatek.yaml +++ b/Documentation/devicetree/bindings/arm/mediatek.yaml @@ -244,6 +244,10 @@ properties: - enum: - mediatek,mt8183-pumpkin - const: mediatek,mt8183 + - items: + - enum: + - mediatek,mt8365-evk + - const: mediatek,mt8365 - items: - enum: - mediatek,mt8516-pumpkin From patchwork Fri Dec 30 20:35:36 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Bernhard_Rosenkr=C3=A4nzer?= X-Patchwork-Id: 37765 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4e01:0:0:0:0:0 with SMTP id p1csp3057740wrt; Fri, 30 Dec 2022 12:36:54 -0800 (PST) X-Google-Smtp-Source: AMrXdXt0W9uv6F9oQZBLjgCfr3685Wg1Nmj+z7KukbyEsEuJYhEGWAEY8vixCpPIHOOt6LMkG1ek X-Received: by 2002:a05:6402:540f:b0:479:96c2:61be with SMTP id ev15-20020a056402540f00b0047996c261bemr36403949edb.10.1672432613989; Fri, 30 Dec 2022 12:36:53 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1672432613; cv=none; d=google.com; s=arc-20160816; b=0Lf5jhNPkv63WdpXqQd85vxpVScfdAUpkB8Nv1ZemF6mckwuWVXbZBk2KjVnDROIcR d9QptxaIQ/Gnd7/8zcat4gxiDArz5B+IqSReg+8eD3kCg2D5I9SaRasGj8BSnfFRSC6T g9miq+0d3nw3NZgW/unAe63IaAi3i9crUIukoHh57HNb2HeU6ti1uyaSQHofl9iJqt0h ZjywhmREPRNZRMyRkr8uS+rpjrY2pUX1nAJjobm+fjFXwUUQ2geaYIamDwvEZbiBfix/ r4A5r7KWTb7waIXWjFGgr7vgsH6CSn9/TU28YoVQePzwZOZgCzLZA4Psp7eRD7CXKZ2p q0ig== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=3Kf0xOoeDeJQWB1TH03nWqIDkbfzo3q+4qiIvdKLrU4=; b=JmpobyEfMHVCcxqnUBhAcFJOA1yZr2YUBWLv6q8lJB1M5/SuXvdYx4uANw1aeIUdN+ KdytE6H7thLWF/b4byJ0jHD99u0d7jxaZdjbA1c52hMyg3vZmr7X+hUVnLshY2GoH67d yI5qaMfHjUKBTLONZ6hYMYDGvFYtDdlevaYnV21Y9Nc0PclbWShCIHMkZV8GmHN3/NH6 WEfMyQzgdNC8FC6lC24zOqsKgrJUYNx4rxbXVEHFG0jA1GbSwfEGxdhVYjHHHpD+4TzN +qUBAduJOr0AS8RDQNNnNS/w2fRQ0SG0ZriYiv/l000wkIhtFh3Dk1qQDj8FbgstpQBJ tcEA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@baylibre-com.20210112.gappssmtp.com header.s=20210112 header.b=LLQoS38O; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. 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[2a01:c22:cd9d:4b00:ef17:3c78:1696:7315]) by smtp.gmail.com with ESMTPSA id c10-20020a056402158a00b00482c1f1a039sm8350500edv.30.2022.12.30.12.35.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Dec 2022 12:35:44 -0800 (PST) From: =?utf-8?q?Bernhard_Rosenkr=C3=A4nzer?= To: linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-usb@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, matthias.bgg@gmail.com, krzysztof.kozlowski+dt@linaro.org, robh+dt@kernel.org, gregkh@linuxfoundation.org, chunfeng.yun@mediatek.com, linus.walleij@linaro.org, lee@kernel.org, maz@kernel.org, tglx@linutronix.de, angelogioacchino.delregno@collabora.com Subject: [PATCH v6 2/7] dt-bindings: irq: mtk, sysirq: add support for mt8365 Date: Fri, 30 Dec 2022 21:35:36 +0100 Message-Id: <20221230203541.146807-3-bero@baylibre.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20221230203541.146807-1-bero@baylibre.com> References: <20221230203541.146807-1-bero@baylibre.com> MIME-Version: 1.0 X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1753672700739272693?= X-GMAIL-MSGID: =?utf-8?q?1753672700739272693?= Add binding documentation of mediatek,sysirq for mt8365 SoC. Signed-off-by: Bernhard Rosenkränzer Acked-by: Krzysztof Kozlowski Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Matthias Brugger --- .../devicetree/bindings/interrupt-controller/mediatek,sysirq.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt b/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt index 84ced3f4179b9..3ffc60184e445 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt +++ b/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt @@ -25,6 +25,7 @@ Required properties: "mediatek,mt6577-sysirq": for MT6577 "mediatek,mt2712-sysirq", "mediatek,mt6577-sysirq": for MT2712 "mediatek,mt2701-sysirq", "mediatek,mt6577-sysirq": for MT2701 + "mediatek,mt8365-sysirq", "mediatek,mt6577-sysirq": for MT8365 - interrupt-controller : Identifies the node as an interrupt controller - #interrupt-cells : Use the same format as specified by GIC in arm,gic.txt. - reg: Physical base address of the intpol registers and length of memory From patchwork Fri Dec 30 20:35:37 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Bernhard_Rosenkr=C3=A4nzer?= X-Patchwork-Id: 37772 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4e01:0:0:0:0:0 with SMTP id p1csp3058323wrt; Fri, 30 Dec 2022 12:38:53 -0800 (PST) X-Google-Smtp-Source: AMrXdXsU3WIWGtkH/snG2jEtsaInASPJL2OQ8f/f6hgjueiaj1NCV1w5FyWQY6wqRoLiMDdz1/J+ X-Received: by 2002:a17:902:854a:b0:192:7a02:31a7 with SMTP id d10-20020a170902854a00b001927a0231a7mr21859267plo.49.1672432733413; Fri, 30 Dec 2022 12:38:53 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1672432733; cv=none; d=google.com; s=arc-20160816; b=qRZVdfW6EzPip6tVWmj7PXIjon2yO/FEfrYpUFb7O5374K+E0sFMSENuAjQVEw5HGe 6lan62cwcEiFcYG9GxWoXkeTO5wTRCImJ+sPjZMTLKFV0O/tql6zUhF18y1o+BJWvhXz 62tmcathopnXvhMnSr1y+oOpuED7iyzHzuWoFquPrM8QGcPkMF4G7pzU4i3VK/Q7HltQ QMndRPjLn0qvoVYpj9OxTEFa86SN6jTY4J4sKI4ERH25gKlZrDMRtym/iDS/v644Es3f EpZmfd/d3o8prFnu8JPZD7kt7r+vNrbCnft0IJVZATGVcMxvIT24j6KcNrh10r6Tus4Z WoDg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=bGuxAnhfIj2x3uYPeVPB/2g8dAYaMTxAZOm/4EaT1sM=; b=X8BtZC6u38znF3ndpQdfC+T3e+MuaGYDZfl4dLPi3tgdBKQgqjafmeT3stB/aruDUv IGHJYtbKnyhV/IUajdQcBdpMhMsE+ez6HFzpFyjOl0e6LkWTK7vPsdAEBCavcj64kkPb riZmPOXjSq/hqasTwe826zsmSiVebW61QtPZ5JfCdbsk2vlX2c1UcGOmsY3I5VgN898i OQa3cWc+FYIIRcYuY7oTRisj28RjX8qy81/CJdzVQMNa0LVJhYDhnCDmXdwU01Stz5qP xYFbdDqVXjpuuOSooyOSntQLXDVgxeBHmYBchALmryGSqF4FoqPYxjLnrQGddswEYsYG qPtA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@baylibre-com.20210112.gappssmtp.com header.s=20210112 header.b=jrBQbD2n; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. 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[2a01:c22:cd9d:4b00:ef17:3c78:1696:7315]) by smtp.gmail.com with ESMTPSA id c10-20020a056402158a00b00482c1f1a039sm8350500edv.30.2022.12.30.12.35.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Dec 2022 12:35:45 -0800 (PST) From: =?utf-8?q?Bernhard_Rosenkr=C3=A4nzer?= To: linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-usb@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, matthias.bgg@gmail.com, krzysztof.kozlowski+dt@linaro.org, robh+dt@kernel.org, gregkh@linuxfoundation.org, chunfeng.yun@mediatek.com, linus.walleij@linaro.org, lee@kernel.org, maz@kernel.org, tglx@linutronix.de, angelogioacchino.delregno@collabora.com Subject: [PATCH v6 3/7] dt-bindings: mfd: syscon: Add mt8365-syscfg Date: Fri, 30 Dec 2022 21:35:37 +0100 Message-Id: <20221230203541.146807-4-bero@baylibre.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20221230203541.146807-1-bero@baylibre.com> References: <20221230203541.146807-1-bero@baylibre.com> MIME-Version: 1.0 X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1753672825749730524?= X-GMAIL-MSGID: =?utf-8?q?1753672825749730524?= Document Mediatek mt8365-syscfg Signed-off-by: Bernhard Rosenkränzer Acked-by: Krzysztof Kozlowski Reviewed-by: Matthias Brugger --- Documentation/devicetree/bindings/mfd/syscon.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/mfd/syscon.yaml b/Documentation/devicetree/bindings/mfd/syscon.yaml index 1b01bd0104316..7beeb0abc4db0 100644 --- a/Documentation/devicetree/bindings/mfd/syscon.yaml +++ b/Documentation/devicetree/bindings/mfd/syscon.yaml @@ -50,6 +50,7 @@ properties: - marvell,armada-3700-usb2-host-misc - mediatek,mt8135-pctl-a-syscfg - mediatek,mt8135-pctl-b-syscfg + - mediatek,mt8365-syscfg - microchip,lan966x-cpu-syscon - microchip,sparx5-cpu-syscon - mstar,msc313-pmsleep From patchwork Fri Dec 30 20:35:38 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Bernhard_Rosenkr=C3=A4nzer?= X-Patchwork-Id: 37771 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4e01:0:0:0:0:0 with SMTP id p1csp3058304wrt; Fri, 30 Dec 2022 12:38:46 -0800 (PST) X-Google-Smtp-Source: AMrXdXuGFhH0oST1WdcPPQEXmFGK1Bu4lBkEj2ygOB93m1tP+52dgzrc5ubzdvuLJeBAprX14Q1c X-Received: by 2002:a05:6a20:d807:b0:a8:79bc:dfae with SMTP id iv7-20020a056a20d80700b000a879bcdfaemr41730869pzb.20.1672432725758; Fri, 30 Dec 2022 12:38:45 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1672432725; cv=none; d=google.com; s=arc-20160816; b=aSpoxygiFQQ9RgpACEAfC7z8851nbgLeLPXi+siZUTdaQCzQ4s4ufBdXBC8wIpbSql 5Oav+PukjXFubqeiI8/xOUnkuEAYghj46wdGX9VLyBVVGx1vRRYtI+zBptmFWe7WrUyG 9UxCqONGmMS+1UmwBowd5OStnG9czyML+agiVmYFL58Ghj2fmT/33+1CNAXE5RG4dwBY UqvUMFMJdKW4HJ3HGGG6I7slYuQeH220tu34gRexmirwePS/bBYAXb/JG+Kw6Hb1ox95 gg2wNiW+ehDTsfvCICKDYFuT3dfs/OnQQsSGbfGNLCRmv0pIDKUlVrB49lOcwrq39C+3 CaVw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=X/YvHElO1B1L96Q/ryL2GcQHBR6R6iwvqncvsZcjNEM=; b=bmhOCVTHFyLCqdQYCcvFw/wruRgyT3zzmVBoaiOzF4ebowb5JAtSTpscC2M9X0krjQ W1x7dmyyzgcaizzVldis8q5mkbA0zYpK/QVn4Xp6dvW8Ok5qNDlGkLEoSw2jaPdM4aRA jb/f61fqaa4G3yKSgtcOJyR+Wkgn5IS986p3g5nkCi+rp5hXDuYtP11F/FmlN0wiVF3a +9aYnbCNEXXr3r3bWDnhhesceXKG2xn4u2NCmUTX2qsOg9xkeZIijTrccEw6xXRJ95IZ ypqarKn0p8wC8Bhd7S/AyZ6gYbR8Lfc73V7PKBhSX/Ak5yOewzBPpC0rv4VC/YNyTnEv 15kA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@baylibre-com.20210112.gappssmtp.com header.s=20210112 header.b="FwHXJj/0"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. 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[2a01:c22:cd9d:4b00:ef17:3c78:1696:7315]) by smtp.gmail.com with ESMTPSA id c10-20020a056402158a00b00482c1f1a039sm8350500edv.30.2022.12.30.12.35.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Dec 2022 12:35:46 -0800 (PST) From: =?utf-8?q?Bernhard_Rosenkr=C3=A4nzer?= To: linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-usb@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, matthias.bgg@gmail.com, krzysztof.kozlowski+dt@linaro.org, robh+dt@kernel.org, gregkh@linuxfoundation.org, chunfeng.yun@mediatek.com, linus.walleij@linaro.org, lee@kernel.org, maz@kernel.org, tglx@linutronix.de, angelogioacchino.delregno@collabora.com Subject: [PATCH v6 4/7] dt-bindings: pinctrl: add bindings for Mediatek MT8365 SoC Date: Fri, 30 Dec 2022 21:35:38 +0100 Message-Id: <20221230203541.146807-5-bero@baylibre.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20221230203541.146807-1-bero@baylibre.com> References: <20221230203541.146807-1-bero@baylibre.com> MIME-Version: 1.0 X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1753672817827305592?= X-GMAIL-MSGID: =?utf-8?q?1753672817827305592?= Add devicetree bindings for Mediatek MT8365 pinctrl driver. Signed-off-by: Bernhard Rosenkränzer --- .../pinctrl/mediatek,mt8365-pinctrl.yaml | 197 ++++++++++++++++++ 1 file changed, 197 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/mediatek,mt8365-pinctrl.yaml diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt8365-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8365-pinctrl.yaml new file mode 100644 index 0000000000000..4b96884a1afc7 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8365-pinctrl.yaml @@ -0,0 +1,197 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/mediatek,mt8365-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Mediatek MT8365 Pin Controller + +maintainers: + - Zhiyong Tao + - Bernhard Rosenkränzer + +description: | + The MediaTek's MT8365 Pin controller is used to control SoC pins. + +properties: + compatible: + const: mediatek,mt8365-pinctrl + + reg: + maxItems: 1 + + mediatek,pctl-regmap: + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + maxItems: 1 + minItems: 1 + maxItems: 2 + description: | + Should be phandles of the syscfg node. + + gpio-controller: true + + "#gpio-cells": + const: 2 + description: | + Number of cells in GPIO specifier. Since the generic GPIO + binding is used, the amount of cells must be specified as 2. See the below + mentioned gpio binding representation for description of particular cells. + + interrupt-controller: true + + interrupts: + maxItems: 1 + + "#interrupt-cells": + const: 2 + +patternProperties: + "-pins$": + type: object + additionalProperties: false + patternProperties: + "pins$": + type: object + additionalProperties: false + description: | + A pinctrl node should contain at least one subnode representing the + pinctrl groups available on the machine. Each subnode will list the + pins it needs, and how they should be configured, with regard to muxer + configuration, pullups, drive strength, input enable/disable and input + schmitt. + $ref: /schemas/pinctrl/pincfg-node.yaml + + properties: + pinmux: + description: + integer array, represents gpio pin number and mux setting. + Supported pin number and mux varies for different SoCs, and are + defined as macros in -pinfunc.h directly. + + bias-disable: true + + bias-pull-up: + description: | + Besides generic pinconfig options, it can be used as the pull up + settings for 2 pull resistors, R0 and R1. User can configure those + special pins. + + bias-pull-down: true + + input-enable: true + + input-disable: true + + output-low: true + + output-high: true + + input-schmitt-enable: true + + input-schmitt-disable: true + + mediatek,drive-strength-adv: + description: | + Describe the specific driving setup property. + For I2C pins, the existing generic driving setup can only support + 2/4/6/8/10/12/14/16mA driving. But in specific driving setup, they + can support 0.125/0.25/0.5/1mA adjustment. If we enable specific + driving setup, the existing generic setup will be disabled. + The specific driving setup is controlled by E1E0EN. + When E1=0/E0=0, the strength is 0.125mA. + When E1=0/E0=1, the strength is 0.25mA. + When E1=1/E0=0, the strength is 0.5mA. + When E1=1/E0=1, the strength is 1mA. + EN is used to enable or disable the specific driving setup. + Valid arguments are described as below: + 0: (E1, E0, EN) = (0, 0, 0) + 1: (E1, E0, EN) = (0, 0, 1) + 2: (E1, E0, EN) = (0, 1, 0) + 3: (E1, E0, EN) = (0, 1, 1) + 4: (E1, E0, EN) = (1, 0, 0) + 5: (E1, E0, EN) = (1, 0, 1) + 6: (E1, E0, EN) = (1, 1, 0) + 7: (E1, E0, EN) = (1, 1, 1) + So the valid arguments are from 0 to 7. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2, 3, 4, 5, 6, 7] + + mediatek,pull-up-adv: + description: | + Pull up setings for 2 pull resistors, R0 and R1. User can + configure those special pins. Valid arguments are described as below: + 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled. + 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled. + 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled. + 3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2, 3] + + mediatek,pull-down-adv: + description: | + Pull down settings for 2 pull resistors, R0 and R1. User can + configure those special pins. Valid arguments are described as below: + 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled. + 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled. + 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled. + 3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2, 3] + + mediatek,tdsel: + description: | + An integer describing the steps for output level shifter duty + cycle when asserted (high pulse width adjustment). Valid arguments + are from 0 to 15. + $ref: /schemas/types.yaml#/definitions/uint32 + + mediatek,rdsel: + description: | + An integer describing the steps for input level shifter duty cycle + when asserted (high pulse width adjustment). Valid arguments are + from 0 to 63. + $ref: /schemas/types.yaml#/definitions/uint32 + + required: + - pinmux + +required: + - compatible + - reg + - gpio-controller + - "#gpio-cells" + +allOf: + - $ref: pinctrl.yaml# + +additionalProperties: false + +examples: + - | + #include + #include + soc { + #address-cells = <2>; + #size-cells = <2>; + + pio: pinctrl@1000b000 { + compatible = "mediatek,mt8365-pinctrl"; + reg = <0 0x1000b000 0 0x1000>; + mediatek,pctl-regmap = <&syscfg_pctl>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = ; + + pio-pins { + pins { + pinmux = , ; + mediatek,pull-up-adv = <3>; + mediatek,drive-strength-adv = <00>; + bias-pull-up; + }; + }; + }; + }; From patchwork Fri Dec 30 20:35:39 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Bernhard_Rosenkr=C3=A4nzer?= X-Patchwork-Id: 37767 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4e01:0:0:0:0:0 with SMTP id p1csp3058188wrt; Fri, 30 Dec 2022 12:38:21 -0800 (PST) X-Google-Smtp-Source: AMrXdXtsiExS6N5jscKHyixLSzuaIvZk1bxzDmOJrPNL1m1zB42X6UzuNDp9KzbpOkiz29fIiWeJ X-Received: by 2002:a17:90b:1985:b0:226:5263:d990 with SMTP id mv5-20020a17090b198500b002265263d990mr805948pjb.20.1672432701184; Fri, 30 Dec 2022 12:38:21 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1672432701; cv=none; d=google.com; s=arc-20160816; b=KJdMfdSzHvVZfR0iGjRsAcQvpSl0aOdpNUGkAp0NqV3wQwBxG3jraFcc8vXnK57acu vBe/dIAtODDfeuS3AzNpE+4ETswPywqaWaeFeUs3yDa+27c7wmC+Aa85a04CCdOuhhiw m21adaqRCYZ+9yWzfuLyUM7HUNHhlVFlwtMKSD34bpVhvyatzrppDJ1hgWgdYglACcap rQAMdLWtbbDgT3NR5wQK38Rt3oe1PQV5tYxnblAAE6976/cv/pM4jSFqGnxtjXbvl1Yh opuH6My7wzXJw9pTMjhGGibWfKbXubEe1ITB5Tw/41dN3xWzHaGeggrdewoVrRrhoFRH BrVw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=nQFWSjnAmXGCxMB5DVpOmGczTzlI1ebWvjBAsrHPlS4=; b=L/1xPOBwcfZpMdjjQUf4OK0NlGoN8jgL3cJmHdC8P8hhLgpRLiPUAhEGb2D1/F99zM jIheQgaR9P0AETZnyxuw+jpsuMW3I42gImvrlJG2YD2tVR9VMG4rCjhVYDUE9qUT8vfg gDhK3Oh9VPiTSARs62eajpA3xyEmbGmO3tgVzXIj67cFeNjcIph3OqcQOY2SbBUJ2zLi kZ3XU8sZpcGioX3tYdBpG7pv7aH915Du3w+UBgFD9wSL4ENuT6s/nbGcPIx5JBl2bwj0 Eto+/yUekdmn/St0Xe8V61ZxiU2ECBhtvKkOj7gyebGS8UAQfWv8TWhYavk1CGDaq4o6 3scQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@baylibre-com.20210112.gappssmtp.com header.s=20210112 header.b=1nNFGNhv; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. 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[2a01:c22:cd9d:4b00:ef17:3c78:1696:7315]) by smtp.gmail.com with ESMTPSA id c10-20020a056402158a00b00482c1f1a039sm8350500edv.30.2022.12.30.12.35.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Dec 2022 12:35:47 -0800 (PST) From: =?utf-8?q?Bernhard_Rosenkr=C3=A4nzer?= To: linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-usb@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, matthias.bgg@gmail.com, krzysztof.kozlowski+dt@linaro.org, robh+dt@kernel.org, gregkh@linuxfoundation.org, chunfeng.yun@mediatek.com, linus.walleij@linaro.org, lee@kernel.org, maz@kernel.org, tglx@linutronix.de, angelogioacchino.delregno@collabora.com Subject: [PATCH v6 5/7] dt-bindings: usb: mediatek,mtu3: add MT8365 SoC bindings Date: Fri, 30 Dec 2022 21:35:39 +0100 Message-Id: <20221230203541.146807-6-bero@baylibre.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20221230203541.146807-1-bero@baylibre.com> References: <20221230203541.146807-1-bero@baylibre.com> MIME-Version: 1.0 X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1753672792170069540?= X-GMAIL-MSGID: =?utf-8?q?1753672792170069540?= From: Fabien Parent Add binding documentation for the MT8365 SoC. Signed-off-by: Fabien Parent Acked-by: Krzysztof Kozlowski Signed-off-by: Bernhard Rosenkränzer Reviewed-by: Matthias Brugger Reviewed-by: Chunfeng Yun --- Documentation/devicetree/bindings/usb/mediatek,mtu3.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/usb/mediatek,mtu3.yaml b/Documentation/devicetree/bindings/usb/mediatek,mtu3.yaml index 7168110e2f9de..d2655173e108c 100644 --- a/Documentation/devicetree/bindings/usb/mediatek,mtu3.yaml +++ b/Documentation/devicetree/bindings/usb/mediatek,mtu3.yaml @@ -28,6 +28,7 @@ properties: - mediatek,mt8188-mtu3 - mediatek,mt8192-mtu3 - mediatek,mt8195-mtu3 + - mediatek,mt8365-mtu3 - const: mediatek,mtu3 reg: From patchwork Fri Dec 30 20:35:40 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Bernhard_Rosenkr=C3=A4nzer?= X-Patchwork-Id: 37768 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4e01:0:0:0:0:0 with SMTP id p1csp3058189wrt; Fri, 30 Dec 2022 12:38:21 -0800 (PST) X-Google-Smtp-Source: AMrXdXvndvCECTOdfuGWGgIqNlypucM6drboNEbS64cmsNhCs6Y+Onh3/UzgbZ3NzhucBov/+1pc X-Received: by 2002:a62:f211:0:b0:581:68ea:50 with SMTP id m17-20020a62f211000000b0058168ea0050mr14071422pfh.26.1672432701241; Fri, 30 Dec 2022 12:38:21 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1672432701; cv=none; d=google.com; s=arc-20160816; b=icTXapMpn7aDreqbkgPsAGSsPQpI2YUaaxKTNdHMdBJVw/EP30BpNXzdPEDuqkQM7J xb5uRRQGE2rXT02OV2WQZIzX1eMObVoc8GVnXbo79+2Nkfiqt9uSrZx2Nyaj30DMdkwI 1eoiXIwP3o/yCbKQISXGIQmbUYwxe/caqK4B2c8eJHINzSZmpxfV1il0p2dhPTMieSIo 8gL2YOPP+AyY9jbdg/nwCao1gFWwbvz0uWnrTaUdz5CRuOXuMjVC/nNSJGIMafCQeILM JxFTz51zXXXEmV+zN47Q6slUve6Ps4BGJpyBmBBcCsLr54K5PFm9hGXsWNbSPtJxfjWy +Peg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=yM7tLQukK3ee+o3GHKaxNTtqE120eC/46qEVclUSCs4=; b=Qil0egLwDmB7aCCkwFofotpeVvL5OwrQimf/tvi6xQk8qeL5hGKk88tOwnuNsmfzZV oh9OFYkCIyJXmAGmmUzaSISL/yMUpKgicBLAD5Lz1BmQ3RWIOS+AkEe4mNWL+VXKBQoq oxv9El/PoOrBLSpHt2/TcGo7iyLSbVEni6rg9gtBDoIX3HJ+Ha+8Qr4wXLaChsvPMimO uT500OnagqgFtAV0qR+flZPNz+apwNccsqxZ2lDgfzllSaFMoMbxofuk6TiMJOCgnCQq 5AbXkjK2DkfEDH4/mpBfFsBxjLVKACz2AeBvB5HskNBTm/GNUD5viVdGXKfi873WIC4f ThSg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@baylibre-com.20210112.gappssmtp.com header.s=20210112 header.b=t5pna3Qq; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. 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[2a01:c22:cd9d:4b00:ef17:3c78:1696:7315]) by smtp.gmail.com with ESMTPSA id c10-20020a056402158a00b00482c1f1a039sm8350500edv.30.2022.12.30.12.35.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Dec 2022 12:35:48 -0800 (PST) From: =?utf-8?q?Bernhard_Rosenkr=C3=A4nzer?= To: linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-usb@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, matthias.bgg@gmail.com, krzysztof.kozlowski+dt@linaro.org, robh+dt@kernel.org, gregkh@linuxfoundation.org, chunfeng.yun@mediatek.com, linus.walleij@linaro.org, lee@kernel.org, maz@kernel.org, tglx@linutronix.de, angelogioacchino.delregno@collabora.com Subject: [PATCH v6 6/7] dt-bindings: usb: mediatek,mtk-xhci: add MT8365 SoC bindings Date: Fri, 30 Dec 2022 21:35:40 +0100 Message-Id: <20221230203541.146807-7-bero@baylibre.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20221230203541.146807-1-bero@baylibre.com> References: <20221230203541.146807-1-bero@baylibre.com> MIME-Version: 1.0 X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1753672792086278591?= X-GMAIL-MSGID: =?utf-8?q?1753672792086278591?= From: Fabien Parent Add binding documentation for the MT8365 SoC. Signed-off-by: Fabien Parent [bero@baylibre.com: Cleanups suggested by reviewers] Signed-off-by: Bernhard Rosenkränzer Acked-by: Krzysztof Kozlowski Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Matthias Brugger Reviewed-by: Chunfeng Yun --- Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.yaml b/Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.yaml index a3c37944c6305..c119caa9ad168 100644 --- a/Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.yaml +++ b/Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.yaml @@ -35,6 +35,7 @@ properties: - mediatek,mt8188-xhci - mediatek,mt8192-xhci - mediatek,mt8195-xhci + - mediatek,mt8365-xhci - const: mediatek,mtk-xhci reg: From patchwork Fri Dec 30 20:35:41 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Bernhard_Rosenkr=C3=A4nzer?= X-Patchwork-Id: 37769 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4e01:0:0:0:0:0 with SMTP id p1csp3058187wrt; Fri, 30 Dec 2022 12:38:21 -0800 (PST) X-Google-Smtp-Source: AMrXdXvIYdKClZbOE+aMv6K4+7Ok/HKxmUJV91SKV4YzAK5PvOtpMjpwPzKE8LUFzCtYWtd8gSY5 X-Received: by 2002:a05:6a20:7da8:b0:a2:c45f:f0fc with SMTP id v40-20020a056a207da800b000a2c45ff0fcmr49770916pzj.27.1672432701216; Fri, 30 Dec 2022 12:38:21 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1672432701; cv=none; d=google.com; s=arc-20160816; b=NffvA2GcvwqupCwxDsDx1NLNWexfzSdRQF7D6xXYIGcgjIYltKlquxLlCHTN+yW1wk 4JFm/d4kM36WZ8Qd+5K6fuMLKPKmIUOouJuOYaE8szyjdAmAnMGNd/SHduiMhBnJ7AxV QhZraNLfau9upWlMesUGX29p69odI+ROPzCVG3gWCXroxlA8G08kP+NxAnwZbIvruSoI BbBGTmWX3Mgks0aI/rE8coB3y7A4MzcLoTgI4ZdDbN5O6LvpL2YK9MO8pYs9mCeeMS/A iaXq37IdAKnHyec6Uq688bdwraFMnGFpM6kESpzrF6U60AKyrZNt8xxuA164jOtCdBzB +7hg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=eTC+mnxU3UPqgX3TH+U6o3Fz1LFcosQFNOD9ojOfvuw=; b=M+QgOQFRjGA7RRhZ78CHMHXe8BuYOSCVKpVHKDjvC+Zm6X5MXxlR4H3Yt0vK1Zwsqr fEJ5FKapOMzrMYXex3m/CJR9Smu0SQ7Sqrr6lOr+9Yd1lL6lJ4X9PHMDpGLOJgP+gRJA 9dEMQ/Brqu8rZRyX0xs/AquLBOqXpTseTjWS095JMaC0SFub6Qu+iEDt8asg+rspJ2zn qlEyFCTCYgighY4sWoXEwMvEOMoWgj2xrIq/C4G2kQNKUy8mk1hF8hhwx0BxeDFA9yr1 NJ7+WJPdNMtBUdg4nsYO1XQ+EXAGIjccTU23v09MaXTTHi8EeBzDa+Yn6BVEh8Lcpv/b UVzQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@baylibre-com.20210112.gappssmtp.com header.s=20210112 header.b=dzrQrINR; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. 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[2a01:c22:cd9d:4b00:ef17:3c78:1696:7315]) by smtp.gmail.com with ESMTPSA id c10-20020a056402158a00b00482c1f1a039sm8350500edv.30.2022.12.30.12.35.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Dec 2022 12:35:49 -0800 (PST) From: =?utf-8?q?Bernhard_Rosenkr=C3=A4nzer?= To: linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-usb@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, matthias.bgg@gmail.com, krzysztof.kozlowski+dt@linaro.org, robh+dt@kernel.org, gregkh@linuxfoundation.org, chunfeng.yun@mediatek.com, linus.walleij@linaro.org, lee@kernel.org, maz@kernel.org, tglx@linutronix.de, angelogioacchino.delregno@collabora.com Subject: [PATCH v6 7/7] arm64: dts: mediatek: Initial mt8365-evk support Date: Fri, 30 Dec 2022 21:35:41 +0100 Message-Id: <20221230203541.146807-8-bero@baylibre.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20221230203541.146807-1-bero@baylibre.com> References: <20221230203541.146807-1-bero@baylibre.com> MIME-Version: 1.0 X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1753672791862542951?= X-GMAIL-MSGID: =?utf-8?q?1753672791862542951?= From: Fabien Parent This adds minimal support for the Mediatek 8365 SOC and the EVK reference board, allowing the board to boot to initramfs with serial port I/O. Signed-off-by: Fabien Parent [bero@baylibre.com: Removed parts depending on drivers that aren't upstream yet, cleanups, add CPU cache layout, add systimer] Signed-off-by: Bernhard Rosenkränzer Tested-by: Kevin Hilman --- arch/arm64/boot/dts/mediatek/Makefile | 1 + arch/arm64/boot/dts/mediatek/mt8365-evk.dts | 169 +++++++++ arch/arm64/boot/dts/mediatek/mt8365.dtsi | 374 ++++++++++++++++++++ 3 files changed, 544 insertions(+) create mode 100644 arch/arm64/boot/dts/mediatek/mt8365-evk.dts create mode 100644 arch/arm64/boot/dts/mediatek/mt8365.dtsi diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile index 813e735c5b96d..d78523c5a7dd6 100644 --- a/arch/arm64/boot/dts/mediatek/Makefile +++ b/arch/arm64/boot/dts/mediatek/Makefile @@ -47,4 +47,5 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-cherry-tomato-r2.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-cherry-tomato-r3.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-demo.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-evb.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8365-evk.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8516-pumpkin.dtb diff --git a/arch/arm64/boot/dts/mediatek/mt8365-evk.dts b/arch/arm64/boot/dts/mediatek/mt8365-evk.dts new file mode 100644 index 0000000000000..275ea3a0e7085 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8365-evk.dts @@ -0,0 +1,169 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2021-2022 BayLibre, SAS. + * Authors: + * Fabien Parent + * Bernhard Rosenkränzer + */ + +/dts-v1/; + +#include +#include +#include +#include "mt8365.dtsi" + +/ { + model = "MediaTek MT8365 Open Platform EVK"; + compatible = "mediatek,mt8365-evk", "mediatek,mt8365"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:921600n8"; + }; + + firmware { + optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + input-name = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&gpio_keys>; + + key-volume-up { + gpios = <&pio 24 GPIO_ACTIVE_LOW>; + label = "volume_up"; + linux,code = ; + wakeup-source; + debounce-interval = <15>; + }; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0 0x40000000 0 0xc0000000>; + }; + + usb_otg_vbus: regulator-0 { + compatible = "regulator-fixed"; + regulator-name = "otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&pio 16 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* 128 KiB reserved for ARM Trusted Firmware (BL31) */ + bl31_secmon_reserved: secmon@43000000 { + no-map; + reg = <0 0x43000000 0 0x20000>; + }; + + /* 12 MiB reserved for OP-TEE (BL32) + * +-----------------------+ 0x43e0_0000 + * | SHMEM 2MiB | + * +-----------------------+ 0x43c0_0000 + * | | TA_RAM 8MiB | + * + TZDRAM +--------------+ 0x4340_0000 + * | | TEE_RAM 2MiB | + * +-----------------------+ 0x4320_0000 + */ + optee_reserved: optee@43200000 { + no-map; + reg = <0 0x43200000 0 0x00c00000>; + }; + }; +}; + +&pio { + gpio_keys: gpio-keys-pins { + pins { + pinmux = ; + bias-pull-up; + input-enable; + }; + }; + + uart0_pins: uart0-pins { + pins { + pinmux = , + ; + }; + }; + + uart1_pins: uart1-pins { + pins { + pinmux = , + ; + }; + }; + + uart2_pins: uart2-pins { + pins { + pinmux = , + ; + }; + }; + + usb_pins: usb-pins { + pins-id { + pinmux = ; + input-enable; + bias-pull-up; + }; + + pins-usb0-vbus { + pinmux = ; + output-high; + }; + + pin-usb1-vbus { + pinmux = ; + output-high; + }; + }; + + pwm_pins: pwm-pins { + pins { + pinmux = , + ; + }; + }; +}; + +&pwm { + pinctrl-0 = <&pwm_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&uart0 { + pinctrl-0 = <&uart0_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&uart1 { + pinctrl-0 = <&uart1_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&uart2 { + pinctrl-0 = <&uart2_pins>; + pinctrl-names = "default"; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8365.dtsi b/arch/arm64/boot/dts/mediatek/mt8365.dtsi new file mode 100644 index 0000000000000..60a211ba91dbd --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8365.dtsi @@ -0,0 +1,374 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * (C) 2018 MediaTek Inc. + * Copyright (C) 2022 BayLibre SAS + * Fabien Parent + * Bernhard Rosenkränzer + */ +#include +#include +#include +#include +#include + +/ { + compatible = "mediatek,mt8365"; + interrupt-parent = <&sysirq>; + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu0>; + }; + core1 { + cpu = <&cpu1>; + }; + core2 { + cpu = <&cpu2>; + }; + core3 { + cpu = <&cpu3>; + }; + }; + }; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0>; + #cooling-cells = <2>; + enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&l2>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x1>; + #cooling-cells = <2>; + enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&l2>; + }; + + cpu2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x2>; + #cooling-cells = <2>; + enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&l2>; + }; + + cpu3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x3>; + #cooling-cells = <2>; + enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&l2>; + }; + + l2: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-size = <0x80000>; + cache-line-size = <64>; + cache-sets = <512>; + cache-unified; + }; + }; + + clk26m: oscillator { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <26000000>; + clock-output-names = "clk26m"; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + soc { + #address-cells = <2>; + #size-cells = <2>; + compatible = "simple-bus"; + ranges; + + gic: interrupt-controller@c000000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <4>; + interrupt-parent = <&gic>; + interrupt-controller; + reg = <0 0x0c000000 0 0x80000>, <0 0x0c080000 0 0x80000>; + + interrupts = ; + }; + + topckgen: syscon@10000000 { + compatible = "mediatek,mt8365-topckgen", "syscon"; + reg = <0 0x10000000 0 0x1000>; + #clock-cells = <1>; + }; + + infracfg: syscon@10001000 { + compatible = "mediatek,mt8365-infracfg", "syscon"; + reg = <0 0x10001000 0 0x1000>; + #clock-cells = <1>; + }; + + pericfg: syscon@10003000 { + compatible = "mediatek,mt8365-pericfg", "syscon"; + reg = <0 0x10003000 0 0x1000>; + #clock-cells = <1>; + }; + + syscfg_pctl: syscfg-pctl@10005000 { + compatible = "mediatek,mt8365-syscfg", "syscon"; + reg = <0 0x10005000 0 0x1000>; + }; + + pio: pinctrl@1000b000 { + compatible = "mediatek,mt8365-pinctrl"; + reg = <0 0x1000b000 0 0x1000>; + mediatek,pctl-regmap = <&syscfg_pctl>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = ; + }; + + apmixedsys: syscon@1000c000 { + compatible = "mediatek,mt8365-apmixedsys", "syscon"; + reg = <0 0x1000c000 0 0x1000>; + #clock-cells = <1>; + }; + + keypad: keypad@10010000 { + compatible = "mediatek,mt6779-keypad"; + reg = <0 0x10010000 0 0x1000>; + wakeup-source; + interrupts = ; + clocks = <&clk26m>; + clock-names = "kpd"; + status = "disabled"; + }; + + mcucfg: syscon@10200000 { + compatible = "mediatek,mt8365-mcucfg", "syscon"; + reg = <0 0x10200000 0 0x2000>; + #clock-cells = <1>; + }; + + sysirq: interrupt-controller@10200a80 { + compatible = "mediatek,mt8365-sysirq", "mediatek,mt6577-sysirq"; + interrupt-controller; + #interrupt-cells = <3>; + interrupt-parent = <&gic>; + reg = <0 0x10200a80 0 0x20>; + }; + + infracfg_nao: infracfg@1020e000 { + compatible = "mediatek,mt8365-infracfg", "syscon"; + reg = <0 0x1020e000 0 0x1000>; + }; + + rng: rng@1020f000 { + compatible = "mediatek,mt8365-rng", "mediatek,mt7623-rng"; + reg = <0 0x1020f000 0 0x100>; + clocks = <&infracfg CLK_IFR_TRNG>; + clock-names = "rng"; + }; + + apdma: dma-controller@11000280 { + compatible = "mediatek,mt8365-uart-dma", "mediatek,mt6577-uart-dma"; + reg = <0 0x11000280 0 0x80>, + <0 0x11000300 0 0x80>, + <0 0x11000380 0 0x80>, + <0 0x11000400 0 0x80>, + <0 0x11000580 0 0x80>, + <0 0x11000600 0 0x80>; + interrupts = , + , + , + , + , + ; + dma-requests = <6>; + clocks = <&infracfg CLK_IFR_AP_DMA>; + clock-names = "apdma"; + #dma-cells = <1>; + }; + + uart0: serial@11002000 { + compatible = "mediatek,mt8365-uart", "mediatek,mt6577-uart"; + reg = <0 0x11002000 0 0x1000>; + interrupts = ; + clocks = <&clk26m>, <&infracfg CLK_IFR_UART0>; + clock-names = "baud", "bus"; + dmas = <&apdma 0>, <&apdma 1>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + uart1: serial@11003000 { + compatible = "mediatek,mt8365-uart", "mediatek,mt6577-uart"; + reg = <0 0x11003000 0 0x1000>; + interrupts = ; + clocks = <&clk26m>, <&infracfg CLK_IFR_UART1>; + clock-names = "baud", "bus"; + dmas = <&apdma 2>, <&apdma 3>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + uart2: serial@11004000 { + compatible = "mediatek,mt8365-uart", "mediatek,mt6577-uart"; + reg = <0 0x11004000 0 0x1000>; + interrupts = ; + clocks = <&clk26m>, <&infracfg CLK_IFR_UART2>; + clock-names = "baud", "bus"; + dmas = <&apdma 4>, <&apdma 5>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + pwm: pwm@11006000 { + compatible = "mediatek,mt8365-pwm"; + reg = <0 0x11006000 0 0x1000>; + #pwm-cells = <2>; + interrupts = ; + clocks = <&infracfg CLK_IFR_PWM_HCLK>, + <&infracfg CLK_IFR_PWM>, + <&infracfg CLK_IFR_PWM1>, + <&infracfg CLK_IFR_PWM2>, + <&infracfg CLK_IFR_PWM3>; + clock-names = "top", "main", "pwm1", "pwm2", "pwm3"; + }; + + spi: spi@1100a000 { + compatible = "mediatek,mt8365-spi", "mediatek,mt7622-spi"; + reg = <0 0x1100a000 0 0x100>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&topckgen CLK_TOP_UNIVPLL2_D4>, + <&topckgen CLK_TOP_SPI_SEL>, + <&infracfg CLK_IFR_SPI0>; + clock-names = "parent-clk", "sel-clk", "spi-clk"; + status = "disabled"; + }; + + ssusb: usb@11201000 { + compatible = "mediatek,mt8365-mtu3", "mediatek,mtu3"; + reg = <0 0x11201000 0 0x2e00>, <0 0x11203e00 0 0x0100>; + reg-names = "mac", "ippc"; + interrupts = ; + phys = <&u2port0 PHY_TYPE_USB2>, + <&u2port1 PHY_TYPE_USB2>; + clocks = <&topckgen CLK_TOP_SSUSB_TOP_CK_EN>, + <&infracfg CLK_IFR_SSUSB_REF>, + <&infracfg CLK_IFR_SSUSB_SYS>, + <&infracfg CLK_IFR_ICUSB>; + clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "disabled"; + + usb_host: usb@11200000 { + compatible = "mediatek,mt8365-xhci", "mediatek,mtk-xhci"; + reg = <0 0x11200000 0 0x1000>; + reg-names = "mac"; + interrupts = ; + clocks = <&topckgen CLK_TOP_SSUSB_TOP_CK_EN>, + <&infracfg CLK_IFR_SSUSB_REF>, + <&infracfg CLK_IFR_SSUSB_SYS>, + <&infracfg CLK_IFR_ICUSB>, + <&infracfg CLK_IFR_SSUSB_XHCI>; + clock-names = "sys_ck", "ref_ck", "mcu_ck", + "dma_ck", "xhci_ck"; + status = "disabled"; + }; + }; + + u3phy: phy@11cc0000 { + compatible = "mediatek,mt8365-tphy", "mediatek,generic-tphy-v2"; + #address-cells = <2>; + #size-cells = <2>; + #phy-cells = <1>; + ranges; + + u2port0: usb-phy@11cc0000 { + reg = <0 0x11cc0000 0 0x400>; + clocks = <&topckgen CLK_TOP_SSUSB_PHY_CK_EN>, + <&topckgen CLK_TOP_USB20_48M_EN>; + clock-names = "ref", "da_ref"; + #phy-cells = <1>; + }; + + u2port1: usb-phy@11cc1000 { + reg = <0 0x11cc1000 0 0x400>; + clocks = <&topckgen CLK_TOP_SSUSB_PHY_CK_EN>, + <&topckgen CLK_TOP_USB20_48M_EN>; + clock-names = "ref", "da_ref"; + #phy-cells = <1>; + }; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupt-parent = <&gic>; + interrupts = , + , + , + ; + }; + + system_clk: dummy13m { + compatible = "fixed-clock"; + clock-frequency = <13000000>; + #clock-cells = <0>; + }; + + systimer: timer@10017000 { + compatible = "mediatek,mt6795-systimer"; + reg = <0 0x10017000 0 0x10>; + interrupts = ; + clocks = <&system_clk>; + clock-names = "clk13m"; + }; +};