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Thu, 29 Dec 2022 23:21:36 -0600 From: Mario Limonciello To: Alex Deucher , CC: Javier Martinez Canillas , Carlos Soriano Sanchez , , , David Airlie , "Daniel Vetter" , , Mario Limonciello , , "Pan, Xinhui" Subject: [PATCH v3 01/11] drm/amd: Delay removal of the firmware framebuffer Date: Thu, 29 Dec 2022 23:21:05 -0600 Message-ID: <20221230052119.15096-2-mario.limonciello@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221230052119.15096-1-mario.limonciello@amd.com> References: <20221230052119.15096-1-mario.limonciello@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1NAM11FT033:EE_|SN7PR12MB7321:EE_ X-MS-Office365-Filtering-Correlation-Id: 6157a733-d474-4321-6fb6-08daea25bbfa X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: tAZs10rkhCzxgSLRHfGEtNwaY974Xg1Z4FX7tGNgg1JGKfrfUKIzvHoGsqeLq1BnoF/vfpPTM4qNXEMIEqoAlXMIdn4mETbGbZR0WVUo2y7/z1jhwNznQiMQWlNdurHQ+5Hmvb+vIYSjTpYLwj8KcrNvue34c6X3N+fugEkdJWyBzOku5wtqPApIbKgQFUQF1qFWxN5YXeh3ea253T3wKEJx7JFaRP2Cgipovt769RMwUqLwyd/7i5nYiLYKckZ27Z/ewlgAH09XQQd2b0GIpgq4nbfbeZAfAkvxvPc5HZfPyoi/vEiB4u/ohZcOghXB2Tih6q5Mj50v7/MwvcohTxiNYzAIae90HmiXwW2gcZmMKEEVrdNpbrgfFc6nFhRUvpRl4pcQ4Pf1UkpYCzScr/BbpPFUsUBosVEZxIU2CApkWWisET47Upf1FjT5nS601Tpa81kNlFFPWXPKKUu4tS/zdchXRnACn0U1mh/iYHIvcPinIXFe+Ydjb0E4w9eZYSuFb3958QfaGgDctsDlX5sZGRkrXAgzAsMWyAPdvVGYn90Qq9/Ub2PNK8H8UQWwQyn/ypmresKQXtUNdhDmxaIqdtFp4+HoOUJ29/NW7k1KP17VI6QVpOGpXkEimIC6uDpejO3ZV1tuit9SrKp3VRukMz8rc0utF6HAGgJ/cNdYZA7r0PBqBEtD14J7Bc+dM6ZfIB1qB4O7Cy4Xmod7aNG8R2dhsp6YO74uEOBPyxQ= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230022)(4636009)(376002)(396003)(136003)(39860400002)(346002)(451199015)(40470700004)(36840700001)(46966006)(86362001)(70206006)(8676002)(4326008)(2906002)(41300700001)(44832011)(8936002)(5660300002)(70586007)(40480700001)(83380400001)(478600001)(2616005)(47076005)(6666004)(26005)(16526019)(1076003)(426003)(40460700003)(186003)(81166007)(316002)(356005)(54906003)(7696005)(110136005)(82740400003)(336012)(36860700001)(82310400005)(36756003)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Dec 2022 05:21:41.3381 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6157a733-d474-4321-6fb6-08daea25bbfa X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT033.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB7321 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1753615182151149619?= X-GMAIL-MSGID: =?utf-8?q?1753615182151149619?= Removing the firmware framebuffer from the driver means that even if the driver doesn't support the IP blocks in a GPU it will no longer be functional after the driver fails to initialize. This change will ensure that unsupported IP blocks at least cause the driver to work with the EFI framebuffer. Cc: stable@vger.kernel.org Suggested-by: Alex Deucher Reviewed-by: Javier Martinez Canillas Reviewed-by: Alex Deucher Signed-off-by: Mario Limonciello --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 8 ++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 6 ------ 2 files changed, 8 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 9a1a5c2864a0..84d83be2087c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -37,6 +37,7 @@ #include #include +#include #include #include #include @@ -89,6 +90,8 @@ MODULE_FIRMWARE("amdgpu/navi12_gpu_info.bin"); #define AMDGPU_MAX_RETRY_LIMIT 2 #define AMDGPU_RETRY_SRIOV_RESET(r) ((r) == -EBUSY || (r) == -ETIMEDOUT || (r) == -EINVAL) +static const struct drm_driver amdgpu_kms_driver; + const char *amdgpu_asic_name[] = { "TAHITI", "PITCAIRN", @@ -2140,6 +2143,11 @@ static int amdgpu_device_ip_early_init(struct amdgpu_device *adev) break; } + /* Get rid of things like offb */ + r = drm_aperture_remove_conflicting_pci_framebuffers(adev->pdev, &amdgpu_kms_driver); + if (r) + return r; + if (amdgpu_has_atpx() && (amdgpu_is_atpx_hybrid() || amdgpu_has_atpx_dgpu_power_cntl()) && diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index db7e34eacc35..b9f14ec9edb2 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -23,7 +23,6 @@ */ #include -#include #include #include #include @@ -2096,11 +2095,6 @@ static int amdgpu_pci_probe(struct pci_dev *pdev, } #endif - /* Get rid of things like offb */ - ret = drm_aperture_remove_conflicting_pci_framebuffers(pdev, &amdgpu_kms_driver); - if (ret) - return ret; - adev = devm_drm_dev_alloc(&pdev->dev, &amdgpu_kms_driver, typeof(*adev), ddev); if (IS_ERR(adev)) return PTR_ERR(adev); From patchwork Fri Dec 30 05:21:06 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mario Limonciello X-Patchwork-Id: 37568 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4e01:0:0:0:0:0 with SMTP id p1csp2735925wrt; Thu, 29 Dec 2022 21:22:54 -0800 (PST) X-Google-Smtp-Source: AMrXdXsnCHjnE4lmqFeDdzV8vhBE7/SIguoq/w3mGojIG+mw0n5ySodKsoOi7GUry5sG9rs7kfTP X-Received: by 2002:a05:6a20:7da3:b0:ad:d982:4538 with SMTP id v35-20020a056a207da300b000add9824538mr48092794pzj.55.1672377774487; Thu, 29 Dec 2022 21:22:54 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1672377774; cv=pass; d=google.com; s=arc-20160816; b=hRozjCPBd8z0iMKpfMjXpxcjaFqNfSWK0YMWquroFnPn2N/85XT2AlpsqoOBRoeIBx FUnjRM1BTtXW8lCuh+PxFB1ljUUTdaNuyn3R/Y5blPldeG7rF7vVP4VtZzOj18WOsxFQ O1+UnqRL06d0FuShT5a+EAtrXAj1Ctl9T+LSgPlsi6eCcIOOgIcdo8YziLESazTBLcTu 3XRi1UUW7EriaOQgMRQlo1Tsm5rGmiYolatCFqWOGkD0zQ6sp0HW7YOFnLvAaIIwyu7A QBqb313qAouEiH/VnXjpVj7Jd3auJNTig7j+UAyN9kBobQk1jOEKX6ULYl2Pweordg5Z HLVw== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=FNTzdji72o46pwicV5EkYUF7sldXH2ebgHPkENhol1U=; b=UG6spxVagII+42VYcFPLqWQyrm04lifCGLOrtFgxoug4lxQH5bdf+syD/RAgVR/bvs h1ETdi1S2W3qiFW+21P0FVUWcoQIv8Gfa4edStKC2cnhfJoMssNFJZGtgVBN7dztcZBK Jmna9pMOckpkDk7mnmq++2RIyQPB2xYbwEFktIT9wG/j8dWqfoGIALAOIe9u6iaNL7Pe oqdk/lY1yGbC0wqay/jENXjdxpC+mQHGrEEbyW/kyO/J5lWafb07UIIEymOWFF+FIZti R/IgpgQXJuK87KcYKwPz7Fzr40Km9+z6M+xvN3qykEAIjLQBJe2gGyP57oSwcW5OUzKD Qjuw== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amd.com header.s=selector1 header.b=T78FMpYd; arc=pass (i=1 spf=pass spfdomain=amd.com dmarc=pass fromdomain=amd.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=amd.com Received: from out1.vger.email (out1.vger.email. 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Thu, 29 Dec 2022 23:21:38 -0600 From: Mario Limonciello To: Alex Deucher , CC: Javier Martinez Canillas , Carlos Soriano Sanchez , , , David Airlie , "Daniel Vetter" , , Mario Limonciello , "Pan, Xinhui" Subject: [PATCH v3 02/11] drm/amd: Add a legacy mapping to "amdgpu_ucode_ip_version_decode" Date: Thu, 29 Dec 2022 23:21:06 -0600 Message-ID: <20221230052119.15096-3-mario.limonciello@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221230052119.15096-1-mario.limonciello@amd.com> References: <20221230052119.15096-1-mario.limonciello@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1NAM11FT043:EE_|DM6PR12MB4927:EE_ X-MS-Office365-Filtering-Correlation-Id: 9402070f-a147-41de-e849-08daea25bbdf X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: H325NaH/GAymvoCWNzbtnzsUdA1jL1JJ8hW5OCerGZ8MohEBt3DkSnLij009zlAAJceQixkWowv0WX3kEoNqZAf4aYZtb9GCGTZPH/2iCJsqMsy81iHz6PgcilJICzw/6Jk3+8Z3zfoGZD7cIsE6dMkpLN5fojXv4ik+NcXqgtksR7OxxoUbXwlQwhOWpHVfUOdKHNmqR2IHOu/OQrI6qFoCOvpaagb2KSa/OtGj5kYmPlY1LcAxyR0zu9tyacIgMLmCpeUUXjK/F04CyBwQqk9FFgXSTQRoOVHeVWmvu684CiM+4yviN54LgTfQeD9VkpXJH8SuOWEJ0eQGTkCdelXW4Axpmunos8HcJZ2byiobEOY8hHvCDpEQW4Hgb56pt1sD26TSf4dst0HmoU80O6WyvDF59EmgisvEgVp9jN137LPvhB+bsB7+CYIpkgjlE4v3GN14SXvqzr/neqUaQ5wETPTIPilWAMKzZfoRTZtcM6/ZpkCS1nJO1xo9tf4pIoejP1ngdMSaYV6tFcJ2nxW/LabKBtzclZmiboxfsuiLoEHxjqVwHcvx1CxFdiNfamQjN8LfT3UJJmd1UVonpu9vxx0rwfef1QP/TBMo3Mvnum3NILeaQ7jr4heRPQfXA+GbUufNGvFxmflG2ubiZ6IjzWyBq4XiuIfGICZ4CpW4yzeayoVChLQS4ioQM/zpnQ4+YX+0rYe/V0t1Ov2ZIJdA/n850BhaQLO4AK4e1jY= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230022)(4636009)(136003)(376002)(396003)(39860400002)(346002)(451199015)(46966006)(40470700004)(36840700001)(356005)(6666004)(5660300002)(82740400003)(81166007)(16526019)(186003)(26005)(2906002)(316002)(40460700003)(7696005)(54906003)(478600001)(86362001)(44832011)(36756003)(110136005)(40480700001)(426003)(47076005)(41300700001)(83380400001)(8936002)(70586007)(82310400005)(70206006)(1076003)(8676002)(2616005)(4326008)(336012)(36860700001)(36900700001);DIR:OUT;SFP:1101; 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Signed-off-by: Mario Limonciello --- v2->v3: * Fixes for GFX9 SDMA --- drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c | 221 ++++++++++++++++++++++ 1 file changed, 221 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c index 5cb62e6249c2..eafcddce58d3 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c @@ -1059,12 +1059,233 @@ int amdgpu_ucode_init_bo(struct amdgpu_device *adev) return 0; } +static const char *amdgpu_ucode_legacy_naming(struct amdgpu_device *adev, int block_type) +{ + if (block_type == MP0_HWIP) { + switch (adev->ip_versions[MP0_HWIP][0]) { + case IP_VERSION(9, 0, 0): + switch (adev->asic_type) { + case CHIP_VEGA10: + return "vega10"; + case CHIP_VEGA12: + return "vega12"; + default: + return NULL; + } + break; + case IP_VERSION(10, 0, 0): + case IP_VERSION(10, 0, 1): + if (adev->asic_type == CHIP_RAVEN) { + if (adev->apu_flags & AMD_APU_IS_RAVEN2) + return "raven2"; + else if (adev->apu_flags & AMD_APU_IS_PICASSO) + return "picasso"; + return "raven"; + } + break; + case IP_VERSION(11, 0, 0): + return "navi10"; + case IP_VERSION(11, 0, 2): + return "vega20"; + case IP_VERSION(11, 0, 4): + return "arcturus"; + case IP_VERSION(11, 0, 5): + return "navi14"; + case IP_VERSION(11, 0, 7): + return "sienna_cichlid"; + case IP_VERSION(11, 0, 9): + return "navi12"; + case IP_VERSION(11, 0, 11): + return "navy_flounder"; + case IP_VERSION(11, 0, 12): + return "dimgrey_cavefish"; + case IP_VERSION(11, 0, 13): + return "beige_goby"; + case IP_VERSION(11, 5, 0): + return "vangogh"; + case IP_VERSION(12, 0, 1): + if (adev->asic_type == CHIP_RENOIR) { + if (adev->apu_flags & AMD_APU_IS_RENOIR) + return "renoir"; + return "green_sardine"; + } + break; + case IP_VERSION(13, 0, 2): + return "aldebaran"; + case IP_VERSION(13, 0, 1): + case IP_VERSION(13, 0, 3): + return "yellow_carp"; + } + } else if (block_type == MP1_HWIP) { + switch (adev->ip_versions[MP1_HWIP][0]) { + case IP_VERSION(9, 0, 0): + case IP_VERSION(10, 0, 0): + case IP_VERSION(10, 0, 1): + case IP_VERSION(11, 0, 2): + if (adev->asic_type == CHIP_ARCTURUS) + return "arcturus_smc"; + return NULL; + case IP_VERSION(11, 0, 0): + return "navi10_smc"; + case IP_VERSION(11, 0, 5): + return "navi14_smc"; + case IP_VERSION(11, 0, 9): + return "navi12_smc"; + case IP_VERSION(11, 0, 7): + return "sienna_cichlid_smc"; + case IP_VERSION(11, 0, 11): + return "navy_flounder_smc"; + case IP_VERSION(11, 0, 12): + return "dimgrey_cavefish_smc"; + case IP_VERSION(11, 0, 13): + return "beige_goby_smc"; + case IP_VERSION(13, 0, 2): + return "aldebaran_smc"; + } + } else if (block_type == SDMA0_HWIP) { + switch (adev->ip_versions[SDMA0_HWIP][0]) { + case IP_VERSION(4, 0, 0): + return "vega10_sdma"; + case IP_VERSION(4, 0, 1): + return "vega12_sdma"; + case IP_VERSION(4, 1, 0): + case IP_VERSION(4, 1, 1): + if (adev->apu_flags & AMD_APU_IS_RAVEN2) + return "raven2_sdma"; + else if (adev->apu_flags & AMD_APU_IS_PICASSO) + return "picasso_sdma"; + return "raven_sdma"; + case IP_VERSION(4, 1, 2): + if (adev->apu_flags & AMD_APU_IS_RENOIR) + return "renoir_sdma"; + return "green_sardine_sdma"; + case IP_VERSION(4, 2, 0): + return "vega20_sdma"; + case IP_VERSION(4, 2, 2): + return "arcturus_sdma"; + case IP_VERSION(4, 4, 0): + return "aldebaran_sdma"; + case IP_VERSION(5, 0, 0): + return "navi10_sdma"; + case IP_VERSION(5, 0, 1): + return "cyan_skillfish2_sdma"; + case IP_VERSION(5, 0, 2): + return "navi14_sdma"; + case IP_VERSION(5, 0, 5): + return "navi12_sdma"; + case IP_VERSION(5, 2, 0): + return "sienna_cichlid_sdma"; + case IP_VERSION(5, 2, 2): + return "navy_flounder_sdma"; + case IP_VERSION(5, 2, 4): + return "dimgrey_cavefish_sdma"; + case IP_VERSION(5, 2, 5): + return "beige_goby_sdma"; + case IP_VERSION(5, 2, 3): + return "yellow_carp_sdma"; + case IP_VERSION(5, 2, 1): + return "vangogh_sdma"; + } + } else if (block_type == UVD_HWIP) { + switch (adev->ip_versions[UVD_HWIP][0]) { + case IP_VERSION(1, 0, 0): + case IP_VERSION(1, 0, 1): + if (adev->apu_flags & AMD_APU_IS_RAVEN2) + return "raven2_vcn"; + else if (adev->apu_flags & AMD_APU_IS_PICASSO) + return "picasso_vcn"; + return "raven_vcn"; + case IP_VERSION(2, 5, 0): + return "arcturus_vcn"; + case IP_VERSION(2, 2, 0): + if (adev->apu_flags & AMD_APU_IS_RENOIR) + return "renoir_vcn"; + return "green_sardine_vcn"; + case IP_VERSION(2, 6, 0): + return "aldebaran_vcn"; + case IP_VERSION(2, 0, 0): + return "navi10_vcn"; + case IP_VERSION(2, 0, 2): + if (adev->asic_type == CHIP_NAVI12) + return "navi12_vcn"; + return "navi14_vcn"; + case IP_VERSION(3, 0, 0): + case IP_VERSION(3, 0, 64): + case IP_VERSION(3, 0, 192): + if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 0)) + return "sienna_cichlid_vcn"; + return "navy_flounder_vcn"; + case IP_VERSION(3, 0, 2): + return "vangogh_vcn"; + case IP_VERSION(3, 0, 16): + return "dimgrey_cavefish_vcn"; + case IP_VERSION(3, 0, 33): + return "beige_goby_vcn"; + case IP_VERSION(3, 1, 1): + return "yellow_carp_vcn"; + } + } else if (block_type == GC_HWIP) { + switch (adev->ip_versions[GC_HWIP][0]) { + case IP_VERSION(9, 0, 1): + return "vega10"; + case IP_VERSION(9, 2, 1): + return "vega12"; + case IP_VERSION(9, 4, 0): + return "vega20"; + case IP_VERSION(9, 2, 2): + case IP_VERSION(9, 1, 0): + if (adev->apu_flags & AMD_APU_IS_RAVEN2) + return "raven2"; + else if (adev->apu_flags & AMD_APU_IS_PICASSO) + return "picasso"; + return "raven"; + case IP_VERSION(9, 4, 1): + return "arcturus"; + case IP_VERSION(9, 3, 0): + if (adev->apu_flags & AMD_APU_IS_RENOIR) + return "renoir"; + return "green_sardine"; + case IP_VERSION(9, 4, 2): + return "aldebaran"; + case IP_VERSION(10, 1, 10): + return "navi10"; + case IP_VERSION(10, 1, 1): + return "navi14"; + case IP_VERSION(10, 1, 2): + return "navi12"; + case IP_VERSION(10, 3, 0): + return "sienna_cichlid"; + case IP_VERSION(10, 3, 2): + return "navy_flounder"; + case IP_VERSION(10, 3, 1): + return "vangogh"; + case IP_VERSION(10, 3, 4): + return "dimgrey_cavefish"; + case IP_VERSION(10, 3, 5): + return "beige_goby"; + case IP_VERSION(10, 3, 3): + return "yellow_carp"; + case IP_VERSION(10, 1, 3): + case IP_VERSION(10, 1, 4): + return "cyan_skillfish2"; + } + } + return NULL; +} + void amdgpu_ucode_ip_version_decode(struct amdgpu_device *adev, int block_type, char *ucode_prefix, int len) { int maj, min, rev; char *ip_name; + const char *legacy; uint32_t version = adev->ip_versions[block_type][0]; + legacy = amdgpu_ucode_legacy_naming(adev, block_type); + if (legacy) { + snprintf(ucode_prefix, len, "%s", legacy); + return; + } + switch (block_type) { case GC_HWIP: ip_name = "gc"; From patchwork Fri Dec 30 05:21:07 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mario Limonciello X-Patchwork-Id: 37569 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4e01:0:0:0:0:0 with SMTP id p1csp2735936wrt; Thu, 29 Dec 2022 21:22:57 -0800 (PST) X-Google-Smtp-Source: AMrXdXvIr5lVXJ4M5KAy40QDrrTe6VjsuKoqjmhKaFz21mSou8rQDCzBNbTot1QKvznd++EnW/R8 X-Received: by 2002:a05:6a00:13a4:b0:57f:f7a4:511a with SMTP id t36-20020a056a0013a400b0057ff7a4511amr40591555pfg.2.1672377777687; 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Thu, 29 Dec 2022 23:21:39 -0600 From: Mario Limonciello To: Alex Deucher , CC: Javier Martinez Canillas , Carlos Soriano Sanchez , , , David Airlie , "Daniel Vetter" , , Mario Limonciello , Evan Quan , "Pan, Xinhui" Subject: [PATCH v3 03/11] drm/amd: Convert SMUv11 microcode init to use `amdgpu_ucode_ip_version_decode` Date: Thu, 29 Dec 2022 23:21:07 -0600 Message-ID: <20221230052119.15096-4-mario.limonciello@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221230052119.15096-1-mario.limonciello@amd.com> References: <20221230052119.15096-1-mario.limonciello@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1NAM11FT043:EE_|CH3PR12MB7596:EE_ X-MS-Office365-Filtering-Correlation-Id: b4eb3d77-078e-4097-1d89-08daea25bc38 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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No intended functional changes. Signed-off-by: Mario Limonciello --- .../gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c | 35 ++----------------- 1 file changed, 3 insertions(+), 32 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c index ad66d57aa102..d4756bd30830 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c @@ -93,7 +93,7 @@ static void smu_v11_0_poll_baco_exit(struct smu_context *smu) int smu_v11_0_init_microcode(struct smu_context *smu) { struct amdgpu_device *adev = smu->adev; - const char *chip_name; + char ucode_prefix[30]; char fw_name[SMU_FW_NAME_LEN]; int err = 0; const struct smc_firmware_header_v1_0 *hdr; @@ -105,38 +105,9 @@ int smu_v11_0_init_microcode(struct smu_context *smu) (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7)))) return 0; - switch (adev->ip_versions[MP1_HWIP][0]) { - case IP_VERSION(11, 0, 0): - chip_name = "navi10"; - break; - case IP_VERSION(11, 0, 5): - chip_name = "navi14"; - break; - case IP_VERSION(11, 0, 9): - chip_name = "navi12"; - break; - case IP_VERSION(11, 0, 7): - chip_name = "sienna_cichlid"; - break; - case IP_VERSION(11, 0, 11): - chip_name = "navy_flounder"; - break; - case IP_VERSION(11, 0, 12): - chip_name = "dimgrey_cavefish"; - break; - case IP_VERSION(11, 0, 13): - chip_name = "beige_goby"; - break; - case IP_VERSION(11, 0, 2): - chip_name = "arcturus"; - break; - default: - dev_err(adev->dev, "Unsupported IP version 0x%x\n", - adev->ip_versions[MP1_HWIP][0]); - return -EINVAL; - } + amdgpu_ucode_ip_version_decode(adev, MP1_HWIP, ucode_prefix, sizeof(ucode_prefix)); - snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_smc.bin", chip_name); + snprintf(fw_name, sizeof(fw_name), "amdgpu/%s.bin", ucode_prefix); err = request_firmware(&adev->pm.fw, fw_name, adev->dev); if (err) From patchwork Fri Dec 30 05:21:08 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mario Limonciello X-Patchwork-Id: 37567 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4e01:0:0:0:0:0 with SMTP id p1csp2735909wrt; Thu, 29 Dec 2022 21:22:51 -0800 (PST) X-Google-Smtp-Source: AMrXdXuHhMvQ+LJRc4oELEemNujL9R7Jx3mUTatG/engSzoDaIDC+yo7o5s65MkKJmx+GGOuZQ0V X-Received: by 2002:a17:902:ee41:b0:191:2f59:9049 with SMTP id 1-20020a170902ee4100b001912f599049mr32356714plo.37.1672377771452; Thu, 29 Dec 2022 21:22:51 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1672377771; cv=pass; d=google.com; s=arc-20160816; b=FqraN0OWTzO0kn69sz/WxCruHMhfIffBWNct35IHQoVutUR2WntmWp1kj3Bxi92lru qVuWWNxfczj6H5a/B+CsGKw5fLsNXQTE5LIBV54rpkipnCzVuup9fdwtCVjGqtpFbHcp +uVuQvktaySZ6tZ+JXSr6nnbD4RZo/gdEt9qGlpCeFqiyPOl0Kw+gKTkeVyyYd2rdmXQ C8VxCzNLFRPf4K0rWsyCwd0ge/RgO08XNE5egLpFyrJr/k2j0jyUlTsVJUjRIfEKHa9U S0kH/TECwJrCNPpGYqN3CV4FJqAtzA92qATNqTAQnGazUVt1HuOV/IbuyWHH0zrRR1HX 5DBA== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=nshup5+hxVNcHqwDBboTY9qGlRob7VdXw+3tgRx/lRA=; b=VEBUebJBRGmMzklMpeOQZ+fHqM9+nMYLBm2vadXB0S/gSt8mkr0x7FpLxS8lQ5Hn5A EZ1uGyscFkacyYxyHP3DfEnO+z8zLjHjDKVrx6W6R+w9cQ6YCOOyQJrFrYygcIWeK/EC 6QeznMmPa1Fna5xOjOrhmn86e0wKRD+H3VFd4kzgKtBnTO1birjP5LtKz7chJa62cqGH 8V+MlnuMEaw0W8skgh3CmHt9EaEqhDyxhBpqhRwAIHruZ3IgZK6TwSy6FdkpJ1fi/hx9 rO/kM2OyD3l/GG31EpDW/CQ6AK/KJZ6TI+7s8phY+kJu71QbyeGYo6WT4UvR7KL6MtXC RWmA== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amd.com header.s=selector1 header.b="w/+P3QYw"; arc=pass (i=1 spf=pass spfdomain=amd.com dmarc=pass fromdomain=amd.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=amd.com Received: from out1.vger.email (out1.vger.email. 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Thu, 29 Dec 2022 23:21:40 -0600 From: Mario Limonciello To: Alex Deucher , CC: Javier Martinez Canillas , Carlos Soriano Sanchez , , , David Airlie , "Daniel Vetter" , , Mario Limonciello , Evan Quan , "Pan, Xinhui" Subject: [PATCH v3 04/11] drm/amd: Convert SMUv13 to use `amdgpu_ucode_ip_version_decode` Date: Thu, 29 Dec 2022 23:21:08 -0600 Message-ID: <20221230052119.15096-5-mario.limonciello@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221230052119.15096-1-mario.limonciello@amd.com> References: <20221230052119.15096-1-mario.limonciello@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1NAM11FT033:EE_|MN2PR12MB4221:EE_ X-MS-Office365-Filtering-Correlation-Id: 9a87a33e-e3e1-4efd-2a41-08daea25bc9a X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Dec 2022 05:21:42.3693 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9a87a33e-e3e1-4efd-2a41-08daea25bc9a X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT033.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4221 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1753615194139859946?= X-GMAIL-MSGID: =?utf-8?q?1753615194139859946?= The special case for the one dGPU has been moved into `amdgpu_ucode_ip_version_decode`, so simplify this code. Reviewed-by: Alex Deucher Signed-off-by: Mario Limonciello --- drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c | 12 ++---------- 1 file changed, 2 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c index 0ac9cac805f9..506a49a4b425 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c @@ -88,7 +88,6 @@ static const int link_speed[] = {25, 50, 80, 160}; int smu_v13_0_init_microcode(struct smu_context *smu) { struct amdgpu_device *adev = smu->adev; - const char *chip_name; char fw_name[30]; char ucode_prefix[30]; int err = 0; @@ -100,16 +99,9 @@ int smu_v13_0_init_microcode(struct smu_context *smu) if (amdgpu_sriov_vf(adev)) return 0; - switch (adev->ip_versions[MP1_HWIP][0]) { - case IP_VERSION(13, 0, 2): - chip_name = "aldebaran_smc"; - break; - default: - amdgpu_ucode_ip_version_decode(adev, MP1_HWIP, ucode_prefix, sizeof(ucode_prefix)); - chip_name = ucode_prefix; - } + amdgpu_ucode_ip_version_decode(adev, MP1_HWIP, ucode_prefix, sizeof(ucode_prefix)); - snprintf(fw_name, sizeof(fw_name), "amdgpu/%s.bin", chip_name); + snprintf(fw_name, sizeof(fw_name), "amdgpu/%s.bin", ucode_prefix); err = request_firmware(&adev->pm.fw, fw_name, adev->dev); if (err) From patchwork Fri Dec 30 05:21:09 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mario Limonciello X-Patchwork-Id: 37571 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4e01:0:0:0:0:0 with SMTP id p1csp2735972wrt; Thu, 29 Dec 2022 21:23:07 -0800 (PST) X-Google-Smtp-Source: AMrXdXsYHKaMOJYbNSN6OTw3ICJ42XQ/UiMl10MO+MCHSbuf287fPV4i7R/41xkBH83cAVOchKXg X-Received: by 2002:a05:6a00:1ca4:b0:566:900d:51f2 with SMTP id y36-20020a056a001ca400b00566900d51f2mr31201134pfw.33.1672377787473; Thu, 29 Dec 2022 21:23:07 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1672377787; cv=pass; d=google.com; s=arc-20160816; b=SI94PKoFLCfJtR/t9cHc1OG0Pme4cAJYO3ikgE3FAZDBvY/foVQ9YmS2JjFXR4Lvyc tiyXeN1GWVtdeFQDGgyeKWYjtlFtUopfv/3DuY0nprycO2aQmGxvEZ3eYE6U7294Z8GJ d+IiAyeXRU4KBuOJ2sbGgTTmJE7syln/XDmIWqdiAwJpBIfSpCns7cKMjUHIxtCNeC5Z qKyf8IzIcVgYslQ3A8NuKkkxRvKTzQ6UPETWl0+v448BA+679gZSoSsrgSO0mflV605n tpzLL+D0xyfQR8gVzxqCbqXJIWYrn+gax2P8Aw40D/5hF0oQBGtyD+UyBuWkHTID/JGi TwZw== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=LdXJyOsWuiZ/m2SwFc/DlH2uI3PLQkTXEWh7qCehFgw=; b=OqR1sv4sM+/UgARE2Fc296HeY7p5xaGinFXeMBrYvTWNYQ3WUlSjMwVsmaoqHRHYw0 d97s/xyrQYJgVdT9E9Whj1quYcBzyY8raoR7vFRccKEhKmoNpKEdFLa57JP1C+J1Xj2Q +/ZEAWDDKlBbuttxqpyvzBSGoDqlRryR8KQtQaQbSCx7g90YtXGQ41EqcvldoH9SwLrn 0wKF5Eu7LPJgLe9FrUM90igJZPRVGOt9sQAPvwzvyvMtE5HHYtaYBVM6j/WnMI0wkEx8 lDENWdPA/iL5KKYs/pG0JjY/u3t+7iM6NR9mN+eXJ8cJXKxS3V7OXd35/utfVBB5FN/q wn3A== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amd.com header.s=selector1 header.b="gpFKx/dM"; arc=pass (i=1 spf=pass spfdomain=amd.com dmarc=pass fromdomain=amd.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=amd.com Received: from out1.vger.email (out1.vger.email. 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Thu, 29 Dec 2022 23:21:41 -0600 From: Mario Limonciello To: Alex Deucher , CC: Javier Martinez Canillas , Carlos Soriano Sanchez , , , David Airlie , "Daniel Vetter" , , Mario Limonciello , "Pan, Xinhui" Subject: [PATCH v3 05/11] drm/amd: Request SDMA microcode during IP discovery Date: Thu, 29 Dec 2022 23:21:09 -0600 Message-ID: <20221230052119.15096-6-mario.limonciello@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221230052119.15096-1-mario.limonciello@amd.com> References: <20221230052119.15096-1-mario.limonciello@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1NAM11FT043:EE_|IA0PR12MB8303:EE_ X-MS-Office365-Filtering-Correlation-Id: 1150b773-e1f9-41a8-739b-08daea25bcf4 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: Fb5JbrIaoPfFThCWi6Qm9oHxH8VwdlBw8wym+Jsee6tVcmtYWIPjTVbvWw9EvuFV0DEO3msTAy85jB3ueA+z3sbLKEBKQrmEg9RCVb0b7BM1XOViaSHqompISMTwADZtQRnvxhGKfTzfu81V9ZtvG8bV7GlO/M8XbSC6O/1/sWwC11Gh6evPifokZBNDY8bhSYb+Tiu+sLr7T4K6lrOLqxsWKIG3EVYYuoG7dt0cAkwOVBCllgJg1XWstdMgIwu3CY0sToW+8WKOumjiVpbRbWi5shY+SuPUotUss30tEafJ2eHVE0QeWyuhi9iLlkw002XM95sGuoOwce3VCQQyjeSovJdP97Ut5jTJ91sU9l6Hv9MLs6Cc+IWAlMx5+n8DRRikPFgfshI9sFVYrRGKarkq0RWiUdRkI2xIzsnx/h7mV6vxN+Knv4uUBT9Ys+wwnw3FYYCFND3MkZB/1NfbEFxzD7ptfDtuXEpFPU+Y4MbpjWN6/r181bYMdAV+FcDmaJro0JxTtKvT+/pDd8/bnrMIOUNHSqH61+5oQSHK7l4L8M7V3tL6FKgaGFY2ctIQT0B++2LRChgyQBlkRuIusREluzFRR1Oc6iez+ToNsrvXbO0TXxWvbKAEapTE+vnmoZmeegnovyyLKPA0R6zuy5DKNR0geJ9QJlKlpZmoNndeTZd55guvdd48JLD66AN93UxqZMrbfVcjTfTFK87bzPi7UgfQLpOyoJ/8abma1zY= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230022)(4636009)(376002)(39860400002)(396003)(346002)(136003)(451199015)(40470700004)(36840700001)(46966006)(40480700001)(356005)(16526019)(40460700003)(110136005)(86362001)(36756003)(6666004)(54906003)(316002)(478600001)(5660300002)(30864003)(44832011)(8936002)(2906002)(70586007)(4326008)(70206006)(8676002)(36860700001)(41300700001)(83380400001)(47076005)(82740400003)(81166007)(1076003)(336012)(82310400005)(7696005)(2616005)(26005)(186003)(426003)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Dec 2022 05:21:42.9610 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1150b773-e1f9-41a8-739b-08daea25bcf4 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT043.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA0PR12MB8303 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1753615210808128457?= X-GMAIL-MSGID: =?utf-8?q?1753615210808128457?= If SDMA microcode is not available during early init, the firmware framebuffer will have already been released and the screen will freeze. Move the request from SDMA microcode into the IP discovery phase so that if it's not available, IP discovery will fail. Signed-off-by: Mario Limonciello --- v2->v3: * Fix dGPU naming scheme --- drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 57 ++++++++++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c | 9 +-- drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h | 2 +- drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 61 +---------------- drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c | 42 +----------- drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c | 65 +------------------ drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c | 30 +-------- 7 files changed, 66 insertions(+), 200 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c index b719852daa07..24d54ab0963a 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c @@ -90,6 +90,40 @@ MODULE_FIRMWARE(FIRMWARE_IP_DISCOVERY); #define mmMM_INDEX_HI 0x6 #define mmMM_DATA 0x1 +MODULE_FIRMWARE("amdgpu/navi10_sdma.bin"); +MODULE_FIRMWARE("amdgpu/navi10_sdma1.bin"); +MODULE_FIRMWARE("amdgpu/navi14_sdma.bin"); +MODULE_FIRMWARE("amdgpu/navi14_sdma1.bin"); +MODULE_FIRMWARE("amdgpu/navi12_sdma.bin"); +MODULE_FIRMWARE("amdgpu/navi12_sdma1.bin"); +MODULE_FIRMWARE("amdgpu/cyan_skillfish2_sdma.bin"); +MODULE_FIRMWARE("amdgpu/cyan_skillfish2_sdma1.bin"); +MODULE_FIRMWARE("amdgpu/vega10_sdma.bin"); +MODULE_FIRMWARE("amdgpu/vega10_sdma1.bin"); +MODULE_FIRMWARE("amdgpu/vega12_sdma.bin"); +MODULE_FIRMWARE("amdgpu/vega12_sdma1.bin"); +MODULE_FIRMWARE("amdgpu/vega20_sdma.bin"); +MODULE_FIRMWARE("amdgpu/vega20_sdma1.bin"); +MODULE_FIRMWARE("amdgpu/raven_sdma.bin"); +MODULE_FIRMWARE("amdgpu/picasso_sdma.bin"); +MODULE_FIRMWARE("amdgpu/raven2_sdma.bin"); +MODULE_FIRMWARE("amdgpu/arcturus_sdma.bin"); +MODULE_FIRMWARE("amdgpu/renoir_sdma.bin"); +MODULE_FIRMWARE("amdgpu/green_sardine_sdma.bin"); +MODULE_FIRMWARE("amdgpu/aldebaran_sdma.bin"); +MODULE_FIRMWARE("amdgpu/sienna_cichlid_sdma.bin"); +MODULE_FIRMWARE("amdgpu/navy_flounder_sdma.bin"); +MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_sdma.bin"); +MODULE_FIRMWARE("amdgpu/beige_goby_sdma.bin"); +MODULE_FIRMWARE("amdgpu/vangogh_sdma.bin"); +MODULE_FIRMWARE("amdgpu/yellow_carp_sdma.bin"); +MODULE_FIRMWARE("amdgpu/sdma_5_2_6.bin"); +MODULE_FIRMWARE("amdgpu/sdma_5_2_7.bin"); +MODULE_FIRMWARE("amdgpu/sdma_6_0_0.bin"); +MODULE_FIRMWARE("amdgpu/sdma_6_0_1.bin"); +MODULE_FIRMWARE("amdgpu/sdma_6_0_2.bin"); +MODULE_FIRMWARE("amdgpu/sdma_6_0_3.bin"); + static const char *hw_id_names[HW_ID_MAX] = { [MP1_HWID] = "MP1", [MP2_HWID] = "MP2", @@ -1821,8 +1855,26 @@ static int amdgpu_discovery_set_gc_ip_blocks(struct amdgpu_device *adev) return 0; } +static int amdgpu_discovery_load_sdma_fw(struct amdgpu_device *adev, u32 instance, + const char *chip_name) +{ + char fw_name[40]; + + if (instance == 0) + snprintf(fw_name, sizeof(fw_name), "amdgpu/%s.bin", chip_name); + else + snprintf(fw_name, sizeof(fw_name), "amdgpu/%s1.bin", chip_name); + + return request_firmware(&adev->sdma.instance[instance].fw, fw_name, adev->dev); +} + static int amdgpu_discovery_set_sdma_ip_blocks(struct amdgpu_device *adev) { + char ucode_prefix[30]; + int i, r; + + amdgpu_ucode_ip_version_decode(adev, SDMA0_HWIP, ucode_prefix, sizeof(ucode_prefix)); + switch (adev->ip_versions[SDMA0_HWIP][0]) { case IP_VERSION(4, 0, 0): case IP_VERSION(4, 0, 1): @@ -1862,6 +1914,11 @@ static int amdgpu_discovery_set_sdma_ip_blocks(struct amdgpu_device *adev) adev->ip_versions[SDMA0_HWIP][0]); return -EINVAL; } + for (i = 0; i < adev->sdma.num_instances; i++) { + r = amdgpu_discovery_load_sdma_fw(adev, i, ucode_prefix); + if (r) + return r; + } return 0; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c index ea5278f094c0..9e46d8034c03 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c @@ -205,8 +205,7 @@ void amdgpu_sdma_destroy_inst_ctx(struct amdgpu_device *adev, } int amdgpu_sdma_init_microcode(struct amdgpu_device *adev, - char *fw_name, u32 instance, - bool duplicate) + u32 instance, bool duplicate) { struct amdgpu_firmware_info *info = NULL; const struct common_firmware_header *header = NULL; @@ -214,10 +213,6 @@ int amdgpu_sdma_init_microcode(struct amdgpu_device *adev, const struct sdma_firmware_header_v2_0 *sdma_hdr; uint16_t version_major; - err = request_firmware(&adev->sdma.instance[instance].fw, fw_name, adev->dev); - if (err) - goto out; - header = (const struct common_firmware_header *) adev->sdma.instance[instance].fw->data; version_major = le16_to_cpu(header->header_version_major); @@ -280,7 +275,7 @@ int amdgpu_sdma_init_microcode(struct amdgpu_device *adev, out: if (err) { - DRM_ERROR("SDMA: Failed to init firmware \"%s\"\n", fw_name); + DRM_ERROR("SDMA: Failed to init sdma firmware\n"); amdgpu_sdma_destroy_inst_ctx(adev, duplicate); } return err; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h index 7d99205c2e01..07b375e89e83 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h @@ -125,7 +125,7 @@ int amdgpu_sdma_process_ecc_irq(struct amdgpu_device *adev, struct amdgpu_irq_src *source, struct amdgpu_iv_entry *entry); int amdgpu_sdma_init_microcode(struct amdgpu_device *adev, - char *fw_name, u32 instance, bool duplicate); + u32 instance, bool duplicate); void amdgpu_sdma_destroy_inst_ctx(struct amdgpu_device *adev, bool duplicate); void amdgpu_sdma_unset_buffer_funcs_helper(struct amdgpu_device *adev); diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c index 4d780e4430e7..bbaee1cfc92d 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c @@ -58,20 +58,6 @@ #include "amdgpu_ras.h" #include "sdma_v4_4.h" -MODULE_FIRMWARE("amdgpu/vega10_sdma.bin"); -MODULE_FIRMWARE("amdgpu/vega10_sdma1.bin"); -MODULE_FIRMWARE("amdgpu/vega12_sdma.bin"); -MODULE_FIRMWARE("amdgpu/vega12_sdma1.bin"); -MODULE_FIRMWARE("amdgpu/vega20_sdma.bin"); -MODULE_FIRMWARE("amdgpu/vega20_sdma1.bin"); -MODULE_FIRMWARE("amdgpu/raven_sdma.bin"); -MODULE_FIRMWARE("amdgpu/picasso_sdma.bin"); -MODULE_FIRMWARE("amdgpu/raven2_sdma.bin"); -MODULE_FIRMWARE("amdgpu/arcturus_sdma.bin"); -MODULE_FIRMWARE("amdgpu/renoir_sdma.bin"); -MODULE_FIRMWARE("amdgpu/green_sardine_sdma.bin"); -MODULE_FIRMWARE("amdgpu/aldebaran_sdma.bin"); - #define SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK 0x000000F8L #define SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK 0xFC000000L @@ -575,60 +561,17 @@ static void sdma_v4_0_setup_ulv(struct amdgpu_device *adev) // vega10 real chip need to use PSP to load firmware static int sdma_v4_0_init_microcode(struct amdgpu_device *adev) { - const char *chip_name; - char fw_name[30]; int ret, i; - DRM_DEBUG("\n"); - - switch (adev->ip_versions[SDMA0_HWIP][0]) { - case IP_VERSION(4, 0, 0): - chip_name = "vega10"; - break; - case IP_VERSION(4, 0, 1): - chip_name = "vega12"; - break; - case IP_VERSION(4, 2, 0): - chip_name = "vega20"; - break; - case IP_VERSION(4, 1, 0): - case IP_VERSION(4, 1, 1): - if (adev->apu_flags & AMD_APU_IS_RAVEN2) - chip_name = "raven2"; - else if (adev->apu_flags & AMD_APU_IS_PICASSO) - chip_name = "picasso"; - else - chip_name = "raven"; - break; - case IP_VERSION(4, 2, 2): - chip_name = "arcturus"; - break; - case IP_VERSION(4, 1, 2): - if (adev->apu_flags & AMD_APU_IS_RENOIR) - chip_name = "renoir"; - else - chip_name = "green_sardine"; - break; - case IP_VERSION(4, 4, 0): - chip_name = "aldebaran"; - break; - default: - BUG(); - } - for (i = 0; i < adev->sdma.num_instances; i++) { - if (i == 0) - snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name); - else - snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma%d.bin", chip_name, i); if (adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(4, 2, 2) || adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(4, 4, 0)) { /* Acturus & Aldebaran will leverage the same FW memory for every SDMA instance */ - ret = amdgpu_sdma_init_microcode(adev, fw_name, 0, true); + ret = amdgpu_sdma_init_microcode(adev, 0, true); break; } else { - ret = amdgpu_sdma_init_microcode(adev, fw_name, i, false); + ret = amdgpu_sdma_init_microcode(adev, i, false); if (ret) return ret; } diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c index d4d9f196db83..4154b511ae94 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c @@ -42,18 +42,6 @@ #include "sdma_common.h" #include "sdma_v5_0.h" -MODULE_FIRMWARE("amdgpu/navi10_sdma.bin"); -MODULE_FIRMWARE("amdgpu/navi10_sdma1.bin"); - -MODULE_FIRMWARE("amdgpu/navi14_sdma.bin"); -MODULE_FIRMWARE("amdgpu/navi14_sdma1.bin"); - -MODULE_FIRMWARE("amdgpu/navi12_sdma.bin"); -MODULE_FIRMWARE("amdgpu/navi12_sdma1.bin"); - -MODULE_FIRMWARE("amdgpu/cyan_skillfish2_sdma.bin"); -MODULE_FIRMWARE("amdgpu/cyan_skillfish2_sdma1.bin"); - #define SDMA1_REG_OFFSET 0x600 #define SDMA0_HYP_DEC_REG_START 0x5880 #define SDMA0_HYP_DEC_REG_END 0x5893 @@ -237,39 +225,13 @@ static void sdma_v5_0_init_golden_registers(struct amdgpu_device *adev) // emulation only, won't work on real chip // navi10 real chip need to use PSP to load firmware static int sdma_v5_0_init_microcode(struct amdgpu_device *adev) -{ - const char *chip_name; - char fw_name[40]; - int ret, i; +{ int ret, i; if (amdgpu_sriov_vf(adev) && (adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(5, 0, 5))) return 0; - DRM_DEBUG("\n"); - - switch (adev->ip_versions[SDMA0_HWIP][0]) { - case IP_VERSION(5, 0, 0): - chip_name = "navi10"; - break; - case IP_VERSION(5, 0, 2): - chip_name = "navi14"; - break; - case IP_VERSION(5, 0, 5): - chip_name = "navi12"; - break; - case IP_VERSION(5, 0, 1): - chip_name = "cyan_skillfish2"; - break; - default: - BUG(); - } - for (i = 0; i < adev->sdma.num_instances; i++) { - if (i == 0) - snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name); - else - snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma1.bin", chip_name); - ret = amdgpu_sdma_init_microcode(adev, fw_name, i, false); + ret = amdgpu_sdma_init_microcode(adev, i, false); if (ret) return ret; } diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c index 65e7a710298d..4757c119cdfe 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c @@ -44,16 +44,6 @@ #include "sdma_common.h" #include "sdma_v5_2.h" -MODULE_FIRMWARE("amdgpu/sienna_cichlid_sdma.bin"); -MODULE_FIRMWARE("amdgpu/navy_flounder_sdma.bin"); -MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_sdma.bin"); -MODULE_FIRMWARE("amdgpu/beige_goby_sdma.bin"); - -MODULE_FIRMWARE("amdgpu/vangogh_sdma.bin"); -MODULE_FIRMWARE("amdgpu/yellow_carp_sdma.bin"); -MODULE_FIRMWARE("amdgpu/sdma_5_2_6.bin"); -MODULE_FIRMWARE("amdgpu/sdma_5_2_7.bin"); - #define SDMA1_REG_OFFSET 0x600 #define SDMA3_REG_OFFSET 0x400 #define SDMA0_HYP_DEC_REG_START 0x5880 @@ -89,59 +79,6 @@ static u32 sdma_v5_2_get_reg_offset(struct amdgpu_device *adev, u32 instance, u3 return base + internal_offset; } -/** - * sdma_v5_2_init_microcode - load ucode images from disk - * - * @adev: amdgpu_device pointer - * - * Use the firmware interface to load the ucode images into - * the driver (not loaded into hw). - * Returns 0 on success, error on failure. - */ - -// emulation only, won't work on real chip -// navi10 real chip need to use PSP to load firmware -static int sdma_v5_2_init_microcode(struct amdgpu_device *adev) -{ - const char *chip_name; - char fw_name[40]; - - DRM_DEBUG("\n"); - - switch (adev->ip_versions[SDMA0_HWIP][0]) { - case IP_VERSION(5, 2, 0): - chip_name = "sienna_cichlid_sdma"; - break; - case IP_VERSION(5, 2, 2): - chip_name = "navy_flounder_sdma"; - break; - case IP_VERSION(5, 2, 1): - chip_name = "vangogh_sdma"; - break; - case IP_VERSION(5, 2, 4): - chip_name = "dimgrey_cavefish_sdma"; - break; - case IP_VERSION(5, 2, 5): - chip_name = "beige_goby_sdma"; - break; - case IP_VERSION(5, 2, 3): - chip_name = "yellow_carp_sdma"; - break; - case IP_VERSION(5, 2, 6): - chip_name = "sdma_5_2_6"; - break; - case IP_VERSION(5, 2, 7): - chip_name = "sdma_5_2_7"; - break; - default: - BUG(); - } - - snprintf(fw_name, sizeof(fw_name), "amdgpu/%s.bin", chip_name); - - return amdgpu_sdma_init_microcode(adev, fw_name, 0, true); -} - static unsigned sdma_v5_2_ring_init_cond_exec(struct amdgpu_ring *ring) { unsigned ret; @@ -1288,7 +1225,7 @@ static int sdma_v5_2_sw_init(void *handle) return r; } - r = sdma_v5_2_init_microcode(adev); + r = amdgpu_sdma_init_microcode(adev, 0, true); if (r) { DRM_ERROR("Failed to load sdma firmware!\n"); return r; diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c index 049c26a45d85..9c65e2f98d44 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c @@ -44,11 +44,6 @@ #include "sdma_v6_0.h" #include "v11_structs.h" -MODULE_FIRMWARE("amdgpu/sdma_6_0_0.bin"); -MODULE_FIRMWARE("amdgpu/sdma_6_0_1.bin"); -MODULE_FIRMWARE("amdgpu/sdma_6_0_2.bin"); -MODULE_FIRMWARE("amdgpu/sdma_6_0_3.bin"); - #define SDMA1_REG_OFFSET 0x600 #define SDMA0_HYP_DEC_REG_START 0x5880 #define SDMA0_HYP_DEC_REG_END 0x589a @@ -78,29 +73,6 @@ static u32 sdma_v6_0_get_reg_offset(struct amdgpu_device *adev, u32 instance, u3 return base + internal_offset; } -/** - * sdma_v6_0_init_microcode - load ucode images from disk - * - * @adev: amdgpu_device pointer - * - * Use the firmware interface to load the ucode images into - * the driver (not loaded into hw). - * Returns 0 on success, error on failure. - */ -static int sdma_v6_0_init_microcode(struct amdgpu_device *adev) -{ - char fw_name[30]; - char ucode_prefix[30]; - - DRM_DEBUG("\n"); - - amdgpu_ucode_ip_version_decode(adev, SDMA0_HWIP, ucode_prefix, sizeof(ucode_prefix)); - - snprintf(fw_name, sizeof(fw_name), "amdgpu/%s.bin", ucode_prefix); - - return amdgpu_sdma_init_microcode(adev, fw_name, 0, true); -} - static unsigned sdma_v6_0_ring_init_cond_exec(struct amdgpu_ring *ring) { unsigned ret; @@ -1260,7 +1232,7 @@ static int sdma_v6_0_sw_init(void *handle) if (r) return r; - r = sdma_v6_0_init_microcode(adev); + r = amdgpu_sdma_init_microcode(adev, 0, true); if (r) { DRM_ERROR("Failed to load sdma firmware!\n"); return r; From patchwork Fri Dec 30 05:21:10 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mario Limonciello X-Patchwork-Id: 37570 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4e01:0:0:0:0:0 with SMTP id p1csp2735963wrt; Thu, 29 Dec 2022 21:23:04 -0800 (PST) X-Google-Smtp-Source: AMrXdXtdWF1pyKoY1JmF1bU0+HwxDUsWwwxuGRRlwlpNeRrzt/TZh5zAg0CSBSndfk33E8M//UBU X-Received: by 2002:a17:902:8688:b0:189:77c1:b5a7 with SMTP id g8-20020a170902868800b0018977c1b5a7mr30122261plo.41.1672377784591; Thu, 29 Dec 2022 21:23:04 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1672377784; cv=pass; d=google.com; s=arc-20160816; b=fV2A0n7agQoovm/tEy+V+W6tWCrKlB6pDjtkSyUfMdxxVTyEpC5w2XXkNz8hda2ka6 RLh6h6K7XoYus3rRPHbXs8suagKoXgThVtAmmVZfoWikggwYABOBiY85O+acc4XW4UgY cpTEqHvuFUPpwG2YATZwkvVsPhGZrCNIAoUv9zigXNNLdcg1EmgnGlHiUJJH899T53gt taGQ+exPQNnhTmFvzJMgsVPIzvwSQ9F87HS/V3a/Y+ffA/XoES9/c/NDx/sA9jh/tqlG 0BrPN3mHf7hj7jIjZ7NdRdRCFmhisF6AKtoUtZZutODPe8xCGgkly8jQYDS9pSvXrp7k 6R9w== ARC-Message-Signature: i=2; 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Thu, 29 Dec 2022 23:21:43 -0600 From: Mario Limonciello To: Alex Deucher , CC: Javier Martinez Canillas , Carlos Soriano Sanchez , , , David Airlie , "Daniel Vetter" , , Mario Limonciello , "Pan, Xinhui" Subject: [PATCH v3 06/11] drm/amd: Request VCN microcode during IP discovery Date: Thu, 29 Dec 2022 23:21:10 -0600 Message-ID: <20221230052119.15096-7-mario.limonciello@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221230052119.15096-1-mario.limonciello@amd.com> References: <20221230052119.15096-1-mario.limonciello@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1NAM11FT043:EE_|SN7PR12MB6691:EE_ X-MS-Office365-Filtering-Correlation-Id: dfaa0f81-4b34-45c4-c9b1-08daea25bdb0 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 6EgP22On75keHqe/zSywae7ldWI5nf9hBB4IqeeHYZtkQy7JN05zC4DCVx6DsCRs75iQBqGC6qwo86O2xGvUIT0KVefILTc2E5A9EVaMXq/1sNvFU4re3JcA+0oJMKesqrgMowGl3Ok3mKkhRejaQOd/cI5hyhohd9tRzo1uJgIdo61q+763yiPqpMX28z2BHtLyNo1u2tJfE9KzT55Q8rFeGHtoJvPjIPGqnQ4u4t9rJ0DTtej2KLo91h41h+mvR0rdq2BYQSJvpy/u7orYXj/nD2/G6YB/SygzHXYWCUXC8LLelbdr9lkjzR0GEMK7hI4A/2EvG1O7Kj3SO/rXp5mWTIe4aK8yN/zUP+guyhuqKYS/meusI+NmDP6k4uLHyU63EQL3Uo7vHsdJBoOVSkLy+TuvyeMqqwneIdBiG+yDOSshr/ht4msMbCMOWX+4j+6ixRitjGrbD80OZirP2lqCavuQdyvIjgMlZedxsYPSKIOn46vaggcVGhw0w4/S+fapjCo7S8YCCwjQgCSq7jwLsX5OmB6wC3jYQTuFKuQyA3vBh4oFPgYJjSpGvc4ruZGN7oemXDxunoV4oortQ+T0nBaj5gKniqdF74kirpDPVmVQ8bGe7LcwQMj9jX28v+BZg5NoWtJEEajL0Yg6wegYKE468x9Pcu3Qt1848nw+fDbnRr3hiYGzwCb5SMCz5NNjTX1gsWsbHmsBOrSb1MZUOmZynpNjY0tqz6Osxxw= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230022)(4636009)(136003)(39860400002)(396003)(346002)(376002)(451199015)(46966006)(36840700001)(40470700004)(356005)(40480700001)(36756003)(40460700003)(86362001)(7696005)(54906003)(6666004)(110136005)(316002)(478600001)(5660300002)(8936002)(2906002)(70586007)(8676002)(70206006)(4326008)(36860700001)(41300700001)(44832011)(47076005)(82740400003)(81166007)(82310400005)(2616005)(1076003)(26005)(336012)(16526019)(426003)(186003)(83380400001)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Dec 2022 05:21:44.2109 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: dfaa0f81-4b34-45c4-c9b1-08daea25bdb0 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT043.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB6691 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1753615207585469466?= X-GMAIL-MSGID: =?utf-8?q?1753615207585469466?= If VCN microcode is not available during early init, the firmware framebuffer will have already been released and the screen will freeze. Move the request for VCN microcode into the IP discovery phase so that if it's not available, IP discovery will fail. Reviewed-by: Alex Deucher Signed-off-by: Mario Limonciello --- drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 41 ++++++++- drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 85 +------------------ 2 files changed, 41 insertions(+), 85 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c index 24d54ab0963a..07c05782a0e3 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c @@ -124,6 +124,27 @@ MODULE_FIRMWARE("amdgpu/sdma_6_0_1.bin"); MODULE_FIRMWARE("amdgpu/sdma_6_0_2.bin"); MODULE_FIRMWARE("amdgpu/sdma_6_0_3.bin"); +MODULE_FIRMWARE("amdgpu/raven_vcn.bin"); +MODULE_FIRMWARE("amdgpu/picasso_vcn.bin"); +MODULE_FIRMWARE("amdgpu/raven2_vcn.bin"); +MODULE_FIRMWARE("amdgpu/arcturus_vcn.bin"); +MODULE_FIRMWARE("amdgpu/renoir_vcn.bin"); +MODULE_FIRMWARE("amdgpu/green_sardine_vcn.bin"); +MODULE_FIRMWARE("amdgpu/aldebaran_vcn.bin"); +MODULE_FIRMWARE("amdgpu/navi10_vcn.bin"); +MODULE_FIRMWARE("amdgpu/navi14_vcn.bin"); +MODULE_FIRMWARE("amdgpu/navi12_vcn.bin"); +MODULE_FIRMWARE("amdgpu/sienna_cichlid_vcn.bin"); +MODULE_FIRMWARE("amdgpu/navy_flounder_vcn.bin"); +MODULE_FIRMWARE("amdgpu/vangogh_vcn.bin"); +MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_vcn.bin"); +MODULE_FIRMWARE("amdgpu/beige_goby_vcn.bin"); +MODULE_FIRMWARE("amdgpu/yellow_carp_vcn.bin"); +MODULE_FIRMWARE("amdgpu/vcn_3_1_2.bin"); +MODULE_FIRMWARE("amdgpu/vcn_4_0_0.bin"); +MODULE_FIRMWARE("amdgpu/vcn_4_0_2.bin"); +MODULE_FIRMWARE("amdgpu/vcn_4_0_4.bin"); + static const char *hw_id_names[HW_ID_MAX] = { [MP1_HWID] = "MP1", [MP2_HWID] = "MP2", @@ -1922,8 +1943,23 @@ static int amdgpu_discovery_set_sdma_ip_blocks(struct amdgpu_device *adev) return 0; } +static int amdgpu_discovery_load_vcn_fw(struct amdgpu_device *adev, + char *fname) +{ + char fw_name[40]; + + snprintf(fw_name, sizeof(fw_name), "amdgpu/%s.bin", fname); + + return request_firmware(&adev->vcn.fw, fw_name, adev->dev); +} + static int amdgpu_discovery_set_mm_ip_blocks(struct amdgpu_device *adev) { + char ucode_prefix[30]; + int r = 0; + + amdgpu_ucode_ip_version_decode(adev, UVD_HWIP, ucode_prefix, sizeof(ucode_prefix)); + if (adev->ip_versions[VCE_HWIP][0]) { switch (adev->ip_versions[UVD_HWIP][0]) { case IP_VERSION(7, 0, 0): @@ -2001,7 +2037,10 @@ static int amdgpu_discovery_set_mm_ip_blocks(struct amdgpu_device *adev) return -EINVAL; } } - return 0; + if (*ucode_prefix) + r = amdgpu_discovery_load_vcn_fw(adev, ucode_prefix); + return r; +} } static int amdgpu_discovery_set_mes_ip_blocks(struct amdgpu_device *adev) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c index a23e26b272b4..370c9644a3b3 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c @@ -35,55 +35,11 @@ #include "amdgpu_vcn.h" #include "soc15d.h" -/* Firmware Names */ -#define FIRMWARE_RAVEN "amdgpu/raven_vcn.bin" -#define FIRMWARE_PICASSO "amdgpu/picasso_vcn.bin" -#define FIRMWARE_RAVEN2 "amdgpu/raven2_vcn.bin" -#define FIRMWARE_ARCTURUS "amdgpu/arcturus_vcn.bin" -#define FIRMWARE_RENOIR "amdgpu/renoir_vcn.bin" -#define FIRMWARE_GREEN_SARDINE "amdgpu/green_sardine_vcn.bin" -#define FIRMWARE_NAVI10 "amdgpu/navi10_vcn.bin" -#define FIRMWARE_NAVI14 "amdgpu/navi14_vcn.bin" -#define FIRMWARE_NAVI12 "amdgpu/navi12_vcn.bin" -#define FIRMWARE_SIENNA_CICHLID "amdgpu/sienna_cichlid_vcn.bin" -#define FIRMWARE_NAVY_FLOUNDER "amdgpu/navy_flounder_vcn.bin" -#define FIRMWARE_VANGOGH "amdgpu/vangogh_vcn.bin" -#define FIRMWARE_DIMGREY_CAVEFISH "amdgpu/dimgrey_cavefish_vcn.bin" -#define FIRMWARE_ALDEBARAN "amdgpu/aldebaran_vcn.bin" -#define FIRMWARE_BEIGE_GOBY "amdgpu/beige_goby_vcn.bin" -#define FIRMWARE_YELLOW_CARP "amdgpu/yellow_carp_vcn.bin" -#define FIRMWARE_VCN_3_1_2 "amdgpu/vcn_3_1_2.bin" -#define FIRMWARE_VCN4_0_0 "amdgpu/vcn_4_0_0.bin" -#define FIRMWARE_VCN4_0_2 "amdgpu/vcn_4_0_2.bin" -#define FIRMWARE_VCN4_0_4 "amdgpu/vcn_4_0_4.bin" - -MODULE_FIRMWARE(FIRMWARE_RAVEN); -MODULE_FIRMWARE(FIRMWARE_PICASSO); -MODULE_FIRMWARE(FIRMWARE_RAVEN2); -MODULE_FIRMWARE(FIRMWARE_ARCTURUS); -MODULE_FIRMWARE(FIRMWARE_RENOIR); -MODULE_FIRMWARE(FIRMWARE_GREEN_SARDINE); -MODULE_FIRMWARE(FIRMWARE_ALDEBARAN); -MODULE_FIRMWARE(FIRMWARE_NAVI10); -MODULE_FIRMWARE(FIRMWARE_NAVI14); -MODULE_FIRMWARE(FIRMWARE_NAVI12); -MODULE_FIRMWARE(FIRMWARE_SIENNA_CICHLID); -MODULE_FIRMWARE(FIRMWARE_NAVY_FLOUNDER); -MODULE_FIRMWARE(FIRMWARE_VANGOGH); -MODULE_FIRMWARE(FIRMWARE_DIMGREY_CAVEFISH); -MODULE_FIRMWARE(FIRMWARE_BEIGE_GOBY); -MODULE_FIRMWARE(FIRMWARE_YELLOW_CARP); -MODULE_FIRMWARE(FIRMWARE_VCN_3_1_2); -MODULE_FIRMWARE(FIRMWARE_VCN4_0_0); -MODULE_FIRMWARE(FIRMWARE_VCN4_0_2); -MODULE_FIRMWARE(FIRMWARE_VCN4_0_4); - static void amdgpu_vcn_idle_work_handler(struct work_struct *work); int amdgpu_vcn_sw_init(struct amdgpu_device *adev) { unsigned long bo_size; - const char *fw_name; const struct common_firmware_header *hdr; unsigned char fw_check; unsigned int fw_shared_size, log_offset; @@ -99,46 +55,27 @@ int amdgpu_vcn_sw_init(struct amdgpu_device *adev) switch (adev->ip_versions[UVD_HWIP][0]) { case IP_VERSION(1, 0, 0): case IP_VERSION(1, 0, 1): - if (adev->apu_flags & AMD_APU_IS_RAVEN2) - fw_name = FIRMWARE_RAVEN2; - else if (adev->apu_flags & AMD_APU_IS_PICASSO) - fw_name = FIRMWARE_PICASSO; - else - fw_name = FIRMWARE_RAVEN; - break; case IP_VERSION(2, 5, 0): - fw_name = FIRMWARE_ARCTURUS; if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) && (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)) adev->vcn.indirect_sram = true; break; case IP_VERSION(2, 2, 0): - if (adev->apu_flags & AMD_APU_IS_RENOIR) - fw_name = FIRMWARE_RENOIR; - else - fw_name = FIRMWARE_GREEN_SARDINE; - if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) && (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)) adev->vcn.indirect_sram = true; break; case IP_VERSION(2, 6, 0): - fw_name = FIRMWARE_ALDEBARAN; if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) && (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)) adev->vcn.indirect_sram = true; break; case IP_VERSION(2, 0, 0): - fw_name = FIRMWARE_NAVI10; if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) && (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)) adev->vcn.indirect_sram = true; break; case IP_VERSION(2, 0, 2): - if (adev->asic_type == CHIP_NAVI12) - fw_name = FIRMWARE_NAVI12; - else - fw_name = FIRMWARE_NAVI14; if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) && (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)) adev->vcn.indirect_sram = true; @@ -146,58 +83,46 @@ int amdgpu_vcn_sw_init(struct amdgpu_device *adev) case IP_VERSION(3, 0, 0): case IP_VERSION(3, 0, 64): case IP_VERSION(3, 0, 192): - if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 0)) - fw_name = FIRMWARE_SIENNA_CICHLID; - else - fw_name = FIRMWARE_NAVY_FLOUNDER; if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) && (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)) adev->vcn.indirect_sram = true; break; case IP_VERSION(3, 0, 2): - fw_name = FIRMWARE_VANGOGH; if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) && (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)) adev->vcn.indirect_sram = true; break; case IP_VERSION(3, 0, 16): - fw_name = FIRMWARE_DIMGREY_CAVEFISH; if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) && (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)) adev->vcn.indirect_sram = true; break; case IP_VERSION(3, 0, 33): - fw_name = FIRMWARE_BEIGE_GOBY; if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) && (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)) adev->vcn.indirect_sram = true; break; case IP_VERSION(3, 1, 1): - fw_name = FIRMWARE_YELLOW_CARP; if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) && (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)) adev->vcn.indirect_sram = true; break; case IP_VERSION(3, 1, 2): - fw_name = FIRMWARE_VCN_3_1_2; if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) && (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)) adev->vcn.indirect_sram = true; break; case IP_VERSION(4, 0, 0): - fw_name = FIRMWARE_VCN4_0_0; if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) && (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)) adev->vcn.indirect_sram = true; break; case IP_VERSION(4, 0, 2): - fw_name = FIRMWARE_VCN4_0_2; if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) && (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)) adev->vcn.indirect_sram = true; break; case IP_VERSION(4, 0, 4): - fw_name = FIRMWARE_VCN4_0_4; if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) && (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)) adev->vcn.indirect_sram = true; @@ -206,17 +131,9 @@ int amdgpu_vcn_sw_init(struct amdgpu_device *adev) return -EINVAL; } - r = request_firmware(&adev->vcn.fw, fw_name, adev->dev); - if (r) { - dev_err(adev->dev, "amdgpu_vcn: Can't load firmware \"%s\"\n", - fw_name); - return r; - } - r = amdgpu_ucode_validate(adev->vcn.fw); if (r) { - dev_err(adev->dev, "amdgpu_vcn: Can't validate firmware \"%s\"\n", - fw_name); + dev_err(adev->dev, "amdgpu_vcn: Can't validate firmware\n"); release_firmware(adev->vcn.fw); adev->vcn.fw = NULL; return r; From patchwork Fri Dec 30 05:21:11 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mario Limonciello X-Patchwork-Id: 37572 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4e01:0:0:0:0:0 with SMTP id p1csp2735993wrt; Thu, 29 Dec 2022 21:23:11 -0800 (PST) X-Google-Smtp-Source: AMrXdXt+b/4ivKlTJBNwbheRkd/+I4RT6+C+MEjoI7k2CwCMcTLLe+V3AFhNf2iwdpd2HfCWBmaZ X-Received: by 2002:a17:902:f706:b0:190:fc28:8cca with SMTP id h6-20020a170902f70600b00190fc288ccamr37055484plo.10.1672377791372; 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Thu, 29 Dec 2022 23:21:44 -0600 From: Mario Limonciello To: Alex Deucher , CC: Javier Martinez Canillas , Carlos Soriano Sanchez , , , David Airlie , "Daniel Vetter" , , Mario Limonciello , "Pan, Xinhui" Subject: [PATCH v3 07/11] drm/amd: Request MES microcode during IP discovery Date: Thu, 29 Dec 2022 23:21:11 -0600 Message-ID: <20221230052119.15096-8-mario.limonciello@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221230052119.15096-1-mario.limonciello@amd.com> References: <20221230052119.15096-1-mario.limonciello@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1NAM11FT055:EE_|BL1PR12MB5253:EE_ X-MS-Office365-Filtering-Correlation-Id: 66e4eb00-936e-4b6d-2e30-08daea25beb1 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: SBI524RAhzE218OZ/fBDsyONZmUNadtNCDP1s8PweaQqPa1wQdNpyqO8XABogv5z34CNCKtEq0xgIuKzy0nHZvood1uOl6NO5gPx1xwHtWQmaiTmmRfFdPNe1cA4AquO2gx4S+4prG+/v6NURQ69jK5yRtYiXWfLH9o6O79XMRR3cX4fDdVxxN3bEoVonab0fE/erkPAaAHVPeOTMVSrfm294mf/wFkdJlYk6rHoy5p9S39F064pYib2vrZMxTu8/yJ1kON2sCtAi0J+9bvVD27PHF+OX4+lXxbEQ4AeENA4gPTVGJLx9TENxoux0HIniAnfyuMPcrLOz4KU0e1LCWsLZH/rvqJZgA3A1seAvXhXsujNVVnFSbz0nN6rcJtj7INV+8ardv4iUMjPDhGQEWiIIL5CLGN2Vkn7QEC3+u0hLIyWqHCIklvzt2wv1rR3R1pbumQ/GzwngEnPrx13++UhUF6dqNc7TKvcVf7z9M86r1QeFJmV7emPQ0Lr6OXttHAkpOSOKXMEnIDEnh8xN1hMs50s7aaHwsdX2WPgIjW8Qn8UspM1z9HLu30VcdTM7ElYeBL3VavBSAXaght5yipPvvlS6F03++mASrWuAnAOZ8wAg6zmVbqjhtQFGYRuavn6SewKjVRnlO+LZs/ZQvvFlegZqvWDMiwvjnjFtWeqGurNwvpA10r5stsr1lHp2ibf8+gS4RWgML3iqFbsJghsNGb3q4K1QepvpM4FcUY= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230022)(4636009)(396003)(376002)(136003)(39860400002)(346002)(451199015)(36840700001)(40470700004)(46966006)(70586007)(5660300002)(4326008)(70206006)(8676002)(16526019)(41300700001)(44832011)(8936002)(26005)(426003)(186003)(2616005)(36756003)(356005)(2906002)(110136005)(54906003)(40460700003)(478600001)(316002)(86362001)(6666004)(40480700001)(336012)(1076003)(7696005)(47076005)(81166007)(82740400003)(82310400005)(83380400001)(36860700001)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Dec 2022 05:21:45.8756 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 66e4eb00-936e-4b6d-2e30-08daea25beb1 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT055.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL1PR12MB5253 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1753615214625311340?= X-GMAIL-MSGID: =?utf-8?q?1753615214625311340?= If MES microcode is required but not available during early init, the firmware framebuffer will have already been released and the screen will freeze. Move the request for MES microcode into the IP discovery phase so that if it's not available, IP discovery will fail. Reviewed-by: Alex Deucher Signed-off-by: Mario Limonciello --- v2->v3: * Add a missing newline --- drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 40 +++++++++++++++++++ drivers/gpu/drm/amd/amdgpu/mes_v10_1.c | 28 ------------- drivers/gpu/drm/amd/amdgpu/mes_v11_0.c | 25 +----------- 3 files changed, 41 insertions(+), 52 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c index 07c05782a0e3..edaeec35c39f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c @@ -145,6 +145,19 @@ MODULE_FIRMWARE("amdgpu/vcn_4_0_0.bin"); MODULE_FIRMWARE("amdgpu/vcn_4_0_2.bin"); MODULE_FIRMWARE("amdgpu/vcn_4_0_4.bin"); +MODULE_FIRMWARE("amdgpu/navi10_mes.bin"); +MODULE_FIRMWARE("amdgpu/sienna_cichlid_mes.bin"); +MODULE_FIRMWARE("amdgpu/sienna_cichlid_mes1.bin"); + +MODULE_FIRMWARE("amdgpu/gc_11_0_0_mes.bin"); +MODULE_FIRMWARE("amdgpu/gc_11_0_0_mes1.bin"); +MODULE_FIRMWARE("amdgpu/gc_11_0_1_mes.bin"); +MODULE_FIRMWARE("amdgpu/gc_11_0_1_mes1.bin"); +MODULE_FIRMWARE("amdgpu/gc_11_0_2_mes.bin"); +MODULE_FIRMWARE("amdgpu/gc_11_0_2_mes1.bin"); +MODULE_FIRMWARE("amdgpu/gc_11_0_3_mes.bin"); +MODULE_FIRMWARE("amdgpu/gc_11_0_3_mes1.bin"); + static const char *hw_id_names[HW_ID_MAX] = { [MP1_HWID] = "MP1", [MP2_HWID] = "MP2", @@ -2041,10 +2054,30 @@ static int amdgpu_discovery_set_mm_ip_blocks(struct amdgpu_device *adev) r = amdgpu_discovery_load_vcn_fw(adev, ucode_prefix); return r; } + +static int amdgpu_discovery_load_mes_fw(struct amdgpu_device *adev, + enum admgpu_mes_pipe pipe, + const char *ucode_prefix) +{ + char fw_name[40]; + + if (pipe == AMDGPU_MES_SCHED_PIPE) + snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mes.bin", + ucode_prefix); + else + snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mes1.bin", + ucode_prefix); + + return request_firmware(&adev->mes.fw[pipe], fw_name, adev->dev); } static int amdgpu_discovery_set_mes_ip_blocks(struct amdgpu_device *adev) { + char ucode_prefix[30]; + int pipe, r; + + amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_prefix)); + switch (adev->ip_versions[GC_HWIP][0]) { case IP_VERSION(10, 1, 10): case IP_VERSION(10, 1, 1): @@ -2077,6 +2110,13 @@ static int amdgpu_discovery_set_mes_ip_blocks(struct amdgpu_device *adev) default: break; } + if (adev->enable_mes) { + for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { + r = amdgpu_discovery_load_mes_fw(adev, pipe, ucode_prefix); + if (r) + return r; + } + } return 0; } diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c b/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c index 614394118a53..9faa9867b3c9 100644 --- a/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c +++ b/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c @@ -37,10 +37,6 @@ #define mmRLC_CP_SCHEDULERS_Sienna_Cichlid 0x4ca1 #define mmRLC_CP_SCHEDULERS_Sienna_Cichlid_BASE_IDX 1 -MODULE_FIRMWARE("amdgpu/navi10_mes.bin"); -MODULE_FIRMWARE("amdgpu/sienna_cichlid_mes.bin"); -MODULE_FIRMWARE("amdgpu/sienna_cichlid_mes1.bin"); - static int mes_v10_1_hw_fini(void *handle); static int mes_v10_1_kiq_hw_init(struct amdgpu_device *adev); @@ -382,34 +378,10 @@ static const struct amdgpu_mes_funcs mes_v10_1_funcs = { static int mes_v10_1_init_microcode(struct amdgpu_device *adev, enum admgpu_mes_pipe pipe) { - const char *chip_name; - char fw_name[30]; int err; const struct mes_firmware_header_v1_0 *mes_hdr; struct amdgpu_firmware_info *info; - switch (adev->ip_versions[GC_HWIP][0]) { - case IP_VERSION(10, 1, 10): - chip_name = "navi10"; - break; - case IP_VERSION(10, 3, 0): - chip_name = "sienna_cichlid"; - break; - default: - BUG(); - } - - if (pipe == AMDGPU_MES_SCHED_PIPE) - snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mes.bin", - chip_name); - else - snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mes1.bin", - chip_name); - - err = request_firmware(&adev->mes.fw[pipe], fw_name, adev->dev); - if (err) - return err; - err = amdgpu_ucode_validate(adev->mes.fw[pipe]); if (err) { release_firmware(adev->mes.fw[pipe]); diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c index 970b066b37bb..27176a1259ac 100644 --- a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c @@ -32,15 +32,6 @@ #include "v11_structs.h" #include "mes_v11_api_def.h" -MODULE_FIRMWARE("amdgpu/gc_11_0_0_mes.bin"); -MODULE_FIRMWARE("amdgpu/gc_11_0_0_mes1.bin"); -MODULE_FIRMWARE("amdgpu/gc_11_0_1_mes.bin"); -MODULE_FIRMWARE("amdgpu/gc_11_0_1_mes1.bin"); -MODULE_FIRMWARE("amdgpu/gc_11_0_2_mes.bin"); -MODULE_FIRMWARE("amdgpu/gc_11_0_2_mes1.bin"); -MODULE_FIRMWARE("amdgpu/gc_11_0_3_mes.bin"); -MODULE_FIRMWARE("amdgpu/gc_11_0_3_mes1.bin"); - static int mes_v11_0_hw_fini(void *handle); static int mes_v11_0_kiq_hw_init(struct amdgpu_device *adev); static int mes_v11_0_kiq_hw_fini(struct amdgpu_device *adev); @@ -462,25 +453,11 @@ static const struct amdgpu_mes_funcs mes_v11_0_funcs = { static int mes_v11_0_init_microcode(struct amdgpu_device *adev, enum admgpu_mes_pipe pipe) { - char fw_name[30]; - char ucode_prefix[30]; + int err; const struct mes_firmware_header_v1_0 *mes_hdr; struct amdgpu_firmware_info *info; - amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_prefix)); - - if (pipe == AMDGPU_MES_SCHED_PIPE) - snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mes.bin", - ucode_prefix); - else - snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mes1.bin", - ucode_prefix); - - err = request_firmware(&adev->mes.fw[pipe], fw_name, adev->dev); - if (err) - return err; - err = amdgpu_ucode_validate(adev->mes.fw[pipe]); if (err) { release_firmware(adev->mes.fw[pipe]); From patchwork Fri Dec 30 05:21:12 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mario Limonciello X-Patchwork-Id: 37575 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4e01:0:0:0:0:0 with SMTP id p1csp2736201wrt; Thu, 29 Dec 2022 21:24:04 -0800 (PST) X-Google-Smtp-Source: AMrXdXv9hZR6Noirmg0dVPOHAmS0BqHzzo/nP3JMbPqtHPYonAWlyLe1wAkPUSlx6xvXey26xteD X-Received: by 2002:a17:903:3311:b0:189:c380:7c7c with SMTP id jk17-20020a170903331100b00189c3807c7cmr34023959plb.23.1672377843984; Thu, 29 Dec 2022 21:24:03 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1672377843; cv=pass; d=google.com; s=arc-20160816; b=y0HHbAKtuWAjE5XsRSM0TZzN8rh8k/+ozG2wLoRt7DoUxwHzuzIUZ/bY1X7ChIhm/r XYqkRmSM7spDzs+sfZWz6f8380kGoSLdyIEkLnb0IhvoBUyIejTbLv7X8CRA0OOZC0T+ S21tyt1nXthg9NQcRrClay0Jq4rvTk4/M9LVMW8Uvjpl5miBKMUDSQjvTpLwp4qTBBwR pxosKTOY/n8qp2+l1dYPV1j9B+EZc/eEjOrre/9BnfYGX2nkRVGva8RIgdtjU+Ly6vF1 ZPr2tYWFKBiyhln9M5AoF6p2ZZKhV91+4nONrfTH2tiPUkbx0epmE2P9WbbeE1OoBCzn 1JNQ== ARC-Message-Signature: i=2; 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Thu, 29 Dec 2022 23:21:45 -0600 From: Mario Limonciello To: Alex Deucher , CC: Javier Martinez Canillas , Carlos Soriano Sanchez , , , David Airlie , "Daniel Vetter" , , Mario Limonciello , "Pan, Xinhui" Subject: [PATCH v3 08/11] drm/amd: Request GFX9 microcode during IP discovery Date: Thu, 29 Dec 2022 23:21:12 -0600 Message-ID: <20221230052119.15096-9-mario.limonciello@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221230052119.15096-1-mario.limonciello@amd.com> References: <20221230052119.15096-1-mario.limonciello@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1NAM11FT055:EE_|SJ0PR12MB5675:EE_ X-MS-Office365-Filtering-Correlation-Id: c2233bcc-73db-4300-8cf2-08daea25c01b X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: nIiMIfcpW5aQIXxpteTV7Bm6TPnfJw1kJj4SpM6mUUIYY6oVOLFVMpajIHEw8HgQwndwG5IBOfemkqgpkFjNrL/GxiJ3w6rL3vs4WZ6AJ1SHT0GUyQG8fXalZivwmfQTFqq/KG2Q02t52BJtefpXOmGrrwWUXw1bOnyPBQmMx3QETm9xktCbd5jrbzGvK5dHued5xIod1dW1NYhcwynIkMm0yuM2v8ySRO2l3p8DdxcF+eSqvYoAX/3yqJSTfOiyZ4mTJUrN31T+9js/KnoUINHIWVPm5dZheHdLAbsBpP4SDgMGWk0Hcbft4I6HDPBCbzgvo0+3xbqd5ZY6rbCYG3kcWvFBCgWyXxMpuojHvDoinSBkIJudKemPvHq6qq+J39/yuHmdDcGU+42Qi1oEZMM+4/VK9AalxcB6yTudKlPVQDqsI+3JDH9BugxrjvahT//Sol339URs7Kt6FxoiC8G9UCXzAQArrD+Nt5Vw/DRMn+Y19xm7luAwovRdfs+fYaEJvzk1MuVmvbiDrKIS81ay4gUY3k5E74H3YD6FJFoo6ZTu2MH4ikHXt7NHIKZhjl1IZWHpW5V9DkTt6X+/Fz1QhMMPJw1z+e07jklr4yZCRXXz6o0hAn1u8kjWrha3ketlz5087zAKw8WT4RlEkIC66sIOl32a37dol12oj8a2w5azzRog3CxW1wIjGvJGQQLzjBsgxP66un/LgOXBR0dtw3nR78NY5rjPGlcLyTA= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230022)(4636009)(136003)(39860400002)(396003)(346002)(376002)(451199015)(46966006)(40470700004)(36840700001)(83380400001)(336012)(426003)(2616005)(1076003)(36756003)(356005)(26005)(16526019)(478600001)(82310400005)(6666004)(7696005)(47076005)(40480700001)(86362001)(36860700001)(40460700003)(81166007)(5660300002)(186003)(30864003)(82740400003)(8936002)(44832011)(2906002)(110136005)(316002)(54906003)(4326008)(70206006)(8676002)(41300700001)(70586007)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Dec 2022 05:21:48.2504 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c2233bcc-73db-4300-8cf2-08daea25c01b X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT055.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ0PR12MB5675 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1753615270125578047?= X-GMAIL-MSGID: =?utf-8?q?1753615270125578047?= If GFX9 microcode is required but not available during early init, the firmware framebuffer will have already been released and the screen will freeze. Move the request for GFX9 microcode into the IP discovery phase so that if it's not available, IP discovery will fail. Signed-off-by: Mario Limonciello --- v2->v3: * Fix issues found on real hardware where num_gfx_rings not set during discovery --- drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 147 +++++++++++++ drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 194 ++---------------- 2 files changed, 161 insertions(+), 180 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c index edaeec35c39f..0ff1b3872441 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c @@ -158,6 +158,68 @@ MODULE_FIRMWARE("amdgpu/gc_11_0_2_mes1.bin"); MODULE_FIRMWARE("amdgpu/gc_11_0_3_mes.bin"); MODULE_FIRMWARE("amdgpu/gc_11_0_3_mes1.bin"); + +/* gfx9 */ +MODULE_FIRMWARE("amdgpu/vega10_ce.bin"); +MODULE_FIRMWARE("amdgpu/vega10_pfp.bin"); +MODULE_FIRMWARE("amdgpu/vega10_me.bin"); +MODULE_FIRMWARE("amdgpu/vega10_mec.bin"); +MODULE_FIRMWARE("amdgpu/vega10_mec2.bin"); +MODULE_FIRMWARE("amdgpu/vega10_rlc.bin"); + +MODULE_FIRMWARE("amdgpu/vega12_ce.bin"); +MODULE_FIRMWARE("amdgpu/vega12_pfp.bin"); +MODULE_FIRMWARE("amdgpu/vega12_me.bin"); +MODULE_FIRMWARE("amdgpu/vega12_mec.bin"); +MODULE_FIRMWARE("amdgpu/vega12_mec2.bin"); +MODULE_FIRMWARE("amdgpu/vega12_rlc.bin"); + +MODULE_FIRMWARE("amdgpu/vega20_ce.bin"); +MODULE_FIRMWARE("amdgpu/vega20_pfp.bin"); +MODULE_FIRMWARE("amdgpu/vega20_me.bin"); +MODULE_FIRMWARE("amdgpu/vega20_mec.bin"); +MODULE_FIRMWARE("amdgpu/vega20_mec2.bin"); +MODULE_FIRMWARE("amdgpu/vega20_rlc.bin"); + +MODULE_FIRMWARE("amdgpu/raven_ce.bin"); +MODULE_FIRMWARE("amdgpu/raven_pfp.bin"); +MODULE_FIRMWARE("amdgpu/raven_me.bin"); +MODULE_FIRMWARE("amdgpu/raven_mec.bin"); +MODULE_FIRMWARE("amdgpu/raven_mec2.bin"); +MODULE_FIRMWARE("amdgpu/raven_rlc.bin"); + +MODULE_FIRMWARE("amdgpu/picasso_ce.bin"); +MODULE_FIRMWARE("amdgpu/picasso_pfp.bin"); +MODULE_FIRMWARE("amdgpu/picasso_me.bin"); +MODULE_FIRMWARE("amdgpu/picasso_mec.bin"); +MODULE_FIRMWARE("amdgpu/picasso_mec2.bin"); +MODULE_FIRMWARE("amdgpu/picasso_rlc.bin"); +MODULE_FIRMWARE("amdgpu/picasso_rlc_am4.bin"); + +MODULE_FIRMWARE("amdgpu/raven2_ce.bin"); +MODULE_FIRMWARE("amdgpu/raven2_pfp.bin"); +MODULE_FIRMWARE("amdgpu/raven2_me.bin"); +MODULE_FIRMWARE("amdgpu/raven2_mec.bin"); +MODULE_FIRMWARE("amdgpu/raven2_mec2.bin"); +MODULE_FIRMWARE("amdgpu/raven2_rlc.bin"); +MODULE_FIRMWARE("amdgpu/raven_kicker_rlc.bin"); + +MODULE_FIRMWARE("amdgpu/arcturus_mec.bin"); +MODULE_FIRMWARE("amdgpu/arcturus_rlc.bin"); + +MODULE_FIRMWARE("amdgpu/renoir_ce.bin"); +MODULE_FIRMWARE("amdgpu/renoir_pfp.bin"); +MODULE_FIRMWARE("amdgpu/renoir_me.bin"); +MODULE_FIRMWARE("amdgpu/renoir_mec.bin"); +MODULE_FIRMWARE("amdgpu/renoir_rlc.bin"); + +MODULE_FIRMWARE("amdgpu/green_sardine_ce.bin"); +MODULE_FIRMWARE("amdgpu/green_sardine_pfp.bin"); +MODULE_FIRMWARE("amdgpu/green_sardine_me.bin"); +MODULE_FIRMWARE("amdgpu/green_sardine_mec.bin"); +MODULE_FIRMWARE("amdgpu/green_sardine_mec2.bin"); +MODULE_FIRMWARE("amdgpu/green_sardine_rlc.bin"); + static const char *hw_id_names[HW_ID_MAX] = { [MP1_HWID] = "MP1", [MP2_HWID] = "MP2", @@ -1845,8 +1907,90 @@ static int amdgpu_discovery_set_display_ip_blocks(struct amdgpu_device *adev) return 0; } +static int amdgpu_discovery_load_gfx9(struct amdgpu_device *adev, char *ucode_prefix) +{ + uint32_t smu_version; + char fw_name[40]; + int r; + + switch (adev->ip_versions[GC_HWIP][0]) { + /* No CPG in Arcturus */ + case IP_VERSION(9, 4, 1): + case IP_VERSION(9, 4, 2): + break; + default: + snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp.bin", ucode_prefix); + r = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev); + if (r) + return r; + + snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", ucode_prefix); + r = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev); + if (r) + return r; + + snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce.bin", ucode_prefix); + r = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev); + if (r) + return r; + } + + if (amdgpu_sriov_vf(adev) && (adev->asic_type == CHIP_ALDEBARAN)) + snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sjt_mec.bin", ucode_prefix); + else + snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", ucode_prefix); + r = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev); + if (r) + return r; + + /* + * For Picasso && AM4 SOCKET board, we use picasso_rlc_am4.bin + * instead of picasso_rlc.bin. + * Judgment method: + * PCO AM4: revision >= 0xC8 && revision <= 0xCF + * or revision >= 0xD8 && revision <= 0xDF + * otherwise is PCO FP5 + */ + if (!strcmp(ucode_prefix, "picasso") && + (((adev->pdev->revision >= 0xC8) && (adev->pdev->revision <= 0xCF)) || + ((adev->pdev->revision >= 0xD8) && (adev->pdev->revision <= 0xDF)))) + snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc_am4.bin", ucode_prefix); + else if (!strcmp(ucode_prefix, "raven") && + (amdgpu_pm_load_smu_firmware(adev, &smu_version) == 0) && + (smu_version >= 0x41e2b)) + /* SMC is loaded by SBIOS on APU & can get the SMU version directly. */ + snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_kicker_rlc.bin", ucode_prefix); + else + snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", ucode_prefix); + r = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev); + if (r) + return r; + + /* mec2 fw bin support */ + if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 2) || + adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 1) || + adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 3, 0)) { + + if (amdgpu_sriov_vf(adev) && (adev->asic_type == CHIP_ALDEBARAN)) + snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sjt_mec2.bin", ucode_prefix); + else + snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2.bin", ucode_prefix); + + r = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev); + if (r) + return r; + } + + return 0; +} + static int amdgpu_discovery_set_gc_ip_blocks(struct amdgpu_device *adev) { + char ucode_prefix[30]; + int r; + + amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_prefix)); + switch (adev->ip_versions[GC_HWIP][0]) { case IP_VERSION(9, 0, 1): case IP_VERSION(9, 1, 0): @@ -1856,6 +2000,9 @@ static int amdgpu_discovery_set_gc_ip_blocks(struct amdgpu_device *adev) case IP_VERSION(9, 4, 0): case IP_VERSION(9, 4, 1): case IP_VERSION(9, 4, 2): + r = amdgpu_discovery_load_gfx9(adev, ucode_prefix); + if (r) + return r; amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block); break; case IP_VERSION(10, 1, 10): diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c index f202b45c413c..9288a3bcb3c1 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c @@ -65,72 +65,6 @@ #define mmGCEA_PROBE_MAP 0x070c #define mmGCEA_PROBE_MAP_BASE_IDX 0 -MODULE_FIRMWARE("amdgpu/vega10_ce.bin"); -MODULE_FIRMWARE("amdgpu/vega10_pfp.bin"); -MODULE_FIRMWARE("amdgpu/vega10_me.bin"); -MODULE_FIRMWARE("amdgpu/vega10_mec.bin"); -MODULE_FIRMWARE("amdgpu/vega10_mec2.bin"); -MODULE_FIRMWARE("amdgpu/vega10_rlc.bin"); - -MODULE_FIRMWARE("amdgpu/vega12_ce.bin"); -MODULE_FIRMWARE("amdgpu/vega12_pfp.bin"); -MODULE_FIRMWARE("amdgpu/vega12_me.bin"); -MODULE_FIRMWARE("amdgpu/vega12_mec.bin"); -MODULE_FIRMWARE("amdgpu/vega12_mec2.bin"); -MODULE_FIRMWARE("amdgpu/vega12_rlc.bin"); - -MODULE_FIRMWARE("amdgpu/vega20_ce.bin"); -MODULE_FIRMWARE("amdgpu/vega20_pfp.bin"); -MODULE_FIRMWARE("amdgpu/vega20_me.bin"); -MODULE_FIRMWARE("amdgpu/vega20_mec.bin"); -MODULE_FIRMWARE("amdgpu/vega20_mec2.bin"); -MODULE_FIRMWARE("amdgpu/vega20_rlc.bin"); - -MODULE_FIRMWARE("amdgpu/raven_ce.bin"); -MODULE_FIRMWARE("amdgpu/raven_pfp.bin"); -MODULE_FIRMWARE("amdgpu/raven_me.bin"); -MODULE_FIRMWARE("amdgpu/raven_mec.bin"); -MODULE_FIRMWARE("amdgpu/raven_mec2.bin"); -MODULE_FIRMWARE("amdgpu/raven_rlc.bin"); - -MODULE_FIRMWARE("amdgpu/picasso_ce.bin"); -MODULE_FIRMWARE("amdgpu/picasso_pfp.bin"); -MODULE_FIRMWARE("amdgpu/picasso_me.bin"); -MODULE_FIRMWARE("amdgpu/picasso_mec.bin"); -MODULE_FIRMWARE("amdgpu/picasso_mec2.bin"); -MODULE_FIRMWARE("amdgpu/picasso_rlc.bin"); -MODULE_FIRMWARE("amdgpu/picasso_rlc_am4.bin"); - -MODULE_FIRMWARE("amdgpu/raven2_ce.bin"); -MODULE_FIRMWARE("amdgpu/raven2_pfp.bin"); -MODULE_FIRMWARE("amdgpu/raven2_me.bin"); -MODULE_FIRMWARE("amdgpu/raven2_mec.bin"); -MODULE_FIRMWARE("amdgpu/raven2_mec2.bin"); -MODULE_FIRMWARE("amdgpu/raven2_rlc.bin"); -MODULE_FIRMWARE("amdgpu/raven_kicker_rlc.bin"); - -MODULE_FIRMWARE("amdgpu/arcturus_mec.bin"); -MODULE_FIRMWARE("amdgpu/arcturus_rlc.bin"); - -MODULE_FIRMWARE("amdgpu/renoir_ce.bin"); -MODULE_FIRMWARE("amdgpu/renoir_pfp.bin"); -MODULE_FIRMWARE("amdgpu/renoir_me.bin"); -MODULE_FIRMWARE("amdgpu/renoir_mec.bin"); -MODULE_FIRMWARE("amdgpu/renoir_rlc.bin"); - -MODULE_FIRMWARE("amdgpu/green_sardine_ce.bin"); -MODULE_FIRMWARE("amdgpu/green_sardine_pfp.bin"); -MODULE_FIRMWARE("amdgpu/green_sardine_me.bin"); -MODULE_FIRMWARE("amdgpu/green_sardine_mec.bin"); -MODULE_FIRMWARE("amdgpu/green_sardine_mec2.bin"); -MODULE_FIRMWARE("amdgpu/green_sardine_rlc.bin"); - -MODULE_FIRMWARE("amdgpu/aldebaran_mec.bin"); -MODULE_FIRMWARE("amdgpu/aldebaran_mec2.bin"); -MODULE_FIRMWARE("amdgpu/aldebaran_rlc.bin"); -MODULE_FIRMWARE("amdgpu/aldebaran_sjt_mec.bin"); -MODULE_FIRMWARE("amdgpu/aldebaran_sjt_mec2.bin"); - #define mmTCP_CHAN_STEER_0_ARCT 0x0b03 #define mmTCP_CHAN_STEER_0_ARCT_BASE_IDX 0 #define mmTCP_CHAN_STEER_1_ARCT 0x0b04 @@ -1250,34 +1184,20 @@ static void gfx_v9_0_check_if_need_gfxoff(struct amdgpu_device *adev) } } -static int gfx_v9_0_init_cp_gfx_microcode(struct amdgpu_device *adev, - const char *chip_name) +static int gfx_v9_0_init_cp_gfx_microcode(struct amdgpu_device *adev) { - char fw_name[30]; int err; - snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp.bin", chip_name); - err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev); - if (err) - goto out; err = amdgpu_ucode_validate(adev->gfx.pfp_fw); if (err) goto out; amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_PFP); - snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", chip_name); - err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev); - if (err) - goto out; err = amdgpu_ucode_validate(adev->gfx.me_fw); if (err) goto out; amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_ME); - snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce.bin", chip_name); - err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev); - if (err) - goto out; err = amdgpu_ucode_validate(adev->gfx.ce_fw); if (err) goto out; @@ -1286,8 +1206,7 @@ static int gfx_v9_0_init_cp_gfx_microcode(struct amdgpu_device *adev, out: if (err) { dev_err(adev->dev, - "gfx9: Failed to init firmware \"%s\"\n", - fw_name); + "gfx9: Failed to init firmware\n"); release_firmware(adev->gfx.pfp_fw); adev->gfx.pfp_fw = NULL; release_firmware(adev->gfx.me_fw); @@ -1298,39 +1217,13 @@ static int gfx_v9_0_init_cp_gfx_microcode(struct amdgpu_device *adev, return err; } -static int gfx_v9_0_init_rlc_microcode(struct amdgpu_device *adev, - const char *chip_name) +static int gfx_v9_0_init_rlc_microcode(struct amdgpu_device *adev) { - char fw_name[30]; int err; const struct rlc_firmware_header_v2_0 *rlc_hdr; uint16_t version_major; uint16_t version_minor; - uint32_t smu_version; - /* - * For Picasso && AM4 SOCKET board, we use picasso_rlc_am4.bin - * instead of picasso_rlc.bin. - * Judgment method: - * PCO AM4: revision >= 0xC8 && revision <= 0xCF - * or revision >= 0xD8 && revision <= 0xDF - * otherwise is PCO FP5 - */ - if (!strcmp(chip_name, "picasso") && - (((adev->pdev->revision >= 0xC8) && (adev->pdev->revision <= 0xCF)) || - ((adev->pdev->revision >= 0xD8) && (adev->pdev->revision <= 0xDF)))) - snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc_am4.bin", chip_name); - else if (!strcmp(chip_name, "raven") && (amdgpu_pm_load_smu_firmware(adev, &smu_version) == 0) && - (smu_version >= 0x41e2b)) - /** - *SMC is loaded by SBIOS on APU and it's able to get the SMU version directly. - */ - snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_kicker_rlc.bin", chip_name); - else - snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name); - err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev); - if (err) - goto out; err = amdgpu_ucode_validate(adev->gfx.rlc_fw); if (err) goto out; @@ -1342,8 +1235,7 @@ static int gfx_v9_0_init_rlc_microcode(struct amdgpu_device *adev, out: if (err) { dev_err(adev->dev, - "gfx9: Failed to init firmware \"%s\"\n", - fw_name); + "gfx9: Failed to init firmware\n"); release_firmware(adev->gfx.rlc_fw); adev->gfx.rlc_fw = NULL; } @@ -1360,20 +1252,10 @@ static bool gfx_v9_0_load_mec2_fw_bin_support(struct amdgpu_device *adev) return true; } -static int gfx_v9_0_init_cp_compute_microcode(struct amdgpu_device *adev, - const char *chip_name) +static int gfx_v9_0_init_cp_compute_microcode(struct amdgpu_device *adev) { - char fw_name[30]; int err; - if (amdgpu_sriov_vf(adev) && (adev->asic_type == CHIP_ALDEBARAN)) - snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sjt_mec.bin", chip_name); - else - snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", chip_name); - - err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev); - if (err) - goto out; err = amdgpu_ucode_validate(adev->gfx.mec_fw); if (err) goto out; @@ -1381,22 +1263,11 @@ static int gfx_v9_0_init_cp_compute_microcode(struct amdgpu_device *adev, amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1_JT); if (gfx_v9_0_load_mec2_fw_bin_support(adev)) { - if (amdgpu_sriov_vf(adev) && (adev->asic_type == CHIP_ALDEBARAN)) - snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sjt_mec2.bin", chip_name); - else - snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2.bin", chip_name); - - err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev); - if (!err) { - err = amdgpu_ucode_validate(adev->gfx.mec2_fw); - if (err) - goto out; - amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC2); - amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC2_JT); - } else { - err = 0; - adev->gfx.mec2_fw = NULL; - } + err = amdgpu_ucode_validate(adev->gfx.mec2_fw); + if (err) + goto out; + amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC2); + amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC2_JT); } else { adev->gfx.mec2_fw_version = adev->gfx.mec_fw_version; adev->gfx.mec2_feature_version = adev->gfx.mec_feature_version; @@ -1407,8 +1278,7 @@ static int gfx_v9_0_init_cp_compute_microcode(struct amdgpu_device *adev, gfx_v9_0_check_fw_write_wait(adev); if (err) { dev_err(adev->dev, - "gfx9: Failed to init firmware \"%s\"\n", - fw_name); + "gfx9: Failed to init firmware\n"); release_firmware(adev->gfx.mec_fw); adev->gfx.mec_fw = NULL; release_firmware(adev->gfx.mec2_fw); @@ -1419,58 +1289,22 @@ static int gfx_v9_0_init_cp_compute_microcode(struct amdgpu_device *adev, static int gfx_v9_0_init_microcode(struct amdgpu_device *adev) { - const char *chip_name; int r; DRM_DEBUG("\n"); - switch (adev->ip_versions[GC_HWIP][0]) { - case IP_VERSION(9, 0, 1): - chip_name = "vega10"; - break; - case IP_VERSION(9, 2, 1): - chip_name = "vega12"; - break; - case IP_VERSION(9, 4, 0): - chip_name = "vega20"; - break; - case IP_VERSION(9, 2, 2): - case IP_VERSION(9, 1, 0): - if (adev->apu_flags & AMD_APU_IS_RAVEN2) - chip_name = "raven2"; - else if (adev->apu_flags & AMD_APU_IS_PICASSO) - chip_name = "picasso"; - else - chip_name = "raven"; - break; - case IP_VERSION(9, 4, 1): - chip_name = "arcturus"; - break; - case IP_VERSION(9, 3, 0): - if (adev->apu_flags & AMD_APU_IS_RENOIR) - chip_name = "renoir"; - else - chip_name = "green_sardine"; - break; - case IP_VERSION(9, 4, 2): - chip_name = "aldebaran"; - break; - default: - BUG(); - } - /* No CPG in Arcturus */ if (adev->gfx.num_gfx_rings) { - r = gfx_v9_0_init_cp_gfx_microcode(adev, chip_name); + r = gfx_v9_0_init_cp_gfx_microcode(adev); if (r) return r; } - r = gfx_v9_0_init_rlc_microcode(adev, chip_name); + r = gfx_v9_0_init_rlc_microcode(adev); if (r) return r; - r = gfx_v9_0_init_cp_compute_microcode(adev, chip_name); + r = gfx_v9_0_init_cp_compute_microcode(adev); if (r) return r; From patchwork Fri Dec 30 05:21:13 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mario Limonciello X-Patchwork-Id: 37574 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4e01:0:0:0:0:0 with SMTP id p1csp2736073wrt; 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Thu, 29 Dec 2022 23:21:47 -0600 From: Mario Limonciello To: Alex Deucher , CC: Javier Martinez Canillas , Carlos Soriano Sanchez , , , David Airlie , "Daniel Vetter" , , Mario Limonciello , "Pan, Xinhui" Subject: [PATCH v3 09/11] drm/amd: Request GFX10 microcode during IP discovery Date: Thu, 29 Dec 2022 23:21:13 -0600 Message-ID: <20221230052119.15096-10-mario.limonciello@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221230052119.15096-1-mario.limonciello@amd.com> References: <20221230052119.15096-1-mario.limonciello@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1NAM11FT055:EE_|BN9PR12MB5033:EE_ X-MS-Office365-Filtering-Correlation-Id: 8fc75c1c-f3ea-449b-5e03-08daea25c090 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 2q2ZlhBbs3eIuNG0BEaip0yH2jnoYU15fFJkzjQ3K5ZLOqHwFX5UZ5mZ7bUT5Hd8uT0+W+gOW7IWJZRdznVf2+AXDK3ELxfSxhPvHoxdipjPPrNg5gSA+e0Kymge6Ic39klYzs8jlJ40Ezy+vq24Rnc8IpYHjNUT/tvJ6zu7M1wBJ3/x8uuUvGvd7Bkbe1Sxztyzbq914xDbWv1n11ud1k/GIO2VBATvuVMwvTMExqkNE9hoA5h5GiwDvyZylnGOZvM24hWOUGidk8YN11vT3Hka6W9nk/d4j6xdUBMD6qrRdUSbG6xThRj3lwS8ucijpAmmyt3AluPW2PszgQEj7i3kr7345OFjqQ37usbxdxWY4pcP2eZOmCxBgBGg9gJm0d1ftNgd97jeItIXTsvUYBHeJlrqiQ7s14K1DDvgoJf9RGCh3XqfYedGEofxshHTC41bvuxLCzaHIuczW36gxSRrhVQjLRaFmmOJuWTl/dFBVhUjtiDK7ZZuLMbfrtciPgtYOUh083yy5H2I8gBSL7567uDyUw0mPE2dp0iW2JmCgrRWo8BQzMW0YxsQUSKa4rFsVLnPU09VVKwRyrN0GTiHKZMMMRw4EfxfNeiiFt/dxChxsN2VHLtF1WhqB8Vr7CQDbtGlIgBUgQfFDLb67hGupYiVkehmCLMJPXxLpIPXDx71R+YxrnrHYKmkcfiJOgrE99MQNGpE4+mvEtQaSheradBbPSapxrV/AQbQV4Y= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230022)(4636009)(39860400002)(396003)(376002)(136003)(346002)(451199015)(36840700001)(46966006)(40470700004)(36756003)(40480700001)(356005)(110136005)(316002)(86362001)(54906003)(6666004)(19627235002)(478600001)(5660300002)(2906002)(30864003)(8936002)(8676002)(70586007)(4326008)(70206006)(36860700001)(44832011)(41300700001)(82740400003)(186003)(83380400001)(81166007)(336012)(7696005)(1076003)(16526019)(40460700003)(2616005)(82310400005)(426003)(47076005)(26005)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Dec 2022 05:21:49.0316 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8fc75c1c-f3ea-449b-5e03-08daea25c090 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT055.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN9PR12MB5033 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1753615230350683679?= X-GMAIL-MSGID: =?utf-8?q?1753615230350683679?= If GFX10 microcode is required but not available during early init, the firmware framebuffer will have already been released and the screen will freeze. Move the request for GFX10 microcode into the IP discovery phase so that if it's not available, IP discovery will fail. Reviewed-by: Alex Deucher Signed-off-by: Mario Limonciello --- drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 137 +++++++++++++ drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 180 +----------------- 2 files changed, 144 insertions(+), 173 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c index 0ff1b3872441..439b10fdff1b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c @@ -220,6 +220,102 @@ MODULE_FIRMWARE("amdgpu/green_sardine_mec.bin"); MODULE_FIRMWARE("amdgpu/green_sardine_mec2.bin"); MODULE_FIRMWARE("amdgpu/green_sardine_rlc.bin"); +/* gfx10 */ +MODULE_FIRMWARE("amdgpu/aldebaran_mec.bin"); +MODULE_FIRMWARE("amdgpu/aldebaran_mec2.bin"); +MODULE_FIRMWARE("amdgpu/aldebaran_rlc.bin"); +MODULE_FIRMWARE("amdgpu/aldebaran_sjt_mec.bin"); +MODULE_FIRMWARE("amdgpu/aldebaran_sjt_mec2.bin"); + +MODULE_FIRMWARE("amdgpu/navi10_ce.bin"); +MODULE_FIRMWARE("amdgpu/navi10_pfp.bin"); +MODULE_FIRMWARE("amdgpu/navi10_me.bin"); +MODULE_FIRMWARE("amdgpu/navi10_mec.bin"); +MODULE_FIRMWARE("amdgpu/navi10_mec2.bin"); +MODULE_FIRMWARE("amdgpu/navi10_rlc.bin"); + +MODULE_FIRMWARE("amdgpu/navi14_ce_wks.bin"); +MODULE_FIRMWARE("amdgpu/navi14_pfp_wks.bin"); +MODULE_FIRMWARE("amdgpu/navi14_me_wks.bin"); +MODULE_FIRMWARE("amdgpu/navi14_mec_wks.bin"); +MODULE_FIRMWARE("amdgpu/navi14_mec2_wks.bin"); +MODULE_FIRMWARE("amdgpu/navi14_ce.bin"); +MODULE_FIRMWARE("amdgpu/navi14_pfp.bin"); +MODULE_FIRMWARE("amdgpu/navi14_me.bin"); +MODULE_FIRMWARE("amdgpu/navi14_mec.bin"); +MODULE_FIRMWARE("amdgpu/navi14_mec2.bin"); +MODULE_FIRMWARE("amdgpu/navi14_rlc.bin"); + +MODULE_FIRMWARE("amdgpu/navi12_ce.bin"); +MODULE_FIRMWARE("amdgpu/navi12_pfp.bin"); +MODULE_FIRMWARE("amdgpu/navi12_me.bin"); +MODULE_FIRMWARE("amdgpu/navi12_mec.bin"); +MODULE_FIRMWARE("amdgpu/navi12_mec2.bin"); +MODULE_FIRMWARE("amdgpu/navi12_rlc.bin"); + +MODULE_FIRMWARE("amdgpu/sienna_cichlid_ce.bin"); +MODULE_FIRMWARE("amdgpu/sienna_cichlid_pfp.bin"); +MODULE_FIRMWARE("amdgpu/sienna_cichlid_me.bin"); +MODULE_FIRMWARE("amdgpu/sienna_cichlid_mec.bin"); +MODULE_FIRMWARE("amdgpu/sienna_cichlid_mec2.bin"); +MODULE_FIRMWARE("amdgpu/sienna_cichlid_rlc.bin"); + +MODULE_FIRMWARE("amdgpu/navy_flounder_ce.bin"); +MODULE_FIRMWARE("amdgpu/navy_flounder_pfp.bin"); +MODULE_FIRMWARE("amdgpu/navy_flounder_me.bin"); +MODULE_FIRMWARE("amdgpu/navy_flounder_mec.bin"); +MODULE_FIRMWARE("amdgpu/navy_flounder_mec2.bin"); +MODULE_FIRMWARE("amdgpu/navy_flounder_rlc.bin"); + +MODULE_FIRMWARE("amdgpu/vangogh_ce.bin"); +MODULE_FIRMWARE("amdgpu/vangogh_pfp.bin"); +MODULE_FIRMWARE("amdgpu/vangogh_me.bin"); +MODULE_FIRMWARE("amdgpu/vangogh_mec.bin"); +MODULE_FIRMWARE("amdgpu/vangogh_mec2.bin"); +MODULE_FIRMWARE("amdgpu/vangogh_rlc.bin"); + +MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_ce.bin"); +MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_pfp.bin"); +MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_me.bin"); +MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_mec.bin"); +MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_mec2.bin"); +MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_rlc.bin"); + +MODULE_FIRMWARE("amdgpu/beige_goby_ce.bin"); +MODULE_FIRMWARE("amdgpu/beige_goby_pfp.bin"); +MODULE_FIRMWARE("amdgpu/beige_goby_me.bin"); +MODULE_FIRMWARE("amdgpu/beige_goby_mec.bin"); +MODULE_FIRMWARE("amdgpu/beige_goby_mec2.bin"); +MODULE_FIRMWARE("amdgpu/beige_goby_rlc.bin"); + +MODULE_FIRMWARE("amdgpu/yellow_carp_ce.bin"); +MODULE_FIRMWARE("amdgpu/yellow_carp_pfp.bin"); +MODULE_FIRMWARE("amdgpu/yellow_carp_me.bin"); +MODULE_FIRMWARE("amdgpu/yellow_carp_mec.bin"); +MODULE_FIRMWARE("amdgpu/yellow_carp_mec2.bin"); +MODULE_FIRMWARE("amdgpu/yellow_carp_rlc.bin"); + +MODULE_FIRMWARE("amdgpu/cyan_skillfish2_ce.bin"); +MODULE_FIRMWARE("amdgpu/cyan_skillfish2_pfp.bin"); +MODULE_FIRMWARE("amdgpu/cyan_skillfish2_me.bin"); +MODULE_FIRMWARE("amdgpu/cyan_skillfish2_mec.bin"); +MODULE_FIRMWARE("amdgpu/cyan_skillfish2_mec2.bin"); +MODULE_FIRMWARE("amdgpu/cyan_skillfish2_rlc.bin"); + +MODULE_FIRMWARE("amdgpu/gc_10_3_6_ce.bin"); +MODULE_FIRMWARE("amdgpu/gc_10_3_6_pfp.bin"); +MODULE_FIRMWARE("amdgpu/gc_10_3_6_me.bin"); +MODULE_FIRMWARE("amdgpu/gc_10_3_6_mec.bin"); +MODULE_FIRMWARE("amdgpu/gc_10_3_6_mec2.bin"); +MODULE_FIRMWARE("amdgpu/gc_10_3_6_rlc.bin"); + +MODULE_FIRMWARE("amdgpu/gc_10_3_7_ce.bin"); +MODULE_FIRMWARE("amdgpu/gc_10_3_7_pfp.bin"); +MODULE_FIRMWARE("amdgpu/gc_10_3_7_me.bin"); +MODULE_FIRMWARE("amdgpu/gc_10_3_7_mec.bin"); +MODULE_FIRMWARE("amdgpu/gc_10_3_7_mec2.bin"); +MODULE_FIRMWARE("amdgpu/gc_10_3_7_rlc.bin"); + static const char *hw_id_names[HW_ID_MAX] = { [MP1_HWID] = "MP1", [MP2_HWID] = "MP2", @@ -1984,6 +2080,44 @@ static int amdgpu_discovery_load_gfx9(struct amdgpu_device *adev, char *ucode_pr return 0; } +static int amdgpu_discovery_load_gfx10(struct amdgpu_device *adev, char *ucode_prefix) +{ + char fw_name[40]; + char *wks = ""; + int r; + + if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 1) && + !(adev->pdev->device == 0x7340 && + adev->pdev->revision != 0x00)) + wks = "_wks"; + snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp%s.bin", ucode_prefix, wks); + r = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev); + if (r) + return r; + snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me%s.bin", ucode_prefix, wks); + r = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev); + if (r) + return r; + snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce%s.bin", ucode_prefix, wks); + r = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev); + if (r) + return r; + snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", ucode_prefix); + r = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev); + if (r) + return r; + snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec%s.bin", ucode_prefix, wks); + r = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev); + if (r) + return r; + snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2%s.bin", ucode_prefix, wks); + r = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev); + if (r) + return r; + + return 0; +} + static int amdgpu_discovery_set_gc_ip_blocks(struct amdgpu_device *adev) { char ucode_prefix[30]; @@ -2018,6 +2152,9 @@ static int amdgpu_discovery_set_gc_ip_blocks(struct amdgpu_device *adev) case IP_VERSION(10, 3, 6): case IP_VERSION(10, 3, 3): case IP_VERSION(10, 3, 7): + r = amdgpu_discovery_load_gfx10(adev, ucode_prefix); + if (r) + return r; amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); break; case IP_VERSION(11, 0, 0): diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c index 49d34c7bbf20..319548b81454 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c @@ -182,95 +182,6 @@ #define mmRLC_SPARE_INT_0_Sienna_Cichlid 0x4ca5 #define mmRLC_SPARE_INT_0_Sienna_Cichlid_BASE_IDX 1 -MODULE_FIRMWARE("amdgpu/navi10_ce.bin"); -MODULE_FIRMWARE("amdgpu/navi10_pfp.bin"); -MODULE_FIRMWARE("amdgpu/navi10_me.bin"); -MODULE_FIRMWARE("amdgpu/navi10_mec.bin"); -MODULE_FIRMWARE("amdgpu/navi10_mec2.bin"); -MODULE_FIRMWARE("amdgpu/navi10_rlc.bin"); - -MODULE_FIRMWARE("amdgpu/navi14_ce_wks.bin"); -MODULE_FIRMWARE("amdgpu/navi14_pfp_wks.bin"); -MODULE_FIRMWARE("amdgpu/navi14_me_wks.bin"); -MODULE_FIRMWARE("amdgpu/navi14_mec_wks.bin"); -MODULE_FIRMWARE("amdgpu/navi14_mec2_wks.bin"); -MODULE_FIRMWARE("amdgpu/navi14_ce.bin"); -MODULE_FIRMWARE("amdgpu/navi14_pfp.bin"); -MODULE_FIRMWARE("amdgpu/navi14_me.bin"); -MODULE_FIRMWARE("amdgpu/navi14_mec.bin"); -MODULE_FIRMWARE("amdgpu/navi14_mec2.bin"); -MODULE_FIRMWARE("amdgpu/navi14_rlc.bin"); - -MODULE_FIRMWARE("amdgpu/navi12_ce.bin"); -MODULE_FIRMWARE("amdgpu/navi12_pfp.bin"); -MODULE_FIRMWARE("amdgpu/navi12_me.bin"); -MODULE_FIRMWARE("amdgpu/navi12_mec.bin"); -MODULE_FIRMWARE("amdgpu/navi12_mec2.bin"); -MODULE_FIRMWARE("amdgpu/navi12_rlc.bin"); - -MODULE_FIRMWARE("amdgpu/sienna_cichlid_ce.bin"); -MODULE_FIRMWARE("amdgpu/sienna_cichlid_pfp.bin"); -MODULE_FIRMWARE("amdgpu/sienna_cichlid_me.bin"); -MODULE_FIRMWARE("amdgpu/sienna_cichlid_mec.bin"); -MODULE_FIRMWARE("amdgpu/sienna_cichlid_mec2.bin"); -MODULE_FIRMWARE("amdgpu/sienna_cichlid_rlc.bin"); - -MODULE_FIRMWARE("amdgpu/navy_flounder_ce.bin"); -MODULE_FIRMWARE("amdgpu/navy_flounder_pfp.bin"); -MODULE_FIRMWARE("amdgpu/navy_flounder_me.bin"); -MODULE_FIRMWARE("amdgpu/navy_flounder_mec.bin"); -MODULE_FIRMWARE("amdgpu/navy_flounder_mec2.bin"); -MODULE_FIRMWARE("amdgpu/navy_flounder_rlc.bin"); - -MODULE_FIRMWARE("amdgpu/vangogh_ce.bin"); -MODULE_FIRMWARE("amdgpu/vangogh_pfp.bin"); -MODULE_FIRMWARE("amdgpu/vangogh_me.bin"); -MODULE_FIRMWARE("amdgpu/vangogh_mec.bin"); -MODULE_FIRMWARE("amdgpu/vangogh_mec2.bin"); -MODULE_FIRMWARE("amdgpu/vangogh_rlc.bin"); - -MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_ce.bin"); -MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_pfp.bin"); -MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_me.bin"); -MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_mec.bin"); -MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_mec2.bin"); -MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_rlc.bin"); - -MODULE_FIRMWARE("amdgpu/beige_goby_ce.bin"); -MODULE_FIRMWARE("amdgpu/beige_goby_pfp.bin"); -MODULE_FIRMWARE("amdgpu/beige_goby_me.bin"); -MODULE_FIRMWARE("amdgpu/beige_goby_mec.bin"); -MODULE_FIRMWARE("amdgpu/beige_goby_mec2.bin"); -MODULE_FIRMWARE("amdgpu/beige_goby_rlc.bin"); - -MODULE_FIRMWARE("amdgpu/yellow_carp_ce.bin"); -MODULE_FIRMWARE("amdgpu/yellow_carp_pfp.bin"); -MODULE_FIRMWARE("amdgpu/yellow_carp_me.bin"); -MODULE_FIRMWARE("amdgpu/yellow_carp_mec.bin"); -MODULE_FIRMWARE("amdgpu/yellow_carp_mec2.bin"); -MODULE_FIRMWARE("amdgpu/yellow_carp_rlc.bin"); - -MODULE_FIRMWARE("amdgpu/cyan_skillfish2_ce.bin"); -MODULE_FIRMWARE("amdgpu/cyan_skillfish2_pfp.bin"); -MODULE_FIRMWARE("amdgpu/cyan_skillfish2_me.bin"); -MODULE_FIRMWARE("amdgpu/cyan_skillfish2_mec.bin"); -MODULE_FIRMWARE("amdgpu/cyan_skillfish2_mec2.bin"); -MODULE_FIRMWARE("amdgpu/cyan_skillfish2_rlc.bin"); - -MODULE_FIRMWARE("amdgpu/gc_10_3_6_ce.bin"); -MODULE_FIRMWARE("amdgpu/gc_10_3_6_pfp.bin"); -MODULE_FIRMWARE("amdgpu/gc_10_3_6_me.bin"); -MODULE_FIRMWARE("amdgpu/gc_10_3_6_mec.bin"); -MODULE_FIRMWARE("amdgpu/gc_10_3_6_mec2.bin"); -MODULE_FIRMWARE("amdgpu/gc_10_3_6_rlc.bin"); - -MODULE_FIRMWARE("amdgpu/gc_10_3_7_ce.bin"); -MODULE_FIRMWARE("amdgpu/gc_10_3_7_pfp.bin"); -MODULE_FIRMWARE("amdgpu/gc_10_3_7_me.bin"); -MODULE_FIRMWARE("amdgpu/gc_10_3_7_mec.bin"); -MODULE_FIRMWARE("amdgpu/gc_10_3_7_mec2.bin"); -MODULE_FIRMWARE("amdgpu/gc_10_3_7_rlc.bin"); - static const struct soc15_reg_golden golden_settings_gc_10_1[] = { SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x00400014), @@ -3974,9 +3885,6 @@ static void gfx_v10_0_check_gfxoff_flag(struct amdgpu_device *adev) static int gfx_v10_0_init_microcode(struct amdgpu_device *adev) { - const char *chip_name; - char fw_name[40]; - char *wks = ""; int err; const struct rlc_firmware_header_v2_0 *rlc_hdr; uint16_t version_major; @@ -3984,91 +3892,29 @@ static int gfx_v10_0_init_microcode(struct amdgpu_device *adev) DRM_DEBUG("\n"); - switch (adev->ip_versions[GC_HWIP][0]) { - case IP_VERSION(10, 1, 10): - chip_name = "navi10"; - break; - case IP_VERSION(10, 1, 1): - chip_name = "navi14"; - if (!(adev->pdev->device == 0x7340 && - adev->pdev->revision != 0x00)) - wks = "_wks"; - break; - case IP_VERSION(10, 1, 2): - chip_name = "navi12"; - break; - case IP_VERSION(10, 3, 0): - chip_name = "sienna_cichlid"; - break; - case IP_VERSION(10, 3, 2): - chip_name = "navy_flounder"; - break; - case IP_VERSION(10, 3, 1): - chip_name = "vangogh"; - break; - case IP_VERSION(10, 3, 4): - chip_name = "dimgrey_cavefish"; - break; - case IP_VERSION(10, 3, 5): - chip_name = "beige_goby"; - break; - case IP_VERSION(10, 3, 3): - chip_name = "yellow_carp"; - break; - case IP_VERSION(10, 3, 6): - chip_name = "gc_10_3_6"; - break; - case IP_VERSION(10, 1, 3): - case IP_VERSION(10, 1, 4): - chip_name = "cyan_skillfish2"; - break; - case IP_VERSION(10, 3, 7): - chip_name = "gc_10_3_7"; - break; - default: - BUG(); - } - - snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp%s.bin", chip_name, wks); - err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev); - if (err) - goto out; err = amdgpu_ucode_validate(adev->gfx.pfp_fw); if (err) goto out; amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_PFP); - snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me%s.bin", chip_name, wks); - err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev); - if (err) - goto out; err = amdgpu_ucode_validate(adev->gfx.me_fw); if (err) goto out; amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_ME); - snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce%s.bin", chip_name, wks); - err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev); - if (err) - goto out; err = amdgpu_ucode_validate(adev->gfx.ce_fw); if (err) goto out; amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_CE); if (!amdgpu_sriov_vf(adev)) { - snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name); - err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev); - if (err) - goto out; /* don't check this. There are apparently firmwares in the wild with * incorrect size in the header */ err = amdgpu_ucode_validate(adev->gfx.rlc_fw); if (err) dev_dbg(adev->dev, - "gfx10: amdgpu_ucode_validate() failed \"%s\"\n", - fw_name); + "gfx10: amdgpu_ucode_validate() failed\n"); rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; version_major = le16_to_cpu(rlc_hdr->header.header_version_major); version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor); @@ -4077,35 +3923,23 @@ static int gfx_v10_0_init_microcode(struct amdgpu_device *adev) goto out; } - snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec%s.bin", chip_name, wks); - err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev); - if (err) - goto out; err = amdgpu_ucode_validate(adev->gfx.mec_fw); if (err) goto out; amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1); amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1_JT); - snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2%s.bin", chip_name, wks); - err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev); - if (!err) { - err = amdgpu_ucode_validate(adev->gfx.mec2_fw); - if (err) - goto out; - amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC2); - amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC2_JT); - } else { - err = 0; - adev->gfx.mec2_fw = NULL; - } + err = amdgpu_ucode_validate(adev->gfx.mec2_fw); + if (err) + goto out; + amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC2); + amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC2_JT); gfx_v10_0_check_fw_write_wait(adev); out: if (err) { dev_err(adev->dev, - "gfx10: Failed to init firmware \"%s\"\n", - fw_name); + "gfx10: Failed to init firmware\n"); release_firmware(adev->gfx.pfp_fw); adev->gfx.pfp_fw = NULL; release_firmware(adev->gfx.me_fw); From patchwork Fri Dec 30 05:21:14 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mario Limonciello X-Patchwork-Id: 37573 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4e01:0:0:0:0:0 with SMTP id p1csp2736054wrt; Thu, 29 Dec 2022 21:23:21 -0800 (PST) X-Google-Smtp-Source: AMrXdXvuulm7jkeR9GrHJHWwMEnhqSqsnGiMfkYYKC2g/JAx0Dk1lNMwDQAt+nzseAZVua6PGObJ X-Received: by 2002:a17:902:e5c5:b0:189:c57c:9a19 with SMTP id u5-20020a170902e5c500b00189c57c9a19mr40595835plf.58.1672377800753; Thu, 29 Dec 2022 21:23:20 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1672377800; cv=pass; d=google.com; s=arc-20160816; b=LVaq2AKAmEoTbyQHeZTHVWEY3fEyYUsAJNDM5PW3t5HmJ/KWJ0V8bcYjtQiuwjNu61 Rg6UJ5USCMQZslI1TFEd4aaVvi8WSrJqh0flZX5WnskfY7q2vmmRWDy40jYFuq9H7/8l PUHqgW1keLwoAMX0iUn9DqwI8/QKkvomwiKRYS7olngW07diiHshPlzvb1fQJOSPOsDf IKSULDMHPz4sjRKRffcmuk6J8VUNEW8eAWE9Y9W8nBT41+6kFewLFqx5Qxgz+NS+f9L5 EgoFdLOe++3tUwNVu4Nf9UahUcbvt6t1WwC2isDOCOoTxmlnqVhxjARhx+QyU03Etfml joYw== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=D2sNT051it6yZuDlp2nekYU8WU55a8CR4j6R3ecmets=; b=V80OPTEd2GRzTO5mqRMPFubABIHQLJZHQMKICtm/GOArDX7tWEg5Rb1AOEpCJh3qOq zXQGoI+uSx0uB6A3OPRnIBN7jAf3YslrCijACk+P6sNVBUhZip6UYSCXakt7IkjzxxIG QACsvsUw91qQaUbvAyT/2v4ZTiyQz7MXmKwHH7ijd/SZ5YIDCv9MtVi6keVHeQ4NXpnj C8lABIukKayeFK+zfDGanCEqsZHd6+DIter7tr7fh3QZ1b/mcDXpCXXnrIB/Bz5zfXnb J4XACXgz6orOCwl6TWptUtBtE5dnoINV4Hqa5fN0Fy8n74+0S1ZfUwsoel4/5dM7NOk9 +A1A== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amd.com header.s=selector1 header.b=N9cCPT3r; arc=pass (i=1 spf=pass spfdomain=amd.com dmarc=pass fromdomain=amd.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=amd.com Received: from out1.vger.email (out1.vger.email. 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Thu, 29 Dec 2022 23:21:48 -0600 From: Mario Limonciello To: Alex Deucher , CC: Javier Martinez Canillas , Carlos Soriano Sanchez , , , David Airlie , "Daniel Vetter" , , Mario Limonciello , "Pan, Xinhui" Subject: [PATCH v3 10/11] drm/amd: Request GFX11 microcode during IP discovery Date: Thu, 29 Dec 2022 23:21:14 -0600 Message-ID: <20221230052119.15096-11-mario.limonciello@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221230052119.15096-1-mario.limonciello@amd.com> References: <20221230052119.15096-1-mario.limonciello@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1NAM11FT055:EE_|DM6PR12MB4203:EE_ X-MS-Office365-Filtering-Correlation-Id: 698b351c-df3b-439d-b452-08daea25c14c X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: MQPP1KJpXWJSFPJd/FE83yIAZA1FiRbh3VKAKnX9T6sJH9oL7ZbG+ELoocZuUReps9DY7MTJ5RU8+BepYCJ0zfN5hoE+1QAWQ27NllN8iL9yCrqjgrWw6P4HldYMM2jMKKK7CijOuXRBkuurNeN2qVM1rrraHUc1FtNtSBTA65AKmC4DCZkdLXyrDgaTGw/Ykd14xmsplqqWi/Sd1KqtTlO3/Z6bfkFCVj7WoTHVDkvdrpZNjRB2+Ibt70+chfH+OpmeDjvdBP9eRFn6Ffl0yHg05uHvoNwQ5f/AnpKQcWqyHg5k+mfjz6TWghfOkSST2bEhK+2ylS/UsW/HeRuzAM7cJmBFwDcrj7W2xRnW5jzbtBoPvj3ivJ2Lq1o1a6zB9fpnAFhhRwjCeffzRJ6pa1ktSKlGhnxnISj4t0886eYCSxpnv+XOpknhND+TzfqJjVE2l1TObpgs+VCMTdXG3i7IN3EVm1P3+ki1iR8NZ3ZQEVSPYAZHYttDC2Rg3g14jFjdysdXDiVrwPiY3OMbAhzvzuUPhOI2KnZoWslEiPNBWx+kSS4l8SLIH/uwIx2Hrbqb0JNjTBSYtvE/GXM62oFNizuNS2uplTeZhVv5i+wbu3I6G0monAc9c4bnrZuKcpqp7zLjZ0h4pV6y+eTfkOpY8IP6LlIMLJn5SfQUIhIeG3xHKbgDxC6oo0oGCQmj37Y62PGAdnMC4GMXRyuYTLtlJB5X/6Y9yMfq0T/u0hg= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230022)(4636009)(136003)(346002)(376002)(396003)(39860400002)(451199015)(40470700004)(36840700001)(46966006)(36756003)(5660300002)(356005)(8936002)(82740400003)(44832011)(41300700001)(81166007)(2906002)(47076005)(36860700001)(426003)(336012)(86362001)(83380400001)(316002)(54906003)(110136005)(7696005)(40460700003)(70586007)(40480700001)(70206006)(82310400005)(6666004)(19627235002)(8676002)(16526019)(4326008)(186003)(26005)(1076003)(2616005)(478600001)(36900700001);DIR:OUT;SFP:1101; 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Move the request for GFX11 microcode into the IP discovery phase so that if it's not available, IP discovery will fail. Reviewed-by: Alex Deucher Signed-off-by: Mario Limonciello --- drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 52 +++++++++++++++ drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 64 +------------------ 2 files changed, 53 insertions(+), 63 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c index 439b10fdff1b..ce1aa7683738 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c @@ -316,6 +316,29 @@ MODULE_FIRMWARE("amdgpu/gc_10_3_7_mec.bin"); MODULE_FIRMWARE("amdgpu/gc_10_3_7_mec2.bin"); MODULE_FIRMWARE("amdgpu/gc_10_3_7_rlc.bin"); +/* gfx11 */ +MODULE_FIRMWARE("amdgpu/gc_11_0_0_pfp.bin"); +MODULE_FIRMWARE("amdgpu/gc_11_0_0_me.bin"); +MODULE_FIRMWARE("amdgpu/gc_11_0_0_mec.bin"); +MODULE_FIRMWARE("amdgpu/gc_11_0_0_rlc.bin"); +MODULE_FIRMWARE("amdgpu/gc_11_0_0_toc.bin"); +MODULE_FIRMWARE("amdgpu/gc_11_0_1_pfp.bin"); +MODULE_FIRMWARE("amdgpu/gc_11_0_1_me.bin"); +MODULE_FIRMWARE("amdgpu/gc_11_0_1_mec.bin"); +MODULE_FIRMWARE("amdgpu/gc_11_0_1_rlc.bin"); +MODULE_FIRMWARE("amdgpu/gc_11_0_2_pfp.bin"); +MODULE_FIRMWARE("amdgpu/gc_11_0_2_me.bin"); +MODULE_FIRMWARE("amdgpu/gc_11_0_2_mec.bin"); +MODULE_FIRMWARE("amdgpu/gc_11_0_2_rlc.bin"); +MODULE_FIRMWARE("amdgpu/gc_11_0_3_pfp.bin"); +MODULE_FIRMWARE("amdgpu/gc_11_0_3_me.bin"); +MODULE_FIRMWARE("amdgpu/gc_11_0_3_mec.bin"); +MODULE_FIRMWARE("amdgpu/gc_11_0_3_rlc.bin"); +MODULE_FIRMWARE("amdgpu/gc_11_0_4_pfp.bin"); +MODULE_FIRMWARE("amdgpu/gc_11_0_4_me.bin"); +MODULE_FIRMWARE("amdgpu/gc_11_0_4_mec.bin"); +MODULE_FIRMWARE("amdgpu/gc_11_0_4_rlc.bin"); + static const char *hw_id_names[HW_ID_MAX] = { [MP1_HWID] = "MP1", [MP2_HWID] = "MP2", @@ -2114,6 +2137,32 @@ static int amdgpu_discovery_load_gfx10(struct amdgpu_device *adev, char *ucode_p r = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev); if (r) return r; + return 0; +} + +static int amdgpu_discovery_load_gfx11(struct amdgpu_device *adev, char *ucode_prefix) +{ + char fw_name[40]; + int r; + + snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp.bin", ucode_prefix); + r = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev); + if (r) + return r; + snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", ucode_prefix); + r = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev); + if (r) + return r; + snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", ucode_prefix); + r = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev); + if (r) + return r; + if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { + snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_toc.bin", ucode_prefix); + r = request_firmware(&adev->psp.toc_fw, fw_name, adev->dev); + if (r) + return r; + } return 0; } @@ -2162,6 +2211,9 @@ static int amdgpu_discovery_set_gc_ip_blocks(struct amdgpu_device *adev) case IP_VERSION(11, 0, 2): case IP_VERSION(11, 0, 3): case IP_VERSION(11, 0, 4): + r = amdgpu_discovery_load_gfx11(adev, ucode_prefix); + if (r) + return r; amdgpu_device_ip_block_add(adev, &gfx_v11_0_ip_block); break; default: diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c index a56c6e106d00..576fa591c6da 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c @@ -60,27 +60,6 @@ #define regRLC_RLCS_BOOTLOAD_STATUS_gc_11_0_1 0x4e7e #define regRLC_RLCS_BOOTLOAD_STATUS_gc_11_0_1_BASE_IDX 1 -MODULE_FIRMWARE("amdgpu/gc_11_0_0_pfp.bin"); -MODULE_FIRMWARE("amdgpu/gc_11_0_0_me.bin"); -MODULE_FIRMWARE("amdgpu/gc_11_0_0_mec.bin"); -MODULE_FIRMWARE("amdgpu/gc_11_0_0_rlc.bin"); -MODULE_FIRMWARE("amdgpu/gc_11_0_0_toc.bin"); -MODULE_FIRMWARE("amdgpu/gc_11_0_1_pfp.bin"); -MODULE_FIRMWARE("amdgpu/gc_11_0_1_me.bin"); -MODULE_FIRMWARE("amdgpu/gc_11_0_1_mec.bin"); -MODULE_FIRMWARE("amdgpu/gc_11_0_1_rlc.bin"); -MODULE_FIRMWARE("amdgpu/gc_11_0_2_pfp.bin"); -MODULE_FIRMWARE("amdgpu/gc_11_0_2_me.bin"); -MODULE_FIRMWARE("amdgpu/gc_11_0_2_mec.bin"); -MODULE_FIRMWARE("amdgpu/gc_11_0_2_rlc.bin"); -MODULE_FIRMWARE("amdgpu/gc_11_0_3_pfp.bin"); -MODULE_FIRMWARE("amdgpu/gc_11_0_3_me.bin"); -MODULE_FIRMWARE("amdgpu/gc_11_0_3_mec.bin"); -MODULE_FIRMWARE("amdgpu/gc_11_0_3_rlc.bin"); -MODULE_FIRMWARE("amdgpu/gc_11_0_4_pfp.bin"); -MODULE_FIRMWARE("amdgpu/gc_11_0_4_me.bin"); -MODULE_FIRMWARE("amdgpu/gc_11_0_4_mec.bin"); -MODULE_FIRMWARE("amdgpu/gc_11_0_4_rlc.bin"); static const struct soc15_reg_golden golden_settings_gc_11_0_1[] = { @@ -445,8 +424,6 @@ static void gfx_v11_0_free_microcode(struct amdgpu_device *adev) static int gfx_v11_0_init_microcode(struct amdgpu_device *adev) { - char fw_name[40]; - char ucode_prefix[30]; int err; const struct rlc_firmware_header_v2_0 *rlc_hdr; uint16_t version_major; @@ -454,12 +431,6 @@ static int gfx_v11_0_init_microcode(struct amdgpu_device *adev) DRM_DEBUG("\n"); - amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_prefix)); - - snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp.bin", ucode_prefix); - err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev); - if (err) - goto out; err = amdgpu_ucode_validate(adev->gfx.pfp_fw); if (err) goto out; @@ -476,10 +447,6 @@ static int gfx_v11_0_init_microcode(struct amdgpu_device *adev) amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_PFP); } - snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", ucode_prefix); - err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev); - if (err) - goto out; err = amdgpu_ucode_validate(adev->gfx.me_fw); if (err) goto out; @@ -492,10 +459,6 @@ static int gfx_v11_0_init_microcode(struct amdgpu_device *adev) } if (!amdgpu_sriov_vf(adev)) { - snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", ucode_prefix); - err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev); - if (err) - goto out; err = amdgpu_ucode_validate(adev->gfx.rlc_fw); if (err) goto out; @@ -507,10 +470,6 @@ static int gfx_v11_0_init_microcode(struct amdgpu_device *adev) goto out; } - snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", ucode_prefix); - err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev); - if (err) - goto out; err = amdgpu_ucode_validate(adev->gfx.mec_fw); if (err) goto out; @@ -530,9 +489,7 @@ static int gfx_v11_0_init_microcode(struct amdgpu_device *adev) out: if (err) { - dev_err(adev->dev, - "gfx11: Failed to init firmware \"%s\"\n", - fw_name); + dev_err(adev->dev, "gfx11: Failed to init firmware\n"); release_firmware(adev->gfx.pfp_fw); adev->gfx.pfp_fw = NULL; release_firmware(adev->gfx.me_fw); @@ -549,20 +506,6 @@ static int gfx_v11_0_init_microcode(struct amdgpu_device *adev) static int gfx_v11_0_init_toc_microcode(struct amdgpu_device *adev) { const struct psp_firmware_header_v1_0 *toc_hdr; - int err = 0; - char fw_name[40]; - char ucode_prefix[30]; - - amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_prefix)); - - snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_toc.bin", ucode_prefix); - err = request_firmware(&adev->psp.toc_fw, fw_name, adev->dev); - if (err) - goto out; - - err = amdgpu_ucode_validate(adev->psp.toc_fw); - if (err) - goto out; toc_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.toc_fw->data; adev->psp.toc.fw_version = le32_to_cpu(toc_hdr->header.ucode_version); @@ -571,11 +514,6 @@ static int gfx_v11_0_init_toc_microcode(struct amdgpu_device *adev) adev->psp.toc.start_addr = (uint8_t *)toc_hdr + le32_to_cpu(toc_hdr->header.ucode_array_offset_bytes); return 0; -out: - dev_err(adev->dev, "Failed to load TOC microcode\n"); - release_firmware(adev->psp.toc_fw); - adev->psp.toc_fw = NULL; - return err; } static u32 gfx_v11_0_get_csb_size(struct amdgpu_device *adev) From patchwork Fri Dec 30 05:21:15 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mario Limonciello X-Patchwork-Id: 37576 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4e01:0:0:0:0:0 with SMTP id p1csp2736329wrt; Thu, 29 Dec 2022 21:24:30 -0800 (PST) X-Google-Smtp-Source: AMrXdXsyoEKzNEJG5PYuD88bNL9Q+LmH2Y+w54RQj89JYmwa/Bpu13LWKBiKAKkU1XXULhDW5f3C X-Received: by 2002:a17:902:d508:b0:190:f82f:c932 with SMTP id b8-20020a170902d50800b00190f82fc932mr45797027plg.12.1672377870390; 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Thu, 29 Dec 2022 23:21:50 -0600 From: Mario Limonciello To: Alex Deucher , CC: Javier Martinez Canillas , Carlos Soriano Sanchez , , , David Airlie , "Daniel Vetter" , , Mario Limonciello , "Pan, Xinhui" Subject: [PATCH v3 11/11] drm/amd: Request PSP microcode during IP discovery Date: Thu, 29 Dec 2022 23:21:15 -0600 Message-ID: <20221230052119.15096-12-mario.limonciello@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221230052119.15096-1-mario.limonciello@amd.com> References: <20221230052119.15096-1-mario.limonciello@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1NAM11FT055:EE_|DS7PR12MB6142:EE_ X-MS-Office365-Filtering-Correlation-Id: 4392865a-a076-4a39-150b-08daea25c298 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: Zw4cNgM6IPchCF2NGSs/3WwqocjrS1SKX1y8JnlDv5Sti7teT1lQiFiKAeLbO95ypgmEZac5SdVDbQkK+M4KUyezvsnpRcu/+awpAxPuU+QqnAN6zCNhDO75MbtpJnEZadng5Kow5uBc/JdMuXqKDOvRktiR0fooRMPjfG40oUCwdMfAnAr+WzMDb3QKYPwl68QQ6ZG9idpUb9PO/hVNh2ljFMwNmICBP4Z/y6hbZTTqDDXZFLzV749HaL1qOdjqo+eP1V8d9zex1DZkO7EyOS3retMaPcTP/A87lUP2vi7iJRXzaMWNexRBnnwCHBNFHzcuDP4Y4bmU6yX2laLq/+BzW57WGqxjSurv94O7LUH1IflbylYERDACpvLvuoDEfvZ43C9g1MgR7x9qnrP/PdlFtgLGtJMmGPpUW7fCWNemGuNDModcQzbRUIe0zDwBQAPLIoI4fK8jMQgIjTmQEJRws0MojcevQGuPzLI115s7l3bFaLppgQKK+h6JWVEdWj/8aN43z4hd7Z6Q6LKQ0opyUIOpG6hu/V/vn98f13exDN6PE/BzmttPMIPGQgRwtkHdlohzzA40N94y5idY/GeQx2PmcuIA2pRtkFulJJR/bg3ohh7KXoQ1E9tY+rZqKCB0EyvkRGR1BUu87nB4ktuYis16MstTqtCoPLv0CTM6fezyBZ4PKuTzscluaAwdZlJsrKMcNUel/UAV9ENaDfwB7P2lLsVm++ZNNyu8Qcw= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230022)(4636009)(39860400002)(136003)(396003)(376002)(346002)(451199015)(40470700004)(36840700001)(46966006)(41300700001)(86362001)(47076005)(478600001)(7696005)(6666004)(8936002)(36756003)(26005)(186003)(16526019)(316002)(40460700003)(110136005)(54906003)(70206006)(4326008)(8676002)(70586007)(1076003)(426003)(2616005)(336012)(40480700001)(44832011)(30864003)(82310400005)(2906002)(356005)(83380400001)(5660300002)(81166007)(82740400003)(36860700001)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Dec 2022 05:21:52.4220 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4392865a-a076-4a39-150b-08daea25c298 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT055.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR12MB6142 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1753615298176375030?= X-GMAIL-MSGID: =?utf-8?q?1753615298176375030?= If PSP microcode is required but not available during early init, the firmware framebuffer will have already been released and the screen will freeze. Move the request for PSP microcode into the IP discovery phase so that if it's not available, IP discovery will fail. Signed-off-by: Mario Limonciello --- v2->v3: * Only request_firmware, don't validate during discovery --- drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 173 +++++++++++++++- drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 58 +----- drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h | 12 +- drivers/gpu/drm/amd/amdgpu/psp_v10_0.c | 99 +++------ drivers/gpu/drm/amd/amdgpu/psp_v11_0.c | 191 +++++------------- drivers/gpu/drm/amd/amdgpu/psp_v12_0.c | 98 +++------ drivers/gpu/drm/amd/amdgpu/psp_v13_0.c | 46 +---- drivers/gpu/drm/amd/amdgpu/psp_v13_0_4.c | 18 +- drivers/gpu/drm/amd/amdgpu/psp_v3_1.c | 16 +- 9 files changed, 297 insertions(+), 414 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c index ce1aa7683738..6b7dd0cf56ad 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c @@ -158,6 +158,40 @@ MODULE_FIRMWARE("amdgpu/gc_11_0_2_mes1.bin"); MODULE_FIRMWARE("amdgpu/gc_11_0_3_mes.bin"); MODULE_FIRMWARE("amdgpu/gc_11_0_3_mes1.bin"); +MODULE_FIRMWARE("amdgpu/aldebaran_sos.bin"); +MODULE_FIRMWARE("amdgpu/aldebaran_ta.bin"); +MODULE_FIRMWARE("amdgpu/aldebaran_cap.bin"); +MODULE_FIRMWARE("amdgpu/green_sardine_asd.bin"); +MODULE_FIRMWARE("amdgpu/green_sardine_ta.bin"); +MODULE_FIRMWARE("amdgpu/raven_asd.bin"); +MODULE_FIRMWARE("amdgpu/picasso_asd.bin"); +MODULE_FIRMWARE("amdgpu/raven2_asd.bin"); +MODULE_FIRMWARE("amdgpu/picasso_ta.bin"); +MODULE_FIRMWARE("amdgpu/raven2_ta.bin"); +MODULE_FIRMWARE("amdgpu/raven_ta.bin"); +MODULE_FIRMWARE("amdgpu/renoir_asd.bin"); +MODULE_FIRMWARE("amdgpu/renoir_ta.bin"); +MODULE_FIRMWARE("amdgpu/yellow_carp_toc.bin"); +MODULE_FIRMWARE("amdgpu/yellow_carp_ta.bin"); +MODULE_FIRMWARE("amdgpu/vega10_sos.bin"); +MODULE_FIRMWARE("amdgpu/vega10_asd.bin"); +MODULE_FIRMWARE("amdgpu/vega10_cap.bin"); +MODULE_FIRMWARE("amdgpu/vega12_sos.bin"); +MODULE_FIRMWARE("amdgpu/vega12_asd.bin"); +MODULE_FIRMWARE("amdgpu/psp_13_0_5_toc.bin"); +MODULE_FIRMWARE("amdgpu/psp_13_0_5_ta.bin"); +MODULE_FIRMWARE("amdgpu/psp_13_0_8_toc.bin"); +MODULE_FIRMWARE("amdgpu/psp_13_0_8_ta.bin"); +MODULE_FIRMWARE("amdgpu/psp_13_0_0_sos.bin"); +MODULE_FIRMWARE("amdgpu/psp_13_0_0_ta.bin"); +MODULE_FIRMWARE("amdgpu/psp_13_0_7_sos.bin"); +MODULE_FIRMWARE("amdgpu/psp_13_0_7_ta.bin"); +MODULE_FIRMWARE("amdgpu/psp_13_0_10_sos.bin"); +MODULE_FIRMWARE("amdgpu/psp_13_0_10_ta.bin"); +MODULE_FIRMWARE("amdgpu/psp_13_0_4_toc.bin"); +MODULE_FIRMWARE("amdgpu/psp_13_0_4_ta.bin"); +MODULE_FIRMWARE("amdgpu/psp_13_0_11_toc.bin"); +MODULE_FIRMWARE("amdgpu/psp_13_0_11_ta.bin"); /* gfx9 */ MODULE_FIRMWARE("amdgpu/vega10_ce.bin"); @@ -339,6 +373,13 @@ MODULE_FIRMWARE("amdgpu/gc_11_0_4_me.bin"); MODULE_FIRMWARE("amdgpu/gc_11_0_4_mec.bin"); MODULE_FIRMWARE("amdgpu/gc_11_0_4_rlc.bin"); +enum amd_psp_microcode_kind { + AMD_PSP_MICROCODE_SOS, + AMD_PSP_MICROCODE_ASD, + AMD_PSP_MICROCODE_TA, + AMD_PSP_MICROCODE_TOC, +}; + static const char *hw_id_names[HW_ID_MAX] = { [MP1_HWID] = "MP1", [MP2_HWID] = "MP2", @@ -1856,14 +1897,59 @@ static int amdgpu_discovery_set_ih_ip_blocks(struct amdgpu_device *adev) return 0; } +static int amdgpu_discovery_load_psp_fw(struct amdgpu_device *adev, + enum amd_psp_microcode_kind kind, + const char *chip_name) +{ + char fw_name[PSP_FW_NAME_LEN]; + + switch (kind) { + case AMD_PSP_MICROCODE_SOS: + snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sos.bin", chip_name); + return request_firmware(&adev->psp.sos_fw, fw_name, adev->dev); + case AMD_PSP_MICROCODE_ASD: + snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_asd.bin", chip_name); + return request_firmware(&adev->psp.asd_fw, fw_name, adev->dev); + case AMD_PSP_MICROCODE_TA: + snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name); + return request_firmware(&adev->psp.ta_fw, fw_name, adev->dev); + case AMD_PSP_MICROCODE_TOC: + snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_toc.bin", chip_name); + return request_firmware(&adev->psp.toc_fw, fw_name, adev->dev); + } + return -EINVAL; +} + static int amdgpu_discovery_set_psp_ip_blocks(struct amdgpu_device *adev) { + char ucode_prefix[30]; + int r; + + amdgpu_ucode_ip_version_decode(adev, MP0_HWIP, ucode_prefix, sizeof(ucode_prefix)); + adev->psp.adev = adev; + switch (adev->ip_versions[MP0_HWIP][0]) { case IP_VERSION(9, 0, 0): + r = amdgpu_discovery_load_psp_fw(adev, AMD_PSP_MICROCODE_SOS, + ucode_prefix); + if (r) + return r; + r = amdgpu_discovery_load_psp_fw(adev, AMD_PSP_MICROCODE_ASD, + ucode_prefix); + if (r) + return r; amdgpu_device_ip_block_add(adev, &psp_v3_1_ip_block); break; case IP_VERSION(10, 0, 0): case IP_VERSION(10, 0, 1): + r = amdgpu_discovery_load_psp_fw(adev, AMD_PSP_MICROCODE_ASD, + ucode_prefix); + if (r) + return r; + r = amdgpu_discovery_load_psp_fw(adev, AMD_PSP_MICROCODE_TA, + ucode_prefix); + if (r) + return r; amdgpu_device_ip_block_add(adev, &psp_v10_0_ip_block); break; case IP_VERSION(11, 0, 0): @@ -1871,11 +1957,41 @@ static int amdgpu_discovery_set_psp_ip_blocks(struct amdgpu_device *adev) case IP_VERSION(11, 0, 4): case IP_VERSION(11, 0, 5): case IP_VERSION(11, 0, 9): + r = amdgpu_discovery_load_psp_fw(adev, AMD_PSP_MICROCODE_SOS, + ucode_prefix); + if (r) + return r; + r = amdgpu_discovery_load_psp_fw(adev, AMD_PSP_MICROCODE_ASD, + ucode_prefix); + if (r) + return r; + r = amdgpu_discovery_load_psp_fw(adev, AMD_PSP_MICROCODE_TA, + ucode_prefix); + if (r) + return r; + break; case IP_VERSION(11, 0, 7): case IP_VERSION(11, 0, 11): case IP_VERSION(11, 0, 12): case IP_VERSION(11, 0, 13): + r = amdgpu_discovery_load_psp_fw(adev, AMD_PSP_MICROCODE_SOS, + ucode_prefix); + if (r) + return r; + r = amdgpu_discovery_load_psp_fw(adev, AMD_PSP_MICROCODE_TA, + ucode_prefix); + if (r) + return r; + break; case IP_VERSION(11, 5, 0): + r = amdgpu_discovery_load_psp_fw(adev, AMD_PSP_MICROCODE_ASD, + ucode_prefix); + if (r) + return r; + r = amdgpu_discovery_load_psp_fw(adev, AMD_PSP_MICROCODE_TOC, + ucode_prefix); + if (r) + return r; amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); break; case IP_VERSION(11, 0, 8): @@ -1883,20 +1999,69 @@ static int amdgpu_discovery_set_psp_ip_blocks(struct amdgpu_device *adev) break; case IP_VERSION(11, 0, 3): case IP_VERSION(12, 0, 1): + r = amdgpu_discovery_load_psp_fw(adev, AMD_PSP_MICROCODE_ASD, + ucode_prefix); + if (r) + return r; + r = amdgpu_discovery_load_psp_fw(adev, AMD_PSP_MICROCODE_TA, + ucode_prefix); + if (r) + return r; amdgpu_device_ip_block_add(adev, &psp_v12_0_ip_block); break; - case IP_VERSION(13, 0, 0): - case IP_VERSION(13, 0, 1): case IP_VERSION(13, 0, 2): + r = amdgpu_discovery_load_psp_fw(adev, AMD_PSP_MICROCODE_SOS, + ucode_prefix); + if (r) + return r; + /* It's not necessary to load ras ta on Guest side */ + if (!amdgpu_sriov_vf(adev)) { + r = amdgpu_discovery_load_psp_fw(adev, + AMD_PSP_MICROCODE_TA, + ucode_prefix); + if (r) + return r; + } + amdgpu_device_ip_block_add(adev, &psp_v13_0_ip_block); + break; + case IP_VERSION(13, 0, 1): case IP_VERSION(13, 0, 3): case IP_VERSION(13, 0, 5): - case IP_VERSION(13, 0, 7): case IP_VERSION(13, 0, 8): - case IP_VERSION(13, 0, 10): case IP_VERSION(13, 0, 11): + r = amdgpu_discovery_load_psp_fw(adev, AMD_PSP_MICROCODE_TOC, + ucode_prefix); + if (r) + return r; + r = amdgpu_discovery_load_psp_fw(adev, AMD_PSP_MICROCODE_TA, + ucode_prefix); + if (r) + return r; + amdgpu_device_ip_block_add(adev, &psp_v13_0_ip_block); + break; + case IP_VERSION(13, 0, 0): + case IP_VERSION(13, 0, 7): + case IP_VERSION(13, 0, 10): + r = amdgpu_discovery_load_psp_fw(adev, AMD_PSP_MICROCODE_SOS, + ucode_prefix); + if (r) + return r; + r = amdgpu_discovery_load_psp_fw(adev, AMD_PSP_MICROCODE_TA, + ucode_prefix); + + if (r) + return r; amdgpu_device_ip_block_add(adev, &psp_v13_0_ip_block); break; case IP_VERSION(13, 0, 4): + r = amdgpu_discovery_load_psp_fw(adev, AMD_PSP_MICROCODE_TOC, + ucode_prefix); + if (r) + return r; + r = amdgpu_discovery_load_psp_fw(adev, AMD_PSP_MICROCODE_TA, + ucode_prefix); + if (r) + return r; amdgpu_device_ip_block_add(adev, &psp_v13_0_4_ip_block); break; default: diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c index 7a2fc920739b..0aabf8d5a457 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c @@ -371,7 +371,7 @@ static int psp_init_sriov_microcode(struct psp_context *psp) case IP_VERSION(13, 0, 2): adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MEC2; ret = psp_init_cap_microcode(psp, "aldebaran"); - ret &= psp_init_ta_microcode(psp, "aldebaran"); + ret &= psp_init_ta_microcode(psp); break; case IP_VERSION(13, 0, 0): adev->virt.autoload_ucode_id = 0; @@ -2908,24 +2908,12 @@ int psp_ring_cmd_submit(struct psp_context *psp, return 0; } -int psp_init_asd_microcode(struct psp_context *psp, - const char *chip_name) +int psp_init_asd_microcode(struct psp_context *psp) { struct amdgpu_device *adev = psp->adev; - char fw_name[PSP_FW_NAME_LEN]; const struct psp_firmware_header_v1_0 *asd_hdr; int err = 0; - if (!chip_name) { - dev_err(adev->dev, "invalid chip name for asd microcode\n"); - return -EINVAL; - } - - snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_asd.bin", chip_name); - err = request_firmware(&adev->psp.asd_fw, fw_name, adev->dev); - if (err) - goto out; - err = amdgpu_ucode_validate(adev->psp.asd_fw); if (err) goto out; @@ -2944,24 +2932,12 @@ int psp_init_asd_microcode(struct psp_context *psp, return err; } -int psp_init_toc_microcode(struct psp_context *psp, - const char *chip_name) +int psp_init_toc_microcode(struct psp_context *psp) { struct amdgpu_device *adev = psp->adev; - char fw_name[PSP_FW_NAME_LEN]; const struct psp_firmware_header_v1_0 *toc_hdr; int err = 0; - if (!chip_name) { - dev_err(adev->dev, "invalid chip name for toc microcode\n"); - return -EINVAL; - } - - snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_toc.bin", chip_name); - err = request_firmware(&adev->psp.toc_fw, fw_name, adev->dev); - if (err) - goto out; - err = amdgpu_ucode_validate(adev->psp.toc_fw); if (err) goto out; @@ -3107,11 +3083,9 @@ static int psp_init_sos_base_fw(struct amdgpu_device *adev) return 0; } -int psp_init_sos_microcode(struct psp_context *psp, - const char *chip_name) +int psp_init_sos_microcode(struct psp_context *psp) { struct amdgpu_device *adev = psp->adev; - char fw_name[PSP_FW_NAME_LEN]; const struct psp_firmware_header_v1_0 *sos_hdr; const struct psp_firmware_header_v1_1 *sos_hdr_v1_1; const struct psp_firmware_header_v1_2 *sos_hdr_v1_2; @@ -3121,16 +3095,6 @@ int psp_init_sos_microcode(struct psp_context *psp, uint8_t *ucode_array_start_addr; int fw_index = 0; - if (!chip_name) { - dev_err(adev->dev, "invalid chip name for sos microcode\n"); - return -EINVAL; - } - - snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sos.bin", chip_name); - err = request_firmware(&adev->psp.sos_fw, fw_name, adev->dev); - if (err) - goto out; - err = amdgpu_ucode_validate(adev->psp.sos_fw); if (err) goto out; @@ -3272,25 +3236,13 @@ static int parse_ta_bin_descriptor(struct psp_context *psp, return 0; } -int psp_init_ta_microcode(struct psp_context *psp, - const char *chip_name) +int psp_init_ta_microcode(struct psp_context *psp) { struct amdgpu_device *adev = psp->adev; - char fw_name[PSP_FW_NAME_LEN]; const struct ta_firmware_header_v2_0 *ta_hdr; int err = 0; int ta_index = 0; - if (!chip_name) { - dev_err(adev->dev, "invalid chip name for ta microcode\n"); - return -EINVAL; - } - - snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name); - err = request_firmware(&adev->psp.ta_fw, fw_name, adev->dev); - if (err) - goto out; - err = amdgpu_ucode_validate(adev->psp.ta_fw); if (err) goto out; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h index cf4f60c66122..530e9ec1e263 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h @@ -502,14 +502,10 @@ int psp_ring_cmd_submit(struct psp_context *psp, uint64_t cmd_buf_mc_addr, uint64_t fence_mc_addr, int index); -int psp_init_asd_microcode(struct psp_context *psp, - const char *chip_name); -int psp_init_toc_microcode(struct psp_context *psp, - const char *chip_name); -int psp_init_sos_microcode(struct psp_context *psp, - const char *chip_name); -int psp_init_ta_microcode(struct psp_context *psp, - const char *chip_name); +int psp_init_asd_microcode(struct psp_context *psp); +int psp_init_toc_microcode(struct psp_context *psp); +int psp_init_sos_microcode(struct psp_context *psp); +int psp_init_ta_microcode(struct psp_context *psp); int psp_init_cap_microcode(struct psp_context *psp, const char *chip_name); int psp_get_fw_attestation_records_addr(struct psp_context *psp, diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c index 9de46fa8f46c..4357e6fbfe40 100644 --- a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c @@ -37,79 +37,45 @@ #include "gc/gc_9_1_offset.h" #include "sdma0/sdma0_4_1_offset.h" -MODULE_FIRMWARE("amdgpu/raven_asd.bin"); -MODULE_FIRMWARE("amdgpu/picasso_asd.bin"); -MODULE_FIRMWARE("amdgpu/raven2_asd.bin"); -MODULE_FIRMWARE("amdgpu/picasso_ta.bin"); -MODULE_FIRMWARE("amdgpu/raven2_ta.bin"); -MODULE_FIRMWARE("amdgpu/raven_ta.bin"); - static int psp_v10_0_init_microcode(struct psp_context *psp) { struct amdgpu_device *adev = psp->adev; - const char *chip_name; - char fw_name[30]; int err = 0; const struct ta_firmware_header_v1_0 *ta_hdr; DRM_DEBUG("\n"); - switch (adev->asic_type) { - case CHIP_RAVEN: - if (adev->apu_flags & AMD_APU_IS_RAVEN2) - chip_name = "raven2"; - else if (adev->apu_flags & AMD_APU_IS_PICASSO) - chip_name = "picasso"; - else - chip_name = "raven"; - break; - default: BUG(); - } - - err = psp_init_asd_microcode(psp, chip_name); + err = psp_init_asd_microcode(psp); if (err) goto out; - snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name); - err = request_firmware(&adev->psp.ta_fw, fw_name, adev->dev); - if (err) { - release_firmware(adev->psp.ta_fw); - adev->psp.ta_fw = NULL; - dev_info(adev->dev, - "psp v10.0: Failed to load firmware \"%s\"\n", - fw_name); - } else { - err = amdgpu_ucode_validate(adev->psp.ta_fw); - if (err) - goto out2; - - ta_hdr = (const struct ta_firmware_header_v1_0 *) - adev->psp.ta_fw->data; - adev->psp.hdcp_context.context.bin_desc.fw_version = - le32_to_cpu(ta_hdr->hdcp.fw_version); - adev->psp.hdcp_context.context.bin_desc.size_bytes = - le32_to_cpu(ta_hdr->hdcp.size_bytes); - adev->psp.hdcp_context.context.bin_desc.start_addr = - (uint8_t *)ta_hdr + - le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes); - - adev->psp.dtm_context.context.bin_desc.fw_version = - le32_to_cpu(ta_hdr->dtm.fw_version); - adev->psp.dtm_context.context.bin_desc.size_bytes = - le32_to_cpu(ta_hdr->dtm.size_bytes); - adev->psp.dtm_context.context.bin_desc.start_addr = - (uint8_t *)adev->psp.hdcp_context.context.bin_desc.start_addr + - le32_to_cpu(ta_hdr->dtm.offset_bytes); - - adev->psp.securedisplay_context.context.bin_desc.fw_version = - le32_to_cpu(ta_hdr->securedisplay.fw_version); - adev->psp.securedisplay_context.context.bin_desc.size_bytes = - le32_to_cpu(ta_hdr->securedisplay.size_bytes); - adev->psp.securedisplay_context.context.bin_desc.start_addr = - (uint8_t *)adev->psp.hdcp_context.context.bin_desc.start_addr + - le32_to_cpu(ta_hdr->securedisplay.offset_bytes); - - adev->psp.ta_fw_version = le32_to_cpu(ta_hdr->header.ucode_version); - } + err = amdgpu_ucode_validate(adev->psp.ta_fw); + if (err) + goto out2; + + ta_hdr = (const struct ta_firmware_header_v1_0 *) + adev->psp.ta_fw->data; + adev->psp.hdcp_context.context.bin_desc.fw_version = + le32_to_cpu(ta_hdr->hdcp.fw_version); + adev->psp.hdcp_context.context.bin_desc.size_bytes = + le32_to_cpu(ta_hdr->hdcp.size_bytes); + adev->psp.hdcp_context.context.bin_desc.start_addr = + (uint8_t *)ta_hdr + + le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes); + adev->psp.dtm_context.context.bin_desc.fw_version = + le32_to_cpu(ta_hdr->dtm.fw_version); + adev->psp.dtm_context.context.bin_desc.size_bytes = + le32_to_cpu(ta_hdr->dtm.size_bytes); + adev->psp.dtm_context.context.bin_desc.start_addr = + (uint8_t *)adev->psp.hdcp_context.context.bin_desc.start_addr + + le32_to_cpu(ta_hdr->dtm.offset_bytes); + adev->psp.securedisplay_context.context.bin_desc.fw_version = + le32_to_cpu(ta_hdr->securedisplay.fw_version); + adev->psp.securedisplay_context.context.bin_desc.size_bytes = + le32_to_cpu(ta_hdr->securedisplay.size_bytes); + adev->psp.securedisplay_context.context.bin_desc.start_addr = + (uint8_t *)adev->psp.hdcp_context.context.bin_desc.start_addr + + le32_to_cpu(ta_hdr->securedisplay.offset_bytes); + adev->psp.ta_fw_version = le32_to_cpu(ta_hdr->header.ucode_version); return 0; @@ -117,11 +83,8 @@ static int psp_v10_0_init_microcode(struct psp_context *psp) release_firmware(adev->psp.ta_fw); adev->psp.ta_fw = NULL; out: - if (err) { - dev_err(adev->dev, - "psp v10.0: Failed to load firmware \"%s\"\n", - fw_name); - } + if (err) + dev_err(adev->dev, "psp v10.0: Failed to load firmware"); return err; } diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c index bd3e3e23a939..34e93232f3e4 100644 --- a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c @@ -41,34 +41,6 @@ #include "oss/osssys_4_0_offset.h" #include "oss/osssys_4_0_sh_mask.h" -MODULE_FIRMWARE("amdgpu/vega20_sos.bin"); -MODULE_FIRMWARE("amdgpu/vega20_asd.bin"); -MODULE_FIRMWARE("amdgpu/vega20_ta.bin"); -MODULE_FIRMWARE("amdgpu/navi10_sos.bin"); -MODULE_FIRMWARE("amdgpu/navi10_asd.bin"); -MODULE_FIRMWARE("amdgpu/navi10_ta.bin"); -MODULE_FIRMWARE("amdgpu/navi14_sos.bin"); -MODULE_FIRMWARE("amdgpu/navi14_asd.bin"); -MODULE_FIRMWARE("amdgpu/navi14_ta.bin"); -MODULE_FIRMWARE("amdgpu/navi12_sos.bin"); -MODULE_FIRMWARE("amdgpu/navi12_asd.bin"); -MODULE_FIRMWARE("amdgpu/navi12_ta.bin"); -MODULE_FIRMWARE("amdgpu/navi12_cap.bin"); -MODULE_FIRMWARE("amdgpu/arcturus_sos.bin"); -MODULE_FIRMWARE("amdgpu/arcturus_asd.bin"); -MODULE_FIRMWARE("amdgpu/arcturus_ta.bin"); -MODULE_FIRMWARE("amdgpu/sienna_cichlid_sos.bin"); -MODULE_FIRMWARE("amdgpu/sienna_cichlid_ta.bin"); -MODULE_FIRMWARE("amdgpu/sienna_cichlid_cap.bin"); -MODULE_FIRMWARE("amdgpu/navy_flounder_sos.bin"); -MODULE_FIRMWARE("amdgpu/navy_flounder_ta.bin"); -MODULE_FIRMWARE("amdgpu/vangogh_asd.bin"); -MODULE_FIRMWARE("amdgpu/vangogh_toc.bin"); -MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_sos.bin"); -MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_ta.bin"); -MODULE_FIRMWARE("amdgpu/beige_goby_sos.bin"); -MODULE_FIRMWARE("amdgpu/beige_goby_ta.bin"); - /* address block */ #define smnMP1_FIRMWARE_FLAGS 0x3010024 /* navi10 reg offset define */ @@ -88,147 +60,89 @@ MODULE_FIRMWARE("amdgpu/beige_goby_ta.bin"); static int psp_v11_0_init_microcode(struct psp_context *psp) { struct amdgpu_device *adev = psp->adev; - const char *chip_name; - char fw_name[PSP_FW_NAME_LEN]; int err = 0; const struct ta_firmware_header_v1_0 *ta_hdr; DRM_DEBUG("\n"); - switch (adev->ip_versions[MP0_HWIP][0]) { - case IP_VERSION(11, 0, 2): - chip_name = "vega20"; - break; - case IP_VERSION(11, 0, 0): - chip_name = "navi10"; - break; - case IP_VERSION(11, 0, 5): - chip_name = "navi14"; - break; - case IP_VERSION(11, 0, 9): - chip_name = "navi12"; - break; - case IP_VERSION(11, 0, 4): - chip_name = "arcturus"; - break; - case IP_VERSION(11, 0, 7): - chip_name = "sienna_cichlid"; - break; - case IP_VERSION(11, 0, 11): - chip_name = "navy_flounder"; - break; - case IP_VERSION(11, 5, 0): - chip_name = "vangogh"; - break; - case IP_VERSION(11, 0, 12): - chip_name = "dimgrey_cavefish"; - break; - case IP_VERSION(11, 0, 13): - chip_name = "beige_goby"; - break; - default: - BUG(); - } - - switch (adev->ip_versions[MP0_HWIP][0]) { case IP_VERSION(11, 0, 2): case IP_VERSION(11, 0, 4): - err = psp_init_sos_microcode(psp, chip_name); + err = psp_init_sos_microcode(psp); if (err) return err; - err = psp_init_asd_microcode(psp, chip_name); + err = psp_init_asd_microcode(psp); if (err) return err; - snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name); - err = request_firmware(&adev->psp.ta_fw, fw_name, adev->dev); - if (err) { - release_firmware(adev->psp.ta_fw); - adev->psp.ta_fw = NULL; - dev_info(adev->dev, - "psp v11.0: Failed to load firmware \"%s\"\n", fw_name); - } else { - err = amdgpu_ucode_validate(adev->psp.ta_fw); - if (err) - goto out2; - - ta_hdr = (const struct ta_firmware_header_v1_0 *)adev->psp.ta_fw->data; - adev->psp.xgmi_context.context.bin_desc.fw_version = - le32_to_cpu(ta_hdr->xgmi.fw_version); - adev->psp.xgmi_context.context.bin_desc.size_bytes = - le32_to_cpu(ta_hdr->xgmi.size_bytes); - adev->psp.xgmi_context.context.bin_desc.start_addr = - (uint8_t *)ta_hdr + - le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes); - adev->psp.ta_fw_version = le32_to_cpu(ta_hdr->header.ucode_version); - adev->psp.ras_context.context.bin_desc.fw_version = - le32_to_cpu(ta_hdr->ras.fw_version); - adev->psp.ras_context.context.bin_desc.size_bytes = - le32_to_cpu(ta_hdr->ras.size_bytes); - adev->psp.ras_context.context.bin_desc.start_addr = - (uint8_t *)adev->psp.xgmi_context.context.bin_desc.start_addr + - le32_to_cpu(ta_hdr->ras.offset_bytes); - } + err = amdgpu_ucode_validate(adev->psp.ta_fw); + if (err) + return err; + + ta_hdr = (const struct ta_firmware_header_v1_0 *)adev->psp.ta_fw->data; + adev->psp.xgmi_context.context.bin_desc.fw_version = + le32_to_cpu(ta_hdr->xgmi.fw_version); + adev->psp.xgmi_context.context.bin_desc.size_bytes = + le32_to_cpu(ta_hdr->xgmi.size_bytes); + adev->psp.xgmi_context.context.bin_desc.start_addr = + (uint8_t *)ta_hdr + + le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes); + adev->psp.ta_fw_version = le32_to_cpu(ta_hdr->header.ucode_version); + adev->psp.ras_context.context.bin_desc.fw_version = + le32_to_cpu(ta_hdr->ras.fw_version); + adev->psp.ras_context.context.bin_desc.size_bytes = + le32_to_cpu(ta_hdr->ras.size_bytes); + adev->psp.ras_context.context.bin_desc.start_addr = + (uint8_t *)adev->psp.xgmi_context.context.bin_desc.start_addr + + le32_to_cpu(ta_hdr->ras.offset_bytes); break; case IP_VERSION(11, 0, 0): case IP_VERSION(11, 0, 5): case IP_VERSION(11, 0, 9): - err = psp_init_sos_microcode(psp, chip_name); + err = psp_init_sos_microcode(psp); if (err) return err; - err = psp_init_asd_microcode(psp, chip_name); + err = psp_init_asd_microcode(psp); if (err) return err; - snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name); - err = request_firmware(&adev->psp.ta_fw, fw_name, adev->dev); - if (err) { - release_firmware(adev->psp.ta_fw); - adev->psp.ta_fw = NULL; - dev_info(adev->dev, - "psp v11.0: Failed to load firmware \"%s\"\n", fw_name); - } else { - err = amdgpu_ucode_validate(adev->psp.ta_fw); - if (err) - goto out2; - - ta_hdr = (const struct ta_firmware_header_v1_0 *)adev->psp.ta_fw->data; - adev->psp.hdcp_context.context.bin_desc.fw_version = - le32_to_cpu(ta_hdr->hdcp.fw_version); - adev->psp.hdcp_context.context.bin_desc.size_bytes = - le32_to_cpu(ta_hdr->hdcp.size_bytes); - adev->psp.hdcp_context.context.bin_desc.start_addr = - (uint8_t *)ta_hdr + - le32_to_cpu( - ta_hdr->header.ucode_array_offset_bytes); - - adev->psp.ta_fw_version = le32_to_cpu(ta_hdr->header.ucode_version); - - adev->psp.dtm_context.context.bin_desc.fw_version = - le32_to_cpu(ta_hdr->dtm.fw_version); - adev->psp.dtm_context.context.bin_desc.size_bytes = - le32_to_cpu(ta_hdr->dtm.size_bytes); - adev->psp.dtm_context.context.bin_desc.start_addr = - (uint8_t *)adev->psp.hdcp_context.context - .bin_desc.start_addr + - le32_to_cpu(ta_hdr->dtm.offset_bytes); - } + err = amdgpu_ucode_validate(adev->psp.ta_fw); + if (err) + return err; + + ta_hdr = (const struct ta_firmware_header_v1_0 *)adev->psp.ta_fw->data; + adev->psp.hdcp_context.context.bin_desc.fw_version = + le32_to_cpu(ta_hdr->hdcp.fw_version); + adev->psp.hdcp_context.context.bin_desc.size_bytes = + le32_to_cpu(ta_hdr->hdcp.size_bytes); + adev->psp.hdcp_context.context.bin_desc.start_addr = + (uint8_t *)ta_hdr + + le32_to_cpu( + ta_hdr->header.ucode_array_offset_bytes); + adev->psp.ta_fw_version = le32_to_cpu(ta_hdr->header.ucode_version); + adev->psp.dtm_context.context.bin_desc.fw_version = + le32_to_cpu(ta_hdr->dtm.fw_version); + adev->psp.dtm_context.context.bin_desc.size_bytes = + le32_to_cpu(ta_hdr->dtm.size_bytes); + adev->psp.dtm_context.context.bin_desc.start_addr = + (uint8_t *)adev->psp.hdcp_context.context + .bin_desc.start_addr + + le32_to_cpu(ta_hdr->dtm.offset_bytes); break; case IP_VERSION(11, 0, 7): case IP_VERSION(11, 0, 11): case IP_VERSION(11, 0, 12): case IP_VERSION(11, 0, 13): - err = psp_init_sos_microcode(psp, chip_name); + err = psp_init_sos_microcode(psp); if (err) return err; - err = psp_init_ta_microcode(psp, chip_name); + err = psp_init_ta_microcode(psp); if (err) return err; break; case IP_VERSION(11, 5, 0): - err = psp_init_asd_microcode(psp, chip_name); + err = psp_init_asd_microcode(psp); if (err) return err; - err = psp_init_toc_microcode(psp, chip_name); + err = psp_init_toc_microcode(psp); if (err) return err; break; @@ -237,11 +151,6 @@ static int psp_v11_0_init_microcode(struct psp_context *psp) } return 0; - -out2: - release_firmware(adev->psp.ta_fw); - adev->psp.ta_fw = NULL; - return err; } static int psp_v11_0_wait_for_bootloader(struct psp_context *psp) diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v12_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v12_0.c index 8ed2281b6557..4fa0cd6d5df9 100644 --- a/drivers/gpu/drm/amd/amdgpu/psp_v12_0.c +++ b/drivers/gpu/drm/amd/amdgpu/psp_v12_0.c @@ -37,94 +37,52 @@ #include "oss/osssys_4_0_offset.h" #include "oss/osssys_4_0_sh_mask.h" -MODULE_FIRMWARE("amdgpu/renoir_asd.bin"); -MODULE_FIRMWARE("amdgpu/renoir_ta.bin"); -MODULE_FIRMWARE("amdgpu/green_sardine_asd.bin"); -MODULE_FIRMWARE("amdgpu/green_sardine_ta.bin"); - /* address block */ #define smnMP1_FIRMWARE_FLAGS 0x3010024 static int psp_v12_0_init_microcode(struct psp_context *psp) { struct amdgpu_device *adev = psp->adev; - const char *chip_name; - char fw_name[30]; int err = 0; const struct ta_firmware_header_v1_0 *ta_hdr; DRM_DEBUG("\n"); - switch (adev->asic_type) { - case CHIP_RENOIR: - if (adev->apu_flags & AMD_APU_IS_RENOIR) - chip_name = "renoir"; - else - chip_name = "green_sardine"; - break; - default: - BUG(); - } + err = psp_init_asd_microcode(psp); + if (err) + return err; - err = psp_init_asd_microcode(psp, chip_name); + err = amdgpu_ucode_validate(adev->psp.ta_fw); if (err) return err; - snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name); - err = request_firmware(&adev->psp.ta_fw, fw_name, adev->dev); - if (err) { - release_firmware(adev->psp.ta_fw); - adev->psp.ta_fw = NULL; - dev_info(adev->dev, - "psp v12.0: Failed to load firmware \"%s\"\n", - fw_name); - } else { - err = amdgpu_ucode_validate(adev->psp.ta_fw); - if (err) - goto out; - - ta_hdr = (const struct ta_firmware_header_v1_0 *) - adev->psp.ta_fw->data; - adev->psp.hdcp_context.context.bin_desc.fw_version = - le32_to_cpu(ta_hdr->hdcp.fw_version); - adev->psp.hdcp_context.context.bin_desc.size_bytes = - le32_to_cpu(ta_hdr->hdcp.size_bytes); - adev->psp.hdcp_context.context.bin_desc.start_addr = - (uint8_t *)ta_hdr + - le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes); - - adev->psp.ta_fw_version = le32_to_cpu(ta_hdr->header.ucode_version); - - adev->psp.dtm_context.context.bin_desc.fw_version = - le32_to_cpu(ta_hdr->dtm.fw_version); - adev->psp.dtm_context.context.bin_desc.size_bytes = - le32_to_cpu(ta_hdr->dtm.size_bytes); - adev->psp.dtm_context.context.bin_desc.start_addr = + ta_hdr = (const struct ta_firmware_header_v1_0 *) + adev->psp.ta_fw->data; + adev->psp.hdcp_context.context.bin_desc.fw_version = + le32_to_cpu(ta_hdr->hdcp.fw_version); + adev->psp.hdcp_context.context.bin_desc.size_bytes = + le32_to_cpu(ta_hdr->hdcp.size_bytes); + adev->psp.hdcp_context.context.bin_desc.start_addr = + (uint8_t *)ta_hdr + + le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes); + adev->psp.ta_fw_version = le32_to_cpu(ta_hdr->header.ucode_version); + adev->psp.dtm_context.context.bin_desc.fw_version = + le32_to_cpu(ta_hdr->dtm.fw_version); + adev->psp.dtm_context.context.bin_desc.size_bytes = + le32_to_cpu(ta_hdr->dtm.size_bytes); + adev->psp.dtm_context.context.bin_desc.start_addr = + (uint8_t *)adev->psp.hdcp_context.context.bin_desc.start_addr + + le32_to_cpu(ta_hdr->dtm.offset_bytes); + if (adev->apu_flags & AMD_APU_IS_RENOIR) { + adev->psp.securedisplay_context.context.bin_desc.fw_version = + le32_to_cpu(ta_hdr->securedisplay.fw_version); + adev->psp.securedisplay_context.context.bin_desc.size_bytes = + le32_to_cpu(ta_hdr->securedisplay.size_bytes); + adev->psp.securedisplay_context.context.bin_desc.start_addr = (uint8_t *)adev->psp.hdcp_context.context.bin_desc.start_addr + - le32_to_cpu(ta_hdr->dtm.offset_bytes); - - if (adev->apu_flags & AMD_APU_IS_RENOIR) { - adev->psp.securedisplay_context.context.bin_desc.fw_version = - le32_to_cpu(ta_hdr->securedisplay.fw_version); - adev->psp.securedisplay_context.context.bin_desc.size_bytes = - le32_to_cpu(ta_hdr->securedisplay.size_bytes); - adev->psp.securedisplay_context.context.bin_desc.start_addr = - (uint8_t *)adev->psp.hdcp_context.context.bin_desc.start_addr + - le32_to_cpu(ta_hdr->securedisplay.offset_bytes); + le32_to_cpu(ta_hdr->securedisplay.offset_bytes); } - } return 0; - -out: - release_firmware(adev->psp.ta_fw); - adev->psp.ta_fw = NULL; - if (err) { - dev_err(adev->dev, - "psp v12.0: Failed to load firmware \"%s\"\n", - fw_name); - } - - return err; } static int psp_v12_0_bootloader_load_sysdrv(struct psp_context *psp) diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c index e6a26a7e5e5e..44026f7f60f2 100644 --- a/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c +++ b/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c @@ -31,24 +31,6 @@ #include "mp/mp_13_0_2_offset.h" #include "mp/mp_13_0_2_sh_mask.h" -MODULE_FIRMWARE("amdgpu/aldebaran_sos.bin"); -MODULE_FIRMWARE("amdgpu/aldebaran_ta.bin"); -MODULE_FIRMWARE("amdgpu/aldebaran_cap.bin"); -MODULE_FIRMWARE("amdgpu/yellow_carp_toc.bin"); -MODULE_FIRMWARE("amdgpu/yellow_carp_ta.bin"); -MODULE_FIRMWARE("amdgpu/psp_13_0_5_toc.bin"); -MODULE_FIRMWARE("amdgpu/psp_13_0_5_ta.bin"); -MODULE_FIRMWARE("amdgpu/psp_13_0_8_toc.bin"); -MODULE_FIRMWARE("amdgpu/psp_13_0_8_ta.bin"); -MODULE_FIRMWARE("amdgpu/psp_13_0_0_sos.bin"); -MODULE_FIRMWARE("amdgpu/psp_13_0_0_ta.bin"); -MODULE_FIRMWARE("amdgpu/psp_13_0_7_sos.bin"); -MODULE_FIRMWARE("amdgpu/psp_13_0_7_ta.bin"); -MODULE_FIRMWARE("amdgpu/psp_13_0_10_sos.bin"); -MODULE_FIRMWARE("amdgpu/psp_13_0_10_ta.bin"); -MODULE_FIRMWARE("amdgpu/psp_13_0_11_toc.bin"); -MODULE_FIRMWARE("amdgpu/psp_13_0_11_ta.bin"); - /* For large FW files the time to complete can be very long */ #define USBC_PD_POLLING_LIMIT_S 240 @@ -70,32 +52,16 @@ MODULE_FIRMWARE("amdgpu/psp_13_0_11_ta.bin"); static int psp_v13_0_init_microcode(struct psp_context *psp) { struct amdgpu_device *adev = psp->adev; - const char *chip_name; - char ucode_prefix[30]; int err = 0; switch (adev->ip_versions[MP0_HWIP][0]) { case IP_VERSION(13, 0, 2): - chip_name = "aldebaran"; - break; - case IP_VERSION(13, 0, 1): - case IP_VERSION(13, 0, 3): - chip_name = "yellow_carp"; - break; - default: - amdgpu_ucode_ip_version_decode(adev, MP0_HWIP, ucode_prefix, sizeof(ucode_prefix)); - chip_name = ucode_prefix; - break; - } - - switch (adev->ip_versions[MP0_HWIP][0]) { - case IP_VERSION(13, 0, 2): - err = psp_init_sos_microcode(psp, chip_name); + err = psp_init_sos_microcode(psp); if (err) return err; /* It's not necessary to load ras ta on Guest side */ if (!amdgpu_sriov_vf(adev)) { - err = psp_init_ta_microcode(&adev->psp, chip_name); + err = psp_init_ta_microcode(&adev->psp); if (err) return err; } @@ -105,21 +71,21 @@ static int psp_v13_0_init_microcode(struct psp_context *psp) case IP_VERSION(13, 0, 5): case IP_VERSION(13, 0, 8): case IP_VERSION(13, 0, 11): - err = psp_init_toc_microcode(psp, chip_name); + err = psp_init_toc_microcode(psp); if (err) return err; - err = psp_init_ta_microcode(psp, chip_name); + err = psp_init_ta_microcode(psp); if (err) return err; break; case IP_VERSION(13, 0, 0): case IP_VERSION(13, 0, 7): case IP_VERSION(13, 0, 10): - err = psp_init_sos_microcode(psp, chip_name); + err = psp_init_sos_microcode(psp); if (err) return err; /* It's not necessary to load ras ta on Guest side */ - err = psp_init_ta_microcode(psp, chip_name); + err = psp_init_ta_microcode(psp); if (err) return err; break; diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v13_0_4.c b/drivers/gpu/drm/amd/amdgpu/psp_v13_0_4.c index 9d4e24e518e8..cef3848cd6a3 100644 --- a/drivers/gpu/drm/amd/amdgpu/psp_v13_0_4.c +++ b/drivers/gpu/drm/amd/amdgpu/psp_v13_0_4.c @@ -29,31 +29,17 @@ #include "mp/mp_13_0_4_offset.h" #include "mp/mp_13_0_4_sh_mask.h" -MODULE_FIRMWARE("amdgpu/psp_13_0_4_toc.bin"); -MODULE_FIRMWARE("amdgpu/psp_13_0_4_ta.bin"); - static int psp_v13_0_4_init_microcode(struct psp_context *psp) { struct amdgpu_device *adev = psp->adev; - const char *chip_name; - char ucode_prefix[30]; int err = 0; switch (adev->ip_versions[MP0_HWIP][0]) { case IP_VERSION(13, 0, 4): - amdgpu_ucode_ip_version_decode(adev, MP0_HWIP, ucode_prefix, sizeof(ucode_prefix)); - chip_name = ucode_prefix; - break; - default: - BUG(); - } - - switch (adev->ip_versions[MP0_HWIP][0]) { - case IP_VERSION(13, 0, 4): - err = psp_init_toc_microcode(psp, chip_name); + err = psp_init_toc_microcode(psp); if (err) return err; - err = psp_init_ta_microcode(psp, chip_name); + err = psp_init_ta_microcode(psp); if (err) return err; break; diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c index 157147c6c94e..d20e69e4c17b 100644 --- a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c +++ b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c @@ -56,27 +56,15 @@ static int psp_v3_1_ring_stop(struct psp_context *psp, static int psp_v3_1_init_microcode(struct psp_context *psp) { - struct amdgpu_device *adev = psp->adev; - const char *chip_name; int err = 0; DRM_DEBUG("\n"); - switch (adev->asic_type) { - case CHIP_VEGA10: - chip_name = "vega10"; - break; - case CHIP_VEGA12: - chip_name = "vega12"; - break; - default: BUG(); - } - - err = psp_init_sos_microcode(psp, chip_name); + err = psp_init_sos_microcode(psp); if (err) return err; - err = psp_init_asd_microcode(psp, chip_name); + err = psp_init_asd_microcode(psp); if (err) return err;