From patchwork Wed Dec 28 06:33:29 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?QmlhbyBIdWFuZyAo6buE5b2qKQ==?= X-Patchwork-Id: 37114 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4e01:0:0:0:0:0 with SMTP id p1csp1746017wrt; Tue, 27 Dec 2022 22:34:14 -0800 (PST) X-Google-Smtp-Source: AMrXdXvJFiYqreZYVo+vdqYNu6EpudDSv8GEQYe1mF0YTT6xFcIRsKLQMbLagBKvDZZdjDC19Sx6 X-Received: by 2002:a05:6a20:5482:b0:a4:491d:d589 with SMTP id i2-20020a056a20548200b000a4491dd589mr43667414pzk.4.1672209253813; Tue, 27 Dec 2022 22:34:13 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1672209253; cv=none; d=google.com; s=arc-20160816; b=gHXXgHHzZnHSAcrOveHurCFX1FNvZicMRvK/QUrIwojLYvZnXfyERkjSszR5zwHUSa AL6yg76cwScyAKqONg1H4aOj1zpZe6hLAkhxCcCvNBGzqtKnR0/fQeA+21f5jV8fbmQ9 5QAkVaB4GRidAP7NiKxoWpXIDKHlKPw2V1JjV74rDnHiaUG2QlVUqLtGQb2n5naOVpsZ LAdMB+9/yrIN4MJL+/fWbnwprUS4NauOdjN21A2TUYNHVAMBjG90mpbg+GyU0Cukml+T yRfc85N9uNHqcfCz3eXn2cCtzNBqKUSoZPAmRaRysofasdlXjI5xI9ouUZpiRBLhyDkw zenA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=gyLi655fRlGzISUNyT/xvu6TEKN5PJCN3blt5ogeZ+M=; b=XhVzsS+TRTQiQDB6h/qonz7NXyZz9RJ66ZbRhuoF1iNmESW6QBybvDaauqZ3K6pLWy nDvA0HlIv1hpCv4x48wrgKTf5Lwh6ABbi+P8lTUQnZto6lu/883quYFFyjx5vxh56/wY cmJmpmL20QeuWwG0pB/O2+P4gWD9Hq5/NXdswRsw0oe1Az8zPk44U17SRG+EOWt1s7P/ /iUhmMZ6z/veZGql42jwyGiytxk+oTSvG6Ye2aBhjt3ECDaFhYB1+v2u6JuXKYz3L0qr ZCJezrFL8cuZBCsIDFtxa3Ur4Iq14jhUJKCSTti5FMBaQXGVaN9LbFGBFOWH68VZ55gQ CKQA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@mediatek.com header.s=dk header.b=qqXPfTzd; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=mediatek.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id w184-20020a6362c1000000b004403ddda6e6si16847887pgb.847.2022.12.27.22.33.59; Tue, 27 Dec 2022 22:34:13 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@mediatek.com header.s=dk header.b=qqXPfTzd; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=mediatek.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229764AbiL1Gds (ORCPT + 99 others); Wed, 28 Dec 2022 01:33:48 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40076 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229526AbiL1Gdp (ORCPT ); Wed, 28 Dec 2022 01:33:45 -0500 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 15DD2DF17; Tue, 27 Dec 2022 22:33:42 -0800 (PST) X-UUID: b77685c05b7547bf88586689e8b9513a-20221228 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=gyLi655fRlGzISUNyT/xvu6TEKN5PJCN3blt5ogeZ+M=; b=qqXPfTzdYAxeCqy+beYe6iL4oN38+oz4/WBmcBD39983I+jB1KHlaQBfCpegrGtZyNe6nw5jME4aVVnV6Jp4SjhRzFkGtwGlaJhscBkipJmN5ZM1bIlPxzQsidtIflyGUXErc8vbfI9djflrIVmufgN6PJoJc+WOpOIEmTn9aAY=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.14,REQID:18ec9696-8c75-4b3b-958f-f248453ffff0,IP:0,U RL:0,TC:0,Content:-5,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION :release,TS:-5 X-CID-META: VersionHash:dcaaed0,CLOUDID:f59b0053-dd49-462e-a4be-2143a3ddc739,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0 X-UUID: b77685c05b7547bf88586689e8b9513a-20221228 Received: from mtkmbs13n2.mediatek.inc [(172.21.101.108)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 354974358; Wed, 28 Dec 2022 14:33:36 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.186) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.3; Wed, 28 Dec 2022 14:33:35 +0800 Received: from localhost.localdomain (10.17.3.154) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Wed, 28 Dec 2022 14:33:33 +0800 From: Biao Huang To: Andrew Lunn , AngeloGioacchino Del Regno , Rob Herring , Krzysztof Kozlowski , Matthias Brugger CC: Giuseppe Cavallaro , Alexandre Torgue , Jose Abreu , "David S . Miller" , Eric Dumazet , "Jakub Kicinski" , Paolo Abeni , Maxime Coquelin , Richard Cochran , , , , , "Biao Huang" , Subject: [PATCH v6 1/2] stmmac: dwmac-mediatek: remove the dwmac_fix_mac_speed Date: Wed, 28 Dec 2022 14:33:29 +0800 Message-ID: <20221228063331.10756-2-biao.huang@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221228063331.10756-1-biao.huang@mediatek.com> References: <20221228063331.10756-1-biao.huang@mediatek.com> MIME-Version: 1.0 X-MTK: N X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS, SPF_PASS,UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1753438490412390054?= X-GMAIL-MSGID: =?utf-8?q?1753438490412390054?= In current driver, MAC will always enable 2ns delay in RGMII mode, but that's not the correct usage. Remove the dwmac_fix_mac_speed() in driver, and recommend "rgmii-id" for phy-mode in device tree. Fixes: f2d356a6ab71 ("stmmac: dwmac-mediatek: add support for mt8195") Signed-off-by: Biao Huang --- .../ethernet/stmicro/stmmac/dwmac-mediatek.c | 26 ------------------- 1 file changed, 26 deletions(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c index d42e1afb6521..2f7d8e4561d9 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c @@ -90,7 +90,6 @@ struct mediatek_dwmac_plat_data { struct mediatek_dwmac_variant { int (*dwmac_set_phy_interface)(struct mediatek_dwmac_plat_data *plat); int (*dwmac_set_delay)(struct mediatek_dwmac_plat_data *plat); - void (*dwmac_fix_mac_speed)(void *priv, unsigned int speed); /* clock ids to be requested */ const char * const *clk_list; @@ -443,32 +442,9 @@ static int mt8195_set_delay(struct mediatek_dwmac_plat_data *plat) return 0; } -static void mt8195_fix_mac_speed(void *priv, unsigned int speed) -{ - struct mediatek_dwmac_plat_data *priv_plat = priv; - - if ((phy_interface_mode_is_rgmii(priv_plat->phy_mode))) { - /* prefer 2ns fixed delay which is controlled by TXC_PHASE_CTRL, - * when link speed is 1Gbps with RGMII interface, - * Fall back to delay macro circuit for 10/100Mbps link speed. - */ - if (speed == SPEED_1000) - regmap_update_bits(priv_plat->peri_regmap, - MT8195_PERI_ETH_CTRL0, - MT8195_RGMII_TXC_PHASE_CTRL | - MT8195_DLY_GTXC_ENABLE | - MT8195_DLY_GTXC_INV | - MT8195_DLY_GTXC_STAGES, - MT8195_RGMII_TXC_PHASE_CTRL); - else - mt8195_set_delay(priv_plat); - } -} - static const struct mediatek_dwmac_variant mt8195_gmac_variant = { .dwmac_set_phy_interface = mt8195_set_interface, .dwmac_set_delay = mt8195_set_delay, - .dwmac_fix_mac_speed = mt8195_fix_mac_speed, .clk_list = mt8195_dwmac_clk_l, .num_clks = ARRAY_SIZE(mt8195_dwmac_clk_l), .dma_bit_mask = 35, @@ -619,8 +595,6 @@ static int mediatek_dwmac_common_data(struct platform_device *pdev, plat->bsp_priv = priv_plat; plat->init = mediatek_dwmac_init; plat->clks_config = mediatek_dwmac_clks_config; - if (priv_plat->variant->dwmac_fix_mac_speed) - plat->fix_mac_speed = priv_plat->variant->dwmac_fix_mac_speed; plat->safety_feat_cfg = devm_kzalloc(&pdev->dev, sizeof(*plat->safety_feat_cfg), From patchwork Wed Dec 28 06:33:30 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?QmlhbyBIdWFuZyAo6buE5b2qKQ==?= X-Patchwork-Id: 37115 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4e01:0:0:0:0:0 with SMTP id p1csp1746133wrt; Tue, 27 Dec 2022 22:34:43 -0800 (PST) X-Google-Smtp-Source: AMrXdXurAgUifQYD1VQeBKmrZvNP2yoz4RSsLqUGbXWuewRY57PTngF46e0KoxnvNVt4OUBlxFbz X-Received: by 2002:a05:6a20:6701:b0:af:ac38:911b with SMTP id q1-20020a056a20670100b000afac38911bmr26073227pzh.21.1672209283198; Tue, 27 Dec 2022 22:34:43 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1672209283; cv=none; d=google.com; s=arc-20160816; b=YqauXdsMTn9W7FsSnW0ii5xfqMFn/sWPFYdFsc3S0TXXR7OwYWFvEKx+QxtSrUOzL7 zRfMHphniWEokxONsKBgmJzVyvdeGrU8XY44JfNksx5Zale12JhUZ8uRRpiXSWJduqng +9ADuvjYKdS8i3OGMGWB1NrjwZsVo4PN2iVgEhjcxawFaPasFQiRqZHpdsvh8bJS/zx8 SIwgrX865JiMDledxSaUgBUP8iPT2wuf3+334B9Eko7WVwm3FO+Q0ZMjmJMMLACPlj5l kE0VhGfpkrAngdq1ETvNneZiONorbcQa1emywihKZ+2wyHpgzJ2dF6w6Cl+C/kpDJ8Mv grRQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=jeiiqoqKwFie5MQ4rjQcD5M4/OBETmdj8o2F7jlFF4Q=; b=ZwLt32UdoixJsKX1x40W9bGJaXd45N24Kql4edWCftUzITS+umXrs4rsEs096HpDJW zPprLkQ54ydFDBreWapYmzp5TmHqFcaMqAWFIw/IRI3ibpIs+IypT1H8vLoyEIfqY/1/ +8YP8J0DZu5xwoOUdSmlxd81ZcCKLKNHPBA+gqU+/ahW2ExLv6Tml1QbvQLrQOP6oyF4 gK9MLTugjMd5eWx4WrwX9oI4E8rGcy+XrH83sg11raISvbHpIUmGOtZBrmqgP+CM+BwQ 7kYrkooiKfqLfzwTOpge67rEnNS9a49bYLQAzcbmZWqO26L9JIw9IZwlNm33SoxHEFTj cgOA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@mediatek.com header.s=dk header.b=M4vxxtKv; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=mediatek.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id t63-20020a637842000000b004820625f0cdsi16538237pgc.689.2022.12.27.22.34.31; Tue, 27 Dec 2022 22:34:43 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@mediatek.com header.s=dk header.b=M4vxxtKv; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=mediatek.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230136AbiL1Gdw (ORCPT + 99 others); Wed, 28 Dec 2022 01:33:52 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40082 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229632AbiL1Gdq (ORCPT ); Wed, 28 Dec 2022 01:33:46 -0500 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1459DDF1C; Tue, 27 Dec 2022 22:33:44 -0800 (PST) X-UUID: f71a861c257445f7b3c5f43973b02622-20221228 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=jeiiqoqKwFie5MQ4rjQcD5M4/OBETmdj8o2F7jlFF4Q=; b=M4vxxtKvlnEgukVfj7+dNcWRkuPUbggL6Rv+9vnkEhE749tPTGQZVLuwAlULXrIqo6agAtoTIAvYEf1j9hF1Hotzm5iRrP0XUlSp48jt8DRtpZoihoLVWcMAYWF76sKftPEmCZOWMyBJ8lu7v94b37Nlj8cZoRPqZHcYFEK7i2s=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.14,REQID:650d08c7-be76-463d-b2fd-112b7f675618,IP:0,U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:95,FILE:0,BULK:0,RULE:Release_Ham,ACTION :release,TS:95 X-CID-INFO: VERSION:1.1.14,REQID:650d08c7-be76-463d-b2fd-112b7f675618,IP:0,URL :0,TC:0,Content:0,EDM:0,RT:0,SF:95,FILE:0,BULK:0,RULE:Spam_GS981B3D,ACTION :quarantine,TS:95 X-CID-META: VersionHash:dcaaed0,CLOUDID:689c0053-dd49-462e-a4be-2143a3ddc739,B ulkID:221228143340FL0QRH0H,BulkQuantity:0,Recheck:0,SF:38|28|17|19|48,TC:n il,Content:0,EDM:-3,IP:nil,URL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0 X-UUID: f71a861c257445f7b3c5f43973b02622-20221228 Received: from mtkmbs10n1.mediatek.inc [(172.21.101.34)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 548425063; Wed, 28 Dec 2022 14:33:37 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.186) by mtkmbs13n2.mediatek.inc (172.21.101.108) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Wed, 28 Dec 2022 14:33:36 +0800 Received: from localhost.localdomain (10.17.3.154) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Wed, 28 Dec 2022 14:33:35 +0800 From: Biao Huang To: Andrew Lunn , AngeloGioacchino Del Regno , Rob Herring , Krzysztof Kozlowski , Matthias Brugger CC: Giuseppe Cavallaro , Alexandre Torgue , Jose Abreu , "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Maxime Coquelin , Richard Cochran , , , , , Biao Huang , Subject: [PATCH v6 2/2] arm64: dts: mt8195: Add Ethernet controller Date: Wed, 28 Dec 2022 14:33:30 +0800 Message-ID: <20221228063331.10756-3-biao.huang@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221228063331.10756-1-biao.huang@mediatek.com> References: <20221228063331.10756-1-biao.huang@mediatek.com> MIME-Version: 1.0 X-MTK: N X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS, SPF_PASS,UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1752967921521951433?= X-GMAIL-MSGID: =?utf-8?q?1753438521531138842?= Add Ethernet controller node for mt8195. Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Biao Huang --- arch/arm64/boot/dts/mediatek/mt8195-demo.dts | 81 ++++++++++++++++++ arch/arm64/boot/dts/mediatek/mt8195.dtsi | 86 ++++++++++++++++++++ 2 files changed, 167 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8195-demo.dts b/arch/arm64/boot/dts/mediatek/mt8195-demo.dts index 4fbd99eb496a..2e6979c47aa6 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195-demo.dts +++ b/arch/arm64/boot/dts/mediatek/mt8195-demo.dts @@ -258,6 +258,66 @@ &mt6359_vsram_others_ldo_reg { }; &pio { + eth_default_pins: eth-default-pins { + pins-txd { + pinmux = , + , + , + ; + drive-strength = ; + }; + pins-cc { + pinmux = , + , + , + ; + drive-strength = ; + }; + pins-rxd { + pinmux = , + , + , + ; + }; + pins-mdio { + pinmux = , + ; + input-enable; + }; + pins-power { + pinmux = , + ; + output-high; + }; + }; + + eth_sleep_pins: eth-sleep-pins { + pins-txd { + pinmux = , + , + , + ; + }; + pins-cc { + pinmux = , + , + , + ; + }; + pins-rxd { + pinmux = , + , + , + ; + }; + pins-mdio { + pinmux = , + ; + input-disable; + bias-disable; + }; + }; + gpio_keys_pins: gpio-keys-pins { pins { pinmux = ; @@ -434,6 +494,27 @@ &xhci0 { status = "okay"; }; +ð { + phy-mode ="rgmii-id"; + phy-handle = <ðernet_phy0>; + snps,reset-gpio = <&pio 93 GPIO_ACTIVE_HIGH>; + snps,reset-delays-us = <0 10000 10000>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <ð_default_pins>; + pinctrl-1 = <ð_sleep_pins>; + status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + ethernet_phy0: ethernet-phy@1 { + compatible = "ethernet-phy-id001c.c916"; + reg = <0x1>; + }; + }; +}; + &xhci1 { vusb33-supply = <&mt6359_vusb_ldo_reg>; status = "okay"; diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi index 5d31536f4c48..b90d38d87aa4 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -1046,6 +1046,92 @@ spis1: spi@1101e000 { status = "disabled"; }; + eth: ethernet@11021000 { + compatible = "mediatek,mt8195-gmac", "snps,dwmac-5.10a"; + reg = <0 0x11021000 0 0x4000>; + interrupts = ; + interrupt-names = "macirq"; + clock-names = "axi", + "apb", + "mac_main", + "ptp_ref", + "rmii_internal", + "mac_cg"; + clocks = <&pericfg_ao CLK_PERI_AO_ETHERNET>, + <&pericfg_ao CLK_PERI_AO_ETHERNET_BUS>, + <&topckgen CLK_TOP_SNPS_ETH_250M>, + <&topckgen CLK_TOP_SNPS_ETH_62P4M_PTP>, + <&topckgen CLK_TOP_SNPS_ETH_50M_RMII>, + <&pericfg_ao CLK_PERI_AO_ETHERNET_MAC>; + assigned-clocks = <&topckgen CLK_TOP_SNPS_ETH_250M>, + <&topckgen CLK_TOP_SNPS_ETH_62P4M_PTP>, + <&topckgen CLK_TOP_SNPS_ETH_50M_RMII>; + assigned-clock-parents = <&topckgen CLK_TOP_ETHPLL_D2>, + <&topckgen CLK_TOP_ETHPLL_D8>, + <&topckgen CLK_TOP_ETHPLL_D10>; + power-domains = <&spm MT8195_POWER_DOMAIN_ETHER>; + mediatek,pericfg = <&infracfg_ao>; + snps,axi-config = <&stmmac_axi_setup>; + snps,mtl-rx-config = <&mtl_rx_setup>; + snps,mtl-tx-config = <&mtl_tx_setup>; + snps,txpbl = <16>; + snps,rxpbl = <16>; + snps,clk-csr = <0>; + status = "disabled"; + + stmmac_axi_setup: stmmac-axi-config { + snps,wr_osr_lmt = <0x7>; + snps,rd_osr_lmt = <0x7>; + snps,blen = <0 0 0 0 16 8 4>; + }; + + mtl_rx_setup: rx-queues-config { + snps,rx-queues-to-use = <4>; + snps,rx-sched-sp; + queue0 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x0>; + }; + queue1 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x0>; + }; + queue2 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x0>; + }; + queue3 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x0>; + }; + }; + + mtl_tx_setup: tx-queues-config { + snps,tx-queues-to-use = <4>; + snps,tx-sched-wrr; + queue0 { + snps,weight = <0x10>; + snps,dcb-algorithm; + snps,priority = <0x0>; + }; + queue1 { + snps,weight = <0x11>; + snps,dcb-algorithm; + snps,priority = <0x1>; + }; + queue2 { + snps,weight = <0x12>; + snps,dcb-algorithm; + snps,priority = <0x2>; + }; + queue3 { + snps,weight = <0x13>; + snps,dcb-algorithm; + snps,priority = <0x3>; + }; + }; + }; + xhci0: usb@11200000 { compatible = "mediatek,mt8195-xhci", "mediatek,mtk-xhci";