From patchwork Tue Dec 27 19:23:35 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ashok Raj X-Patchwork-Id: 36984 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4e01:0:0:0:0:0 with SMTP id p1csp1544102wrt; Tue, 27 Dec 2022 11:24:42 -0800 (PST) X-Google-Smtp-Source: AMrXdXtNfq3WvGqwSBPwrqWfmmzFZOerYPiMXWaC9SD7ZlvfO1hdX/sFLPOyP1DkifwC+klN4OBa X-Received: by 2002:a05:6a20:7d89:b0:af:ae01:547a with SMTP id v9-20020a056a207d8900b000afae01547amr35989260pzj.20.1672169082605; Tue, 27 Dec 2022 11:24:42 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1672169082; cv=none; d=google.com; s=arc-20160816; b=DhOBH6gl2kqe585sjpNDt22s2h33ke4aTEHegXymmx6UVFrjqoD3w/D60jDXvaqQO4 GXVcNHZjo7MdSwbIZUr5oMaXr8mJAXWAshnmfSkjt7yCbfSgSIdd3DcRLByIUEprxNqq DSYjggel1vRiy1REGasygB164D7NqKbyroOFxlDg6ykH0N5UU6e8ui9l2gUUwAMVhEs+ Q8fdsn2+CQj7P58H8eMmiaWQ3NOREe7WdF9khBoO3YPYeU460M0xWX1EQ46wyeaRssYM QY6QBxVmmoqPngMPE0wRmaET6fkGsNg/9z3eal5mxBWNAy0Pwxea/oh+IOIyVon3HTpP 7nnw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=NtZ6C+CGMpIbEj/7+mbp7g4PjUd8LaIvex3dLZfPEV0=; b=t6vRuPMb0D5Kjr3MTOsh8aWW9JUl1KKUHoTevO1B6gVaNSHQpjmzR4cpXMJj33cttj wDPmy3HQI+Yp40I1vZvKAYbqaonhQOiMw1210P1/7TMCkO5TqMu4RLT64KTYSV4q7ydh 1dcYUC2YzT/mZc7w1EahhQOX1Ncm6xkawu8nd13vJlYZIPyHvOLmGSYQEluAOeAThl8M eKLAuVMrq9CVwh2JwGnCzTBtomj6lj9HujdpP8zlvjnu/RGEuD+egvO+laOGeJB+9EUH Pm8VpzON+DALEPw4Z9q1O9ZU+syNht3G2LmysB8h+1/S1L7/+pHjCTr3oPfb5SYBZzps U38Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=LrkODz25; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id k75-20020a636f4e000000b0043adff6d43dsi15129627pgc.583.2022.12.27.11.24.30; Tue, 27 Dec 2022 11:24:42 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=LrkODz25; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231691AbiL0TYR (ORCPT + 99 others); Tue, 27 Dec 2022 14:24:17 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44936 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230037AbiL0TX5 (ORCPT ); Tue, 27 Dec 2022 14:23:57 -0500 Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7CE4A7666 for ; Tue, 27 Dec 2022 11:23:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1672169036; x=1703705036; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=AkG2Hj1V9FOORMr1pc5kfG9A0Vq/BVt3h5MQvlr7sgw=; b=LrkODz25ghcqg4twwF7/7Wk/gaRrMlh3YETlc0E6gdPu36p0PuANPFkG VKwAKOM3g1uwzjSD+kVLXviWXjR0Xu9oQCJFyRDHXhfZkSbgw0HN2wryg Uqh/0SlRTIts+arFKQjM5ekEQHZzRY18zIFjHIisVxt9N3RmfTBZnWgow U99c6wiusDTGNfI4p7F/63VppoUgCPoBUwD+xikZFb6S00zb7EYlg1IoR 16/VvIFZwcqluHgGgiDpXV02EYp4h4MA7RqC2ub7b30bo9pmBJOgVs8Ls vB0apBjUrennE1xOUJeYCrCc/Zg/lRAYZ1MFkUQZ5dOXQCjeHAX92W9Qy A==; X-IronPort-AV: E=McAfee;i="6500,9779,10573"; a="407011175" X-IronPort-AV: E=Sophos;i="5.96,279,1665471600"; d="scan'208";a="407011175" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Dec 2022 11:23:55 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10573"; a="777234199" X-IronPort-AV: E=Sophos;i="5.96,279,1665471600"; d="scan'208";a="777234199" Received: from araj-ucode.jf.intel.com ([10.23.0.19]) by orsmga004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Dec 2022 11:23:54 -0800 From: Ashok Raj To: Borislav Petkov , Thomas Gleixner Cc: X86-kernel , LKML Mailing List , Ashok Raj , Dave Hansen , Tony Luck , Alison Schofield , Reinette Chatre , Tom Lendacky Subject: [PATCH v2 1/6] x86/microcode/core: Move microcode_check() to cpu/microcode/core.c Date: Tue, 27 Dec 2022 11:23:35 -0800 Message-Id: <20221227192340.8358-2-ashok.raj@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221227192340.8358-1-ashok.raj@intel.com> References: <20221227192340.8358-1-ashok.raj@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1753396367808300360?= X-GMAIL-MSGID: =?utf-8?q?1753396367808300360?= microcode_check() is only called from microcode/core.c. Move it and make it static to prepare for upcoming fix for false negative when checking CPU features after a microcode update. Also move get_cpu_cap() to processor.h for general use outside of arch/x86/kernel/cpu/cpu.h No functional change. Suggested-by: Alison Schofield Signed-off-by: Ashok Raj Reviewed-by: Thomas Gleixner Cc: LKML Cc: x86 Cc: Tony Luck Cc: Dave Hansen Cc: Alison Schofield Cc: Reinette Chatre Cc: Thomas Gleixner Cc: Tom Lendacky --- arch/x86/include/asm/processor.h | 3 +-- arch/x86/kernel/cpu/cpu.h | 1 - arch/x86/kernel/cpu/common.c | 32 ---------------------------- arch/x86/kernel/cpu/microcode/core.c | 31 +++++++++++++++++++++++++++ 4 files changed, 32 insertions(+), 35 deletions(-) diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/processor.h index 4e35c66edeb7..70d01ecc39a4 100644 --- a/arch/x86/include/asm/processor.h +++ b/arch/x86/include/asm/processor.h @@ -182,8 +182,8 @@ extern const struct seq_operations cpuinfo_op; #define cache_line_size() (boot_cpu_data.x86_cache_alignment) +extern void get_cpu_cap(struct cpuinfo_x86 *c); extern void cpu_detect(struct cpuinfo_x86 *c); - static inline unsigned long long l1tf_pfn_limit(void) { return BIT_ULL(boot_cpu_data.x86_cache_bits - 1 - PAGE_SHIFT); @@ -697,7 +697,6 @@ bool xen_set_default_idle(void); #endif void __noreturn stop_this_cpu(void *dummy); -void microcode_check(void); enum l1tf_mitigations { L1TF_MITIGATION_OFF, diff --git a/arch/x86/kernel/cpu/cpu.h b/arch/x86/kernel/cpu/cpu.h index 7c9b5893c30a..a142b8d543a3 100644 --- a/arch/x86/kernel/cpu/cpu.h +++ b/arch/x86/kernel/cpu/cpu.h @@ -63,7 +63,6 @@ static inline void tsx_ap_init(void) { } extern void init_spectral_chicken(struct cpuinfo_x86 *c); -extern void get_cpu_cap(struct cpuinfo_x86 *c); extern void get_cpu_address_sizes(struct cpuinfo_x86 *c); extern void cpu_detect_cache_sizes(struct cpuinfo_x86 *c); extern void init_scattered_cpuid_features(struct cpuinfo_x86 *c); diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c index 9cfca3d7d0e2..7b06034eeddc 100644 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -2296,38 +2296,6 @@ void cpu_init_secondary(void) } #endif -#ifdef CONFIG_MICROCODE_LATE_LOADING -/* - * The microcode loader calls this upon late microcode load to recheck features, - * only when microcode has been updated. Caller holds microcode_mutex and CPU - * hotplug lock. - */ -void microcode_check(void) -{ - struct cpuinfo_x86 info; - - perf_check_microcode(); - - /* Reload CPUID max function as it might've changed. */ - info.cpuid_level = cpuid_eax(0); - - /* - * Copy all capability leafs to pick up the synthetic ones so that - * memcmp() below doesn't fail on that. The ones coming from CPUID will - * get overwritten in get_cpu_cap(). - */ - memcpy(&info.x86_capability, &boot_cpu_data.x86_capability, sizeof(info.x86_capability)); - - get_cpu_cap(&info); - - if (!memcmp(&info.x86_capability, &boot_cpu_data.x86_capability, sizeof(info.x86_capability))) - return; - - pr_warn("x86/CPU: CPU features have changed after loading microcode, but might not take effect.\n"); - pr_warn("x86/CPU: Please consider either early loading through initrd/built-in or a potential BIOS update.\n"); -} -#endif - /* * Invoked from core CPU hotplug code after hotplug operations */ diff --git a/arch/x86/kernel/cpu/microcode/core.c b/arch/x86/kernel/cpu/microcode/core.c index c4cd7328177b..0051ebf7c53e 100644 --- a/arch/x86/kernel/cpu/microcode/core.c +++ b/arch/x86/kernel/cpu/microcode/core.c @@ -432,6 +432,37 @@ static int __reload_late(void *info) return ret; } +/* + * The microcode loader calls this upon late microcode load to recheck features, + * only when microcode has been updated. Caller holds microcode_mutex and CPU + * hotplug lock. + */ +static void microcode_check(void) +{ + struct cpuinfo_x86 info; + + perf_check_microcode(); + + /* Reload CPUID max function as it might've changed. */ + info.cpuid_level = cpuid_eax(0); + + /* + * Copy all capability leafs to pick up the synthetic ones so that + * memcmp() below doesn't fail on that. The ones coming from CPUID will + * get overwritten in get_cpu_cap(). + */ + memcpy(&info.x86_capability, &boot_cpu_data.x86_capability, sizeof(info.x86_capability)); + + get_cpu_cap(&info); + + if (!memcmp(&info.x86_capability, &boot_cpu_data.x86_capability, + sizeof(info.x86_capability))) + return; + + pr_warn("x86/CPU: CPU features have changed after loading microcode, but might not take effect.\n"); + pr_warn("x86/CPU: Please consider either early loading through initrd/built-in or a potential BIOS update.\n"); +} + /* * Reload microcode late on all CPUs. Wait for a sec until they * all gather together. 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[2620:137:e000::1:20]) by mx.google.com with ESMTP id 22-20020a630516000000b0046004666d82si15144089pgf.497.2022.12.27.11.24.14; Tue, 27 Dec 2022 11:24:34 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=OZVPXAt1; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231305AbiL0TYB (ORCPT + 99 others); Tue, 27 Dec 2022 14:24:01 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44926 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229488AbiL0TX4 (ORCPT ); Tue, 27 Dec 2022 14:23:56 -0500 Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9C6A27655 for ; Tue, 27 Dec 2022 11:23:55 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1672169035; x=1703705035; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=mmKFDsVIHTIc0c7YKddPATrNwY7UmiRaXdv65jV60NA=; b=OZVPXAt1n324jZ+5cnLuP1qxJkQgfwKmgYUfP+mMy9OwG+TKGQLRTt9v Ly3V76P2NDBWx94xPDedxO75pU0XBuGWhWVwDjxI6li1M7Wcpi+/3P5mU k4mmjPlZCo02LNMLxKIqx0j/SH7qSLcJ5ZnbimnoGB2dHMDWUkRUNkohr a2BzC9L5zGuqvjVlivpzGHnunlLAuTdtQn3Nb+/jN1vvanzpeYLlP2dr3 atWtg7+GqJDFAc4TWf4KAIFuwKlPMRit9Ylqp/wl5cz2emcRLb7HOT5d1 bum7TH5dLkXw18PpK5K6ofkccPtQuQ9JVXtB3eQtqTYspPOhyIaIBeDw8 w==; X-IronPort-AV: E=McAfee;i="6500,9779,10573"; a="407011166" X-IronPort-AV: E=Sophos;i="5.96,279,1665471600"; d="scan'208";a="407011166" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Dec 2022 11:23:54 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10573"; a="777234194" X-IronPort-AV: E=Sophos;i="5.96,279,1665471600"; d="scan'208";a="777234194" Received: from araj-ucode.jf.intel.com ([10.23.0.19]) by orsmga004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Dec 2022 11:23:54 -0800 From: Ashok Raj To: Borislav Petkov , Thomas Gleixner Cc: X86-kernel , LKML Mailing List , Ashok Raj , Dave Hansen , Tony Luck , Alison Schofield , Reinette Chatre , Tom Lendacky Subject: [PATCH v2 2/6] x86/microcode/core: Take a snapshot before and after applying microcode Date: Tue, 27 Dec 2022 11:23:36 -0800 Message-Id: <20221227192340.8358-3-ashok.raj@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221227192340.8358-1-ashok.raj@intel.com> References: <20221227192340.8358-1-ashok.raj@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1753396359197775479?= X-GMAIL-MSGID: =?utf-8?q?1753396359197775479?= The kernel caches features about each CPU's features at boot in an x86_capability[] structure. The microcode update takes one snapshot and compares it with the saved copy at boot. However, the capabilities in the boot copy can be turned off as a result of certain command line parameters or configuration restrictions. This can cause a mismatch when comparing the values before and after the microcode update. microcode_check() is called after an update to report any previously cached CPUID bits might have changed due to the update. store_cpu_caps() basically stores the original CPU reported values and not the OS modified values. This will avoid giving a false warning even if no capabilities have changed. Ignore the capabilities recorded at boot. Take a new snapshot before the update and compare with a snapshot after the update to eliminate the false warning. Fixes: 1008c52c09dc ("x86/CPU: Add a microcode loader callback") Signed-off-by: Ashok Raj Cc: LKML Cc: x86 Cc: Tony Luck Cc: Dave Hansen Cc: Alison Schofield Cc: Reinette Chatre Cc: Thomas Gleixner Cc: Tom Lendacky --- Changes since last post - Boris : Change function from copy_cpu_caps() -> store_cpu_caps() - Thomas : Commit log changes. --- arch/x86/kernel/cpu/microcode/core.c | 42 +++++++++++++++++++++------- 1 file changed, 32 insertions(+), 10 deletions(-) diff --git a/arch/x86/kernel/cpu/microcode/core.c b/arch/x86/kernel/cpu/microcode/core.c index 0051ebf7c53e..e2cdf3e989e7 100644 --- a/arch/x86/kernel/cpu/microcode/core.c +++ b/arch/x86/kernel/cpu/microcode/core.c @@ -432,12 +432,28 @@ static int __reload_late(void *info) return ret; } +static void store_cpu_caps(struct cpuinfo_x86 *info) +{ + /* Reload CPUID max function as it might've changed. */ + info->cpuid_level = cpuid_eax(0); + + /* + * Copy all capability leafs to pick up the synthetic ones so that + * memcmp() below doesn't fail on that. The ones coming from CPUID will + * get overwritten in get_cpu_cap(). + */ + memcpy(info->x86_capability, &boot_cpu_data.x86_capability, + sizeof(info->x86_capability)); + + get_cpu_cap(info); +} + /* * The microcode loader calls this upon late microcode load to recheck features, * only when microcode has been updated. Caller holds microcode_mutex and CPU * hotplug lock. */ -static void microcode_check(void) +static void microcode_check(struct cpuinfo_x86 *orig) { struct cpuinfo_x86 info; @@ -447,15 +463,13 @@ static void microcode_check(void) info.cpuid_level = cpuid_eax(0); /* - * Copy all capability leafs to pick up the synthetic ones so that - * memcmp() below doesn't fail on that. The ones coming from CPUID will - * get overwritten in get_cpu_cap(). - */ - memcpy(&info.x86_capability, &boot_cpu_data.x86_capability, sizeof(info.x86_capability)); + * Copy all capability leafs to pick up the synthetic ones so that + * memcmp() below doesn't fail on that. The ones coming from CPUID will + * get overwritten in get_cpu_cap(). + */ + store_cpu_caps(&info); - get_cpu_cap(&info); - - if (!memcmp(&info.x86_capability, &boot_cpu_data.x86_capability, + if (!memcmp(&info.x86_capability, &orig->x86_capability, sizeof(info.x86_capability))) return; @@ -470,6 +484,7 @@ static void microcode_check(void) static int microcode_reload_late(void) { int old = boot_cpu_data.microcode, ret; + struct cpuinfo_x86 info; pr_err("Attempting late microcode loading - it is dangerous and taints the kernel.\n"); pr_err("You should switch to early loading, if possible.\n"); @@ -477,9 +492,16 @@ static int microcode_reload_late(void) atomic_set(&late_cpus_in, 0); atomic_set(&late_cpus_out, 0); + /* + * Take a snapshot before the microcode update, so we can compare + * them after the update is successful to check for any bits + * changed. + */ + store_cpu_caps(&info); + ret = stop_machine_cpuslocked(__reload_late, NULL, cpu_online_mask); if (ret == 0) - microcode_check(); + microcode_check(&info); pr_info("Reload completed, microcode revision: 0x%x -> 0x%x\n", old, boot_cpu_data.microcode); From patchwork Tue Dec 27 19:23:37 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ashok Raj X-Patchwork-Id: 36983 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4e01:0:0:0:0:0 with SMTP id p1csp1544059wrt; Tue, 27 Dec 2022 11:24:35 -0800 (PST) X-Google-Smtp-Source: AMrXdXud12uWtl7mW7PfCFMhRoOak97H+/W6vwJ6FnbYYDL7ZK3EHYBGAOnD90Nb+Ca6kjdyc4eW X-Received: by 2002:a17:903:2411:b0:192:7518:af94 with SMTP id e17-20020a170903241100b001927518af94mr9345438plo.27.1672169074891; Tue, 27 Dec 2022 11:24:34 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1672169074; cv=none; d=google.com; s=arc-20160816; b=cLkRJrKJHgPFYOVPI5DcUe1lG7YiqIJaQ2/JnQNltoxMjDX+z/tVLCvxXGBnqM5sBI TZfDoV65l4hrUecrNmHtkz74DdZkvRBGYFSsTXPT8f/HV2gHTsdiFB2ApLy+FCkLdamX QRrAC158NTpdHja5Ujfai7NIZYd7UbX86oBQa7T2+iCJRTHNFppswAhbESeGZGi1aOLe HStVUPePRBPBFMTSD0SQzjvTF8HcjJkmIoAs4uq6rfKlEU3o5UVPzrXCbTCyIbkvEEXY 7WT5b4iPdIC+KkckWXOLnaqGQsvX2EGy08lyhHJGowgZNdrtThmuC5WFDQ7POf+mCQN1 x0Iw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=Gkv4dd8mAPNi3Cg4hJ7Qm1SqnENbB7CFqAiGohkZcu8=; b=l/OgED2YWHG6gLHgnXImGiauVvia3Gif41eEHwDo6p0M2KRl3MCSUHfwr6o1S4juH9 7nDrmu2dfjNWBus5IHffgCJQ1NRpqi0tKHJYWWqsE1dqTPgrPqDU4ihejiQTLuwwJ1TJ ZW0aVTQJzaH9Q2C9DF61+/Murr1Ld9fYFRo6COloSqPpha+zizM60IVboCFBGqLBAX8X XX/81i/5dcBboB31jOScekhXwvPo9FCb5ipv0eOZ++4tF7pqTpBucW97yOLYRKgpSXV6 h/up1qjKmdNvlbqTbLA1Kga35L6GbCJCitYLqspZuuUNJTzRSIy+cMSGTuk1ADk2wTpu l5Kg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=jznyb4w5; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id x4-20020a170902ec8400b0018997e90c80si15795910plg.275.2022.12.27.11.24.21; Tue, 27 Dec 2022 11:24:34 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=jznyb4w5; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231426AbiL0TYE (ORCPT + 99 others); Tue, 27 Dec 2022 14:24:04 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44926 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230410AbiL0TX5 (ORCPT ); Tue, 27 Dec 2022 14:23:57 -0500 Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5D0576572 for ; Tue, 27 Dec 2022 11:23:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1672169036; x=1703705036; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=RGIUoDUWMennNq2BZ7d/bh2PdiZqgI1/L+XCRzyCHqE=; b=jznyb4w5iIJ2SmzUetS3e6lPFSMafkRTHLlThFjWn9ilcA0f6mcXvWVZ ne4c4yVSV8DByxod4vXd7+htqwyCNzFbfsjtYk81WSzQR2r/DrII/rkhf eJ+1JrtUVXe2OQciWt+3v0oFrlkAV+4wXjBDTzqOg6y6NQgDR3hXqHdaN UFWhS0VVjxtBptH8R7XH9N7NLTo8L2+1bST21NEBesg41N2aZLVyxdcA6 x6jfJelQ8KDjGphrPBuMhGZf8p2PFSkellTzsXXxfM13HvK68l5SKCFnG MD0mtaSRZYJizFWlhqjDBO8QXEDYfZVEncK5Ps2SO1ZuqrUBEr2nrNeqU w==; X-IronPort-AV: E=McAfee;i="6500,9779,10573"; a="407011170" X-IronPort-AV: E=Sophos;i="5.96,279,1665471600"; d="scan'208";a="407011170" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Dec 2022 11:23:54 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10573"; a="777234197" X-IronPort-AV: E=Sophos;i="5.96,279,1665471600"; d="scan'208";a="777234197" Received: from araj-ucode.jf.intel.com ([10.23.0.19]) by orsmga004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Dec 2022 11:23:54 -0800 From: Ashok Raj To: Borislav Petkov , Thomas Gleixner Cc: X86-kernel , LKML Mailing List , Ashok Raj , Dave Hansen , Tony Luck , Alison Schofield , Reinette Chatre , Tom Lendacky Subject: [PATCH v2 3/6] x86/microcode: Display revisions only when update is successful Date: Tue, 27 Dec 2022 11:23:37 -0800 Message-Id: <20221227192340.8358-4-ashok.raj@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221227192340.8358-1-ashok.raj@intel.com> References: <20221227192340.8358-1-ashok.raj@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1753396359939930032?= X-GMAIL-MSGID: =?utf-8?q?1753396359939930032?= Right now, microcode loading failures and successes print the same message "Reloading completed". This is misleading to users. Display the updated revision number only if an update was successful. Suggested-by: Thomas Gleixner Signed-off-by: Ashok Raj Reviewed-by: Tony Luck Link: https://lore.kernel.org/lkml/874judpqqd.ffs@tglx/ Cc: LKML Cc: x86 Cc: Tony Luck Cc: Dave Hansen Cc: Alison Schofield Cc: Reinette Chatre Cc: Thomas Gleixner Cc: Tom Lendacky --- arch/x86/kernel/cpu/microcode/core.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/arch/x86/kernel/cpu/microcode/core.c b/arch/x86/kernel/cpu/microcode/core.c index e2cdf3e989e7..e60cf0f66bf5 100644 --- a/arch/x86/kernel/cpu/microcode/core.c +++ b/arch/x86/kernel/cpu/microcode/core.c @@ -500,11 +500,12 @@ static int microcode_reload_late(void) store_cpu_caps(&info); ret = stop_machine_cpuslocked(__reload_late, NULL, cpu_online_mask); - if (ret == 0) - microcode_check(&info); - pr_info("Reload completed, microcode revision: 0x%x -> 0x%x\n", - old, boot_cpu_data.microcode); + if (ret == 0) { + pr_info("Reload completed, microcode revision: 0x%x -> 0x%x\n", + old, boot_cpu_data.microcode); + microcode_check(&info); + } return ret; } From patchwork Tue Dec 27 19:23:38 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ashok Raj X-Patchwork-Id: 36985 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4e01:0:0:0:0:0 with SMTP id p1csp1544128wrt; Tue, 27 Dec 2022 11:24:47 -0800 (PST) X-Google-Smtp-Source: AMrXdXt8w140XjoJE1Mipqpr9GdfXrMMgRv8mdj0C1Dc+VHXs8P+5v3+ZgyDPMt/7ZKwBqnCrQ2i X-Received: by 2002:a17:90a:9a86:b0:226:1537:f0c7 with SMTP id e6-20020a17090a9a8600b002261537f0c7mr2033695pjp.11.1672169087189; Tue, 27 Dec 2022 11:24:47 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1672169087; cv=none; d=google.com; s=arc-20160816; b=ZJjAi1w/CtL1Nz/n99cMNSDBOzpZ0voz5017qdzHCEAr7SZQM7NWErWAmLh56EzKJM WS1V+umcVh7CfyoclUq9W72vyxpbNVBxIEWzv1/6jbcYBF9rCYfBpSTfY4/GxSeR1OGO qNRpBH2pw38lF74RuM/zoMm8IKXhEoD/uJ2RBOi/4cYUpEGg+xUZqq5ScPEEdDcgdP4c 9kfIV1MTipjAhSAJSQ0RrGe7Op+y8zH44HT69+avw2QWkgJ60BqRD166qIg0Fh2hPZHk JESTAOm16urqvSNmfoMxdcU7xaiK4fkujDBeWyN0UUnFdVoa1/5IITQCFsr80uI43Jb1 RvMQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=Wj9SnnoW3+QUsrElLaCSEx+KtaocMDLeXkG5A6cBpZI=; b=0p4+DMu5QIBXVaC2BXE5Pp1ZXWtce09NP52B5i7axHpQVVxOu14dYeNSSGqf2SuJyD rugiD2w1I+x7pIEfCzAcqBCyqWstMVJ4Mzb1f4rNfkWKHzNwL3ZXJUa+ySFAE4gnypld qvwf/JpEhzNPFnYa3P9vWGva6JQmPoCBgR+Ms+fnhLqovouB/SjjRR3y1cb52UX8f/dO dKGp1HJ1dK0Sfx7U3tK4EqC2ljD/g5JWrLSvQJ2OHQRt5a/Yw9nlZfIs0R0qufayb0eR +OnVb/R45o/mlLSWRB93MlQBH1iC9Zp8w9H61dqceHLzc/RvCIbJYvqiLLv/fZKUDFrL AiUQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=VvADsats; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id ob3-20020a17090b390300b00205f1a25a31si15280945pjb.161.2022.12.27.11.24.35; Tue, 27 Dec 2022 11:24:47 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=VvADsats; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231468AbiL0TY0 (ORCPT + 99 others); Tue, 27 Dec 2022 14:24:26 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44950 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230475AbiL0TX5 (ORCPT ); Tue, 27 Dec 2022 14:23:57 -0500 Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0CBF5D4C for ; Tue, 27 Dec 2022 11:23:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1672169037; x=1703705037; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=lzIse4ZWwsUKwU2q15GNya0zg7eYgzn0naky1H7IqGc=; b=VvADsatsO0DSVDGTQ1c6Ag448IxZWYu+ued11wSh4qteom7PAxpCW9cJ HTlVZyQezER5TOKJ6+kz3DspNLBbpk2syr9AoQA1vfAzywJBRcnxKCiSP uFSxsFzuAGJTBEFNPjyjoBBdqhHr/opDlzLKnmgOJnn1DDRGg4KVMq/wJ YY4FXC/MUNxgRe0zCrOtm5VJna8MnMuVBLZlzucCKhtVw+e8SjP2K8//P sRTnTsQHVKYHFUdRJwxsA/2m/bSFBAaCypU0QIo9MHYhKLn2SZ2Vrm8yG NLW/xKVbf1fXOG9dAvYsNosvNsJ6v11AdSWz7gWl1zh6BfgMqHYDSSbnp w==; X-IronPort-AV: E=McAfee;i="6500,9779,10573"; a="407011180" X-IronPort-AV: E=Sophos;i="5.96,279,1665471600"; d="scan'208";a="407011180" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Dec 2022 11:23:55 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10573"; a="777234201" X-IronPort-AV: E=Sophos;i="5.96,279,1665471600"; d="scan'208";a="777234201" Received: from araj-ucode.jf.intel.com ([10.23.0.19]) by orsmga004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Dec 2022 11:23:54 -0800 From: Ashok Raj To: Borislav Petkov , Thomas Gleixner Cc: X86-kernel , LKML Mailing List , Ashok Raj , Dave Hansen , Tony Luck , Alison Schofield , Reinette Chatre , Tom Lendacky Subject: [PATCH v2 4/6] x86/microcode/intel: Use a plain revision argument for print_ucode_rev() Date: Tue, 27 Dec 2022 11:23:38 -0800 Message-Id: <20221227192340.8358-5-ashok.raj@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221227192340.8358-1-ashok.raj@intel.com> References: <20221227192340.8358-1-ashok.raj@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1753396372719364720?= X-GMAIL-MSGID: =?utf-8?q?1753396372719364720?= print_ucode_rev() takes a struct ucode_cpu_info argument. The sole purpose of it is to print the microcode revision. The only available ucode_cpu_info always describes the currently loaded microcode revision. After a microcode update is successful, this is the new revision, or on failure it is the original revision. Subsequent changes need to print both the original and new revision, but the original version will be cached in a plain integer, which makes the code inconsistent. Replace the struct ucode_cpu_info argument with a plain integer which contains the revision number and adjust the call sites accordingly. No functional change. Signed-off-by: Ashok Raj Reviewed-by: Thomas Gleixner Cc: LKML Cc: x86 Cc: Tony Luck Cc: Dave Hansen Cc: Alison Schofield Cc: Reinette Chatre Cc: Thomas Gleixner Cc: Tom Lendacky --- Changes since earlier post. Thomas: - Updated commit log as suggested - Remove the line break after static void before print_ucode_info --- arch/x86/kernel/cpu/microcode/intel.c | 31 ++++++++------------------- 1 file changed, 9 insertions(+), 22 deletions(-) diff --git a/arch/x86/kernel/cpu/microcode/intel.c b/arch/x86/kernel/cpu/microcode/intel.c index 6bebc46ad8b1..1d709b72cfd0 100644 --- a/arch/x86/kernel/cpu/microcode/intel.c +++ b/arch/x86/kernel/cpu/microcode/intel.c @@ -310,13 +310,10 @@ static bool load_builtin_intel_microcode(struct cpio_data *cp) /* * Print ucode update info. */ -static void -print_ucode_info(struct ucode_cpu_info *uci, unsigned int date) +static void print_ucode_info(unsigned int new_rev, unsigned int date) { pr_info_once("microcode updated early to revision 0x%x, date = %04x-%02x-%02x\n", - uci->cpu_sig.rev, - date & 0xffff, - date >> 24, + new_rev, date & 0xffff, date >> 24, (date >> 16) & 0xff); } @@ -334,7 +331,7 @@ void show_ucode_info_early(void) if (delay_ucode_info) { intel_cpu_collect_info(&uci); - print_ucode_info(&uci, current_mc_date); + print_ucode_info(uci.cpu_sig.rev. current_mc_date); delay_ucode_info = 0; } } @@ -343,33 +340,23 @@ void show_ucode_info_early(void) * At this point, we can not call printk() yet. Delay printing microcode info in * show_ucode_info_early() until printk() works. */ -static void print_ucode(struct ucode_cpu_info *uci) +static void print_ucode(int new_rev, int date) { struct microcode_intel *mc; int *delay_ucode_info_p; int *current_mc_date_p; - mc = uci->mc; - if (!mc) - return; - delay_ucode_info_p = (int *)__pa_nodebug(&delay_ucode_info); current_mc_date_p = (int *)__pa_nodebug(¤t_mc_date); *delay_ucode_info_p = 1; - *current_mc_date_p = mc->hdr.date; + *current_mc_date_p = date; } #else -static inline void print_ucode(struct ucode_cpu_info *uci) +static inline void print_ucode(int new_rev, int date) { - struct microcode_intel *mc; - - mc = uci->mc; - if (!mc) - return; - - print_ucode_info(uci, mc->hdr.date); + print_ucode_info(new_rev, date); } #endif @@ -409,9 +396,9 @@ static int apply_microcode_early(struct ucode_cpu_info *uci, bool early) uci->cpu_sig.rev = rev; if (early) - print_ucode(uci); + print_ucode(uci->cpu_sig.rev, mc->hdr.date); else - print_ucode_info(uci, mc->hdr.date); + print_ucode_info(uci->cpu_sig.rev, mc->hdr.date); return 0; } From patchwork Tue Dec 27 19:23:39 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ashok Raj X-Patchwork-Id: 36987 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4e01:0:0:0:0:0 with SMTP id p1csp1544180wrt; Tue, 27 Dec 2022 11:25:00 -0800 (PST) X-Google-Smtp-Source: AMrXdXsLFYXjM260IXyasofcN6s30jDAf4Y5/E4DgmQ7x3vMTBrjwE2UENGx3/IGsk1RZYDgNWtD X-Received: by 2002:a17:903:2c2:b0:189:c8d9:ed30 with SMTP id s2-20020a17090302c200b00189c8d9ed30mr22392819plk.24.1672169099894; Tue, 27 Dec 2022 11:24:59 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1672169099; cv=none; d=google.com; s=arc-20160816; b=Fwswpu4RoeoA0GSJx3D1T1x5wQ5CSCc5WGot4xgqQhXOnLH3Rt7dXbIWvn9/gt1U3+ y91W74TUfjZSW6/3zRjUZwmvf9FU7r+HmqNWCPoNAVw+qYXLG52VEcbMrwcU6Zacpqfr Y+dA6A//MlFtjlEqL6YGfEuC9SXswfoHoEZ99naGNyBWdWhcYFQvfvGcueGzvEg6Ndc0 CoOp1pCRZw+mO4+RfrBQY4BWmfcuzaLlvGH1JuVBs8L3859JWSUAy3nyDzIym9RBxleJ +vHTi53uM7iRN1LxBYp70wsyxU7RFFxmWl4UE9vKFjWnxXmRrJBTa+XF9kxtnNiUSmLl 1njg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=QoRj3DXPVUPlNmVpcPhUeVeCQtZgBqi3bNB9/9XzVbI=; b=aZVP6nhNZix3m54guJ3iT2gojt5YEehSyZZLwLpzFVzeDdOoKMz9d4aMqsxRjld50e RkNZSRkV1MgIl05NVlb9jrRxScI9o2wcG9AVvGwWLJ7FUNcs04GHSqAT5N5P4TF2RD9t EzZ7KVPIRJkOd9ikD3dXeB5fEAophHy/Yk/4xkAfN0cULjvAupLUGB8l6WDT1v7vSJqw sktU1Vxo1nHGps/cbMI9o8nGU/MMpJlCyPF1hxPNyxjWla+gwXNkVuR0JBRELOInjr1a oNwfpVN2BOl2rLN4IOFbwQmWUKRpDCqvORXQ7+5ApQZiUpypdYTC12MGR03umjJnUrWE yVxg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=ZoD7EV9Z; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id m11-20020a170902db0b00b001910cb3adcasi15464217plx.235.2022.12.27.11.24.48; Tue, 27 Dec 2022 11:24:59 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=ZoD7EV9Z; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232026AbiL0TYg (ORCPT + 99 others); Tue, 27 Dec 2022 14:24:36 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44926 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230500AbiL0TX5 (ORCPT ); Tue, 27 Dec 2022 14:23:57 -0500 Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 564007655 for ; Tue, 27 Dec 2022 11:23:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1672169037; x=1703705037; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=iKTyz4kG5wNghmRCTt8/fCMlWiOtY5ulPwSrncqRr5Q=; b=ZoD7EV9Z2HYQx7bnX8OHrr89HAc5SfAtsuZcY/TxHoAPmUNHoYBX67KK 5wfqDnqDV54AVqTw2n6BelTU97TgI9hnx/z5RPITAg21To35GhrZGHgOt x6XYxpPraVWYN2OgS24mSdJdxHeODMjdJSDebNFmc1FJ1MKZQqiJPAF5z r2WxsFqK3Z4RJkAJ3HT3GscaxfFzb3QwbkLMsBtnMsKYizJk6olfSYMSk 9sh6gx5dwmlytW29yXZnnnnXfJvIwv0Zt35qg02OwGI3hIbY+CcKY9vBv Cr162bL7i3P+eKkQRjU0NjkXpCDKKb6OGF/6cLmVkQtNpSrF6H09FHz/m w==; X-IronPort-AV: E=McAfee;i="6500,9779,10573"; a="407011183" X-IronPort-AV: E=Sophos;i="5.96,279,1665471600"; d="scan'208";a="407011183" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Dec 2022 11:23:55 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10573"; a="777234206" X-IronPort-AV: E=Sophos;i="5.96,279,1665471600"; d="scan'208";a="777234206" Received: from araj-ucode.jf.intel.com ([10.23.0.19]) by orsmga004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Dec 2022 11:23:54 -0800 From: Ashok Raj To: Borislav Petkov , Thomas Gleixner Cc: X86-kernel , LKML Mailing List , Ashok Raj , Dave Hansen , Tony Luck , Alison Schofield , Reinette Chatre , Tom Lendacky Subject: [PATCH v2 5/6] x86/microcode/intel: Print old and new rev during early boot Date: Tue, 27 Dec 2022 11:23:39 -0800 Message-Id: <20221227192340.8358-6-ashok.raj@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221227192340.8358-1-ashok.raj@intel.com> References: <20221227192340.8358-1-ashok.raj@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1753396386042587289?= X-GMAIL-MSGID: =?utf-8?q?1753396386042587289?= Make early loading message to match late loading messages. Print both old and new revisions. This is helpful to know what the BIOS loaded revision is before an early update. New dmesg log is shown below. microcode: early update: 0x2b000041 -> 0x2b000070 date = 2000-01-01 Cache the early BIOS revision before the microcode update and change the print_ucode_info() so it prints both the old and new revision in the same format as microcode_reload_late(). Signed-off-by: Ashok Raj Reviewed-by: Thomas Gleixner Cc: LKML Cc: x86 Cc: Tony Luck Cc: Dave Hansen Cc: Alison Schofield Cc: Reinette Chatre Cc: Thomas Gleixner Cc: Tom Lendacky --- Updates since previous post. Thomas: Commit log updates as suggested. --- arch/x86/kernel/cpu/microcode/intel.c | 25 +++++++++++++++---------- 1 file changed, 15 insertions(+), 10 deletions(-) diff --git a/arch/x86/kernel/cpu/microcode/intel.c b/arch/x86/kernel/cpu/microcode/intel.c index 1d709b72cfd0..f24300830ed7 100644 --- a/arch/x86/kernel/cpu/microcode/intel.c +++ b/arch/x86/kernel/cpu/microcode/intel.c @@ -310,10 +310,10 @@ static bool load_builtin_intel_microcode(struct cpio_data *cp) /* * Print ucode update info. */ -static void print_ucode_info(unsigned int new_rev, unsigned int date) +static void print_ucode_info(int old_rev, int new_rev, unsigned int date) { - pr_info_once("microcode updated early to revision 0x%x, date = %04x-%02x-%02x\n", - new_rev, date & 0xffff, date >> 24, + pr_info_once("early update: 0x%x -> 0x%x, date = %04x-%02x-%02x\n", + old_rev, new_rev, date & 0xffff, date >> 24, (date >> 16) & 0xff); } @@ -321,6 +321,7 @@ static void print_ucode_info(unsigned int new_rev, unsigned int date) static int delay_ucode_info; static int current_mc_date; +static int early_old_rev; /* * Print early updated ucode info after printk works. This is delayed info dump. @@ -331,7 +332,7 @@ void show_ucode_info_early(void) if (delay_ucode_info) { intel_cpu_collect_info(&uci); - print_ucode_info(uci.cpu_sig.rev. current_mc_date); + print_ucode_info(early_old_rev, uci.cpu_sig.rev, current_mc_date); delay_ucode_info = 0; } } @@ -340,30 +341,33 @@ void show_ucode_info_early(void) * At this point, we can not call printk() yet. Delay printing microcode info in * show_ucode_info_early() until printk() works. */ -static void print_ucode(int new_rev, int date) +static void print_ucode(int old_rev, int new_rev, int date) { struct microcode_intel *mc; int *delay_ucode_info_p; int *current_mc_date_p; + int *early_old_rev_p; delay_ucode_info_p = (int *)__pa_nodebug(&delay_ucode_info); current_mc_date_p = (int *)__pa_nodebug(¤t_mc_date); + early_old_rev_p = (int *)__pa_nodebug(&early_old_rev); *delay_ucode_info_p = 1; *current_mc_date_p = date; + *early_old_rev_p = old_rev; } #else -static inline void print_ucode(int new_rev, int date) +static inline void print_ucode(int old_rev, int new_rev, int date) { - print_ucode_info(new_rev, date); + print_ucode_info(old_rev, new_rev, date); } #endif static int apply_microcode_early(struct ucode_cpu_info *uci, bool early) { struct microcode_intel *mc; - u32 rev; + u32 rev, old_rev; mc = uci->mc; if (!mc) @@ -389,6 +393,7 @@ static int apply_microcode_early(struct ucode_cpu_info *uci, bool early) /* write microcode via MSR 0x79 */ native_wrmsrl(MSR_IA32_UCODE_WRITE, (unsigned long)mc->bits); + old_rev = rev; rev = intel_get_microcode_revision(); if (rev != mc->hdr.rev) return -1; @@ -396,9 +401,9 @@ static int apply_microcode_early(struct ucode_cpu_info *uci, bool early) uci->cpu_sig.rev = rev; if (early) - print_ucode(uci->cpu_sig.rev, mc->hdr.date); + print_ucode(old_rev, uci->cpu_sig.rev, mc->hdr.date); else - print_ucode_info(uci->cpu_sig.rev, mc->hdr.date); + print_ucode_info(old_rev, uci->cpu_sig.rev, mc->hdr.date); return 0; } From patchwork Tue Dec 27 19:23:40 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ashok Raj X-Patchwork-Id: 36986 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4e01:0:0:0:0:0 with SMTP id p1csp1544170wrt; Tue, 27 Dec 2022 11:24:58 -0800 (PST) X-Google-Smtp-Source: AMrXdXuwXRE3IqNkW6JmJep3Z7KVv/ZjZghzf4wbHN9o8aC4JvLAYOl2VDk1akIoyS4YhMFC/T6U X-Received: by 2002:a17:902:6a85:b0:191:420e:e6b1 with SMTP id n5-20020a1709026a8500b00191420ee6b1mr25255366plk.32.1672169097982; Tue, 27 Dec 2022 11:24:57 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1672169097; cv=none; d=google.com; s=arc-20160816; b=o9kAl8x+pRjirYhz8yOFwtw8QF2qGsW0yRWD8ixwSDegoAxg78mlfLONuiCGED0wW9 5tYyx1bSC+/1WKPN+aOZ8MAzoZ4bIpF+QerXzsFy427+zgLZbVE2LApqHQHGcbqgdC3q Ab6xyaFTdtpoV5pARo968R7Ac8lkl4XUyGivdo8PEUN/cr21Gw1UG+SRTRx7dcQN6Iee Gqmfu4Keb6OORy2+Lh9Zdz1/G24zi2okpwcf6XmH141i/U74TL6uLakgMbBPrtyOtJuQ G+dBhpAJsLBQ08XhFKP6ny36Hex6pL8yswI31FqPXOyo9Qn0Vf9i3P7+lhd5d7PXi/bf DOYA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=l5pxbQTYC0zbTTffNJDuInwIYZlUb2PNvtrq46V44mw=; b=m0y1zgJH0BODU3ZnUXdDCPhPT6VqP6toZ0KcVD7pq3ggfm78G3xgrKv87dPy4UEEVN IN5oK9ACP+W2pE4/BbinYRvMtfMEwohQdpKD64iEVbOZHnW3HVZ7ZX2fiXIvxm7g7dbb N0bBqxp6DxoW15HnQIAMmow4yxoZZz3SrxlqTOtUMPuYQYRxKup61hnYi3s1PDr+7tzc WM2/+HvnfyvMr7vXM1XIZ91TsIOfiSj9Q5f91JSLaf7h+Qfkqp0m3KnX9prBoCu3kM/k l5NU/FnEt1MhaZZGBmszhs5l1A6mErNhXpnj+lpi2ZouP5ns4P61k0x1yw2enG0wQ1vl tOIg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=RpnbaynZ; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id l7-20020a170903244700b001925c7c0eb7si14845402pls.90.2022.12.27.11.24.46; Tue, 27 Dec 2022 11:24:57 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=RpnbaynZ; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232001AbiL0TYa (ORCPT + 99 others); Tue, 27 Dec 2022 14:24:30 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44936 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231167AbiL0TX6 (ORCPT ); Tue, 27 Dec 2022 14:23:58 -0500 Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 923227674 for ; Tue, 27 Dec 2022 11:23:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1672169037; x=1703705037; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Rpu7Ee31xVGs/Ge1cmadMTPDkLVc3s122FBVNn8fO8I=; b=RpnbaynZ0AGHJKADzwNhfHIns+0vYzjknJX3Iv66FxSVnR/J4hXWeZW0 aN7iEUAX7LBsAX3e/dSiSXrdG53RxqoGCa3D8VUSyX5E170zmTL94Vn/o s+f++iyLCrQ4bCew7cwbrH7+VgUxppf59CpLpyW9nrZxzAya9MgsC+zIf yVK1OncpcZUxmnuPglDAmZU3IPFcg2XtbBsI2xK/OGiS0bCzVPTq8KF6w IKjSy49OPy534vKJGJFh6OC322o77Feov+yKidT2xm/3wbX9Mj3jSOf+i sIfkq6fYo+5oUUn8Qfedk8yHrQ6voC1GeU2h5Gm8oRiRLc1wTnjoc9xsO Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10573"; a="407011188" X-IronPort-AV: E=Sophos;i="5.96,279,1665471600"; d="scan'208";a="407011188" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Dec 2022 11:23:55 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10573"; a="777234208" X-IronPort-AV: E=Sophos;i="5.96,279,1665471600"; d="scan'208";a="777234208" Received: from araj-ucode.jf.intel.com ([10.23.0.19]) by orsmga004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Dec 2022 11:23:54 -0800 From: Ashok Raj To: Borislav Petkov , Thomas Gleixner Cc: X86-kernel , LKML Mailing List , Ashok Raj , Dave Hansen , Tony Luck , Alison Schofield , Reinette Chatre , Tom Lendacky Subject: [PATCH v2 6/6] x86/microcode/intel: Print when early microcode loading fails Date: Tue, 27 Dec 2022 11:23:40 -0800 Message-Id: <20221227192340.8358-7-ashok.raj@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221227192340.8358-1-ashok.raj@intel.com> References: <20221227192340.8358-1-ashok.raj@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1753396383962894904?= X-GMAIL-MSGID: =?utf-8?q?1753396383962894904?= Currently when early microcode loading fails there is no way for the user to know that the update failed. Store the failed status and pass it to print_ucode_info() so that early loading failures are captured in dmesg. Signed-off-by: Ashok Raj Cc: LKML Cc: x86 Cc: Tony Luck Cc: Dave Hansen Cc: Alison Schofield Cc: Reinette Chatre Cc: Thomas Gleixner Cc: Tom Lendacky --- Changes since last post. Thomas: Fix commit log as suggested. --- arch/x86/kernel/cpu/microcode/intel.c | 28 +++++++++++++++------------ 1 file changed, 16 insertions(+), 12 deletions(-) diff --git a/arch/x86/kernel/cpu/microcode/intel.c b/arch/x86/kernel/cpu/microcode/intel.c index f24300830ed7..0cdff9ed2a4e 100644 --- a/arch/x86/kernel/cpu/microcode/intel.c +++ b/arch/x86/kernel/cpu/microcode/intel.c @@ -310,11 +310,11 @@ static bool load_builtin_intel_microcode(struct cpio_data *cp) /* * Print ucode update info. */ -static void print_ucode_info(int old_rev, int new_rev, unsigned int date) +static void print_ucode_info(bool failed, int old_rev, int new_rev, unsigned int date) { - pr_info_once("early update: 0x%x -> 0x%x, date = %04x-%02x-%02x\n", + pr_info_once("early update: 0x%x -> 0x%x, date = %04x-%02x-%02x %s\n", old_rev, new_rev, date & 0xffff, date >> 24, - (date >> 16) & 0xff); + (date >> 16) & 0xff, failed ? "FAILED" : ""); } #ifdef CONFIG_X86_32 @@ -322,6 +322,7 @@ static void print_ucode_info(int old_rev, int new_rev, unsigned int date) static int delay_ucode_info; static int current_mc_date; static int early_old_rev; +static bool early_failed; /* * Print early updated ucode info after printk works. This is delayed info dump. @@ -332,7 +333,7 @@ void show_ucode_info_early(void) if (delay_ucode_info) { intel_cpu_collect_info(&uci); - print_ucode_info(early_old_rev, uci.cpu_sig.rev, current_mc_date); + print_ucode_info(early_failed, early_old_rev, uci.cpu_sig.rev, current_mc_date); delay_ucode_info = 0; } } @@ -341,26 +342,28 @@ void show_ucode_info_early(void) * At this point, we can not call printk() yet. Delay printing microcode info in * show_ucode_info_early() until printk() works. */ -static void print_ucode(int old_rev, int new_rev, int date) +static void print_ucode(bool failed, int old_rev, int new_rev, int date) { - struct microcode_intel *mc; int *delay_ucode_info_p; int *current_mc_date_p; int *early_old_rev_p; + bool *early_failed_p; delay_ucode_info_p = (int *)__pa_nodebug(&delay_ucode_info); current_mc_date_p = (int *)__pa_nodebug(¤t_mc_date); early_old_rev_p = (int *)__pa_nodebug(&early_old_rev); + early_failed_p = (bool *)__pa_nodebug(&early_failed); *delay_ucode_info_p = 1; *current_mc_date_p = date; *early_old_rev_p = old_rev; + *early_failed_p = failed; } #else -static inline void print_ucode(int old_rev, int new_rev, int date) +static inline void print_ucode(bool failed, int old_rev, int new_rev, int date) { - print_ucode_info(old_rev, new_rev, date); + print_ucode_info(failed, old_rev, new_rev, date); } #endif @@ -368,6 +371,7 @@ static int apply_microcode_early(struct ucode_cpu_info *uci, bool early) { struct microcode_intel *mc; u32 rev, old_rev; + int retval = 0; mc = uci->mc; if (!mc) @@ -396,16 +400,16 @@ static int apply_microcode_early(struct ucode_cpu_info *uci, bool early) old_rev = rev; rev = intel_get_microcode_revision(); if (rev != mc->hdr.rev) - return -1; + retval = -1; uci->cpu_sig.rev = rev; if (early) - print_ucode(old_rev, uci->cpu_sig.rev, mc->hdr.date); + print_ucode(retval, old_rev, mc->hdr.rev, mc->hdr.date); else - print_ucode_info(old_rev, uci->cpu_sig.rev, mc->hdr.date); + print_ucode_info(retval, old_rev, uci->cpu_sig.rev, mc->hdr.date); - return 0; + return retval; } int __init save_microcode_in_initrd_intel(void)