From patchwork Thu Oct 6 04:40:15 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tsukasa OI X-Patchwork-Id: 1751 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4ac7:0:0:0:0:0 with SMTP id y7csp138530wrs; Wed, 5 Oct 2022 21:40:47 -0700 (PDT) X-Google-Smtp-Source: AMsMyM6cEvJxP4kadC9lcKE5jQcElKTFzXu/EDf62ngDkK8Uhxruj6YunND/hlAXgul822c9ew+J X-Received: by 2002:a17:906:8a50:b0:78d:36d9:b9f2 with SMTP id gx16-20020a1709068a5000b0078d36d9b9f2mr2429849ejc.287.1665031246999; Wed, 05 Oct 2022 21:40:46 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1665031246; cv=none; d=google.com; s=arc-20160816; b=n0cWapVNqFJuXIdDQSOgxDi95JgbCwLNC2YhX8cqWWpFFcNJjjMUm8m/Vk9YPNlv8L jYDW7eUEyndqIHrx9FG4spN383JGhwB0iRBhWpPVgK1Q4YG6WorKqkJ478WydKV+g5MQ xz3UV4nCHsCE1huDBznubgUBDaGbA4v3AXTSuF2zXV8Vl88c+NgF+nR1cxutft2t93FS 8RVBVKRe2iMsRBkoQIfTWw7PCkrmScehOsg634O4kwISbiTTXTW4M/xLjCW9tgj5kCZ4 K0NczfIX3gu8hLLnYxCs63uaSRAnhUfzWK3O6inByEdPvaI/PCjmSayOOCUjF3YLbPp7 YlQw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:reply-to:from:list-subscribe:list-help :list-post:list-archive:list-unsubscribe:list-id:precedence :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:dmarc-filter:delivered-to:dkim-signature :dkim-filter; bh=tm3/4eR857ngj5HKGrQGF1IZcsysp2jSPEuTQjwVyWA=; b=AV9D2HIb1tMefAqqfTU8bwIfDCdTluPnibgaABkH6rR5bUQDOQGtEI1w0v8hiUnKAk hq5vaphmT0Mw3a/aJCyyBy5AKAb0BAP7tg+zRbNqYZoYL5NswyMPyonTlv1stZWtGt8b K4T8t2gKLPzuUlwKaQi/IlZ8j5jI7k7MVH/fxxbreyNMtdkpTR4pqDHE9DiKNZQPe2ds L6r6Whg/gulP60gYKaVQLEI7HuXj1a4D/bddgJfHaP6jdqsVtFwrVa3UmJY3/SgUtF8r N6+Y1A+QSDtCwEotSuSROwOKuVU8LfU9Aa4sSzl3rIZX5EVb4FF1EtYDWUduUARVE/KO 13fQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@sourceware.org header.s=default header.b=AzwIKr5L; spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=sourceware.org Received: from sourceware.org (server2.sourceware.org. [2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id t4-20020a056402240400b00458bf560cbasi12884406eda.90.2022.10.05.21.40.46 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Oct 2022 21:40:46 -0700 (PDT) Received-SPF: pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; dkim=pass header.i=@sourceware.org header.s=default header.b=AzwIKr5L; spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 8CD4B384D15C for ; Thu, 6 Oct 2022 04:40:45 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 8CD4B384D15C DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1665031245; bh=tm3/4eR857ngj5HKGrQGF1IZcsysp2jSPEuTQjwVyWA=; h=To:Subject:Date:In-Reply-To:References:List-Id:List-Unsubscribe: List-Archive:List-Post:List-Help:List-Subscribe:From:Reply-To:Cc: From; b=AzwIKr5LCGCEEnDSVrtSShgMonnV600Yxv0H1og0bqbzOaEnjH07qIQZ7Wz+Nhhr/ Y4GIhWemJGnmDftyjRdX97koVw6Q7kqN1v5lMFOLUwFNQR6nmFY2BQYTzrHBE6xkKb F/txMrNS1tX5CzjN0SxTc0vGeSSYdHacHIlGcxuw= X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from mail-sender-0.a4lg.com (mail-sender.a4lg.com [153.120.152.154]) by sourceware.org (Postfix) with ESMTPS id 606CA384D148 for ; Thu, 6 Oct 2022 04:40:37 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 606CA384D148 Received: from [127.0.0.1] (localhost [127.0.0.1]) by mail-sender-0.a4lg.com (Postfix) with ESMTPSA id 4C37930008A; Thu, 6 Oct 2022 04:40:34 +0000 (UTC) To: Tsukasa OI , Nelson Chu , Kito Cheng , Palmer Dabbelt Subject: [PATCH v2 1/2] RISC-V: Fallback for instructions longer than 64b Date: Thu, 6 Oct 2022 04:40:15 +0000 Message-Id: In-Reply-To: References: Mime-Version: 1.0 X-Spam-Status: No, score=-12.1 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, GIT_PATCH_0, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Tsukasa OI via Binutils From: Tsukasa OI Reply-To: Tsukasa OI Cc: binutils@sourceware.org Errors-To: binutils-bounces+ouuuleilei=gmail.com@sourceware.org Sender: "Binutils" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1745911805079942387?= X-GMAIL-MSGID: =?utf-8?q?1745911805079942387?= We don't support instructions longer than 64-bits yet. Still, we can modify validate_riscv_insn function to prevent unexpected behavior by limiting the "length" of an instruction to 64-bit (or less). gas/ChangeLog: * config/tc-riscv.c (validate_riscv_insn): Fix function description comment based on current usage. Limit instruction length up to 64-bit for now. Make sure that required_bits does not corrupt even if unsigned long long is longer than 64-bit. --- gas/config/tc-riscv.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c index 22385d1baa0..2e41cec5c9f 100644 --- a/gas/config/tc-riscv.c +++ b/gas/config/tc-riscv.c @@ -1109,7 +1109,7 @@ arg_lookup (char **s, const char *const *array, size_t size, unsigned *regnop) /* For consistency checking, verify that all bits are specified either by the match/mask part of the instruction definition, or by the - operand list. The `length` could be 0, 4 or 8, 0 for auto detection. */ + operand list. The `length` could be 0, 2 or 4, 0 for auto detection. */ static bool validate_riscv_insn (const struct riscv_opcode *opc, int length) @@ -1120,11 +1120,13 @@ validate_riscv_insn (const struct riscv_opcode *opc, int length) insn_t required_bits; if (length == 0) - insn_width = 8 * riscv_insn_length (opc->match); - else - insn_width = 8 * length; + length = riscv_insn_length (opc->match); + /* We don't support instructions longer than 64-bits yet. */ + if (length > 8) + length = 8; + insn_width = 8 * length; - required_bits = ~0ULL >> (64 - insn_width); + required_bits = ((insn_t)~0ULL) >> (64 - insn_width); if ((used_bits & opc->match) != (opc->match & required_bits)) { From patchwork Thu Oct 6 04:40:16 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tsukasa OI X-Patchwork-Id: 1752 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4ac7:0:0:0:0:0 with SMTP id y7csp138577wrs; Wed, 5 Oct 2022 21:41:01 -0700 (PDT) X-Google-Smtp-Source: AMsMyM5OFHGM2O6eHhaO4UthGLdp02w1poiInzA5gQV4Tjz1Tj/ys7RNEu/jfMMurQY9ZF4hZkLi X-Received: by 2002:a05:6402:1e92:b0:451:dcf:641d with SMTP id f18-20020a0564021e9200b004510dcf641dmr2843882edf.335.1665031261241; Wed, 05 Oct 2022 21:41:01 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1665031261; cv=none; d=google.com; s=arc-20160816; b=C6eDtTJ75OyOnXj24BE94BPnXG0n0laov6ut4O0yxV2iPi/edUes0IjoE9Bd+3pSu2 +8r/JgDmU7ttf13evNrzRamxzLgSowvseI+WgiB3yWTMbM9/M61SwuLw4GsWvvKqXdrx EngbZAYos8t+3MGhY1jFlPHOl2eILR8743n2XcX+uV8mMacaChJZJgpOOWW914Oi0CiY EQ9yg8Nw4r/obIstWS043QlMDTRlqkYAVZVoTRQHYLRvrjDmorx5aziIIjeu+ukz349k 7uYE04gLhUZG16Tpd6QJtzjx6m0WCGFjiBMjhN8MkHwYnaZ08z0EnSBlghDKd2tciywx dsaA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:reply-to:from:list-subscribe:list-help :list-post:list-archive:list-unsubscribe:list-id:precedence :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:dmarc-filter:delivered-to:dkim-signature :dkim-filter; bh=/vCTF/G4QVs7ROme/TFeEqos4+xs1uuKLN+Z6Zsnsus=; b=ZBamyInUk22mn5SV0+jk1ot1RH7dn4gW4OVfCOignX9NI+/KqExRPZManHk+JJWa2M sqdjBqxZTmjhVUfgCz+v/8z3LQt0ss3vwZtkYC6sL7g8Fdvo4BwKx6PBvXq5Z1jGHz8O uRqjv/0rkqETOLo6zzs2nhFy8EEnrP8wUGK3w9c3S7SP12RGbsVtWYS/ePsZ9LhIKpDd CbZqiaJrxA56k5dwgm/awXPIX366A8DlK4Y4d7nEMn9x1fSaQKuupb0Y47h4GSu4M3AH 0Ol9chPjKeRho2ai8wQrgx9mgQDz91eIoMZGYchhHbvQw5WoPst2hSLIi0ju6D/BL94R MNIg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@sourceware.org header.s=default header.b=D5uYjd1e; spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=sourceware.org Received: from sourceware.org (server2.sourceware.org. [2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id fd16-20020a056402389000b00458ebd62c70si10075216edb.32.2022.10.05.21.41.01 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Oct 2022 21:41:01 -0700 (PDT) Received-SPF: pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; dkim=pass header.i=@sourceware.org header.s=default header.b=D5uYjd1e; spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id EDF80384D16E for ; Thu, 6 Oct 2022 04:40:53 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org EDF80384D16E DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1665031254; bh=/vCTF/G4QVs7ROme/TFeEqos4+xs1uuKLN+Z6Zsnsus=; h=To:Subject:Date:In-Reply-To:References:List-Id:List-Unsubscribe: List-Archive:List-Post:List-Help:List-Subscribe:From:Reply-To:Cc: From; b=D5uYjd1eVTtEJZFREh8hGFkUiZUWsV6pUEpX/1/5KbWjw3pDTpVwbTbbzs3xMwgIx xMtGa62Qfm94gCJCWYufB5drMBvDbReg1iD+LScJPiePhGmvsGE/bKu6X+eanLx6Ua X9YWYISYKg73vX1ByAxDwdOLJa2HG2sMy+0huaEg= X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from mail-sender-0.a4lg.com (mail-sender-0.a4lg.com [IPv6:2401:2500:203:30b:4000:6bfe:4757:0]) by sourceware.org (Postfix) with ESMTPS id 7A34A384D14E for ; Thu, 6 Oct 2022 04:40:46 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 7A34A384D14E Received: from [127.0.0.1] (localhost [127.0.0.1]) by mail-sender-0.a4lg.com (Postfix) with ESMTPSA id CC7DF300089; Thu, 6 Oct 2022 04:40:44 +0000 (UTC) To: Tsukasa OI , Nelson Chu , Kito Cheng , Palmer Dabbelt Subject: [PATCH v2 2/2] RISC-V: Improve "bits undefined" diagnostics Date: Thu, 6 Oct 2022 04:40:16 +0000 Message-Id: In-Reply-To: References: Mime-Version: 1.0 X-Spam-Status: No, score=-12.1 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, GIT_PATCH_0, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Tsukasa OI via Binutils From: Tsukasa OI Reply-To: Tsukasa OI Cc: binutils@sourceware.org Errors-To: binutils-bounces+ouuuleilei=gmail.com@sourceware.org Sender: "Binutils" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1745911799964221706?= X-GMAIL-MSGID: =?utf-8?q?1745911819903752076?= This commit improves internal error message "internal: bad RISC-V opcode (bits 0x%lx undefined): %s %s" to display actual unused bits (excluding non-instruction bits). gas/ChangeLog: * config/tc-riscv.c (validate_riscv_insn): Exclude non- instruction bits from displaying internal diagnostics. Change error message slightly. --- gas/config/tc-riscv.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c index 2e41cec5c9f..34973d7803c 100644 --- a/gas/config/tc-riscv.c +++ b/gas/config/tc-riscv.c @@ -1312,8 +1312,8 @@ validate_riscv_insn (const struct riscv_opcode *opc, int length) if (used_bits != required_bits) { as_bad (_("internal: bad RISC-V opcode " - "(bits 0x%lx undefined): %s %s"), - ~(unsigned long)(used_bits & required_bits), + "(bits 0x%llx undefined or invalid): %s %s"), + (unsigned long long)(used_bits ^ required_bits), opc->name, opc->args); return false; }