From patchwork Tue Dec 27 11:58:54 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: William Qiu X-Patchwork-Id: 36835 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4e01:0:0:0:0:0 with SMTP id p1csp1354228wrt; Tue, 27 Dec 2022 04:00:21 -0800 (PST) X-Google-Smtp-Source: AMrXdXvx/inoqjbYdIKvL74hMAgOsLBNL8rP5N4dU22fqp+12B3J1ulVqpegNt716D7d/hKiAknc X-Received: by 2002:a17:906:3702:b0:7c1:22a9:ba8b with SMTP id d2-20020a170906370200b007c122a9ba8bmr19182898ejc.50.1672142420917; Tue, 27 Dec 2022 04:00:20 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1672142420; cv=none; d=google.com; s=arc-20160816; b=0qp2ksDA6n6LiNLjDAHEy35/IuK0LmveAI2A5tY15xPDQFlBq6Q1/9nsdCnhOS2jmr 2RKxm6B6CyqU7pToNO22KtprlSvY3DrAV48XnJY63nij9J62ZWW+G6a4QfZvKkPSRGGY w0fSmq7imk3TSArVMo2vXLKlisb86xFFjdsPvCl5r5zBhWtB6YSea19WiTjZ2Rrzqmn4 I4hHA2g1QlmC4Vjujdmk/ErHLOD4zxNRsyM06ZC/G+RJCR0dntJZzftwpBxY05wnJ4o3 CDJWSA4bHTA1qgfJNAmOkmND/tpUdY6HFjG715mp8rBCyu8UhOfbLKjr/DOsgUFemKNS J4pg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=IHoGTSXgsv7shMV2Co0/e5fx3PSJZqnI82peEKqyENg=; b=No2eLFJD/FxjRPY6wDMLSis61WS0piOzgfEYKOR6HktHkJTIthksoPS2XIicnQa13B oG0jY74cXUvkf3jVIQFK3E5KFgn1s9roYyQYBgXvePQAt8eYqhZXfNf4E4X2NMKBKx8S SetkmSer6FqhemjPtf/huUBU2HDzeTkeA6ZitTlx2CblzdYLJcqsj2Kd7GP/Kl3U25k4 Fwv8RQEJ5gKkyAZF4xIJ+TNDhRpL/QdVJv4wQRd4CWZ698Vfd3A9+KYTAhEr14lm9ZTn lA3rxp7GQCzRkpCiiUrwmgzab3IPU3BZYROK9GkL/N+KU7QzG2NMlq17DPW3OPIrVVX2 xmTQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id b26-20020a170906151a00b007707b853e46si7781459ejd.882.2022.12.27.03.59.56; Tue, 27 Dec 2022 04:00:20 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232001AbiL0L7n convert rfc822-to-8bit (ORCPT + 99 others); Tue, 27 Dec 2022 06:59:43 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44418 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232035AbiL0L7N (ORCPT ); Tue, 27 Dec 2022 06:59:13 -0500 Received: from ex01.ufhost.com (ex01.ufhost.com [61.152.239.75]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 711E4B845; Tue, 27 Dec 2022 03:59:09 -0800 (PST) Received: from EXMBX165.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX165", Issuer "EXMBX165" (not verified)) by ex01.ufhost.com (Postfix) with ESMTP id 5944824DDB2; Tue, 27 Dec 2022 19:59:07 +0800 (CST) Received: from EXMBX168.cuchost.com (172.16.6.78) by EXMBX165.cuchost.com (172.16.6.75) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Tue, 27 Dec 2022 19:59:06 +0800 Received: from williamqiu-virtual-machine.starfivetech.com (171.223.208.138) by EXMBX168.cuchost.com (172.16.6.78) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Tue, 27 Dec 2022 19:59:05 +0800 From: William Qiu To: , CC: Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , Hal Feng , Subject: [PATCH v2 1/3] dt-bindings: mmc: Add bindings for StarFive Date: Tue, 27 Dec 2022 19:58:54 +0800 Message-ID: <20221227115856.460790-2-william.qiu@starfivetech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221227115856.460790-1-william.qiu@starfivetech.com> References: <20221227115856.460790-1-william.qiu@starfivetech.com> MIME-Version: 1.0 X-Originating-IP: [171.223.208.138] X-ClientProxiedBy: EXCAS066.cuchost.com (172.16.6.26) To EXMBX168.cuchost.com (172.16.6.78) X-YovoleRuleAgent: yovoleflag X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1753368410821449508?= X-GMAIL-MSGID: =?utf-8?q?1753368410821449508?= Add documentation to describe StarFive designware mobile storage host controller driver. Signed-off-by: William Qiu --- .../bindings/mmc/starfive,jh7110-mmc.yaml | 72 +++++++++++++++++++ 1 file changed, 72 insertions(+) create mode 100644 Documentation/devicetree/bindings/mmc/starfive,jh7110-mmc.yaml diff --git a/Documentation/devicetree/bindings/mmc/starfive,jh7110-mmc.yaml b/Documentation/devicetree/bindings/mmc/starfive,jh7110-mmc.yaml new file mode 100644 index 000000000000..430dd5f24933 --- /dev/null +++ b/Documentation/devicetree/bindings/mmc/starfive,jh7110-mmc.yaml @@ -0,0 +1,72 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mmc/starfive,jh7110-mmc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: StarFive Designware Mobile Storage Host Controller + +description: + StarFive uses the Synopsys designware mobile storage host controller + to interface a SoC with storage medium such as eMMC or SD/MMC cards. + +allOf: + - $ref: synopsys-dw-mshc-common.yaml# + +maintainers: + - William Qiu + +properties: + compatible: + const: starfive,jh7110-mmc + + reg: + maxItems: 1 + + clocks: + items: + - description: biu clock + - description: ciu clock + + clock-names: + items: + - const: biu + - const: ciu + + interrupts: + maxItems: 1 + + starfive,syscon: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: + arg0:arg0 is syscon. + arg1:arg1 is syscon register offset, used to enable MMC function. + arg2:arg2 is used to enable the register shift of the MMC function. + arg3:arg3 is used to enable the register mask of the MMC function. + +required: + - compatible + - reg + - clocks + - clock-names + - interrupts + - starfive,syscon + +unevaluatedProperties: false + +examples: + - | + mmc@16010000 { + compatible = "starfive,jh7110-mmc"; + reg = <0x16010000 0x10000>; + clocks = <&syscrg 91>, + <&syscrg 93>; + clock-names = "biu","ciu"; + resets = <&syscrg 64>; + reset-names = "reset"; + interrupts = <74>; + fifo-depth = <32>; + fifo-watermark-aligned; + data-addr = <0>; + starfive,syscon = <&syscon 0x14 0x1a 0x7c000000>; + }; From patchwork Tue Dec 27 11:58:55 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: William Qiu X-Patchwork-Id: 36837 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4e01:0:0:0:0:0 with SMTP id p1csp1354361wrt; Tue, 27 Dec 2022 04:00:36 -0800 (PST) X-Google-Smtp-Source: AMrXdXsBIyPlzDl8R1+10I7V+PiV9yMNsVDso5uWhpjwY75eN49CwyBdsPA0InDOGm3WfFZuRj5q X-Received: by 2002:a17:907:d08d:b0:7aa:76a:fb3 with SMTP id vc13-20020a170907d08d00b007aa076a0fb3mr20204204ejc.66.1672142436607; Tue, 27 Dec 2022 04:00:36 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1672142436; cv=none; d=google.com; s=arc-20160816; b=edUnBiieBS9ecbIhUWynQZ/Cyw6G/BYbAW/UjTg92qazwyISdsvcaWo4EyAIDG5cf8 gcOAmBU7ZPbXrR6Hkm60Tt+RAagZlWZvIkCh/aj5cJ8yuyLGhQjMDyci6UeMcBFzojZO gX0/p+MUeShrc1DPkziyf+0NzuGEn4eVbLdAglMvamI+gIBD6bfHyNGcUuxKXq3QJNzv gw4gSN8grCxvDZO2IYDR4HjjJFwhcdz8E4as/6Ipkom4u3WRTuUqTdG+Vtb7r5Hgi/BY fGYKHOF3G6SZRBoWiTyYhBNiwGNYapBNnYNuCl7zqbpWnT3yUNX9+avHWnqNkVTxfKSt 7NGQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=jGnWSBtAFuClGSid946JdWdYgIB2lVnWj2S0Ouv6PJw=; b=ykXAOypte6Ivcl2b7Mv+BwoYYtJScYqaxOZ8WA4O8hi12QyNl6AN6X0lQX14WQCj42 2KltkNjjTH5H2yHInSGCcykFYLQrgJBygCv0Wehbfab8jd52pH4XfCBo6VGKFjGXxdin KQe962FpfBvFDpJCjbq28WX31UcY+ipKLENqC0G9EIJVJ8DMGzEMB2jdr1Mg7xVF2KfA xmH9TqqS8q3ir5ZEvz6O7x1axVhorVQ3ajq0/wbKR51TC1RwicYD0xgveyt9nDaEtkp2 0d5JSsb9t+MCmVQkglbBYc5BYe71bKVKFSQj0nvW8x/fGmbW8kl9SKAURCYc1hHGcWXY cJ4A== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id b13-20020a056402084d00b0046afb32bfd9si11341685edz.302.2022.12.27.04.00.11; Tue, 27 Dec 2022 04:00:36 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232151AbiL0L7t convert rfc822-to-8bit (ORCPT + 99 others); Tue, 27 Dec 2022 06:59:49 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43872 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232040AbiL0L7N (ORCPT ); Tue, 27 Dec 2022 06:59:13 -0500 Received: from fd01.gateway.ufhost.com (fd01.gateway.ufhost.com [61.152.239.71]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F3CB9B7F2; Tue, 27 Dec 2022 03:59:09 -0800 (PST) Received: from EXMBX166.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX166", Issuer "EXMBX166" (not verified)) by fd01.gateway.ufhost.com (Postfix) with ESMTP id F3FDE24DBDE; Tue, 27 Dec 2022 19:59:07 +0800 (CST) Received: from EXMBX168.cuchost.com (172.16.6.78) by EXMBX166.cuchost.com (172.16.6.76) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Tue, 27 Dec 2022 19:59:07 +0800 Received: from williamqiu-virtual-machine.starfivetech.com (171.223.208.138) by EXMBX168.cuchost.com (172.16.6.78) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Tue, 27 Dec 2022 19:59:06 +0800 From: William Qiu To: , CC: Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , Hal Feng , Subject: [PATCH v2 2/3] mmc: starfive: Add sdio/emmc driver support Date: Tue, 27 Dec 2022 19:58:55 +0800 Message-ID: <20221227115856.460790-3-william.qiu@starfivetech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221227115856.460790-1-william.qiu@starfivetech.com> References: <20221227115856.460790-1-william.qiu@starfivetech.com> MIME-Version: 1.0 X-Originating-IP: [171.223.208.138] X-ClientProxiedBy: EXCAS066.cuchost.com (172.16.6.26) To EXMBX168.cuchost.com (172.16.6.78) X-YovoleRuleAgent: yovoleflag X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,RCVD_IN_MSPIKE_H2, SPF_HELO_PASS,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1753368427620286836?= X-GMAIL-MSGID: =?utf-8?q?1753368427620286836?= Add sdio/emmc driver support for StarFive JH7110 soc. Signed-off-by: William Qiu --- MAINTAINERS | 6 + drivers/mmc/host/Kconfig | 10 ++ drivers/mmc/host/Makefile | 1 + drivers/mmc/host/dw_mmc-starfive.c | 185 +++++++++++++++++++++++++++++ 4 files changed, 202 insertions(+) create mode 100644 drivers/mmc/host/dw_mmc-starfive.c diff --git a/MAINTAINERS b/MAINTAINERS index a70c1d0f303e..2b46ef07f5dc 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -19623,6 +19623,12 @@ F: Documentation/devicetree/bindings/reset/starfive,jh7100-reset.yaml F: drivers/reset/starfive/ F: include/dt-bindings/reset/starfive* +STARFIVE JH7110 MMC/SD/SDIO DRIVER +M: William Qiu +S: Maintained +F: Documentation/devicetree/bindings/mmc/starfive* +F: drivers/mmc/dw_mmc-starfive.c + STATIC BRANCH/CALL M: Peter Zijlstra M: Josh Poimboeuf diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig index fb1062a6394c..b87262503403 100644 --- a/drivers/mmc/host/Kconfig +++ b/drivers/mmc/host/Kconfig @@ -871,6 +871,16 @@ config MMC_DW_ROCKCHIP Synopsys DesignWare Memory Card Interface driver. Select this option for platforms based on RK3066, RK3188 and RK3288 SoC's. +config MMC_DW_STARFIVE + tristate "StarFive specific extensions for Synopsys DW Memory Card Interface" + depends on SOC_STARFIVE + depends on MMC_DW + select MMC_DW_PLTFM + help + This selects support for StarFive JH7110 SoC specific extensions to the + Synopsys DesignWare Memory Card Interface driver. Select this option + for platforms based on StarFive JH7110 SoC. + config MMC_SH_MMCIF tristate "SuperH Internal MMCIF support" depends on SUPERH || ARCH_RENESAS || COMPILE_TEST diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile index 4e4ceb32c4b4..32c0e5564b9a 100644 --- a/drivers/mmc/host/Makefile +++ b/drivers/mmc/host/Makefile @@ -56,6 +56,7 @@ obj-$(CONFIG_MMC_DW_HI3798CV200) += dw_mmc-hi3798cv200.o obj-$(CONFIG_MMC_DW_K3) += dw_mmc-k3.o obj-$(CONFIG_MMC_DW_PCI) += dw_mmc-pci.o obj-$(CONFIG_MMC_DW_ROCKCHIP) += dw_mmc-rockchip.o +obj-$(CONFIG_MMC_DW_STARFIVE) += dw_mmc-starfive.o obj-$(CONFIG_MMC_SH_MMCIF) += sh_mmcif.o obj-$(CONFIG_MMC_JZ4740) += jz4740_mmc.o obj-$(CONFIG_MMC_VUB300) += vub300.o diff --git a/drivers/mmc/host/dw_mmc-starfive.c b/drivers/mmc/host/dw_mmc-starfive.c new file mode 100644 index 000000000000..e4d0bdb40d12 --- /dev/null +++ b/drivers/mmc/host/dw_mmc-starfive.c @@ -0,0 +1,185 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * StarFive Designware Mobile Storage Host Controller Driver + * + * Copyright (c) 2022 StarFive Technology Co., Ltd. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "dw_mmc.h" +#include "dw_mmc-pltfm.h" + +#define ALL_INT_CLR 0x1ffff +#define MAX_DELAY_CHAIN 32 + +struct starfive_priv { + struct device *dev; + struct regmap *reg_syscon; + u32 syscon_offset; + u32 syscon_shift; + u32 syscon_mask; +}; + +static void dw_mci_starfive_set_ios(struct dw_mci *host, struct mmc_ios *ios) +{ + int ret; + unsigned int clock; + + if (ios->timing == MMC_TIMING_MMC_DDR52 || ios->timing == MMC_TIMING_UHS_DDR50) { + clock = (ios->clock > 50000000 && ios->clock <= 52000000) ? 100000000 : ios->clock; + ret = clk_set_rate(host->ciu_clk, clock); + if (ret) + dev_dbg(host->dev, "Use an external frequency divider %uHz\n", ios->clock); + host->bus_hz = clk_get_rate(host->ciu_clk); + } else { + dev_dbg(host->dev, "Using the internal divider\n"); + } +} + +static int dw_mci_starfive_execute_tuning(struct dw_mci_slot *slot, + u32 opcode) +{ + static const int grade = MAX_DELAY_CHAIN; + struct dw_mci *host = slot->host; + struct starfive_priv *priv = host->priv; + int rise_point = -1, fall_point = -1; + int err, prev_err; + int i; + bool found = 0; + u32 regval; + + /* Use grade as the max delay chain, and use the rise_point and + * fall_point to ensure the best sampling point of a data input + * signals. + */ + for (i = 0; i < grade; i++) { + regval = i << priv->syscon_shift; + err = regmap_update_bits(priv->reg_syscon, priv->syscon_offset, + priv->syscon_mask, regval); + if (err) + return err; + mci_writel(host, RINTSTS, ALL_INT_CLR); + + err = mmc_send_tuning(slot->mmc, opcode, NULL); + if (!err) + found = 1; + + if (i > 0) { + if (err && !prev_err) + fall_point = i - 1; + if (!err && prev_err) + rise_point = i; + } + + if (rise_point != -1 && fall_point != -1) + goto tuning_out; + + prev_err = err; + err = 0; + } + +tuning_out: + if (found) { + if (rise_point == -1) + rise_point = 0; + if (fall_point == -1) + fall_point = grade - 1; + if (fall_point < rise_point) { + if ((rise_point + fall_point) > + (grade - 1)) + i = fall_point / 2; + else + i = (rise_point + grade - 1) / 2; + } else { + i = (rise_point + fall_point) / 2; + } + + regval = i << priv->syscon_shift; + err = regmap_update_bits(priv->reg_syscon, priv->syscon_offset, + priv->syscon_mask, regval); + if (err) + return err; + mci_writel(host, RINTSTS, ALL_INT_CLR); + + dev_info(host->dev, "Found valid delay chain! use it [delay=%d]\n", i); + } else { + dev_err(host->dev, "No valid delay chain! use default\n"); + err = -EINVAL; + } + + mci_writel(host, RINTSTS, ALL_INT_CLR); + return err; +} + +static int dw_mci_starfive_parse_dt(struct dw_mci *host) +{ + struct of_phandle_args args; + struct starfive_priv *priv; + int ret; + + priv = devm_kzalloc(host->dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + ret = of_parse_phandle_with_fixed_args(host->dev->of_node, + "starfive,syscon", 3, 0, &args); + if (ret) { + dev_err(host->dev, "Failed to parse starfive,syscon\n"); + return -EINVAL; + } + + priv->reg_syscon = syscon_node_to_regmap(args.np); + of_node_put(args.np); + if (IS_ERR(priv->reg_syscon)) + return PTR_ERR(priv->reg_syscon); + + priv->syscon_offset = args.args[0]; + priv->syscon_shift = args.args[1]; + priv->syscon_mask = args.args[2]; + + host->priv = priv; + + return 0; +} + +static const struct dw_mci_drv_data starfive_data = { + .common_caps = MMC_CAP_CMD23, + .set_ios = dw_mci_starfive_set_ios, + .parse_dt = dw_mci_starfive_parse_dt, + .execute_tuning = dw_mci_starfive_execute_tuning, +}; + +static const struct of_device_id dw_mci_starfive_match[] = { + { .compatible = "starfive,jh7110-mmc", + .data = &starfive_data }, + {}, +}; +MODULE_DEVICE_TABLE(of, dw_mci_starfive_match); + +static int dw_mci_starfive_probe(struct platform_device *pdev) +{ + return dw_mci_pltfm_register(pdev, &starfive_data);; +} + +static struct platform_driver dw_mci_starfive_driver = { + .probe = dw_mci_starfive_probe, + .remove = dw_mci_pltfm_remove, + .driver = { + .name = "dwmmc_starfive", + .probe_type = PROBE_PREFER_ASYNCHRONOUS, + .of_match_table = dw_mci_starfive_match, + }, +}; +module_platform_driver(dw_mci_starfive_driver); + +MODULE_DESCRIPTION("StarFive JH7110 Specific DW-MSHC Driver Extension"); +MODULE_LICENSE("GPL"); +MODULE_ALIAS("platform:dwmmc_starfive"); From patchwork Tue Dec 27 11:58:56 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: William Qiu X-Patchwork-Id: 36838 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4e01:0:0:0:0:0 with SMTP id p1csp1354575wrt; Tue, 27 Dec 2022 04:01:04 -0800 (PST) X-Google-Smtp-Source: AMrXdXt4K8kmshVnDf9s6t/OAzfwIg1sVksW0PUvoKhnjhiO1WhEL4V2FZqxrCy8+AH0J0ZNrr2h X-Received: by 2002:a17:906:19db:b0:7c0:8578:f4c0 with SMTP id h27-20020a17090619db00b007c08578f4c0mr16528073ejd.67.1672142464539; Tue, 27 Dec 2022 04:01:04 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1672142464; cv=none; d=google.com; s=arc-20160816; b=QJ775ak7P/kELoZsJbLr8U9KfTm3RH5mhpWQuD3xwvDp7i1k06gn4pTK7sBWh8igxH 1KlmXXLpOFvN2ZmkkGUrBJzswAoKKrulJ1ZcHP6w5tUZj5iEiALP9WF76MGqWhV8U5uP 0SbZcx0dL1auYeC07S843NWah50KILH0X/+0HOAUEXmkwrLSErHEjFvcg33hC0WNtjJU zPcOwvHSmmz2QAiU2pJ3TXBSI8j8+v4xljO+ecrxZhypTrxQhP/8jfbDZg6PRKX6zC12 K6yH+jgGppPaz5Jt+alt+FU0OD/85D1xIAqrZPxwr41+s/Fi8j3xtKQWx/d8TwBPDDXI Rb7w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=kOds+8Xx9Q1qAChTnXHFHGSRZoeIGtv9K/JQvlpZY7o=; b=alCYtEbXdINOTqIle8/Cf4JJB5deRHWvB4kIKHBQMhEtm5dL9aApB5/gKvcJSNBqa0 /J/n1yInkEsirtjKE4DrWh7zFWxOAmBhjSUS5uW/pCNWINcyIvlGXRWzxCQVgd+Q18jg FossMpV4eIrNr76rTgZUsAU7GG6XhIu+AmeBrxpvWIQmPS6YNUHjwFp77jeIwwC6nypg 1jCrZBCA7BkLnptjEBZGrOALoCeUCOKSwqYn5wQ57c78lhvAHgmxGFYv/5EkT9A/Xhw3 B2a0GTDHYai5qoCVRAYYuVn1UK83WGr/8ob2+MHoGsJLe17eIH8MmDc65PQjg3m892EW yFkw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id gt7-20020a1709072d8700b007d6105e0adasi11670889ejc.12.2022.12.27.04.00.40; Tue, 27 Dec 2022 04:01:04 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231204AbiL0MAT convert rfc822-to-8bit (ORCPT + 99 others); Tue, 27 Dec 2022 07:00:19 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44156 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232060AbiL0L70 (ORCPT ); Tue, 27 Dec 2022 06:59:26 -0500 Received: from fd01.gateway.ufhost.com (fd01.gateway.ufhost.com [61.152.239.71]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9020BB860; Tue, 27 Dec 2022 03:59:15 -0800 (PST) Received: from EXMBX165.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX165", Issuer "EXMBX165" (not verified)) by fd01.gateway.ufhost.com (Postfix) with ESMTP id 9C2A824DF1F; Tue, 27 Dec 2022 19:59:08 +0800 (CST) Received: from EXMBX168.cuchost.com (172.16.6.78) by EXMBX165.cuchost.com (172.16.6.75) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Tue, 27 Dec 2022 19:59:08 +0800 Received: from williamqiu-virtual-machine.starfivetech.com (171.223.208.138) by EXMBX168.cuchost.com (172.16.6.78) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Tue, 27 Dec 2022 19:59:07 +0800 From: William Qiu To: , CC: Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , Hal Feng , Subject: [PATCH v2 3/3] riscv: dts: starfive: Add mmc node Date: Tue, 27 Dec 2022 19:58:56 +0800 Message-ID: <20221227115856.460790-4-william.qiu@starfivetech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221227115856.460790-1-william.qiu@starfivetech.com> References: <20221227115856.460790-1-william.qiu@starfivetech.com> MIME-Version: 1.0 X-Originating-IP: [171.223.208.138] X-ClientProxiedBy: EXCAS066.cuchost.com (172.16.6.26) To EXMBX168.cuchost.com (172.16.6.78) X-YovoleRuleAgent: yovoleflag X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,RCVD_IN_MSPIKE_H2, SPF_HELO_PASS,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1753368457123851093?= X-GMAIL-MSGID: =?utf-8?q?1753368457123851093?= This adds the mmc node for the StarFive JH7110 SoC. Set sdioo node to emmc and set sdio1 node to sd. Signed-off-by: William Qiu --- .../jh7110-starfive-visionfive-v2.dts | 25 ++++++++++++ arch/riscv/boot/dts/starfive/jh7110.dtsi | 38 +++++++++++++++++++ 2 files changed, 63 insertions(+) diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-v2.dts b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-v2.dts index c8946cf3a268..d8244fd1f5a0 100644 --- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-v2.dts +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-v2.dts @@ -47,6 +47,31 @@ &clk_rtc { clock-frequency = <32768>; }; +&mmc0 { + max-frequency = <100000000>; + card-detect-delay = <300>; + bus-width = <8>; + cap-mmc-highspeed; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + non-removable; + cap-mmc-hw-reset; + post-power-on-delay-ms = <200>; + status = "okay"; +}; + +&mmc1 { + max-frequency = <100000000>; + card-detect-delay = <300>; + bus-width = <4>; + no-sdio; + no-mmc; + broken-cd; + cap-sd-highspeed; + post-power-on-delay-ms = <200>; + status = "okay"; +}; + &gmac0_rmii_refin { clock-frequency = <50000000>; }; diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi index c22e8f1d2640..08a780d2c0f4 100644 --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi @@ -331,6 +331,11 @@ aoncrg: clock-controller@17000000 { #reset-cells = <1>; }; + syscon: syscon@13030000 { + compatible = "starfive,syscon", "syscon"; + reg = <0x0 0x13030000 0x0 0x1000>; + }; + gpio: gpio@13040000 { compatible = "starfive,jh7110-sys-pinctrl"; reg = <0x0 0x13040000 0x0 0x10000>; @@ -433,5 +438,38 @@ uart5: serial@12020000 { reg-shift = <2>; status = "disabled"; }; + + /* unremovable emmc as mmcblk0 */ + mmc0: mmc@16010000 { + compatible = "starfive,jh7110-mmc"; + reg = <0x0 0x16010000 0x0 0x10000>; + clocks = <&syscrg JH7110_SYSCLK_SDIO0_AHB>, + <&syscrg JH7110_SYSCLK_SDIO0_SDCARD>; + clock-names = "biu","ciu"; + resets = <&syscrg JH7110_SYSRST_SDIO0_AHB>; + reset-names = "reset"; + interrupts = <74>; + fifo-depth = <32>; + fifo-watermark-aligned; + data-addr = <0>; + starfive,syscon = <&syscon 0x14 0x1a 0x7c000000>; + status = "disabled"; + }; + + mmc1: mmc@16020000 { + compatible = "starfive,jh7110-mmc"; + reg = <0x0 0x16020000 0x0 0x10000>; + clocks = <&syscrg JH7110_SYSCLK_SDIO1_AHB>, + <&syscrg JH7110_SYSCLK_SDIO1_SDCARD>; + clock-names = "biu","ciu"; + resets = <&syscrg JH7110_SYSRST_SDIO1_AHB>; + reset-names = "reset"; + interrupts = <75>; + fifo-depth = <32>; + fifo-watermark-aligned; + data-addr = <0>; + starfive,syscon = <&syscon 0x9c 0x1 0x3e>; + status = "disabled"; + }; }; };