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[2620:137:e000::1:20]) by mx.google.com with ESMTP id bo24-20020a0564020b3800b004672d4e4ff2si7809696edb.171.2022.12.26.06.41.17; Mon, 26 Dec 2022 06:41:41 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=fail header.i=@metrotek.ru header.s=mail header.b=ZzCcLf00; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229547AbiLZOhI (ORCPT + 99 others); Mon, 26 Dec 2022 09:37:08 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45934 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232053AbiLZO3K (ORCPT ); Mon, 26 Dec 2022 09:29:10 -0500 Received: from mail.pr-group.ru (mail.pr-group.ru [178.18.215.3]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 856A364E4; Mon, 26 Dec 2022 06:26:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=metrotek.ru; s=mail; h=from:subject:date:message-id:to:cc:mime-version:content-transfer-encoding: in-reply-to:references; bh=MFUNeq3Y8GcJH9bDlEKq9WaByHZjyHz4SS+VcCmqW98=; b=ZzCcLf00xTnENl4pK52cRM4CMgKnlRLuvCZhJ6z9pbipcXFnIt7gmZGta0MaWXPPqncO9e487S/wk gBX4cCXBmulvb6KwlL6C6udNAgpYZ5gF6lq55YAnyPABe1Vt6WmjgC2e86kPL6W8+UvKVfeKYGEzvi NCbZGkxNRkoDnusd8egqoLhOQF3zxvkJp14GE/sxLHpFI6/ipepK6/JvOoF5j9PFy405eXM71rnkh2 cdiU6zFl1bg/w3PH8ghwxMDS8JHsioCn0xinLFxKgC6Tb8d7bqjjiwLZ70HrV3+8PNABuVWLd6UKla SS2mAZFKoYTfGt0HpL517HI24ZjN5Zg== X-Kerio-Anti-Spam: Build: [Engines: 2.16.5.1460, Stamp: 3], Multi: [Enabled, t: (0.000011,0.030556)], BW: [Enabled, t: (0.000024,0.000002)], RTDA: [Enabled, t: (0.084856), Hit: No, Details: v2.42.0; Id: 15.52k1a6.1gl7d6sdq.3c; mclb], total: 0(700) X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Level: X-Footer: bWV0cm90ZWsucnU= Received: from localhost.localdomain ([78.37.162.181]) (authenticated user i.bornyakov@metrotek.ru) by mail.pr-group.ru with ESMTPSA (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256 bits)); Mon, 26 Dec 2022 17:25:56 +0300 From: Ivan Bornyakov To: Conor Dooley , Moritz Fischer , Wu Hao , Xu Yilun , Tom Rix Cc: Ivan Bornyakov , linux-fpga@vger.kernel.org, linux-kernel@vger.kernel.org, system@metrotek.ru Subject: [PATCH v2 1/3] fpga: microchip-spi: move SPI I/O buffers out of stack Date: Mon, 26 Dec 2022 17:23:24 +0300 Message-Id: <20221226142326.8111-2-i.bornyakov@metrotek.ru> X-Mailer: git-send-email 2.38.2 In-Reply-To: <20221226142326.8111-1-i.bornyakov@metrotek.ru> References: <20221226142326.8111-1-i.bornyakov@metrotek.ru> MIME-Version: 1.0 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1753287965126641130?= X-GMAIL-MSGID: =?utf-8?q?1753287965126641130?= As spi-summary doc says: > I/O buffers use the usual Linux rules, and must be DMA-safe. > You'd normally allocate them from the heap or free page pool. > Don't use the stack, or anything that's declared "static". Replace spi_write() with spi_write_then_read(), which is dma-safe for on-stack buffers. Use allocated buffers for transfers used in spi_sync_transfer(). Although everything works OK with stack-located I/O buffers, better follow the doc to be safe. Fixes: 5f8d4a900830 ("fpga: microchip-spi: add Microchip MPF FPGA manager") Signed-off-by: Ivan Bornyakov --- drivers/fpga/microchip-spi.c | 93 ++++++++++++++++++------------------ 1 file changed, 47 insertions(+), 46 deletions(-) diff --git a/drivers/fpga/microchip-spi.c b/drivers/fpga/microchip-spi.c index 7436976ea904..e72fedd93a27 100644 --- a/drivers/fpga/microchip-spi.c +++ b/drivers/fpga/microchip-spi.c @@ -42,46 +42,55 @@ struct mpf_priv { struct spi_device *spi; bool program_mode; + u8 tx __aligned(ARCH_KMALLOC_MINALIGN); + u8 rx __aligned(ARCH_KMALLOC_MINALIGN); }; -static int mpf_read_status(struct spi_device *spi) +static int mpf_read_status(struct mpf_priv *priv) { - u8 status = 0, status_command = MPF_SPI_READ_STATUS; - struct spi_transfer xfers[2] = { 0 }; - int ret; - /* * HW status is returned on MISO in the first byte after CS went * active. However, first reading can be inadequate, so we submit * two identical SPI transfers and use result of the later one. */ - xfers[0].tx_buf = &status_command; - xfers[1].tx_buf = &status_command; - xfers[0].rx_buf = &status; - xfers[1].rx_buf = &status; - xfers[0].len = 1; - xfers[1].len = 1; - xfers[0].cs_change = 1; + struct spi_transfer xfers[2] = { + { + .tx_buf = &priv->tx, + .rx_buf = &priv->rx, + .len = 1, + .cs_change = 1, + }, { + .tx_buf = &priv->tx, + .rx_buf = &priv->rx, + .len = 1, + }, + }; + u8 status; + int ret; + + priv->tx = MPF_SPI_READ_STATUS; + + ret = spi_sync_transfer(priv->spi, xfers, 2); + if (ret) + return ret; - ret = spi_sync_transfer(spi, xfers, 2); + status = priv->rx; if ((status & MPF_STATUS_SPI_VIOLATION) || (status & MPF_STATUS_SPI_ERROR)) - ret = -EIO; + return -EIO; - return ret ? : status; + return status; } static enum fpga_mgr_states mpf_ops_state(struct fpga_manager *mgr) { struct mpf_priv *priv = mgr->priv; - struct spi_device *spi; bool program_mode; int status; - spi = priv->spi; program_mode = priv->program_mode; - status = mpf_read_status(spi); + status = mpf_read_status(priv); if (!program_mode && !status) return FPGA_MGR_STATE_OPERATING; @@ -186,12 +195,12 @@ static int mpf_ops_parse_header(struct fpga_manager *mgr, } /* Poll HW status until busy bit is cleared and mask bits are set. */ -static int mpf_poll_status(struct spi_device *spi, u8 mask) +static int mpf_poll_status(struct mpf_priv *priv, u8 mask) { int status, retries = MPF_STATUS_POLL_RETRIES; while (retries--) { - status = mpf_read_status(spi); + status = mpf_read_status(priv); if (status < 0) return status; @@ -205,32 +214,32 @@ static int mpf_poll_status(struct spi_device *spi, u8 mask) return -EBUSY; } -static int mpf_spi_write(struct spi_device *spi, const void *buf, size_t buf_size) +static int mpf_spi_write(struct mpf_priv *priv, const void *buf, size_t buf_size) { - int status = mpf_poll_status(spi, 0); + int status = mpf_poll_status(priv, 0); if (status < 0) return status; - return spi_write(spi, buf, buf_size); + return spi_write_then_read(priv->spi, buf, buf_size, NULL, 0); } -static int mpf_spi_write_then_read(struct spi_device *spi, +static int mpf_spi_write_then_read(struct mpf_priv *priv, const void *txbuf, size_t txbuf_size, void *rxbuf, size_t rxbuf_size) { const u8 read_command[] = { MPF_SPI_READ_DATA }; int ret; - ret = mpf_spi_write(spi, txbuf, txbuf_size); + ret = mpf_spi_write(priv, txbuf, txbuf_size); if (ret) return ret; - ret = mpf_poll_status(spi, MPF_STATUS_READY); + ret = mpf_poll_status(priv, MPF_STATUS_READY); if (ret < 0) return ret; - return spi_write_then_read(spi, read_command, sizeof(read_command), + return spi_write_then_read(priv->spi, read_command, sizeof(read_command), rxbuf, rxbuf_size); } @@ -242,7 +251,6 @@ static int mpf_ops_write_init(struct fpga_manager *mgr, const u8 isc_en_command[] = { MPF_SPI_ISC_ENABLE }; struct mpf_priv *priv = mgr->priv; struct device *dev = &mgr->dev; - struct spi_device *spi; u32 isc_ret = 0; int ret; @@ -251,9 +259,7 @@ static int mpf_ops_write_init(struct fpga_manager *mgr, return -EOPNOTSUPP; } - spi = priv->spi; - - ret = mpf_spi_write_then_read(spi, isc_en_command, sizeof(isc_en_command), + ret = mpf_spi_write_then_read(priv, isc_en_command, sizeof(isc_en_command), &isc_ret, sizeof(isc_ret)); if (ret || isc_ret) { dev_err(dev, "Failed to enable ISC: spi_ret %d, isc_ret %u\n", @@ -261,7 +267,7 @@ static int mpf_ops_write_init(struct fpga_manager *mgr, return -EFAULT; } - ret = mpf_spi_write(spi, program_mode, sizeof(program_mode)); + ret = mpf_spi_write(priv, program_mode, sizeof(program_mode)); if (ret) { dev_err(dev, "Failed to enter program mode: %d\n", ret); return ret; @@ -274,11 +280,9 @@ static int mpf_ops_write_init(struct fpga_manager *mgr, static int mpf_ops_write(struct fpga_manager *mgr, const char *buf, size_t count) { - u8 spi_frame_command[] = { MPF_SPI_FRAME }; struct spi_transfer xfers[2] = { 0 }; struct mpf_priv *priv = mgr->priv; struct device *dev = &mgr->dev; - struct spi_device *spi; int ret, i; if (count % MPF_SPI_FRAME_SIZE) { @@ -287,18 +291,18 @@ static int mpf_ops_write(struct fpga_manager *mgr, const char *buf, size_t count return -EINVAL; } - spi = priv->spi; - - xfers[0].tx_buf = spi_frame_command; - xfers[0].len = sizeof(spi_frame_command); + xfers[0].tx_buf = &priv->tx; + xfers[0].len = 1; for (i = 0; i < count / MPF_SPI_FRAME_SIZE; i++) { xfers[1].tx_buf = buf + i * MPF_SPI_FRAME_SIZE; xfers[1].len = MPF_SPI_FRAME_SIZE; - ret = mpf_poll_status(spi, 0); - if (ret >= 0) - ret = spi_sync_transfer(spi, xfers, ARRAY_SIZE(xfers)); + ret = mpf_poll_status(priv, 0); + if (ret >= 0) { + priv->tx = MPF_SPI_FRAME; + ret = spi_sync_transfer(priv->spi, xfers, ARRAY_SIZE(xfers)); + } if (ret) { dev_err(dev, "Failed to write bitstream frame %d/%zu\n", @@ -317,12 +321,9 @@ static int mpf_ops_write_complete(struct fpga_manager *mgr, const u8 release_command[] = { MPF_SPI_RELEASE }; struct mpf_priv *priv = mgr->priv; struct device *dev = &mgr->dev; - struct spi_device *spi; int ret; - spi = priv->spi; - - ret = mpf_spi_write(spi, isc_dis_command, sizeof(isc_dis_command)); + ret = mpf_spi_write(priv, isc_dis_command, sizeof(isc_dis_command)); if (ret) { dev_err(dev, "Failed to disable ISC: %d\n", ret); return ret; @@ -330,7 +331,7 @@ static int mpf_ops_write_complete(struct fpga_manager *mgr, usleep_range(1000, 2000); - ret = mpf_spi_write(spi, release_command, sizeof(release_command)); + ret = mpf_spi_write(priv, release_command, sizeof(release_command)); if (ret) { dev_err(dev, "Failed to exit program mode: %d\n", ret); return ret; From patchwork Mon Dec 26 14:23:25 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ivan Bornyakov X-Patchwork-Id: 36650 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4e01:0:0:0:0:0 with SMTP id p1csp946835wrt; Mon, 26 Dec 2022 06:51:24 -0800 (PST) X-Google-Smtp-Source: AMrXdXvnTVbKPJcNJr1WvR4v19KP/Z73eT+11Dxw7dgBdrtwB7r4bkJQfHN2WQpRf5DrTTOvoANa X-Received: by 2002:a17:907:8b09:b0:7c1:bb5:5704 with SMTP id sz9-20020a1709078b0900b007c10bb55704mr16431945ejc.26.1672066284407; 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Replace it with read_poll_timeout() macro. Fixes: 5f8d4a900830 ("fpga: microchip-spi: add Microchip MPF FPGA manager") Signed-off-by: Ivan Bornyakov --- drivers/fpga/microchip-spi.c | 25 +++++++++++-------------- 1 file changed, 11 insertions(+), 14 deletions(-) diff --git a/drivers/fpga/microchip-spi.c b/drivers/fpga/microchip-spi.c index e72fedd93a27..f3ddfab87499 100644 --- a/drivers/fpga/microchip-spi.c +++ b/drivers/fpga/microchip-spi.c @@ -6,6 +6,7 @@ #include #include #include +#include #include #include #include @@ -33,7 +34,7 @@ #define MPF_BITS_PER_COMPONENT_SIZE 22 -#define MPF_STATUS_POLL_RETRIES 10000 +#define MPF_STATUS_POLL_TIMEOUT (2 * USEC_PER_SEC) #define MPF_STATUS_BUSY BIT(0) #define MPF_STATUS_READY BIT(1) #define MPF_STATUS_SPI_VIOLATION BIT(2) @@ -197,21 +198,17 @@ static int mpf_ops_parse_header(struct fpga_manager *mgr, /* Poll HW status until busy bit is cleared and mask bits are set. */ static int mpf_poll_status(struct mpf_priv *priv, u8 mask) { - int status, retries = MPF_STATUS_POLL_RETRIES; + int ret, status; - while (retries--) { - status = mpf_read_status(priv); - if (status < 0) - return status; - - if (status & MPF_STATUS_BUSY) - continue; - - if (!mask || (status & mask)) - return status; - } + ret = read_poll_timeout(mpf_read_status, status, + (status < 0) || + (!(status & MPF_STATUS_BUSY) && + (!mask || (status & mask))), + 0, MPF_STATUS_POLL_TIMEOUT, false, priv); + if (ret < 0) + return ret; - return -EBUSY; + return status; } static int mpf_spi_write(struct mpf_priv *priv, const void *buf, size_t buf_size) From patchwork Mon Dec 26 14:23:26 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ivan Bornyakov X-Patchwork-Id: 36649 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4e01:0:0:0:0:0 with SMTP id p1csp946833wrt; Mon, 26 Dec 2022 06:51:24 -0800 (PST) X-Google-Smtp-Source: AMrXdXtKIaXb34I8/0MdkaYo16kT8T2XyawE2wHM/cpl6D9DO/1AVPplnR1D42aE2wNlI18T6zF6 X-Received: by 2002:a17:907:c203:b0:7ad:84c7:503a with SMTP id ti3-20020a170907c20300b007ad84c7503amr15538869ejc.72.1672066284056; Mon, 26 Dec 2022 06:51:24 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1672066284; cv=none; d=google.com; s=arc-20160816; b=bYzZpC/UfC0tP7tZe2v8KiV7OWoXWGSPrqrpWr1ZFk+wAIRZ6iqQ2QAwhPGR9KQeI0 hKO9uQyLIVecREdpPCbRrxnDS75JyS5x7Qrjo1l98/zDkG6NJQQw8Ri4u5pTK8cYivHF odymrLG6ElGgMqsgNFvX3XUE0IcRkYb+17LjdQj/HukhomkyPzf9MY7z9R/PcQH5KhQn jvBrMY0k7ufJPyWMIqZDPcGjyoHPOYP4j8rU5Ebzd5yuY7rC+Z3nvX/Elk5Noi8LEcR4 cCMaMJpP6xOlqygycZu8RvKFYzr+iGhRzQ5GUMPOd5i+3ym+dx1yZ2MtcWlATg0o9Olz sdbQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=RuIiOKKec4Vi6brkpGWS3hysRoxv6XIDdPnDhv7wgL4=; b=TWJIrItUcjflo51pzEXQi8441t+1cewSsTNi8GmnHEQclWDjRcAXCALAHtZbKbEPAi bFG+d5G7yXM0V6xh/sRq2pebSfGTCDm8DcfgEWri0UIK5Xa+xsjAcZcSnG68bTwlqnPZ gzTJ2s8Flfhpx1FnKY40Iil3hB2j5I8SsZ009Hcw/p+4/yv681slo1aZftij/yuJMxzC 036UZKIt3c9Ph3ayed6TxTsM3cO1luPdAOiX+91NImfFdnVpvGbUC4SkVlBpscmigagM 3dl80RXvIszI54E6gsLrPlVnlUpUOQKLUvPtPIn/2rSZnlSZk6XurPctgupyh0kbpZBt cZog== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@metrotek.ru header.s=mail header.b=Hy78NZ8S; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id h7-20020a056402094700b0046b2b37ff70si7939206edz.631.2022.12.26.06.51.00; Mon, 26 Dec 2022 06:51:24 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=fail header.i=@metrotek.ru header.s=mail header.b=Hy78NZ8S; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231937AbiLZOhK (ORCPT + 99 others); Mon, 26 Dec 2022 09:37:10 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46056 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232046AbiLZO3K (ORCPT ); Mon, 26 Dec 2022 09:29:10 -0500 Received: from mail.pr-group.ru (mail.pr-group.ru [178.18.215.3]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 27B8464E6; Mon, 26 Dec 2022 06:26:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=metrotek.ru; s=mail; h=from:subject:date:message-id:to:cc:mime-version:content-transfer-encoding: in-reply-to:references; bh=OPFaov/D+WEk0jxM8EJ2ri7LYnuA1DGPmJbwAx21UNU=; b=Hy78NZ8SqKHl8t6eaajQ7/qYdr5N2hZ73fPnyOtJzn1boVp3Asa2dn/LYrzqhvL/Fwcm0VbqO70xF Qe8ULUll2rLuz9CI/mEEqcYYGg0XgVY9hllvgjFVa/tztAf9tzABpyJGZ3WVoFCT/UWEqSyYvv8XRn aSDYBjC/43eos7wds50TX+TToG/BZyFQtj79XNGu6gYhsDZUuUTzkQkEiqJx3FWn4J0BkESM17okfK Fw9wBKcz/O5WxzoaGC2Nnf4ffx37F7Y9xDGIf8Wpvy82SwkQigzNy8mtYZnVXizb+ioeCCKATuExtV 3N/3sPipGxQQjjx2amWHYk/bAuE9dpw== X-Kerio-Anti-Spam: Build: [Engines: 2.16.5.1460, Stamp: 3], Multi: [Enabled, t: (0.000008,0.010166)], BW: [Enabled, t: (0.000023,0.000001)], RTDA: [Enabled, t: (0.126371), Hit: No, Details: v2.42.0; Id: 15.52k53i.1gl7d6ud3.2p; mclb], total: 0(700) X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Level: X-Footer: bWV0cm90ZWsucnU= Received: from localhost.localdomain ([78.37.162.181]) (authenticated user i.bornyakov@metrotek.ru) by mail.pr-group.ru with ESMTPSA (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256 bits)); Mon, 26 Dec 2022 17:25:59 +0300 From: Ivan Bornyakov To: Conor Dooley , Moritz Fischer , Wu Hao , Xu Yilun , Tom Rix Cc: Ivan Bornyakov , linux-fpga@vger.kernel.org, linux-kernel@vger.kernel.org, system@metrotek.ru Subject: [PATCH v2 3/3] fpga: microchip-spi: separate data frame write routine Date: Mon, 26 Dec 2022 17:23:26 +0300 Message-Id: <20221226142326.8111-4-i.bornyakov@metrotek.ru> X-Mailer: git-send-email 2.38.2 In-Reply-To: <20221226142326.8111-1-i.bornyakov@metrotek.ru> References: <20221226142326.8111-1-i.bornyakov@metrotek.ru> MIME-Version: 1.0 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1753288576190583251?= X-GMAIL-MSGID: =?utf-8?q?1753288576190583251?= mpf_ops_write() function writes bitstream data to the FPGA by a smaller frames. Introduce mpf_spi_frame_write() function which is for writing a single data frame and use it in mpf_ops_write(). No functional changes intended. Signed-off-by: Ivan Bornyakov --- drivers/fpga/microchip-spi.c | 36 +++++++++++++++++++++++------------- 1 file changed, 23 insertions(+), 13 deletions(-) diff --git a/drivers/fpga/microchip-spi.c b/drivers/fpga/microchip-spi.c index f3ddfab87499..f8a6872c865b 100644 --- a/drivers/fpga/microchip-spi.c +++ b/drivers/fpga/microchip-spi.c @@ -275,9 +275,30 @@ static int mpf_ops_write_init(struct fpga_manager *mgr, return 0; } +static int mpf_spi_frame_write(struct mpf_priv *priv, const char *buf) +{ + struct spi_transfer xfers[2] = { + { + .tx_buf = &priv->tx, + .len = 1, + }, { + .tx_buf = buf, + .len = MPF_SPI_FRAME_SIZE, + }, + }; + int ret; + + ret = mpf_poll_status(priv, 0); + if (ret < 0) + return ret; + + priv->tx = MPF_SPI_FRAME; + + return spi_sync_transfer(priv->spi, xfers, ARRAY_SIZE(xfers)); +} + static int mpf_ops_write(struct fpga_manager *mgr, const char *buf, size_t count) { - struct spi_transfer xfers[2] = { 0 }; struct mpf_priv *priv = mgr->priv; struct device *dev = &mgr->dev; int ret, i; @@ -288,19 +309,8 @@ static int mpf_ops_write(struct fpga_manager *mgr, const char *buf, size_t count return -EINVAL; } - xfers[0].tx_buf = &priv->tx; - xfers[0].len = 1; - for (i = 0; i < count / MPF_SPI_FRAME_SIZE; i++) { - xfers[1].tx_buf = buf + i * MPF_SPI_FRAME_SIZE; - xfers[1].len = MPF_SPI_FRAME_SIZE; - - ret = mpf_poll_status(priv, 0); - if (ret >= 0) { - priv->tx = MPF_SPI_FRAME; - ret = spi_sync_transfer(priv->spi, xfers, ARRAY_SIZE(xfers)); - } - + ret = mpf_spi_frame_write(priv, buf + i * MPF_SPI_FRAME_SIZE); if (ret) { dev_err(dev, "Failed to write bitstream frame %d/%zu\n", i, count / MPF_SPI_FRAME_SIZE);