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Miller" , Eric Dumazet , "Jakub Kicinski" , Paolo Abeni , Maxime Coquelin , Richard Cochran , , , , , "Biao Huang" , Subject: [PATCH v5 1/2] stmmac: dwmac-mediatek: enable 2ns delay only for special cases Date: Fri, 23 Dec 2022 09:50:28 +0800 Message-ID: <20221223015029.24978-2-biao.huang@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221223015029.24978-1-biao.huang@mediatek.com> References: <20221223015029.24978-1-biao.huang@mediatek.com> MIME-Version: 1.0 X-MTK: N X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS, SPF_PASS,UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1752967812079422884?= X-GMAIL-MSGID: =?utf-8?q?1752967812079422884?= In current driver, MAC will always enable 2ns delay in RGMII mode, but that will lead to transmission failures for "rgmii-id"/"rgmii-txid" cases. Modify the implementation of fix_mac_speed() to ensure the 2ns delay will only take effect for "rgmii-rxid"/"rgmii" cases, then user can choose phy-mode freely. Fixes: f2d356a6ab71 ("stmmac: dwmac-mediatek: add support for mt8195") Signed-off-by: Biao Huang Reviewed-by: AngeloGioacchino Del Regno --- drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c index d42e1afb6521..cde4fb81d596 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c @@ -447,7 +447,9 @@ static void mt8195_fix_mac_speed(void *priv, unsigned int speed) { struct mediatek_dwmac_plat_data *priv_plat = priv; - if ((phy_interface_mode_is_rgmii(priv_plat->phy_mode))) { + switch (priv_plat->phy_mode) { + case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_RXID: /* prefer 2ns fixed delay which is controlled by TXC_PHASE_CTRL, * when link speed is 1Gbps with RGMII interface, * Fall back to delay macro circuit for 10/100Mbps link speed. @@ -462,6 +464,9 @@ static void mt8195_fix_mac_speed(void *priv, unsigned int speed) MT8195_RGMII_TXC_PHASE_CTRL); else mt8195_set_delay(priv_plat); + break; + default: + break; } } From patchwork Fri Dec 23 01:50:29 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?QmlhbyBIdWFuZyAo6buE5b2qKQ==?= X-Patchwork-Id: 36057 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:e747:0:0:0:0:0 with SMTP id c7csp87849wrn; Thu, 22 Dec 2022 17:56:12 -0800 (PST) X-Google-Smtp-Source: AMrXdXs6UsNqftvtZSBStXPCLDJecMi40b3vNnXBAhvtP2h8QIYD8uL+QwYuPH6AUpuL/sFkWNso X-Received: by 2002:a17:907:c78e:b0:7c5:f0a3:5d71 with SMTP id tz14-20020a170907c78e00b007c5f0a35d71mr6642300ejc.0.1671760572708; Thu, 22 Dec 2022 17:56:12 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1671760572; cv=none; d=google.com; s=arc-20160816; b=DJzwwl7fljHA4w5vBs8Y+VrR1mSXF8aN2MuH5akfBgkHkfG4gvGk5X9uuJ6xSIFla4 ehNy/eRjvsdianbZkC7I73RmTUvVtuPJWYwJUa2sU6l6V7QjUG9hplxaV3WMgpoOEill LfxV+OGXlZJNeVTrHLX0o+RCIRtYcStROG2FXU7gTDgm3/lG1Qqut2Dme/Z3CT9Whe9F HGEgmaQ1NbM22RbQEjOfqXanfGwI/99LAWm6IKBIqWADyHF2KvKyLm1XwLRZ9KUCMAT/ PZnCXEb5HGYuimJ9r4afiZNYxJvYJbwhMk74b8yF7ipoPXDrq8d/X3Y/hE+0ZCo+2ZgP hlaQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=RetU9plkC6PlzdhyrPl9diuDAf2ccELX3EGs8VyzYRM=; b=txONpb0bNpIknR59qhC8LiEVGGthardqJNVf4lytH1Se1ZB5HIim4PDVIHIq59DScU BqlJrUk4x9k8OD6WhJlvCFtOFhNg+reGWLurxM30Id2TronZLB1nsS00M9pCoEC50Jdv 4JAVkfvGjx8GElnL3eh01mRhjt5hRAon/lyVqI3yNWHu/st1S1gispYa2uB3yTj4kUTB 2TPEWPTFGbERNgWBH8nnKKhQ5UcPKfVvspEJ5133vnP/XxeGKwOwB+YazeQ248RPw95+ G52KUW4yAxlF2tRVBnk3KsJ0mlpuhGWxAYboT8/eM4aJzsypsZu3DyFzss1LVOHOIQ/C QYmQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@mediatek.com header.s=dk header.b="D52o/J04"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=mediatek.com Received: from out1.vger.email (out1.vger.email. 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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Maxime Coquelin , Richard Cochran , , , , , Biao Huang , Subject: [PATCH v5 2/2] arm64: dts: mt8195: Add Ethernet controller Date: Fri, 23 Dec 2022 09:50:29 +0800 Message-ID: <20221223015029.24978-3-biao.huang@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221223015029.24978-1-biao.huang@mediatek.com> References: <20221223015029.24978-1-biao.huang@mediatek.com> MIME-Version: 1.0 X-MTK: N X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS, SPF_PASS,UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1752967921521951433?= X-GMAIL-MSGID: =?utf-8?q?1752968014275015011?= Add Ethernet controller node for mt8195. Signed-off-by: Biao Huang Reviewed-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8195-demo.dts | 81 ++++++++++++++++++ arch/arm64/boot/dts/mediatek/mt8195.dtsi | 86 ++++++++++++++++++++ 2 files changed, 167 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8195-demo.dts b/arch/arm64/boot/dts/mediatek/mt8195-demo.dts index 4fbd99eb496a..2e6979c47aa6 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195-demo.dts +++ b/arch/arm64/boot/dts/mediatek/mt8195-demo.dts @@ -258,6 +258,66 @@ &mt6359_vsram_others_ldo_reg { }; &pio { + eth_default_pins: eth-default-pins { + pins-txd { + pinmux = , + , + , + ; + drive-strength = ; + }; + pins-cc { + pinmux = , + , + , + ; + drive-strength = ; + }; + pins-rxd { + pinmux = , + , + , + ; + }; + pins-mdio { + pinmux = , + ; + input-enable; + }; + pins-power { + pinmux = , + ; + output-high; + }; + }; + + eth_sleep_pins: eth-sleep-pins { + pins-txd { + pinmux = , + , + , + ; + }; + pins-cc { + pinmux = , + , + , + ; + }; + pins-rxd { + pinmux = , + , + , + ; + }; + pins-mdio { + pinmux = , + ; + input-disable; + bias-disable; + }; + }; + gpio_keys_pins: gpio-keys-pins { pins { pinmux = ; @@ -434,6 +494,27 @@ &xhci0 { status = "okay"; }; +ð { + phy-mode ="rgmii-id"; + phy-handle = <ðernet_phy0>; + snps,reset-gpio = <&pio 93 GPIO_ACTIVE_HIGH>; + snps,reset-delays-us = <0 10000 10000>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <ð_default_pins>; + pinctrl-1 = <ð_sleep_pins>; + status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + ethernet_phy0: ethernet-phy@1 { + compatible = "ethernet-phy-id001c.c916"; + reg = <0x1>; + }; + }; +}; + &xhci1 { vusb33-supply = <&mt6359_vusb_ldo_reg>; status = "okay"; diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi index 5d31536f4c48..b90d38d87aa4 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -1046,6 +1046,92 @@ spis1: spi@1101e000 { status = "disabled"; }; + eth: ethernet@11021000 { + compatible = "mediatek,mt8195-gmac", "snps,dwmac-5.10a"; + reg = <0 0x11021000 0 0x4000>; + interrupts = ; + interrupt-names = "macirq"; + clock-names = "axi", + "apb", + "mac_main", + "ptp_ref", + "rmii_internal", + "mac_cg"; + clocks = <&pericfg_ao CLK_PERI_AO_ETHERNET>, + <&pericfg_ao CLK_PERI_AO_ETHERNET_BUS>, + <&topckgen CLK_TOP_SNPS_ETH_250M>, + <&topckgen CLK_TOP_SNPS_ETH_62P4M_PTP>, + <&topckgen CLK_TOP_SNPS_ETH_50M_RMII>, + <&pericfg_ao CLK_PERI_AO_ETHERNET_MAC>; + assigned-clocks = <&topckgen CLK_TOP_SNPS_ETH_250M>, + <&topckgen CLK_TOP_SNPS_ETH_62P4M_PTP>, + <&topckgen CLK_TOP_SNPS_ETH_50M_RMII>; + assigned-clock-parents = <&topckgen CLK_TOP_ETHPLL_D2>, + <&topckgen CLK_TOP_ETHPLL_D8>, + <&topckgen CLK_TOP_ETHPLL_D10>; + power-domains = <&spm MT8195_POWER_DOMAIN_ETHER>; + mediatek,pericfg = <&infracfg_ao>; + snps,axi-config = <&stmmac_axi_setup>; + snps,mtl-rx-config = <&mtl_rx_setup>; + snps,mtl-tx-config = <&mtl_tx_setup>; + snps,txpbl = <16>; + snps,rxpbl = <16>; + snps,clk-csr = <0>; + status = "disabled"; + + stmmac_axi_setup: stmmac-axi-config { + snps,wr_osr_lmt = <0x7>; + snps,rd_osr_lmt = <0x7>; + snps,blen = <0 0 0 0 16 8 4>; + }; + + mtl_rx_setup: rx-queues-config { + snps,rx-queues-to-use = <4>; + snps,rx-sched-sp; + queue0 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x0>; + }; + queue1 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x0>; + }; + queue2 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x0>; + }; + queue3 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x0>; + }; + }; + + mtl_tx_setup: tx-queues-config { + snps,tx-queues-to-use = <4>; + snps,tx-sched-wrr; + queue0 { + snps,weight = <0x10>; + snps,dcb-algorithm; + snps,priority = <0x0>; + }; + queue1 { + snps,weight = <0x11>; + snps,dcb-algorithm; + snps,priority = <0x1>; + }; + queue2 { + snps,weight = <0x12>; + snps,dcb-algorithm; + snps,priority = <0x2>; + }; + queue3 { + snps,weight = <0x13>; + snps,dcb-algorithm; + snps,priority = <0x3>; + }; + }; + }; + xhci0: usb@11200000 { compatible = "mediatek,mt8195-xhci", "mediatek,mtk-xhci";