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So his entry can be removed. Adding myself as the co-maintainer since I took over the PCIe RC driver maintainership from Stanimir. Acked-by: Krzysztof Kozlowski Signed-off-by: Manivannan Sadhasivam --- Documentation/devicetree/bindings/pci/qcom,pcie.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml index 54f07852d279..02450fb26bb9 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml @@ -8,7 +8,7 @@ title: Qualcomm PCI express root complex maintainers: - Bjorn Andersson - - Stanimir Varbanov + - Manivannan Sadhasivam description: | Qualcomm PCIe root complex controller is based on the Synopsys DesignWare From patchwork Thu Dec 22 13:31:22 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 35770 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:e747:0:0:0:0:0 with SMTP id c7csp327221wrn; Thu, 22 Dec 2022 05:34:58 -0800 (PST) X-Google-Smtp-Source: AMrXdXv9VpjTw2/tNklnmTFUH/PfhhIUgvG09eCtzeASaLBA323HQFxEaI+l/6kBuvu02Cfb6qE/ X-Received: by 2002:a17:906:704a:b0:83f:cbc0:1b30 with SMTP id r10-20020a170906704a00b0083fcbc01b30mr3915969ejj.10.1671716098084; Thu, 22 Dec 2022 05:34:58 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1671716098; cv=none; d=google.com; s=arc-20160816; b=F9QFf7ls892idvkGz2C5Zvn++guiXNvEvRf+D0uk27yoWo0HRA6h/xohdxIE68zpW5 TJN7SkvoDuJgxT10fF1uiLGM2/3rNrkXqkZfyUwguduaxut5FrYVucgaUWd4zw5oGpv9 3PNxGHVI8b9fbayohlx8hjK1MQNfKXUSXjri1+yTmnGO4WCOojF482ShvAQzP8TgWbju O2uxNKu6pc6frzwjBE6cA8BUk5wU5supWExWxVGDbeV5kQsBHyUzN+2u9og7rj4ddcjm wNqYeTRbfw/+GDl/UG6i8zBuvv8RU6axpy4BXkSsHud39toy1IJgjzHXLdUN6rO0nnW8 4m3g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=jOniKrb0GQ9WjhoUQcWo7o7ITGbjHRsfNlny869TuiA=; b=YOsNqTIicQbNzPVbs1qurtjoAFkhf2EFXR2mU975FVMQde4xJZE+gDmgS6W+3AloLb 4lBL8EoEqBQd0SlS4QVMEwJB8fRckbeTY5cUsg6VSjZdZQnJOA+jZMJlpLB8PMC1tlHg GsrxirddY1q7yjkWw2uwO9/xyf8XAB442218gtQy2T1UszOmbBOLaqLtmDZNkwaSUuBh chlCAfstOZxO3Xbr32F6CP60sPOlFfjD2TH5OmyH65OzLLa371LC0HBp3O8d9u0/S2G6 8qNfzoTjOAFTjh8UAwFyeUvSveX+eStD3a/ZUnnkY/M+8NsDMwqkn7f0047lnX83cOIy q4Uw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=RXfCUc6D; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. 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Currently, the binding only documents the internal MSI implementation. Let's document the GIC-ITS imeplementation by making use of msi-map and msi-map-mask properties. Only one of the implementation should be used at a time. Signed-off-by: Manivannan Sadhasivam --- Documentation/devicetree/bindings/pci/qcom,pcie.yaml | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml index 02450fb26bb9..10fec6a7abfc 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml @@ -104,14 +104,20 @@ required: - compatible - reg - reg-names - - interrupts - - interrupt-names - - "#interrupt-cells" - interrupt-map-mask - interrupt-map - clocks - clock-names +oneOf: + - required: + - interrupts + - interrupt-names + - "#interrupt-cells" + - required: + - msi-map + - msi-map-mask + allOf: - $ref: /schemas/pci/pci-bus.yaml# - if: From patchwork Thu Dec 22 13:31:23 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 35771 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:e747:0:0:0:0:0 with SMTP id c7csp327357wrn; Thu, 22 Dec 2022 05:35:12 -0800 (PST) X-Google-Smtp-Source: AMrXdXuGBss0/Oi0yAtJVeNTFRN+Vrjztr3uCIC9ABDgsict62k5QQP9JxUBZCDFfSMyD9HQzMW9 X-Received: by 2002:a17:906:99d1:b0:7c1:12ef:bf52 with SMTP id s17-20020a17090699d100b007c112efbf52mr4249586ejn.3.1671716112486; Thu, 22 Dec 2022 05:35:12 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1671716112; cv=none; d=google.com; s=arc-20160816; b=MMJGusUS5VDTulJIxsJbrGejMNepynW2ICilSqeeIuX5CQ8vNf3RKmiiyN4Cem237k tg9nhU8br+Fc0ivz4YDunvdlmVlXsdLBlRmcW/HQSv+KBoAf1JlH/LDOulFH7F0gI7cm v4wPNhhHbQ+YbQDz5t8CBqz49UNfKTZyRhnIueeqQ0Fqfa/UZsjtrpaQW820yQ7l/gIH t5/MqGvCqDuz+RxLrz7VDH7scL70uaDXuwqo1dk6z3MTME7D/zG8ATgfSP4QNg1JUdM/ BfXNkxOf8jYPjttx5vbHQvdXkYmwgYIrw/nJcsbybzt8V7LrWnoK8qay0jX6m6NO4Rll 3cXw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=2xuFcNG+Lmd6sCAcx37A72Ddu+m83mu9NNvxLdsptSw=; b=egkgE5tAk7hYYYbMyE5S1NCFeCmcX7hpRwUFJeW4mHnXOFlp9lPd6m3kEL9lxs8ELE qGRrbo/fhozj0fukeZlfgJ4EfKWNXvPMNTrERoF2p1uG4W55kPHJ4acoTMxeqbkChaCs NI5L0f1GLUKbqs/ETbghL1wG2K2XdCcTgpTbIhcK05rtHfTWn9clUPCwJaT2icY2MUA5 8cZErZ/rocauTtyN6K3jacTe3WSLIDYPcAQlhP52W1aO/8tglvLNQ4k78vTAY3o/2cW1 ChO9sPLA3IJDBbgbxGfppY9V7pHpqyuBsLKK9rphdZrmhtsswEBoTVgkW7MDirbNbBWf ebNw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=nA0ejjbc; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. 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Add support for it. Currently, BDF (0:0.0) and BDF (1:0.0) are enabled and with the msi-map-mask of 0xff00, all the 32 devices under these two busses can share the same Device ID. The GIC-ITS MSI implementation provides an advantage over internal MSI implementation using Locality-specific Peripheral Interrupts (LPI) that would allow MSIs to be targeted for each CPU core. It should be noted that the MSIs for BDF (1:0.0) only works with Device ID of 0x5980 and 0x5a00. Hence, the IDs are swapped. Signed-off-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 20 ++++++++++++++------ 1 file changed, 14 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 570475040d95..c4dd5838fac6 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -1733,9 +1733,13 @@ pcie0: pci@1c00000 { ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>, <0x02000000 0x0 0x60300000 0 0x60300000 0x0 0x3d00000>; - interrupts = ; - interrupt-names = "msi"; - #interrupt-cells = <1>; + /* + * MSIs for BDF (1:0.0) only works with Device ID 0x5980. + * Hence, the IDs are swapped. + */ + msi-map = <0x0 &gic_its 0x5981 0x1>, + <0x100 &gic_its 0x5980 0x1>; + msi-map-mask = <0xff00>; interrupt-map-mask = <0 0 0 0x7>; interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ @@ -1842,9 +1846,13 @@ pcie1: pci@1c08000 { ranges = <0x01000000 0x0 0x40200000 0 0x40200000 0x0 0x100000>, <0x02000000 0x0 0x40300000 0 0x40300000 0x0 0x1fd00000>; - interrupts = ; - interrupt-names = "msi"; - #interrupt-cells = <1>; + /* + * MSIs for BDF (1:0.0) only works with Device ID 0x5a00. + * Hence, the IDs are swapped. + */ + msi-map = <0x0 &gic_its 0x5a01 0x1>, + <0x100 &gic_its 0x5a00 0x1>; + msi-map-mask = <0xff00>; interrupt-map-mask = <0 0 0 0x7>; interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */