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[2620:137:e000::1:20]) by mx.google.com with ESMTP id i15-20020a1709061ccf00b007c16b3feca1si12588500ejh.903.2022.12.21.23.24.00; Wed, 21 Dec 2022 23:24:23 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@mediatek.com header.s=dk header.b="Ne9/n5LG"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=mediatek.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235003AbiLVHXa (ORCPT + 99 others); Thu, 22 Dec 2022 02:23:30 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39586 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229630AbiLVHXT (ORCPT ); Thu, 22 Dec 2022 02:23:19 -0500 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2C52622BCA; Wed, 21 Dec 2022 23:23:12 -0800 (PST) X-UUID: 0e8f84e0bd994a7ab49d5c7f9525bfd2-20221222 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=3+kQOOAluuad33TOX24wc74FGuc0dtmBWE3kGB5GO5g=; b=Ne9/n5LG0lPSF20yEj5u775CnHz3cUuRu6cQQ7/C5klQXEvtO+ZXaE0rRZdXukf2VdLhaxbTwA3kewlbAI0OlhpTFqNFkYgwTpbOFRsWepYc25ttMW1HNWHOnibEllwTQgGzpQI9RBwK28hpIqFBPIT9auWohhjV/GtoM5JsWGQ=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.14,REQID:a686a633-2368-4332-8fd4-6d59d33d7299,IP:0,U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:95,FILE:0,BULK:0,RULE:Release_Ham,ACTION :release,TS:95 X-CID-INFO: VERSION:1.1.14,REQID:a686a633-2368-4332-8fd4-6d59d33d7299,IP:0,URL :0,TC:0,Content:0,EDM:0,RT:0,SF:95,FILE:0,BULK:0,RULE:Spam_GS981B3D,ACTION :quarantine,TS:95 X-CID-META: VersionHash:dcaaed0,CLOUDID:030da6f3-ff42-4fb0-b929-626456a83c14,B ulkID:221222152308CAQ3QGKX,BulkQuantity:0,Recheck:0,SF:38|28|17|19|48,TC:n il,Content:0,EDM:-3,IP:nil,URL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0 X-UUID: 0e8f84e0bd994a7ab49d5c7f9525bfd2-20221222 Received: from mtkmbs10n1.mediatek.inc [(172.21.101.34)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 795364170; Thu, 22 Dec 2022 15:23:06 +0800 Received: from mtkmbs13n1.mediatek.inc (172.21.101.193) by mtkmbs11n1.mediatek.inc (172.21.101.185) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Thu, 22 Dec 2022 15:23:05 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs13n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Thu, 22 Dec 2022 15:23:05 +0800 From: Tinghan Shen To: Rob Herring , Krzysztof Kozlowski , Matthias Brugger , Pierre-Louis Bossart , Liam Girdwood , Peter Ujfalusi , Bard Liao , Ranjani Sridharan , Kai Vehmanen , Daniel Baluta , Mark Brown , Jaroslav Kysela , Takashi Iwai , Tinghan Shen , Chunxu Li , Dan Carpenter , YC Hung , AngeloGioacchino Del Regno , Allen-KH Cheng CC: , , , , , , Subject: [PATCH v1 1/3] dt-bindings: dsp: mediatek: Add mt8188 dsp compatible Date: Thu, 22 Dec 2022 15:21:48 +0800 Message-ID: <20221222072150.10627-2-tinghan.shen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20221222072150.10627-1-tinghan.shen@mediatek.com> References: <20221222072150.10627-1-tinghan.shen@mediatek.com> MIME-Version: 1.0 X-MTK: N X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS, SPF_PASS,UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1752898065065766767?= X-GMAIL-MSGID: =?utf-8?q?1752898065065766767?= Add support of the single-core HiFi5 audio DSP on MediaTek MT8188 SoC for pre- and post- audio processing. Signed-off-by: Tinghan Shen Reviewed-by: AngeloGioacchino Del Regno Acked-by: Krzysztof Kozlowski --- .../devicetree/bindings/dsp/mediatek,mt8186-dsp.yaml | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/dsp/mediatek,mt8186-dsp.yaml b/Documentation/devicetree/bindings/dsp/mediatek,mt8186-dsp.yaml index 3e63f79890b4..88575da1e6d5 100644 --- a/Documentation/devicetree/bindings/dsp/mediatek,mt8186-dsp.yaml +++ b/Documentation/devicetree/bindings/dsp/mediatek,mt8186-dsp.yaml @@ -15,7 +15,9 @@ description: | properties: compatible: - const: mediatek,mt8186-dsp + enum: + - mediatek,mt8186-dsp + - mediatek,mt8188-dsp reg: items: From patchwork Thu Dec 22 07:21:49 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Tinghan Shen X-Patchwork-Id: 35633 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:e747:0:0:0:0:0 with SMTP id c7csp182353wrn; Wed, 21 Dec 2022 23:24:18 -0800 (PST) X-Google-Smtp-Source: AMrXdXte2WK36j6mDxP3ddDqJ9kkaVXBvn4FY49o5hFAHxTnjWk6buZm0zJ2VkOWdQZpYvUE5S4U X-Received: by 2002:aa7:d14d:0:b0:46a:cc65:5797 with SMTP id r13-20020aa7d14d000000b0046acc655797mr3922712edo.8.1671693858795; Wed, 21 Dec 2022 23:24:18 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1671693858; cv=none; d=google.com; s=arc-20160816; b=qsecPvi6QOgcCoipOx8vwtSSigo4axM9yTtx/Inq92jvtAZV27WgQ8ZccMzl7IVeYz sh5CwR2YntilqFnuu4Lu0kchxJM5SMQ6oQXp9Cip3V0ZlaFLo2igaQQbSoP8oyvj1pDw 5pp0HIpRKEx9Lt8DfWbERrQ1c1CEixmzprzQXC0WbE1bNbNo1snjsGTmK+lCyMf+/LnQ +ea+eacvouUhoUYLSEEtooYuel3ItJzFLr34GEd7Af71W1r6jIdgaSTOqNOOP2D1fJsg kl+yUcHo+TI4WxfvV4VDCK8wpa4uSoczaSn+EFcv245fOe1O7sj2tTOUnAe/HRQ4tam0 ASdw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=lFz2Y/xxwkpdqewHbikoBaP7PZtSmri9F7IdaOcr4HM=; b=ahwMJVTJH/2VEuvri4eLTLO8Ku0rBQU1d1T0cWB/dlFNrkVmLB6U9qLnrrUoVO6r8L YNL+UIugkC41IUYX4zgl7znohE1j1s1yNa6beWtiKjI1mgVv6ndSaPnzA67MXGiMU3SU ShlGIWkLfEWRTeoCoEGnFFE4mzBeVYPp3qCAPCct4c3sRTQN8ih6t6CAicjygoI1q6gX a42tyB+hQvOaaGlWNGpK7x3yX3fbXpWmrHigU8b2jVUVW7er2gVRWaOEdNWJ4BUuPDOC drOZDLMpf5My9CV0uWDKcImXt6wI7l6AHzCd4JRQzt+ZySLVTwhrGEpofYJJKvlT6Pjq qOjQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@mediatek.com header.s=dk header.b=XTWknGrG; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=mediatek.com Received: from out1.vger.email (out1.vger.email. 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MT8188 ADSP integrates with a single core Cadence HiFi-5 DSP. The IPC communication between AP and DSP is based on shared DRAM and mailbox interrupt. The change in the mt8186.h is compatible on both mt8186 and mt8188. The register controls booting the DSP core with the default address or the user specified address. Both mt8186 and mt8188 should boot with the user specified boot in the driver. The usage of the register is the same on both SoC, but the control bit is different on mt8186 and mt8188, which is bit 1 on mt8186 and bit 0 on mt8188. Configure the redundant bit has noside effect on both SoCs. Signed-off-by: Tinghan Shen Reviewed-by: Péter Ujfalusi Reviewed-by: Pierre-Louis Bossart Reviewed-by: Ranjani Sridharan --- sound/soc/sof/mediatek/mt8186/mt8186.c | 17 +++++++++++++++++ sound/soc/sof/mediatek/mt8186/mt8186.h | 3 ++- 2 files changed, 19 insertions(+), 1 deletion(-) diff --git a/sound/soc/sof/mediatek/mt8186/mt8186.c b/sound/soc/sof/mediatek/mt8186/mt8186.c index 79da25725987..af0dfc2fc4cc 100644 --- a/sound/soc/sof/mediatek/mt8186/mt8186.c +++ b/sound/soc/sof/mediatek/mt8186/mt8186.c @@ -625,8 +625,25 @@ static const struct sof_dev_desc sof_of_mt8186_desc = { .ops = &sof_mt8186_ops, }; +static const struct sof_dev_desc sof_of_mt8188_desc = { + .ipc_supported_mask = BIT(SOF_IPC), + .ipc_default = SOF_IPC, + .default_fw_path = { + [SOF_IPC] = "mediatek/sof", + }, + .default_tplg_path = { + [SOF_IPC] = "mediatek/sof-tplg", + }, + .default_fw_filename = { + [SOF_IPC] = "sof-mt8188.ri", + }, + .nocodec_tplg_filename = "sof-mt8188-nocodec.tplg", + .ops = &sof_mt8186_ops, +}; + static const struct of_device_id sof_of_mt8186_ids[] = { { .compatible = "mediatek,mt8186-dsp", .data = &sof_of_mt8186_desc}, + { .compatible = "mediatek,mt8188-dsp", .data = &sof_of_mt8188_desc}, { } }; MODULE_DEVICE_TABLE(of, sof_of_mt8186_ids); diff --git a/sound/soc/sof/mediatek/mt8186/mt8186.h b/sound/soc/sof/mediatek/mt8186/mt8186.h index 98b2965e5ba6..886d687449e3 100644 --- a/sound/soc/sof/mediatek/mt8186/mt8186.h +++ b/sound/soc/sof/mediatek/mt8186/mt8186.h @@ -52,7 +52,8 @@ struct snd_sof_dev; #define ADSP_PRID 0x0 #define ADSP_ALTVEC_C0 0x04 #define ADSP_ALTVECSEL 0x0C -#define ADSP_ALTVECSEL_C0 BIT(1) +/* BIT(1) for mt8186. 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Signed-off-by: Tinghan Shen Reviewed-by: Péter Ujfalusi Reviewed-by: Pierre-Louis Bossart Reviewed-by: Ranjani Sridharan Reviewed-by: AngeloGioacchino Del Regno --- sound/soc/sof/mediatek/mt8186/mt8186.c | 3 +++ sound/soc/sof/mediatek/mt8195/mt8195.c | 1 + 2 files changed, 4 insertions(+) diff --git a/sound/soc/sof/mediatek/mt8186/mt8186.c b/sound/soc/sof/mediatek/mt8186/mt8186.c index af0dfc2fc4cc..dbea604ebc04 100644 --- a/sound/soc/sof/mediatek/mt8186/mt8186.c +++ b/sound/soc/sof/mediatek/mt8186/mt8186.c @@ -588,6 +588,9 @@ static struct snd_sof_dsp_ops sof_mt8186_ops = { .drv = mt8186_dai, .num_drv = ARRAY_SIZE(mt8186_dai), + /* Debug information */ + .debugfs_add_region_item = snd_sof_debugfs_add_region_item_iomem, + /* PM */ .suspend = mt8186_dsp_suspend, .resume = mt8186_dsp_resume, diff --git a/sound/soc/sof/mediatek/mt8195/mt8195.c b/sound/soc/sof/mediatek/mt8195/mt8195.c index 3c81e84fcecf..11ceff3acc54 100644 --- a/sound/soc/sof/mediatek/mt8195/mt8195.c +++ b/sound/soc/sof/mediatek/mt8195/mt8195.c @@ -642,6 +642,7 @@ static struct snd_sof_dsp_ops sof_mt8195_ops = { /* Debug information */ .dbg_dump = mt8195_adsp_dump, + .debugfs_add_region_item = snd_sof_debugfs_add_region_item_iomem, /* DAI drivers */ .drv = mt8195_dai,