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[62.178.148.172]) by smtp.gmail.com with ESMTPSA id i26-20020a170906a29a00b00782e3cf7277sm7328764ejz.120.2022.12.21.10.31.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 21 Dec 2022 10:31:05 -0800 (PST) From: Christoph Muellner To: gcc-patches@gcc.gnu.org, Kito Cheng , Jim Wilson , Palmer Dabbelt , Andrew Waterman , Philipp Tomsich , Jeff Law , Aaron Durbin , Vineet Gupta , Andrew de los Reyes , Eric Gouriou , Barna Ibrahim Cc: =?utf-8?q?Christoph_M=C3=BCllner?= Subject: [RFC PATCH] RISC-V: Add support for vector crypto extensions Date: Wed, 21 Dec 2022 19:31:03 +0100 Message-Id: <20221221183103.3800844-1-christoph.muellner@vrull.eu> X-Mailer: git-send-email 2.38.1 MIME-Version: 1.0 X-Spam-Status: No, score=-12.5 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, JMQ_SPF_NEUTRAL, KAM_MANYTO, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1752844148693599387?= X-GMAIL-MSGID: =?utf-8?q?1752849445067788464?= From: Christoph Müllner This series adds basic support for the vector crypto extensions: * Zvkb * Zvkg * Zvkh[a,b] * Zvkn * Zvksed * Zvksh The implementation follows the version 20221220 of the specification, which can be found here: https://github.com/riscv/riscv-crypto/releases/tag/v20221220 Note, that this specification is not frozen yet, meaning that incompatible changes are possible. Therefore, this patchset is marked as RFC and should not be considered for upstream inclusion. All extensions come with (passing) tests for the feature test macros. A Binutils patch series for vector crypto support can be found here: https://sourceware.org/pipermail/binutils/2022-December/125272.html Signed-off-by: Christoph Müllner --- gcc/common/config/riscv/riscv-common.cc | 16 ++++++++++++++++ gcc/config/riscv/riscv-opts.h | 16 ++++++++++++++++ gcc/config/riscv/riscv.opt | 3 +++ gcc/testsuite/gcc.target/riscv/zvkb.c | 13 +++++++++++++ gcc/testsuite/gcc.target/riscv/zvkg.c | 13 +++++++++++++ gcc/testsuite/gcc.target/riscv/zvkha.c | 13 +++++++++++++ gcc/testsuite/gcc.target/riscv/zvkhb.c | 13 +++++++++++++ gcc/testsuite/gcc.target/riscv/zvkn.c | 13 +++++++++++++ gcc/testsuite/gcc.target/riscv/zvksed.c | 13 +++++++++++++ gcc/testsuite/gcc.target/riscv/zvksh.c | 13 +++++++++++++ 10 files changed, 126 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/zvkb.c create mode 100644 gcc/testsuite/gcc.target/riscv/zvkg.c create mode 100644 gcc/testsuite/gcc.target/riscv/zvkha.c create mode 100644 gcc/testsuite/gcc.target/riscv/zvkhb.c create mode 100644 gcc/testsuite/gcc.target/riscv/zvkn.c create mode 100644 gcc/testsuite/gcc.target/riscv/zvksed.c create mode 100644 gcc/testsuite/gcc.target/riscv/zvksh.c diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc index 4b7f777c103..dfd654eea24 100644 --- a/gcc/common/config/riscv/riscv-common.cc +++ b/gcc/common/config/riscv/riscv-common.cc @@ -201,6 +201,14 @@ static const struct riscv_ext_version riscv_ext_version_table[] = {"zve64f", ISA_SPEC_CLASS_NONE, 1, 0}, {"zve64d", ISA_SPEC_CLASS_NONE, 1, 0}, + {"zvkb", ISA_SPEC_CLASS_NONE, 1, 0}, + {"zvkg", ISA_SPEC_CLASS_NONE, 1, 0}, + {"zvkha", ISA_SPEC_CLASS_NONE, 1, 0}, + {"zvkhb", ISA_SPEC_CLASS_NONE, 1, 0}, + {"zvkn", ISA_SPEC_CLASS_NONE, 1, 0}, + {"zvksed", ISA_SPEC_CLASS_NONE, 1, 0}, + {"zvksh", ISA_SPEC_CLASS_NONE, 1, 0}, + {"zvl32b", ISA_SPEC_CLASS_NONE, 1, 0}, {"zvl64b", ISA_SPEC_CLASS_NONE, 1, 0}, {"zvl128b", ISA_SPEC_CLASS_NONE, 1, 0}, @@ -1226,6 +1234,14 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] = {"zve64f", &gcc_options::x_riscv_vector_elen_flags, MASK_VECTOR_ELEN_FP_32}, {"zve64d", &gcc_options::x_riscv_vector_elen_flags, MASK_VECTOR_ELEN_FP_64}, + {"zvkb", &gcc_options::x_riscv_zvk_subext, MASK_ZVKB}, + {"zvkg", &gcc_options::x_riscv_zvk_subext, MASK_ZVKG}, + {"zvkha", &gcc_options::x_riscv_zvk_subext, MASK_ZVKHA}, + {"zvkhb", &gcc_options::x_riscv_zvk_subext, MASK_ZVKHB}, + {"zvkn", &gcc_options::x_riscv_zvk_subext, MASK_ZVKN}, + {"zvksed", &gcc_options::x_riscv_zvk_subext, MASK_ZVKSED}, + {"zvksh", &gcc_options::x_riscv_zvk_subext, MASK_ZVKSH}, + {"zvl32b", &gcc_options::x_riscv_zvl_flags, MASK_ZVL32B}, {"zvl64b", &gcc_options::x_riscv_zvl_flags, MASK_ZVL64B}, {"zvl128b", &gcc_options::x_riscv_zvl_flags, MASK_ZVL128B}, diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h index 25fd85b09b1..5b367bd194c 100644 --- a/gcc/config/riscv/riscv-opts.h +++ b/gcc/config/riscv/riscv-opts.h @@ -132,6 +132,22 @@ enum stack_protector_guard { #define TARGET_VECTOR_ELEN_FP_64 \ ((riscv_vector_elen_flags & MASK_VECTOR_ELEN_FP_64) != 0) +#define MASK_ZVKB (1 << 0) +#define MASK_ZVKG (1 << 1) +#define MASK_ZVKHA (1 << 2) +#define MASK_ZVKHB (1 << 3) +#define MASK_ZVKN (1 << 4) +#define MASK_ZVKSED (1 << 5) +#define MASK_ZVKSH (1 << 6) + +#define TARGET_ZVKB ((riscv_zvk_subext & MASK_ZVKB) != 0) +#define TARGET_ZVKG ((riscv_zvk_subext & MASK_ZVKG) != 0) +#define TARGET_ZVKHA ((riscv_zvk_subext & MASK_ZVKHA) != 0) +#define TARGET_ZVKHB ((riscv_zvk_subext & MASK_ZVKHB) != 0) +#define TARGET_ZVKN ((riscv_zvk_subext & MASK_ZVKN) != 0) +#define TARGET_ZVKSED ((riscv_zvk_subext & MASK_ZVKSED) != 0) +#define TARGET_ZVKSH ((riscv_zvk_subext & MASK_ZVKSH) != 0) + #define MASK_ZVL32B (1 << 0) #define MASK_ZVL64B (1 << 1) #define MASK_ZVL128B (1 << 2) diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt index 7c3ca48d1cc..ea24a80d734 100644 --- a/gcc/config/riscv/riscv.opt +++ b/gcc/config/riscv/riscv.opt @@ -218,6 +218,9 @@ int riscv_zk_subext TargetVariable int riscv_vector_elen_flags +TargetVariable +int riscv_zvk_subext + TargetVariable int riscv_zvl_flags diff --git a/gcc/testsuite/gcc.target/riscv/zvkb.c b/gcc/testsuite/gcc.target/riscv/zvkb.c new file mode 100644 index 00000000000..7116e98921c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/zvkb.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zvkb" { target { rv64 } } } */ +/* { dg-options "-march=rv32gc_zvkb" { target { rv32 } } } */ + +#ifndef __riscv_zvkb +#error Feature macro not defined +#endif + +int +foo (int a) +{ + return a; +} diff --git a/gcc/testsuite/gcc.target/riscv/zvkg.c b/gcc/testsuite/gcc.target/riscv/zvkg.c new file mode 100644 index 00000000000..1e2a05aa1d8 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/zvkg.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zvkg" { target { rv64 } } } */ +/* { dg-options "-march=rv32gc_zvkg" { target { rv32 } } } */ + +#ifndef __riscv_zvkg +#error Feature macro not defined +#endif + +int +foo (int a) +{ + return a; +} diff --git a/gcc/testsuite/gcc.target/riscv/zvkha.c b/gcc/testsuite/gcc.target/riscv/zvkha.c new file mode 100644 index 00000000000..ca4e8d4c561 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/zvkha.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zvkha" { target { rv64 } } } */ +/* { dg-options "-march=rv32gc_zvkha" { target { rv32 } } } */ + +#ifndef __riscv_zvkha +#error Feature macro not defined +#endif + +int +foo (int a) +{ + return a; +} diff --git a/gcc/testsuite/gcc.target/riscv/zvkhb.c b/gcc/testsuite/gcc.target/riscv/zvkhb.c new file mode 100644 index 00000000000..8fa25ff52ee --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/zvkhb.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zvkhb" { target { rv64 } } } */ +/* { dg-options "-march=rv32gc_zvkhb" { target { rv32 } } } */ + +#ifndef __riscv_zvkhb +#error Feature macro not defined +#endif + +int +foo (int a) +{ + return a; +} diff --git a/gcc/testsuite/gcc.target/riscv/zvkn.c b/gcc/testsuite/gcc.target/riscv/zvkn.c new file mode 100644 index 00000000000..3647936d9e9 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/zvkn.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zvkn" { target { rv64 } } } */ +/* { dg-options "-march=rv32gc_zvkn" { target { rv32 } } } */ + +#ifndef __riscv_zvkn +#error Feature macro not defined +#endif + +int +foo (int a) +{ + return a; +} diff --git a/gcc/testsuite/gcc.target/riscv/zvksed.c b/gcc/testsuite/gcc.target/riscv/zvksed.c new file mode 100644 index 00000000000..439b546bb8a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/zvksed.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zvksed" { target { rv64 } } } */ +/* { dg-options "-march=rv32gc_zvksed" { target { rv32 } } } */ + +#ifndef __riscv_zvksed +#error Feature macro not defined +#endif + +int +foo (int a) +{ + return a; +} diff --git a/gcc/testsuite/gcc.target/riscv/zvksh.c b/gcc/testsuite/gcc.target/riscv/zvksh.c new file mode 100644 index 00000000000..5359ca50281 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/zvksh.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zvksh" { target { rv64 } } } */ +/* { dg-options "-march=rv32gc_zvksh" { target { rv32 } } } */ + +#ifndef __riscv_zvksh +#error Feature macro not defined +#endif + +int +foo (int a) +{ + return a; +}