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[2620:137:e000::1:20]) by mx.google.com with ESMTP id hv15-20020a17090760cf00b007c1727f7c57si14288776ejc.243.2022.12.21.02.26.05; Wed, 21 Dec 2022 02:26:28 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=SOWxj1gF; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234821AbiLUKX2 (ORCPT + 99 others); Wed, 21 Dec 2022 05:23:28 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44968 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234730AbiLUKWQ (ORCPT ); Wed, 21 Dec 2022 05:22:16 -0500 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8D3511580B; Wed, 21 Dec 2022 02:21:35 -0800 (PST) Received: from pps.filterd (m0279870.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 2BL8vNY6003041; Wed, 21 Dec 2022 10:21:27 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=qcppdkim1; bh=lYRTcPZnMaOHFb77W6tF65D6R/PUwgVwpk+jemZHCCw=; b=SOWxj1gFFkdfSdKGbioAGYUJMuqwCJLEK3I0N5UsPAmnUx8SOp8wF0HHdvsTnhEHXcWw 1scKYNHIEYBlipvn/+fsnx1pnKimM05FLev6aDVCirqAveZ+EQSEzufeMDizff3gPmbz qOZwCiQJSOkG1QnXYbbjNRcYLCaw5eQYpQK8kbtT8zCaOM98vcZDxXdWtHn9oqoAD//O XOUKkMVhDTX7mqbpto7x/Ncm7N9UhMUFp8T79f4Cwp/p+BUtgfGwBDGW2QFK5bX050bs UZQN9mdBryNZ8OqIGh49PpNgdqJUQFPjqdOeFd1bflbZ51MeJ3j2qFowRB26p1OFXrBW FA== Received: from nalasppmta01.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3mk85xu40v-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 21 Dec 2022 10:21:27 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA01.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 2BLALQ8l008838 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 21 Dec 2022 10:21:26 GMT Received: from hu-srivasam-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.36; Wed, 21 Dec 2022 02:21:21 -0800 From: Srinivasa Rao Mandadapu To: , , , , , , , , , , , , , CC: Srinivasa Rao Mandadapu Subject: [PATCH 1/2] dt-bindings: clock: SC7280: Add resets for LPASS audio clock controller Date: Wed, 21 Dec 2022 15:51:00 +0530 Message-ID: <1671618061-6329-2-git-send-email-quic_srivasam@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1671618061-6329-1-git-send-email-quic_srivasam@quicinc.com> References: <1671618061-6329-1-git-send-email-quic_srivasam@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: YZGGUuPTK_Bs17zDCnln1OJQTUSCPvfj X-Proofpoint-GUID: YZGGUuPTK_Bs17zDCnln1OJQTUSCPvfj X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.923,Hydra:6.0.545,FMLib:17.11.122.1 definitions=2022-12-21_04,2022-12-21_01,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 mlxscore=0 lowpriorityscore=0 phishscore=0 mlxlogscore=999 bulkscore=0 adultscore=0 spamscore=0 suspectscore=0 malwarescore=0 impostorscore=0 clxscore=1015 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2212070000 definitions=main-2212210083 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1752818923157363091?= X-GMAIL-MSGID: =?utf-8?q?1752818923157363091?= Add support for LPASS audio clock gating for RX/TX/SWA core bus clocks for audioreach based SC7280 platforms. Signed-off-by: Srinivasa Rao Mandadapu --- Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscc.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscc.yaml b/Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscc.yaml index 6151fde..b9be5f1 100644 --- a/Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscc.yaml @@ -31,6 +31,9 @@ properties: '#clock-cells': const: 1 + '#reset-cells': + const: 1 + reg: items: - description: LPASS qdsp6ss register @@ -61,5 +64,6 @@ examples: clocks = <&gcc GCC_CFG_NOC_LPASS_CLK>; clock-names = "iface"; #clock-cells = <1>; + #reset-cells = <1>; }; ... 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Thus add the support for the reset clocks in audioreach based clock driver. Signed-off-by: Srinivasa Rao Mandadapu --- drivers/clk/qcom/lpasscc-sc7280.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/drivers/clk/qcom/lpasscc-sc7280.c b/drivers/clk/qcom/lpasscc-sc7280.c index 5c1e17b..d81d81b 100644 --- a/drivers/clk/qcom/lpasscc-sc7280.c +++ b/drivers/clk/qcom/lpasscc-sc7280.c @@ -12,10 +12,12 @@ #include #include +#include #include "clk-regmap.h" #include "clk-branch.h" #include "common.h" +#include "reset.h" static struct clk_branch lpass_top_cc_lpi_q6_axim_hs_clk = { .halt_reg = 0x0, @@ -102,6 +104,18 @@ static const struct qcom_cc_desc lpass_qdsp6ss_sc7280_desc = { .num_clks = ARRAY_SIZE(lpass_qdsp6ss_sc7280_clocks), }; +static const struct qcom_reset_map lpass_cc_sc7280_resets[] = { + [LPASS_AUDIO_SWR_RX_CGCR] = { 0xa0, 1 }, + [LPASS_AUDIO_SWR_TX_CGCR] = { 0xa8, 1 }, + [LPASS_AUDIO_SWR_WSA_CGCR] = { 0xb0, 1 }, +}; + +static const struct qcom_cc_desc lpass_audio_cc_reset_sc7280_desc = { + .config = &lpass_regmap_config, + .resets = lpass_cc_sc7280_resets, + .num_resets = ARRAY_SIZE(lpass_cc_sc7280_resets), +}; + static int lpass_cc_sc7280_probe(struct platform_device *pdev) { const struct qcom_cc_desc *desc; @@ -132,6 +146,10 @@ static int lpass_cc_sc7280_probe(struct platform_device *pdev) if (ret) goto destroy_pm_clk; + ret = qcom_cc_probe_by_index(pdev, 1, &lpass_audio_cc_reset_sc7280_desc); + if (ret) + goto destroy_pm_clk; + return 0; destroy_pm_clk: