From patchwork Wed Dec 21 05:51:44 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bhavya Kapoor X-Patchwork-Id: 35257 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:e747:0:0:0:0:0 with SMTP id c7csp3355262wrn; Tue, 20 Dec 2022 21:56:41 -0800 (PST) X-Google-Smtp-Source: AMrXdXvGuMeLWK8Gf3RUxlvcArDz+GqIPJsCKRtFf6ayIad0iYFZOv5xrTmH7pNoeAZlL+D1nygl X-Received: by 2002:aa7:9f0d:0:b0:576:daea:fed8 with SMTP id g13-20020aa79f0d000000b00576daeafed8mr952617pfr.29.1671602201406; Tue, 20 Dec 2022 21:56:41 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1671602201; cv=none; d=google.com; s=arc-20160816; b=WwKmsFs/tlcHkW0IWmkxRsC+XjWepaBn57F0mY0x8osLnqZ5CIyrIur3VVC+Hb45ZS Yac4iguFa8yqgkHLQ7zzlPQgolubdXQaEv/iuJr3Mdn3NQYjs8MGEKxg/Q6nw0it/bDn 9sixiVZ9eGuF+zb8z16KZGykXRNihzblaprK/SOHcbRA3hZOH4HQp6FtIVBvAQvlfiRL nTUywUp3ZJri4zSukzaQa8fQZ0jUXBv46v8+UFLEHcL2lNji9yafDBLD07YCPzOVyCqD ntUneqsu5D1TgyUUyPGpV3VzyH8C0B131vtdF4cVLAMK6iRNq5Vn0YZB8Kb0i329X+oD XWtA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :message-id:date:subject:cc:to:from:dkim-signature; bh=3S4ZeUleyG+PnGNO2verHlttc0+y095lVFPc0EWwtkw=; b=g4jgVYUc3WLKIGFk+SBzc0d/VBt0FytjrZ6lSUhQNdiJsK0MtrCUyOoHOUPt8JfWtG orOH3TSv85gf3Pe+Mbp9N6rSTCr4Cdc5fhcpHdjRsCcul2H/CmxsPBPmWjIrpiM27V+3 XUVMMLXwLkHWxIQ4FHMqrOKpe/f4tTvu8VpGG8smv3rpMUtXxV19k6aFl77/2SpNdD4T l0MIluCVKQabmwrg3mNHw61sMLvY7kUwxn3nxvjSZpgx8XaZFAoQAhazSEGQtjP8Qlj8 MLqpEwdmU6wRrcGxqoORkWxzFRbRsPpi8K5RcTcYBl/FJ7U3SEk3mX5xYEzdgAdkkqjv u78w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=bm9rMRRt; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id f14-20020a056a00238e00b0057fe4c0dbe6si6524403pfc.298.2022.12.20.21.56.28; Tue, 20 Dec 2022 21:56:41 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=bm9rMRRt; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234345AbiLUFwK (ORCPT + 99 others); Wed, 21 Dec 2022 00:52:10 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55248 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229652AbiLUFwI (ORCPT ); Wed, 21 Dec 2022 00:52:08 -0500 Received: from fllv0016.ext.ti.com (fllv0016.ext.ti.com [198.47.19.142]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C2C661DA6F; Tue, 20 Dec 2022 21:52:06 -0800 (PST) Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 2BL5pvaX088946; Tue, 20 Dec 2022 23:51:58 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1671601918; bh=3S4ZeUleyG+PnGNO2verHlttc0+y095lVFPc0EWwtkw=; h=From:To:CC:Subject:Date; b=bm9rMRRtJ/3eFqO0KuWIurW22/fIrzbeO/ymAzxLdvHUG+Zy34u/nh6S75g/yCVDq qgagMHxS0OEJf7A6L4Tp7QO9h3wM/FiH/8UrUISR6Y2YhNWAUH2BXB4bsn0nXwt6h8 U9ou12Wj085q+4MX2OcGnymuAJWrB3NSBCqRJhns= Received: from DFLE107.ent.ti.com (dfle107.ent.ti.com [10.64.6.28]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 2BL5pvOC027818 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 20 Dec 2022 23:51:57 -0600 Received: from DFLE104.ent.ti.com (10.64.6.25) by DFLE107.ent.ti.com (10.64.6.28) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16; Tue, 20 Dec 2022 23:51:57 -0600 Received: from fllv0040.itg.ti.com (10.64.41.20) by DFLE104.ent.ti.com (10.64.6.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16 via Frontend Transport; Tue, 20 Dec 2022 23:51:57 -0600 Received: from localhost (ileaxei01-snat.itg.ti.com [10.180.69.5]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 2BL5poGD003821; Tue, 20 Dec 2022 23:51:55 -0600 From: Bhavya Kapoor To: , CC: , , , , Subject: [PATCH v2] arm64: dts: ti: k3-j721s2: Add support for ADC nodes Date: Wed, 21 Dec 2022 11:21:44 +0530 Message-ID: <20221221055144.7181-1-b-kapoor@ti.com> X-Mailer: git-send-email 2.37.2 MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1748912574425926947?= X-GMAIL-MSGID: =?utf-8?q?1752801949693749009?= J721s2 has two instances of 8 channel ADCs in MCU domain. Add DT nodes for 8 channel ADCs for J721s2 SoC. Signed-off-by: Bhavya Kapoor --- Changelog v1 -> v2: - Updated Interrupt Values for tscadc .../dts/ti/k3-j721s2-common-proc-board.dts | 14 +++++++ .../boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi | 42 ++++++++++++++++++- 2 files changed, 55 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts index a7aa6cf08acd..67593aa69327 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts @@ -309,3 +309,17 @@ &mcu_mcan1 { pinctrl-0 = <&mcu_mcan1_pins_default>; phys = <&transceiver2>; }; + +&tscadc0 { + status = "okay"; + adc { + ti,adc-channels = <0 1 2 3 4 5 6 7>; + }; +}; + +&tscadc1 { + status = "okay"; + adc { + ti,adc-channels = <0 1 2 3 4 5 6 7>; + }; +}; \ No newline at end of file diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi index 0af242aa9816..8673eb1309c3 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi @@ -306,4 +306,44 @@ cpts@3d000 { ti,cpts-periodic-outputs = <2>; }; }; -}; + + tscadc0: tscadc@40200000 { + compatible = "ti,am3359-tscadc"; + reg = <0x0 0x40200000 0x0 0x1000>; + interrupts = ; + power-domains = <&k3_pds 0 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 0 0>; + assigned-clocks = <&k3_clks 0 2>; + assigned-clock-rates = <60000000>; + clock-names = "adc_tsc_fck"; + dmas = <&main_udmap 0x7400>, + <&main_udmap 0x7401>; + dma-names = "fifo0", "fifo1"; + status = "disabled"; + + adc { + #io-channel-cells = <1>; + compatible = "ti,am3359-adc"; + }; + }; + + tscadc1: tscadc@40210000 { + compatible = "ti,am3359-tscadc"; + reg = <0x0 0x40210000 0x0 0x1000>; + interrupts = ; + power-domains = <&k3_pds 1 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 1 0>; + assigned-clocks = <&k3_clks 1 2>; + assigned-clock-rates = <60000000>; + clock-names = "adc_tsc_fck"; + dmas = <&main_udmap 0x7402>, + <&main_udmap 0x7403>; + dma-names = "fifo0", "fifo1"; + status = "disabled"; + + adc { + #io-channel-cells = <1>; + compatible = "ti,am3359-adc"; + }; + }; + }; \ No newline at end of file