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[2620:137:e000::1:20]) by mx.google.com with ESMTP id 132-20020a63068a000000b0047048d81089si15346878pgg.186.2022.12.20.19.46.50; Tue, 20 Dec 2022 19:47:03 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@mediatek.com header.s=dk header.b="l2D9/fKD"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=mediatek.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234413AbiLUDo0 (ORCPT + 99 others); Tue, 20 Dec 2022 22:44:26 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49566 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229448AbiLUDoW (ORCPT ); Tue, 20 Dec 2022 22:44:22 -0500 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A01831EAD7; Tue, 20 Dec 2022 19:44:17 -0800 (PST) X-UUID: 3e33cd9b3f5944c9893ba0809ab23b7c-20221221 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=hkqKJdQLfbeXJfgg20ZloYGxwStSpQ6SVH54+huC6OI=; b=l2D9/fKDrDYlugATadHgbJ6T09SuL7pJBY6DYSfiAySEaM3KcFXUyw+c++wKqK7zf/AobGb0zE46+TXvgSA+m2gjAQjuML6s+8NB402uXfVmOlTugfmVvKFzjyqy3oiK61jml9CnWlDWgbm6Riwq/bp9scQoKgI54Jgfw0XgEBY=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.14,REQID:3eb1bf69-2683-45d2-af77-a1ef8eb70a0a,IP:0,U RL:0,TC:0,Content:-5,EDM:0,RT:0,SF:95,FILE:0,BULK:0,RULE:Release_Ham,ACTIO N:release,TS:90 X-CID-INFO: VERSION:1.1.14,REQID:3eb1bf69-2683-45d2-af77-a1ef8eb70a0a,IP:0,URL :0,TC:0,Content:-5,EDM:0,RT:0,SF:95,FILE:0,BULK:0,RULE:Spam_GS981B3D,ACTIO N:quarantine,TS:90 X-CID-META: VersionHash:dcaaed0,CLOUDID:1f3283f3-ff42-4fb0-b929-626456a83c14,B ulkID:221221114413EKZW7EKR,BulkQuantity:0,Recheck:0,SF:38|28|17|19|48,TC:n il,Content:0,EDM:-3,IP:nil,URL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0 X-UUID: 3e33cd9b3f5944c9893ba0809ab23b7c-20221221 Received: from mtkcas10.mediatek.inc [(172.21.101.39)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1098570935; Wed, 21 Dec 2022 11:44:11 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs11n2.mediatek.inc (172.21.101.187) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Wed, 21 Dec 2022 11:44:10 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Wed, 21 Dec 2022 11:44:10 +0800 From: Allen-KH Cheng To: Rob Herring , Krzysztof Kozlowski , Matthias Brugger , Chun-Jie Chen , Stephen Boyd , Ikjoon Jang CC: , , , , , , Chen-Yu Tsai , Allen-KH Cheng Subject: [PATCH v2 1/6] soc: mediatek: pm-domains: Add buck isolation offset and mask to power domain data Date: Wed, 21 Dec 2022 11:44:02 +0800 Message-ID: <20221221034407.19605-2-allen-kh.cheng@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20221221034407.19605-1-allen-kh.cheng@mediatek.com> References: <20221221034407.19605-1-allen-kh.cheng@mediatek.com> MIME-Version: 1.0 X-MTK: N X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS, T_SPF_TEMPERROR,UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1752793794428452197?= X-GMAIL-MSGID: =?utf-8?q?1752793794428452197?= Add buck isolation offset and mask to power domain data. Signed-off-by: Allen-KH Cheng Reviewed-by: AngeloGioacchino Del Regno --- drivers/soc/mediatek/mtk-pm-domains.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/soc/mediatek/mtk-pm-domains.h b/drivers/soc/mediatek/mtk-pm-domains.h index 7d3c0c36316c..a5f24c58e35a 100644 --- a/drivers/soc/mediatek/mtk-pm-domains.h +++ b/drivers/soc/mediatek/mtk-pm-domains.h @@ -81,6 +81,8 @@ struct scpsys_bus_prot_data { * @ctl_offs: The offset for main power control register. * @sram_pdn_bits: The mask for sram power control bits. * @sram_pdn_ack_bits: The mask for sram power control acked bits. + * @ext_buck_iso_offs: The offset for external buck isolation + * @ext_buck_iso_mask: The mask for external buck isolation * @caps: The flag for active wake-up action. * @bp_infracfg: bus protection for infracfg subsystem * @bp_smi: bus protection for smi subsystem @@ -91,6 +93,8 @@ struct scpsys_domain_data { int ctl_offs; u32 sram_pdn_bits; u32 sram_pdn_ack_bits; + int ext_buck_iso_offs; + u32 ext_buck_iso_mask; u8 caps; const struct scpsys_bus_prot_data bp_infracfg[SPM_MAX_BUS_PROT_DATA]; const struct scpsys_bus_prot_data bp_smi[SPM_MAX_BUS_PROT_DATA]; From patchwork Wed Dec 21 03:44:03 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Allen-KH Cheng X-Patchwork-Id: 35238 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:e747:0:0:0:0:0 with SMTP id c7csp3319049wrn; Tue, 20 Dec 2022 19:46:46 -0800 (PST) X-Google-Smtp-Source: AMrXdXuEK0vuI7y98qukqjvroHnau73yKc7P60xgrsL4utyVBuSlrI/FgZRnAUYnCtFzteROId0G X-Received: by 2002:a05:6a20:1455:b0:ae:661c:5553 with SMTP id a21-20020a056a20145500b000ae661c5553mr1222243pzi.4.1671594406332; Tue, 20 Dec 2022 19:46:46 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1671594406; cv=none; d=google.com; s=arc-20160816; b=UseNNN/WMjt3hwzPo1J0rvjzdAOwU//XfoPZpl5R+Y9LK9nugZ+QyuIo5yAieQoMYe mgswBXIhd8Un4ZvhO8x6p3QAwtmXO7SCrayW9AV4xxRJ4BlZUdw2QoO481xmiNcFBg2I qQyjkEMOE8YovJKJoTENumZwI4Llzq5+GpXiw2fM2oNXXKxgNDU9tAA9o6mn/e3MHYvp gXOb1lKXobdOy2my53iicuuDLf6G+5P7+8YN0s4mVOCkFdbZ8rEKB6on7gcjQoTR+q6h ia4Vy/CjO2Mwb0+BOphkCiktK7p2LfIYGbR4NKtJB2ItOnsfhiZ9+zbXvwSqD8lr4SPE 2Lfw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=8A0q6r84X2XKK3CAuRIml9dZUg+GB7moOddAKx6LC+0=; b=AE5V8iV06fMR7059cfgQiPPg2QiEW4phQES8I1saNlOxw+ckNDOHFeOn7UPHrMHIbj 73QQuCfXMwBSi5HZTJ4sYi7mRepafctEFdc9ZM3Az/0MX1PT65do2KxdwuedHq465tG0 0Sap2Eg+Fd71RE4fsCOBau9Jz0StIFn+xZmgMunuUCPIpg+h+s0UvbhYV9pefPHg2etC y31bzqev7jEV6ykpojtQERYF60aGmTJ7s9FSljVC0Cz4QC8/5gnFA7MwNRqEq7qUMwHe PQNxqHOpz8n33M7eMBHyOca50YbQSZextA0wCbT4gnkLernZkMWQuZlCDUWMROngUejE Kh5w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@mediatek.com header.s=dk header.b="CLUZa6/E"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=mediatek.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id y63-20020a638a42000000b0047856c2590esi16610746pgd.35.2022.12.20.19.46.33; Tue, 20 Dec 2022 19:46:46 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@mediatek.com header.s=dk header.b="CLUZa6/E"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=mediatek.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234404AbiLUDoY (ORCPT + 99 others); Tue, 20 Dec 2022 22:44:24 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49568 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233411AbiLUDoW (ORCPT ); Tue, 20 Dec 2022 22:44:22 -0500 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1E74B1EADC; Tue, 20 Dec 2022 19:44:17 -0800 (PST) X-UUID: fb46169b23a743fc913fa85c80cba7d3-20221221 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=8A0q6r84X2XKK3CAuRIml9dZUg+GB7moOddAKx6LC+0=; b=CLUZa6/EthcMKPGjYUzE7HS7bwOzVf1daE8B4VpX8I5qKNL9oqDqWcgPN8RRwo6zXeGF5icW+cBH9VwmoZDoBYmmq/yMx/mn00Ii+qCBDovT7hTTOpaF1/YQ4JIXyicdYesqgwMEb+vNMkcGFBgL0t/1b5kyK9X4MnhYm7hpa+Y=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.14,REQID:6c485bc7-588c-46a7-b36b-1c70315953c7,IP:0,U RL:0,TC:0,Content:-25,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTIO N:release,TS:-25 X-CID-META: VersionHash:dcaaed0,CLOUDID:a89df489-8530-4eff-9f77-222cf6e2895b,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0 X-UUID: fb46169b23a743fc913fa85c80cba7d3-20221221 Received: from mtkmbs10n2.mediatek.inc [(172.21.101.183)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 702773652; Wed, 21 Dec 2022 11:44:12 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs11n1.mediatek.inc (172.21.101.185) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Wed, 21 Dec 2022 11:44:11 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Wed, 21 Dec 2022 11:44:11 +0800 From: Allen-KH Cheng To: Rob Herring , Krzysztof Kozlowski , Matthias Brugger , Chun-Jie Chen , Stephen Boyd , Ikjoon Jang CC: , , , , , , Chen-Yu Tsai , Allen-KH Cheng Subject: [PATCH v2 2/6] soc: mediatek: pm-domains: Add buck isolation setting in power domain Date: Wed, 21 Dec 2022 11:44:03 +0800 Message-ID: <20221221034407.19605-3-allen-kh.cheng@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20221221034407.19605-1-allen-kh.cheng@mediatek.com> References: <20221221034407.19605-1-allen-kh.cheng@mediatek.com> MIME-Version: 1.0 X-MTK: N X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS, T_SPF_TEMPERROR,UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1752793775868345714?= X-GMAIL-MSGID: =?utf-8?q?1752793775868345714?= In MT8192, we need to disable EXT_BUCK_ISO before turning on the ADSP power pm-domains (mtcmos). Add the MTK_SCPD_EXT_BUCK_ISO flag to control the buck isolation setting in the mediatek power domain driver. Fixes: 59b644b01cf4 ("soc: mediatek: Add MediaTek SCPSYS power domains") Signed-off-by: Allen-KH Cheng --- drivers/soc/mediatek/mtk-pm-domains.c | 8 ++++++++ drivers/soc/mediatek/mtk-pm-domains.h | 1 + 2 files changed, 9 insertions(+) diff --git a/drivers/soc/mediatek/mtk-pm-domains.c b/drivers/soc/mediatek/mtk-pm-domains.c index 09e3c38b8466..63f1e183f645 100644 --- a/drivers/soc/mediatek/mtk-pm-domains.c +++ b/drivers/soc/mediatek/mtk-pm-domains.c @@ -218,6 +218,10 @@ static int scpsys_power_on(struct generic_pm_domain *genpd) if (ret) goto err_reg; + if (MTK_SCPD_CAPS(pd, MTK_SCPD_EXT_BUCK_ISO)) + regmap_clear_bits(scpsys->base, pd->data->ext_buck_iso_offs, + pd->data->ext_buck_iso_mask); + /* subsys power on */ regmap_set_bits(scpsys->base, pd->data->ctl_offs, PWR_ON_BIT); regmap_set_bits(scpsys->base, pd->data->ctl_offs, PWR_ON_2ND_BIT); @@ -272,6 +276,10 @@ static int scpsys_power_off(struct generic_pm_domain *genpd) if (ret < 0) return ret; + if (MTK_SCPD_CAPS(pd, MTK_SCPD_EXT_BUCK_ISO)) + regmap_set_bits(scpsys->base, pd->data->ext_buck_iso_offs, + pd->data->ext_buck_iso_mask); + clk_bulk_disable_unprepare(pd->num_subsys_clks, pd->subsys_clks); /* subsys power off */ diff --git a/drivers/soc/mediatek/mtk-pm-domains.h b/drivers/soc/mediatek/mtk-pm-domains.h index a5f24c58e35a..5ec53ee073c4 100644 --- a/drivers/soc/mediatek/mtk-pm-domains.h +++ b/drivers/soc/mediatek/mtk-pm-domains.h @@ -10,6 +10,7 @@ #define MTK_SCPD_DOMAIN_SUPPLY BIT(4) /* can't set MTK_SCPD_KEEP_DEFAULT_OFF at the same time */ #define MTK_SCPD_ALWAYS_ON BIT(5) +#define MTK_SCPD_EXT_BUCK_ISO BIT(6) #define MTK_SCPD_CAPS(_scpd, _x) ((_scpd)->data->caps & (_x)) #define SPM_VDE_PWR_CON 0x0210 From patchwork Wed Dec 21 03:44:04 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Allen-KH Cheng X-Patchwork-Id: 35243 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:e747:0:0:0:0:0 with SMTP id c7csp3319584wrn; Tue, 20 Dec 2022 19:48:38 -0800 (PST) X-Google-Smtp-Source: AMrXdXtjSM6yuiwcD6yAteTUBxTVVE1J+Andag/TdDbdoVb/eflcxt2Ek+yUIAv/ENk5ITYwZPrO X-Received: by 2002:a05:6a20:2a07:b0:af:6d54:239a with SMTP id e7-20020a056a202a0700b000af6d54239amr18822622pzh.38.1671594518644; Tue, 20 Dec 2022 19:48:38 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1671594518; cv=none; d=google.com; s=arc-20160816; b=S/TURpDRbztO4sfgr9oTv9lvO41+gvRnXpw5qaPi2DwuY2RlA0vQLXqEds3UcTTFXb QEmVTxB6iWWYIQTXMElM6eRQ3yCDv91o1sKEZqmZY2I7R8cd2C3Gv4XLyXmsII+XiASC ZSJfhV86fHtVials9exG3RhPzfYTklZ/i05q4/bv7/LCMSsJLKPl0zGChB8tusMyFyFl ZntTLJjvi76XhW9W3rZ6czfhiYL6tM9+zJWeqo6EHdhHHHT74iRvktxsHeOfZA0HtLOW KwzCgtfM4Ewvs24EDDKlFxB3i7SnzujtZ7lHH7/UlNAx9FImiwwbbLyEvAPetrYRboHY w+rA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=XxTUsxvSetrznStelFhNNQIH6eOjSESJoSSPJi/S8LM=; b=kL3O4RA3nM8SOQ1sHzIAkOo7822XI6l6OL3zzRGnHo7E9Y2n/HKjaVoG6IkszsTMgm cUjx4mXvuvWFplt69iEhFLnv05M1hyKJSRhLAgBNE0ZhwnANfkE1UYlotRmjs5xD+rHF ZFGRsp82rYgwjCk8davOwUY+3KTbBW2qcrBRngw9ev5OBUz8aAr71muJ4z47EKelPzFF EL2SA4vKMdG+jR97DiN6KhrvXTdZMcznKPimA5XHxHQmNqOLd4SMbqkUUU5XCd39oR0f iw3n/24lov5cbzoEjEml3Jf2E3nVHhKecbDYpgPYWqOTTyBT4lnkC28ytSOvyKGTP5X5 BjpA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@mediatek.com header.s=dk header.b=Zh89NlVw; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=mediatek.com Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Allen-KH Cheng Acked-by: Krzysztof Kozlowski Reviewed-by: AngeloGioacchino Del Regno --- include/dt-bindings/power/mt8192-power.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/dt-bindings/power/mt8192-power.h b/include/dt-bindings/power/mt8192-power.h index 4eaa53d7270a..63e81cd0d06d 100644 --- a/include/dt-bindings/power/mt8192-power.h +++ b/include/dt-bindings/power/mt8192-power.h @@ -28,5 +28,6 @@ #define MT8192_POWER_DOMAIN_CAM_RAWA 18 #define MT8192_POWER_DOMAIN_CAM_RAWB 19 #define MT8192_POWER_DOMAIN_CAM_RAWC 20 +#define MT8192_POWER_DOMAIN_ADSP 21 #endif /* _DT_BINDINGS_POWER_MT8192_POWER_H */ From patchwork Wed Dec 21 03:44:05 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Allen-KH Cheng X-Patchwork-Id: 35242 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:e747:0:0:0:0:0 with SMTP id c7csp3319441wrn; Tue, 20 Dec 2022 19:48:14 -0800 (PST) X-Google-Smtp-Source: AMrXdXvWFAPbFfBSt7lgz/nZFHPYU1i3SeEwUgVy/cKcSossPkF5N5gaGPrYhihh1vLXzWVl81xb X-Received: by 2002:a05:6a21:3d0d:b0:b2:6191:fdef with SMTP id bi13-20020a056a213d0d00b000b26191fdefmr901953pzc.43.1671594494221; Tue, 20 Dec 2022 19:48:14 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1671594494; cv=none; d=google.com; s=arc-20160816; b=wuOMBxQkidIZQgers9G6l1l849gR7feZ8WcMgZQgFT7cGlZu7K3Icfw4CjrHdeYUae iyiA4XkdKO1C+MpntJH6yPTYvPzd2H6O4951dsU1GN+6Xrsdhj+rSGTmEmsar8vY1eoA Ru1nW8UcERhTGjiomVGl1CQBufezLb2iDzDP9DnIC4FjZn2qE2LoXCiZP4PoH/Ae8wKq 1rMZ466F2S2z3jtCpNTe67/aN91WJwPf1k11ixf4uWFbi2/+xdsQzFjnvHL9m4X+XHuT xJpFK67i+kyxzM+w45blx61qysL8rjBb5Y8IxuUZR3R6vj0ijDuLQgoIVGAJo7lVgoNK bTqQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=FxQw7bHLyA5vKeEmlF/GvXF0yb0AjLvtCurZOZUuMoM=; b=qwXNzVaPkV7bkySgc1ELUNqQsWg2coNx4+TltBanrTM2A6gyawoCKUDTum8l5wD/rK Ja+xpkDcPb61UAbMTywlQbiQPcUi12ra5FWuklNWKPc6kbiZJmxXN18AboYmiaB8XrUw kKVBSDU6rAxUcf+OZvXncPy+inoBRarRWERykjzr5ZMpggDY9t6W88cjqM/bRKALiVgM V32UksAvcZDGt/QCGaMpLSj+X7yVIb4lZqdkydG5c+ZR12ci/3WsdNNnSMNMuf4ggUNg Jcns1f8LcN+p7G9fEHb6VNykUh0o/KVbZnS0QAr7tRPT8VLNY6MexpWZEnRTqFxH96mC n/UQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@mediatek.com header.s=dk header.b=KK1ydztx; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=mediatek.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id r9-20020a63fc49000000b00475abba079bsi14902768pgk.405.2022.12.20.19.48.00; Tue, 20 Dec 2022 19:48:14 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@mediatek.com header.s=dk header.b=KK1ydztx; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=mediatek.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234457AbiLUDon (ORCPT + 99 others); Tue, 20 Dec 2022 22:44:43 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49592 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234415AbiLUDo0 (ORCPT ); Tue, 20 Dec 2022 22:44:26 -0500 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E4C151EC48; Tue, 20 Dec 2022 19:44:21 -0800 (PST) X-UUID: f583dd13bece4a8997b7ded1560c77f3-20221221 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=FxQw7bHLyA5vKeEmlF/GvXF0yb0AjLvtCurZOZUuMoM=; b=KK1ydztxHUjVY4ugvuUZGUXIS+MMCP9KR7Diy67C0LcVTnY6bq6xfy9ppZYBxOteJIAAhux953f8rmJq5fnxCo2iykCr/x2YBzOWQwt5VHAgAFvYTI04GTY7fVOvF9fa4YSn4BXtbSXVIXSZC0B1v4j4fgjwDwR4DT3ZBH8er9g=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.14,REQID:e9ccb55f-89fe-4435-9def-32335d8494fb,IP:0,U RL:0,TC:0,Content:-5,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION :release,TS:-5 X-CID-META: VersionHash:dcaaed0,CLOUDID:039ef489-8530-4eff-9f77-222cf6e2895b,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0 X-UUID: f583dd13bece4a8997b7ded1560c77f3-20221221 Received: from mtkmbs11n1.mediatek.inc [(172.21.101.185)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 632725121; Wed, 21 Dec 2022 11:44:14 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs13n1.mediatek.inc (172.21.101.193) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Wed, 21 Dec 2022 11:44:12 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Wed, 21 Dec 2022 11:44:12 +0800 From: Allen-KH Cheng To: Rob Herring , Krzysztof Kozlowski , Matthias Brugger , Chun-Jie Chen , Stephen Boyd , Ikjoon Jang CC: , , , , , , Chen-Yu Tsai , Allen-KH Cheng Subject: [PATCH v2 4/6] soc: mediatek: pm-domains: Add ADSP power domain data for MT8192 Date: Wed, 21 Dec 2022 11:44:05 +0800 Message-ID: <20221221034407.19605-5-allen-kh.cheng@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20221221034407.19605-1-allen-kh.cheng@mediatek.com> References: <20221221034407.19605-1-allen-kh.cheng@mediatek.com> MIME-Version: 1.0 X-MTK: N X-Spam-Status: No, score=-1.3 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_MSPIKE_H2,RDNS_NONE, SPF_HELO_PASS,SPF_PASS,UNPARSEABLE_RELAY autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1752793868397572686?= X-GMAIL-MSGID: =?utf-8?q?1752793868397572686?= Add ADSP pm-domains (mtcmos) data for MT8192 SoC. Signed-off-by: Allen-KH Cheng Reviewed-by: AngeloGioacchino Del Regno --- drivers/soc/mediatek/mt8192-pm-domains.h | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/drivers/soc/mediatek/mt8192-pm-domains.h b/drivers/soc/mediatek/mt8192-pm-domains.h index b97b2051920f..19e58f0ca1df 100644 --- a/drivers/soc/mediatek/mt8192-pm-domains.h +++ b/drivers/soc/mediatek/mt8192-pm-domains.h @@ -287,6 +287,22 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8192[] = { .sram_pdn_bits = GENMASK(8, 8), .sram_pdn_ack_bits = GENMASK(12, 12), }, + [MT8192_POWER_DOMAIN_ADSP] = { + .name = "adsp", + .sta_mask = BIT(22), + .ctl_offs = 0x0358, + .sram_pdn_bits = GENMASK(8, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + .ext_buck_iso_offs = 0x039C, + .ext_buck_iso_mask = BIT(2), + .bp_infracfg = { + BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_2_ADSP, + MT8192_TOP_AXI_PROT_EN_2_SET, + MT8192_TOP_AXI_PROT_EN_2_CLR, + MT8192_TOP_AXI_PROT_EN_2_STA1), + }, + .caps = MTK_SCPD_SRAM_ISO | MTK_SCPD_EXT_BUCK_ISO, + }, [MT8192_POWER_DOMAIN_CAM] = { .name = "cam", .sta_mask = BIT(23), From patchwork Wed Dec 21 03:44:06 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Allen-KH Cheng X-Patchwork-Id: 35239 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:e747:0:0:0:0:0 with SMTP id c7csp3319097wrn; Tue, 20 Dec 2022 19:46:57 -0800 (PST) X-Google-Smtp-Source: AMrXdXtfnYIPfqN3Sz8I1w+nMcuxxzUMuSVYenUebWaL0bwxUXK2ygQNQqcVhcWer85eP3P6USqf X-Received: by 2002:aa7:804c:0:b0:576:cd93:2b06 with SMTP id y12-20020aa7804c000000b00576cd932b06mr714794pfm.6.1671594417261; Tue, 20 Dec 2022 19:46:57 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1671594417; cv=none; d=google.com; s=arc-20160816; b=zuDbr5j2L2zh+/OigscImUIno5z+J2wCAlb2A0RGpVK5WfrJP0cceUpbaoChLUbp4I G5MQm0IjF421V26BK5kAp8rqH/s7sPF4zZbOkrWWx0cw4U0I9B88kKe4dK094w9lERAf d0MlFF94F7ZDoPRx93q2bIjLmVg/+4w/6rqxsmByDSUZ1ytBtBGpfVpEvNOez4wewCLP N7zJLwpGw+CvbOrlJQQjVkdPaWQZEN2Uxr/+homonDbvQVKonmwOUDlPccRB1iRE2wis 1IdZIWxAlwhOlOwsqBzELqTz6B964xSbYqZIy/WZBZD+zAZBd1677MRwo3i6OmWkG8vB iv8Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=BdUxFNzQWMfOlVhrDimIZG6FxQhwlQm+RNutrnpG9Yg=; b=gIZ1bFBxLKw9jhmfbS1SdtSP60X9gbM0w4cbSUuH6GbMGD8ojnSvo8tQjr6wtCi2LW rvdCnCG2WNAabpAlNTPOKz2KztvN9w7z6RSTgn8VkuHutvSIf758zosVpCYKrtLoteJU 5/lwdjVsmFyXf6zExt8R5CQvmnPtKxGv5Lu+SuwaGsM47tUYhNP6p/mnAX5rYjT4r7LT p22djpf9wXAT1wfWgsVFhkCLBdXG6kP07nrwVEEfk7dnUv3YmFghG1qHej9UcYK5eHby IWTpr7EKc8vIQTIFCs3mdJ/YDbHmPbu1zS7PRWTh7Lk2QB/yVcK3+D3HzFhVSBga/yNE XuUA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@mediatek.com header.s=dk header.b=JUwXgzvw; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=mediatek.com Received: from out1.vger.email (out1.vger.email. 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Fixes: 4a803990aeb1 ("dt-bindings: ARM: Mediatek: Add new document bindings of MT8192 clock") Signed-off-by: Allen-KH Cheng --- .../arm/mediatek/mediatek,mt8192-clock.yaml | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8192-clock.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8192-clock.yaml index b57cc2e69efb..ce8dd2bfb533 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8192-clock.yaml +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8192-clock.yaml @@ -40,6 +40,9 @@ properties: reg: maxItems: 1 + power-domains: + maxItems: 1 + '#clock-cells': const: 1 @@ -47,13 +50,27 @@ required: - compatible - reg +allOf: + - if: + properties: + compatible: + contains: + enum: + - mediatek,mt8192-scp_adsp + then: + required: + - power-domains + additionalProperties: false examples: - | + #include + scp_adsp: clock-controller@10720000 { compatible = "mediatek,mt8192-scp_adsp"; reg = <0x10720000 0x1000>; + power-domains = <&spm MT8192_POWER_DOMAIN_ADSP>; #clock-cells = <1>; }; From patchwork Wed Dec 21 03:44:07 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Allen-KH Cheng X-Patchwork-Id: 35241 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:e747:0:0:0:0:0 with SMTP id c7csp3319321wrn; Tue, 20 Dec 2022 19:47:50 -0800 (PST) X-Google-Smtp-Source: AMrXdXu29aOvqR3N91RJ5Si9X10mpGU+cOlOxcV0SJMmNcel5JKEzibh3XHuzVvVMRCNqxC/J+9e X-Received: by 2002:a17:90a:5901:b0:219:b936:6bd7 with SMTP id k1-20020a17090a590100b00219b9366bd7mr583944pji.19.1671594470028; Tue, 20 Dec 2022 19:47:50 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1671594470; cv=none; d=google.com; s=arc-20160816; b=kHYxt2vX8wYJXQiTx7n8T9XMXkMUva2HCReXNUs/hfk51zNxT6LYig5q9dHdqMxyAI In8GSedjgKRuXzSLmNlEGt0fSlk3BJ1rWBY2jHu7B3z55wQsfQhza1012yb3OKPgSEq3 V27KNSrZdvfGIuMD11WO++7HgXTrK2ArgfKr7MHCrnYv97QcidnxMMVC9aAGWY8Uy4R1 iYNUzxVbn5VCVgE/FO6kvPZKSWMwZOWDMsiF5VTSEeuU2G3BaPf0OcsdSItuCZLdcv2a wiJK9l5qjZV0orRiKoN71QNsx0zAXCgrXP3O6yKuAbA3UftGAD5ogKs3W/fP0GfFD0MD KgnQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=vpKkQlPxOc+D9lcuAshw5hI22iECWZhtKc+FVAsWhts=; b=vMGLId7OHgIErofSnGeV9qBvjNq9VYTsh5B1IEL8opE3MHF5TqBmZBQxaaab/HIlCs Gj2dh7qqIV0V+kz3p0p6hmUACM55vvgOOaI+pjtlmAsjGiDcKzStnOb1j9ys+sOQ1oHJ VaFPrxAiDvrw8ZOEoJ0jTb21g8w7MHJgsdUg55XGzKy2cfFMN08Xywdbodn0fGqedclF LoBolu+NlerLaZM3HRuYAHU4bkr5/Es+F0828fN+U6+17oDku68UQHrCTaXg+mqPuee5 yZKa3RrR2DP2a9piFRydtgzhBpXxvE6A/zMecSP4TlgSXwJmeDdN0SK+9tn/x+lrkkrt Dmvg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@mediatek.com header.s=dk header.b=LP6sXgJn; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=mediatek.com Received: from out1.vger.email (out1.vger.email. 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Fixes: 5d2b897bc6f5 ("arm64: dts: mediatek: Add mt8192 clock controllers") Signed-off-by: Allen-KH Cheng Reviewed-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi index 6b20376191a7..6ee60db3ac23 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -511,6 +511,14 @@ }; }; }; + + power-domain@MT8192_POWER_DOMAIN_ADSP { + reg = ; + clocks = <&topckgen CLK_TOP_ADSP_SEL>; + clock-names = "adsp"; + mediatek,infracfg = <&infracfg>; + #power-domain-cells = <0>; + }; }; }; @@ -574,6 +582,7 @@ scp_adsp: clock-controller@10720000 { compatible = "mediatek,mt8192-scp_adsp"; reg = <0 0x10720000 0 0x1000>; + power-domains = <&spm MT8192_POWER_DOMAIN_ADSP>; #clock-cells = <1>; };