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So his entry can be removed. Adding myself as the co-maintainer since I took over the PCIe RC driver maintainership from Stanimir. Signed-off-by: Manivannan Sadhasivam Acked-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/pci/qcom,pcie.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml index 54f07852d279..02450fb26bb9 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml @@ -8,7 +8,7 @@ title: Qualcomm PCI express root complex maintainers: - Bjorn Andersson - - Stanimir Varbanov + - Manivannan Sadhasivam description: | Qualcomm PCIe root complex controller is based on the Synopsys DesignWare From patchwork Mon Dec 19 19:14:26 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 34716 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:e747:0:0:0:0:0 with SMTP id c7csp2571347wrn; Mon, 19 Dec 2022 11:17:50 -0800 (PST) X-Google-Smtp-Source: AMrXdXvq3Y80+m+RWeV0EkTTU3uPQ21mCFF57NqlZDk2ToLgZ1b9OKfZ67g9IDzKMUsLZXYDkU+m X-Received: by 2002:a17:907:a641:b0:819:2756:e090 with SMTP id vu1-20020a170907a64100b008192756e090mr5569004ejc.50.1671477470560; Mon, 19 Dec 2022 11:17:50 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1671477470; cv=none; d=google.com; s=arc-20160816; b=VpQGCtjd4xYvSwByJevANbzGX2rGHTa52Xc2kyjSd+pCkPF6kBWpYBUnHYKN1q+qmu hDUGUVxTxZT/AjaXgQi+r6kpWkAftdFwyAXZmcU0fEXr2+g14Xe4/QSE9jEvxmT589kN u6N/paelbe8rHUqc/+kIUb21l/6JBZadrJX00uoCNVHsoMfZYp+FUkQmhZhXnMNDnPkZ yq6pP11H7tmM2F0P6spCz5Z3eJ9C/8ZMt5wYK+AOaeMtjGxMaryy3TLiO7pQ2R8xD1B/ PEG7gPz2r5ct2VK3LTv0KKo6L7/Zbke6BhOW1uuqIoA+o0kyTL/CtU3yPtPZF5FoO3os uGSA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=9agN2hOf+CL4HJ9ZbGXzkjZqDPOgTWQAwGYfyipiHIQ=; b=bvpqk6Yr2WaT0UyeX6OdH+/6k/zX437bfNP9kPbnEw8oj3aoABX6TTtaDiaKk9EmM8 GVLC692/t/EkmpmHWu6vCgvrKkMjURiJ1CJM3OxB9qRoa1ThuwsZ4YhPr1ir6+rHEoym 5K8SFCDgK0/trednjtLo9DvxdYXMX58qokri7y+LBAnmue1N904XcHz65Qz9d7AFSFE4 v1lLckhIJUCJm0spP6jG0KLj9jNBfA6UkOuzFb1bnDeZ0j11B0kHjbLvaFVx2ZKIYR59 zfj9eLQFtU+xZBEhgWLezu1wmtK3ozw4t65d0IAn4o/9FuGdoU6jOkioJcitd57l+IgX mSSA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=btxnOBxz; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. 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Currently, the binding only documents the internal MSI implementation. Let's document the GIC-ITS imeplementation by making use of msi-map and msi-map-mask properties. Signed-off-by: Manivannan Sadhasivam --- .../devicetree/bindings/pci/qcom,pcie.yaml | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml index 02450fb26bb9..24c3e7ef14eb 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml @@ -100,18 +100,28 @@ properties: description: GPIO controlled connection to WAKE# signal maxItems: 1 + msi-map: true + + msi-map-mask: true + required: - compatible - reg - reg-names - - interrupts - - interrupt-names - - "#interrupt-cells" - interrupt-map-mask - interrupt-map - clocks - clock-names +oneOf: + - required: + - interrupts + - interrupt-names + - "#interrupt-cells" + - required: + - msi-map + - msi-map-mask + allOf: - $ref: /schemas/pci/pci-bus.yaml# - if: From patchwork Mon Dec 19 19:14:27 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 34717 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:e747:0:0:0:0:0 with SMTP id c7csp2571372wrn; Mon, 19 Dec 2022 11:17:54 -0800 (PST) X-Google-Smtp-Source: AMrXdXsX1YWMDGfYGOcu50FpMsVZROGvrlFCSn7YwcGp3nViDvKiqJ3WCLR4DSfXkb1qyxMmnkTU X-Received: by 2002:aa7:db92:0:b0:479:6c4f:40df with SMTP id u18-20020aa7db92000000b004796c4f40dfmr5657796edt.18.1671477474485; Mon, 19 Dec 2022 11:17:54 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1671477474; cv=none; d=google.com; s=arc-20160816; b=SnRTATj7G3hJZ+1dTQ9Wbr1B+zDnFspKqMedtT0tbSP/KzZ646IkKwvLf/YIkemGCE qyzTKUl+XHKE5hX3rXH/pKvVxMR5U2jH/H8m1JiMcaqStD1hQy3q/0MKT+DQAbipGHMF 9yC5BXTG3U0qnUTmKNPDDkyHxrkkZnwSLaSutuiJ3sXqPjObknHIAumv/Jl+nfDstZqH GQkQ6qjSCAr3VmkgLmOA+J7MOX9S/CAFI70gPRHUXCzK8VkBpfKDi3N+rmPvKoUElb8y Xk5yD2CasCfzuv64+lj0JCUmY4LwLfdEGZcZfPbvhTS7E7aWEX7dOYsh5MyuFcC28CRC iJ9A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=sAubOkJvINNojNKQySo7fdvunMLKmBVll3HExCwexwo=; b=GMFZFHasOrFwt50OuKKgLrGJNbcQg6tG4fes3OrhU0uTnI2Ukm6lTnRuieLm263BUB wr7MegKV0gqVZmP2LGVu1zJpEX1WJR7uaEBuvTwBsYYxjFu/oJV7JWJxL1pxBusECyJ2 jUbtYeYaCYVom7s7LfncnlL4ntiXBA2myYdRG/WyrfzcbYpx2BDVf0vCUzNI65rymkfB tj/MPkMfirTyAT73oGZ+tKuJeRDfOWCRTO69dDNWevdEFb5eZzoGPy7YOWk2ANQPURpO XaF3IzKVP7iv/Om9PQNyo1ROuZfza5EOTt8RrY6KEWxg2Y+pPdcBw11+qH1TeBCnN5Dz bAOQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=JuHzAjEt; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. 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Add support for it. Currently, BDF (0:0.0) and BDF (1:0.0) are enabled and with the msi-map-mask of 0xff00, all the 32 devices under these two busses can share the same Device ID. The GIC-ITS MSI implementation provides an advantage over internal MSI implementation using Locality-specific Peripheral Interrupts (LPI) that would allow MSIs to be targeted for each CPU core. Signed-off-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 570475040d95..276ceba4c247 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -1733,9 +1733,9 @@ pcie0: pci@1c00000 { ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>, <0x02000000 0x0 0x60300000 0 0x60300000 0x0 0x3d00000>; - interrupts = ; - interrupt-names = "msi"; - #interrupt-cells = <1>; + msi-map = <0x0 &gic_its 0x5980 0x1>, + <0x100 &gic_its 0x5981 0x1>; + msi-map-mask = <0xff00>; interrupt-map-mask = <0 0 0 0x7>; interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ @@ -1842,9 +1842,9 @@ pcie1: pci@1c08000 { ranges = <0x01000000 0x0 0x40200000 0 0x40200000 0x0 0x100000>, <0x02000000 0x0 0x40300000 0 0x40300000 0x0 0x1fd00000>; - interrupts = ; - interrupt-names = "msi"; - #interrupt-cells = <1>; + msi-map = <0x0 &gic_its 0x5a01 0x1>, + <0x100 &gic_its 0x5a00 0x1>; + msi-map-mask = <0xff00>; interrupt-map-mask = <0 0 0 0x7>; interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */