From patchwork Mon Dec 19 15:06:26 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Earnshaw X-Patchwork-Id: 34606 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:e747:0:0:0:0:0 with SMTP id c7csp2442087wrn; Mon, 19 Dec 2022 07:08:12 -0800 (PST) X-Google-Smtp-Source: AA0mqf4HA+V7p/ijLa3v2lu+7HYsu7qnSQ99jiNqq48sQXIWvp/b7uEd1jv3sclPyCsD5HjPyLhx X-Received: by 2002:a17:906:7043:b0:7b1:316c:38f5 with SMTP id r3-20020a170906704300b007b1316c38f5mr35212572ejj.30.1671462492499; Mon, 19 Dec 2022 07:08:12 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1671462492; cv=none; d=google.com; s=arc-20160816; b=UoSnZhuE1Fi8EjkDdpWsGMgC1RKPuHemxEZHtgs6jtJDjGMxJKJLjyrVmfZZLutsrY C9HJ/mzXaoxUGxkyEZUbIBKPUQOGePJFFFLuo+rEVENBQJMe4EXJP3BumNtEAU7x8RmI q9iGkLssuKYyjbXUMCzFR2a6YIgAiCR/e2MnZk+MZ71mzaLtw7KPPMi5ub0Twb2yIMH+ HL0DBLQqvCdTC/WBiCaIMH0zHVbV6ob2qWr61Gk4tDdj0x91FjGa2aUaP/jSGhrhzwWR Npol5F6kPKTqqeO9/GAUeMTaAyaHUYkCOnH4zpg4eJqZrPBqUl4ceaEYKawrT60DigcF 3Mdw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:reply-to:from:list-subscribe:list-help:list-post :list-archive:list-unsubscribe:list-id:precedence :content-transfer-encoding:mime-version:message-id:date:subject:cc :to:dmarc-filter:delivered-to:dkim-signature:dkim-filter; bh=tYwL+eiaAjXwYgQ6SsVMRRwnd+1w3WHOV+8QZfRx7zY=; b=EZoJw5euR13P90/JmLudu91lRE8Rzr0Da6CIi+zBO4Yusrne4QX2mf02i0PNBDIJOv ksXPeMo9qRLC8JA5010whe/SaTSKjcMjgX3wjKj/SRJkt53+1kR/KwyK9xnQAMOhJ2/o WfL3j9XcyMseczGy2bdF5Cwq2vOEx084md7fWwc+9WTgqxCHwWVRGxhal+7vZaKJHEut ZCM5Ui+aDz8p0uFzyfKwjQsfW4noFx9J8R6NeHz9jZxQgspcpIHvAxRNJhQBr9uxI9DG reQoSzPwyFCICN2dEstQtRB2gd8TuyLd8z5XE9m264954pkP6M1475BpUJ/VC67QMZYj uEjg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=FRq0RxNv; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from sourceware.org (ip-8-43-85-97.sourceware.org. [8.43.85.97]) by mx.google.com with ESMTPS id tl2-20020a170907c30200b007c0baa5000csi7440309ejc.340.2022.12.19.07.08.12 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Dec 2022 07:08:12 -0800 (PST) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=FRq0RxNv; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id C5E47385828D for ; Mon, 19 Dec 2022 15:07:24 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org C5E47385828D DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1671462444; bh=tYwL+eiaAjXwYgQ6SsVMRRwnd+1w3WHOV+8QZfRx7zY=; h=To:Cc:Subject:Date:List-Id:List-Unsubscribe:List-Archive: List-Post:List-Help:List-Subscribe:From:Reply-To:From; b=FRq0RxNv6FZlvXoM9bkJGCATUKD/PRLmEDNPDO1l3G6jKm1GKV5ZXtgfgtbstsGer GAUDEtj/gkNiT+C/yVcsX4GUbPEUUqvRxdgRQz51oLC3GxrlXOWzL2AAvhahVOVYxZ gn9O9e4CQgqe982fJhmpwOzuzixFp4rXwIXdUGSk= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by sourceware.org (Postfix) with ESMTP id 5E26038582A3 for ; Mon, 19 Dec 2022 15:06:41 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 5E26038582A3 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id E08E4AD7; Mon, 19 Dec 2022 07:07:21 -0800 (PST) Received: from e126323.arm.com (unknown [10.57.11.95]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 80B3C3F71A; Mon, 19 Dec 2022 07:06:40 -0800 (PST) To: gcc-patches@gcc.gnu.org Cc: Richard Earnshaw Subject: [committed] arm: correctly define __ARM_FEATURE_CLZ Date: Mon, 19 Dec 2022 15:06:26 +0000 Message-Id: <20221219150626.2972660-1-rearnsha@arm.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-Spam-Status: No, score=-16.8 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_NONE, KAM_DMARC_STATUS, KAM_LAZY_DOMAIN_SECURITY, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Richard Earnshaw via Gcc-patches From: Richard Earnshaw Reply-To: Richard Earnshaw Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1752655454408130599?= X-GMAIL-MSGID: =?utf-8?q?1752655454408130599?= The ACLE requires that __ARM_FEATURE_CLZ be defined if the hardware supports it; it's also clear that this doesn't mean the current ISA, so we must define this even when compiling for Thumb1 if the target supports CLZ in A32. This brings GCC into alignment with Clang. gcc/ChangeLog: * config/arm/arm-c.cc (__ARM_FEATURE_CLZ): Fix definition of preprocessor macro when target has CLZ in another ISA. --- gcc/config/arm/arm-c.cc | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/gcc/config/arm/arm-c.cc b/gcc/config/arm/arm-c.cc index 86c56bf2680..202898fa041 100644 --- a/gcc/config/arm/arm-c.cc +++ b/gcc/config/arm/arm-c.cc @@ -238,8 +238,12 @@ arm_cpu_builtins (struct cpp_reader* pfile) builtin_define_with_int_value ("__ARM_FEATURE_LDREX", TARGET_ARM_FEATURE_LDREX); + /* ACLE says that __ARM_FEATURE_CLZ is defined if the hardware + supports it; it's also clear that this doesn't mean the current + ISA, so we define this even when compiling for Thumb1 if the + target supports CLZ in A32. */ def_or_undef_macro (pfile, "__ARM_FEATURE_CLZ", - ((TARGET_ARM_ARCH >= 5 && !TARGET_THUMB) + ((TARGET_ARM_ARCH >= 5 && arm_arch_notm) || TARGET_ARM_ARCH_ISA_THUMB >=2)); def_or_undef_macro (pfile, "__ARM_FEATURE_NUMERIC_MAXMIN",