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Mon, 19 Dec 2022 00:41:03 -0600 From: Perry Yuan To: , , , CC: , , , , , , , , Subject: [PATCH v8 01/13] ACPI: CPPC: Add AMD pstate energy performance preference cppc control Date: Mon, 19 Dec 2022 14:40:30 +0800 Message-ID: <20221219064042.661122-2-perry.yuan@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221219064042.661122-1-perry.yuan@amd.com> References: <20221219064042.661122-1-perry.yuan@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT101:EE_|BY5PR12MB4034:EE_ X-MS-Office365-Filtering-Correlation-Id: d56afac0-309f-4c98-ad5a-08dae18c0207 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: DuHmAbSrkiG/y/PB/K8CVtqz9d8jDmxv0HrAA5TJw4i5GXi0F8GK8otACIw99ptbR/MnpVHmaXssIA5sBMeBywwSzi0txpP++CG0meZ5L4ccrH3YlTAobps/uFkQJpBsWsT7nIWzsZ+I8PgP6KQC8zSAzcbyxyhOS9pQFJ2jTATUM2GXgcdr0VaftuD5JSuxg84Ig/aXWUmAaF2yb5z1/0LAtyCyn6BDx7QVXoaoIk9w0OJTglwv9PzJthppqiHJ2kmgfEylV/gJAu00fFGFdRF513LDw5V4BtIJe1PCy5R5D6/A43GP16UN0aN7zKfSeGCYmAzNdWe1NfXhlYgL4/7KgYQap7gBCqmjKQYxUjViagpbTT9Fc4P5ggi38wF3XYuEfqZTJB2FTZbsjhdhD+F/Zl123PApkTZtmRVk3ZV14lgaec16Jq5tLQPjCSKl8c7zZcJ5lqNd7dEgKNB/Fc9XuHvY/YdhKHuVNfdDQ+7a3gNbfld2jupq9k8r8sY70qTkHbPvV9iOOCv63ab6Q6VkIHNn9brn1CUUlE2JRSxSvfrueQX3O5FXa58PBeqWH2swI6TdFRr2hchockCtHVGDMfS7kTPZNck/aTEzRi7VpqBnVdHEWtyMspoqJAZ+1eX0GhQQsxCWgrR16F4mXQzlSSQEDaLeedmdzyEUtlLxUY8bv5Hak5Xo4t0VqBPVAVuNx4cuLD8MFFJO9R0i1t2UvqjwOt50wILJYZGOXq8= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230022)(4636009)(396003)(136003)(346002)(376002)(39860400002)(451199015)(46966006)(40470700004)(36840700001)(86362001)(70586007)(40460700003)(70206006)(4326008)(8936002)(8676002)(5660300002)(36756003)(41300700001)(2616005)(1076003)(6666004)(7696005)(26005)(426003)(186003)(83380400001)(47076005)(336012)(36860700001)(40480700001)(356005)(110136005)(82740400003)(16526019)(82310400005)(54906003)(316002)(81166007)(478600001)(44832011)(2906002)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Dec 2022 06:41:07.1293 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d56afac0-309f-4c98-ad5a-08dae18c0207 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT101.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR12MB4034 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1752623670204884333?= X-GMAIL-MSGID: =?utf-8?q?1752623670204884333?= From: Perry Yuan Add support for setting and querying EPP preferences to the generic CPPC driver. This enables downstream drivers such as amd-pstate to discover and use these values Downstream drivers that want to use the new symbols cppc_get_epp_caps and cppc_set_epp_perf for querying and setting EPP preferences will need to call cppc_set_epp_perf to enable the EPP function firstly. Signed-off-by: Perry Yuan Reviewed-by: Mario Limonciello --- drivers/acpi/cppc_acpi.c | 76 +++++++++++++++++++++++++++++++++++++--- include/acpi/cppc_acpi.h | 12 +++++++ 2 files changed, 83 insertions(+), 5 deletions(-) diff --git a/drivers/acpi/cppc_acpi.c b/drivers/acpi/cppc_acpi.c index 093675b1a1ff..81081eb899ea 100644 --- a/drivers/acpi/cppc_acpi.c +++ b/drivers/acpi/cppc_acpi.c @@ -1093,6 +1093,9 @@ static int cppc_get_perf(int cpunum, enum cppc_regs reg_idx, u64 *perf) { struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpunum); struct cpc_register_resource *reg; + int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpunum); + struct cppc_pcc_data *pcc_ss_data = NULL; + int ret = -EINVAL; if (!cpc_desc) { pr_debug("No CPC descriptor for CPU:%d\n", cpunum); @@ -1102,10 +1105,6 @@ static int cppc_get_perf(int cpunum, enum cppc_regs reg_idx, u64 *perf) reg = &cpc_desc->cpc_regs[reg_idx]; if (CPC_IN_PCC(reg)) { - int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpunum); - struct cppc_pcc_data *pcc_ss_data = NULL; - int ret = 0; - if (pcc_ss_id < 0) return -EIO; @@ -1125,7 +1124,7 @@ static int cppc_get_perf(int cpunum, enum cppc_regs reg_idx, u64 *perf) cpc_read(cpunum, reg, perf); - return 0; + return ret; } /** @@ -1153,6 +1152,19 @@ int cppc_get_nominal_perf(int cpunum, u64 *nominal_perf) return cppc_get_perf(cpunum, NOMINAL_PERF, nominal_perf); } +/** + * cppc_get_epp_perf - Get the epp register value. + * @cpunum: CPU from which to get epp preference value. + * @epp_perf: Return address. + * + * Return: 0 for success, -EIO otherwise. + */ +int cppc_get_epp_perf(int cpunum, u64 *epp_perf) +{ + return cppc_get_perf(cpunum, ENERGY_PERF, epp_perf); +} +EXPORT_SYMBOL_GPL(cppc_get_epp_perf); + /** * cppc_get_perf_caps - Get a CPU's performance capabilities. * @cpunum: CPU from which to get capabilities info. @@ -1365,6 +1377,60 @@ int cppc_get_perf_ctrs(int cpunum, struct cppc_perf_fb_ctrs *perf_fb_ctrs) } EXPORT_SYMBOL_GPL(cppc_get_perf_ctrs); +/* + * Set Energy Performance Preference Register value through + * Performance Controls Interface + */ +int cppc_set_epp_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls, bool enable) +{ + int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu); + struct cpc_register_resource *epp_set_reg; + struct cpc_register_resource *auto_sel_reg; + struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpu); + struct cppc_pcc_data *pcc_ss_data = NULL; + int ret = -EINVAL; + + if (!cpc_desc) { + pr_debug("No CPC descriptor for CPU:%d\n", cpu); + return -ENODEV; + } + + auto_sel_reg = &cpc_desc->cpc_regs[AUTO_SEL_ENABLE]; + epp_set_reg = &cpc_desc->cpc_regs[ENERGY_PERF]; + + if (CPC_IN_PCC(epp_set_reg) || CPC_IN_PCC(auto_sel_reg)) { + if (pcc_ss_id < 0) { + pr_debug("Invalid pcc_ss_id\n"); + return -ENODEV; + } + + if (CPC_SUPPORTED(auto_sel_reg)) { + ret = cpc_write(cpu, auto_sel_reg, enable); + if (ret) + return ret; + } + + if (CPC_SUPPORTED(epp_set_reg)) { + ret = cpc_write(cpu, epp_set_reg, perf_ctrls->energy_perf); + if (ret) + return ret; + } + + pcc_ss_data = pcc_data[pcc_ss_id]; + + down_write(&pcc_ss_data->pcc_lock); + /* after writing CPC, transfer the ownership of PCC to platform */ + ret = send_pcc_cmd(pcc_ss_id, CMD_WRITE); + up_write(&pcc_ss_data->pcc_lock); + } else { + ret = -ENOTSUPP; + pr_debug("_CPC in PCC is not supported\n"); + } + + return ret; +} +EXPORT_SYMBOL_GPL(cppc_set_epp_perf); + /** * cppc_set_enable - Set to enable CPPC on the processor by writing the * Continuous Performance Control package EnableRegister field. diff --git a/include/acpi/cppc_acpi.h b/include/acpi/cppc_acpi.h index c5614444031f..6b487a5bd638 100644 --- a/include/acpi/cppc_acpi.h +++ b/include/acpi/cppc_acpi.h @@ -108,12 +108,14 @@ struct cppc_perf_caps { u32 lowest_nonlinear_perf; u32 lowest_freq; u32 nominal_freq; + u32 energy_perf; }; struct cppc_perf_ctrls { u32 max_perf; u32 min_perf; u32 desired_perf; + u32 energy_perf; }; struct cppc_perf_fb_ctrs { @@ -149,6 +151,8 @@ extern bool cpc_ffh_supported(void); extern bool cpc_supported_by_cpu(void); extern int cpc_read_ffh(int cpunum, struct cpc_reg *reg, u64 *val); extern int cpc_write_ffh(int cpunum, struct cpc_reg *reg, u64 val); +extern int cppc_get_epp_perf(int cpunum, u64 *epp_perf); +extern int cppc_set_epp_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls, bool enable); #else /* !CONFIG_ACPI_CPPC_LIB */ static inline int cppc_get_desired_perf(int cpunum, u64 *desired_perf) { @@ -202,6 +206,14 @@ static inline int cpc_write_ffh(int cpunum, struct cpc_reg *reg, u64 val) { return -ENOTSUPP; } +static inline int cppc_set_epp_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls, bool enable) +{ + return -ENOTSUPP; +} +static inline int cppc_get_epp_perf(int cpunum, u64 *epp_perf) +{ + return -ENOTSUPP; +} #endif /* !CONFIG_ACPI_CPPC_LIB */ #endif /* _CPPC_ACPI_H*/ From patchwork Mon Dec 19 06:40:31 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Yuan, Perry" X-Patchwork-Id: 34415 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:e747:0:0:0:0:0 with SMTP id c7csp2229906wrn; Sun, 18 Dec 2022 22:44:04 -0800 (PST) X-Google-Smtp-Source: AA0mqf57vTaisl/lsL2E9gicqrP5pqlOKAJjqDaRgM/WSUPmpbDYKduevOCgI53EjS/7PyDhLmAb X-Received: by 2002:a05:6a21:158a:b0:9d:efbe:a116 with SMTP id nr10-20020a056a21158a00b0009defbea116mr23617311pzb.38.1671432243881; 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Mon, 19 Dec 2022 00:41:06 -0600 From: Perry Yuan To: , , , CC: , , , , , , , , Subject: [PATCH v8 02/13] Documentation: amd-pstate: add EPP profiles introduction Date: Mon, 19 Dec 2022 14:40:31 +0800 Message-ID: <20221219064042.661122-3-perry.yuan@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221219064042.661122-1-perry.yuan@amd.com> References: <20221219064042.661122-1-perry.yuan@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT101:EE_|BY1PR12MB8447:EE_ X-MS-Office365-Filtering-Correlation-Id: fe681a5d-5763-4885-bd1c-08dae18c0499 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: INonliDLMgbDtdthLwvn4Df/ItlWVo2ZqjHfPAoVdkyf/WcmVhmiDuGWAABbs6PK6MZinMufCzt4glPTD51sAxYPcM9eRdXmIe9efOcQ+F6hFOGHUhKkgqwhna1tLNx4PbOza2fbFTyqk1KinKF2HwIKkXor44iNluz9fp5o0LVy3/rW1GvkaOXe9Atil4yEl8ECdvTfcmL8rnswxhubYFHtkcrsvmxAzkFHQVSjg0+5seLwE61GA25HH13zNg0EgBM9R2xVVdC70rwA7zd9nY1ZTcnshfbpX2UmIt2F1rV/TCuwOvmuQEUK+mIZEr/+ne3AJa6iXAsMv9Hqj40CDLoXDjiOeJfG5HNbdyICo4lu/piPid8pYIzL0+ccvN/Hm99ku6gN/2Yk06Ytzx2KfRFkZU4s+2pKq02kHAYVQG9I9ntWUJdtD4JUyw2m3+ojpempUafNzxuEGXyeE8PJWJFnexPGyq1iOABRn4uAujIU/e3Fd1Bn1I3NECbSUHoXx8W+kqUSYzOCD4EloIUgyqgox19qO+KX35+P0baWOfPGMserLTUZWSqW/zZv4PDlnKo5y0Es2G6CBDKcWJ2dcuX8qHrObipyrLXVIzqJMT1wCS9fxDpcZF4E7egIy7dtodscH13anRE2zIx5Q38wbYa/AIOoeyWrlbm/2KHgyS5/Xf1ZI66kC0fKYHe9wqesTn9XguETg6xwOscQem7lyJH5nmubbcCYlzhwFY082ho= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230022)(4636009)(136003)(346002)(376002)(39860400002)(396003)(451199015)(40470700004)(36840700001)(46966006)(86362001)(356005)(36756003)(83380400001)(426003)(336012)(47076005)(1076003)(36860700001)(16526019)(26005)(6666004)(81166007)(186003)(8676002)(478600001)(7696005)(54906003)(110136005)(316002)(2616005)(70586007)(70206006)(4326008)(41300700001)(8936002)(2906002)(82310400005)(44832011)(82740400003)(5660300002)(40480700001)(40460700003)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Dec 2022 06:41:11.4420 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: fe681a5d-5763-4885-bd1c-08dae18c0499 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT101.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY1PR12MB8447 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1752623736588487301?= X-GMAIL-MSGID: =?utf-8?q?1752623736588487301?= From: Perry Yuan The patch add AMD pstate EPP feature introduction and what EPP preference supported for AMD processors. User can get supported list from energy_performance_available_preferences attribute file, or update current profile to energy_performance_preference file 1) See all EPP profiles $ sudo cat /sys/devices/system/cpu/cpu0/cpufreq/energy_performance_available_preferences default performance balance_performance balance_power power 2) Check current EPP profile $ sudo cat /sys/devices/system/cpu/cpu0/cpufreq/energy_performance_preference performance 3) Set new EPP profile $ sudo bash -c "echo power > /sys/devices/system/cpu/cpu0/cpufreq/energy_performance_preference" Signed-off-by: Perry Yuan --- Documentation/admin-guide/pm/amd-pstate.rst | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/Documentation/admin-guide/pm/amd-pstate.rst b/Documentation/admin-guide/pm/amd-pstate.rst index 06e23538f79c..33ab8ec8fc2f 100644 --- a/Documentation/admin-guide/pm/amd-pstate.rst +++ b/Documentation/admin-guide/pm/amd-pstate.rst @@ -262,6 +262,25 @@ lowest non-linear performance in `AMD CPPC Performance Capability `_.) This attribute is read-only. +``energy_performance_available_preferences`` + +A list of all the supported EPP preferences that could be used for +``energy_performance_preference`` on this system. +These profiles represent different hints that are provided +to the low-level firmware about the user's desired energy vs efficiency +tradeoff. ``default`` represents the epp value is set by platform +firmware. This attribute is read-only. + +``energy_performance_preference`` + +The current energy performance preference can be read from this attribute. +and user can change current preference according to energy or performance needs +Please get all support profiles list from +``energy_performance_available_preferences`` attribute, all the profiles are +integer values defined between 0 to 255 when EPP feature is enabled by platform +firmware, if EPP feature is disabled, driver will ignore the written value +This attribute is read-write. + Other performance and frequency values can be read back from ``/sys/devices/system/cpu/cpuX/acpi_cppc/``, see :ref:`cppc_sysfs`. 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Mon, 19 Dec 2022 00:41:10 -0600 From: Perry Yuan To: , , , CC: , , , , , , , , Subject: [PATCH v8 03/13] cpufreq: intel_pstate: use common macro definition for Energy Preference Performance(EPP) Date: Mon, 19 Dec 2022 14:40:32 +0800 Message-ID: <20221219064042.661122-4-perry.yuan@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221219064042.661122-1-perry.yuan@amd.com> References: <20221219064042.661122-1-perry.yuan@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT101:EE_|DM4PR12MB6664:EE_ X-MS-Office365-Filtering-Correlation-Id: 28c77821-82d4-4a1f-8c04-08dae18c0657 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: K/YS4Wc1nO4ZuNSqx2ono+2aU1YLIxBKQYFtG538BkTiXlttX9aM2Wmk4Y/Qhoa6QRPc8Le8qhALwO/2/M9eo8Yukvd6nD8+gaW5/WhkupZBCa7vZsJl1BGxcUd7jO149OY0RwolPV4RkpF9Bg0031J68BB2miflyF/V8dU1uq2rCyq3rZp1FnW1Fj0USOlzhFS0pDfMgGyKEdOaEmk4kLtajVm/1Z8Tddlwm1CUKKnhpxSr3HetfZ4KhvJYD1vfd5Iv7agPQgGOYoVbbysqojx6J9jCJCjUXfQLK39XMGQOvTXNJgBkHF7WBekVI1GC2R4rywJeukNRGak1BJQ/IF4PLhuscqe20dazKlU3+HU1RyiV6E2jk5ARsOrGgLmZZ/+bNS1OsFjjT88MAFi0+0Tt0+MFVCaUmMqiKI4kUKlux9BsE8O0BU7Yd9zPOUeOdOcqvrMiBXGJ9rk/33SQBWIXUANOmD/jk8lOxF0SapfFoyH2UCQYLdEE64pD19yrsnGLeZzruhbYsFoHDJWG3ot4dGI7rUAQJ9q/syGXvQFFSJDA4kbX/ns+7kHfqJATWvscpwNrcJm6HUPozpwCJpPVNDGh1Eh9K1VwXhF7cJFhXvTNbw9rzhzsGvbY9Bfhrynb6SrGjVrHteDL/n1zKID+IPeBZN7QLd0s1Q3hMQE3JO4Bv5Bb4x/r2pXYS5UnU9fwCpfdXVjVU4fyzhaDpTpm6BIoo5OExPvjzsDVqZU= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230022)(4636009)(376002)(396003)(136003)(39860400002)(346002)(451199015)(46966006)(40470700004)(36840700001)(6666004)(54906003)(316002)(110136005)(36860700001)(40480700001)(2906002)(70586007)(70206006)(40460700003)(478600001)(1076003)(47076005)(426003)(86362001)(2616005)(26005)(4326008)(8676002)(16526019)(186003)(36756003)(8936002)(44832011)(81166007)(82740400003)(7696005)(82310400005)(41300700001)(356005)(83380400001)(5660300002)(336012)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Dec 2022 06:41:14.3793 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 28c77821-82d4-4a1f-8c04-08dae18c0657 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT101.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB6664 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1752623684940299707?= X-GMAIL-MSGID: =?utf-8?q?1752623684940299707?= make the energy preference performance strings and profiles using one common header for intel_pstate driver, then the amd_pstate epp driver can use the common header as well. This will simpify the intel_pstate and amd_pstate driver. Signed-off-by: Perry Yuan --- drivers/cpufreq/intel_pstate.c | 13 +++---------- include/linux/cpufreq.h | 11 +++++++++++ 2 files changed, 14 insertions(+), 10 deletions(-) diff --git a/drivers/cpufreq/intel_pstate.c b/drivers/cpufreq/intel_pstate.c index ad9be31753b6..93a60fdac0fc 100644 --- a/drivers/cpufreq/intel_pstate.c +++ b/drivers/cpufreq/intel_pstate.c @@ -640,15 +640,7 @@ static int intel_pstate_set_epb(int cpu, s16 pref) * 4 power */ -enum energy_perf_value_index { - EPP_INDEX_DEFAULT = 0, - EPP_INDEX_PERFORMANCE, - EPP_INDEX_BALANCE_PERFORMANCE, - EPP_INDEX_BALANCE_POWERSAVE, - EPP_INDEX_POWERSAVE, -}; - -static const char * const energy_perf_strings[] = { +const char * const energy_perf_strings[] = { [EPP_INDEX_DEFAULT] = "default", [EPP_INDEX_PERFORMANCE] = "performance", [EPP_INDEX_BALANCE_PERFORMANCE] = "balance_performance", @@ -656,7 +648,8 @@ static const char * const energy_perf_strings[] = { [EPP_INDEX_POWERSAVE] = "power", NULL }; -static unsigned int epp_values[] = { + +unsigned int epp_values[] = { [EPP_INDEX_DEFAULT] = 0, /* Unused index */ [EPP_INDEX_PERFORMANCE] = HWP_EPP_PERFORMANCE, [EPP_INDEX_BALANCE_PERFORMANCE] = HWP_EPP_BALANCE_PERFORMANCE, diff --git a/include/linux/cpufreq.h b/include/linux/cpufreq.h index d5595d57f4e5..e63309d497fe 100644 --- a/include/linux/cpufreq.h +++ b/include/linux/cpufreq.h @@ -20,6 +20,7 @@ #include #include #include +#include /********************************************************************* * CPUFREQ INTERFACE * @@ -185,6 +186,16 @@ struct cpufreq_freqs { u8 flags; /* flags of cpufreq_driver, see below. */ }; +enum energy_perf_value_index { + EPP_INDEX_DEFAULT = 0, + EPP_INDEX_PERFORMANCE, + EPP_INDEX_BALANCE_PERFORMANCE, + EPP_INDEX_BALANCE_POWERSAVE, + EPP_INDEX_POWERSAVE, +}; +extern const char * const energy_perf_strings[]; +extern unsigned int epp_values[]; + /* Only for ACPI */ #define CPUFREQ_SHARED_TYPE_NONE (0) /* None */ #define CPUFREQ_SHARED_TYPE_HW (1) /* HW does needed coordination */ From patchwork Mon Dec 19 06:40:33 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Yuan, Perry" X-Patchwork-Id: 34412 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:e747:0:0:0:0:0 with SMTP id c7csp2229704wrn; Sun, 18 Dec 2022 22:43:29 -0800 (PST) X-Google-Smtp-Source: AA0mqf4UE4aILA7V6SwMOes1Cs/0Z12pePvxCkgrpWSpnNv810+j4X5dQ2dt1W/sAHZRb3tQL310 X-Received: by 2002:a17:902:f601:b0:187:c49:5a1a with SMTP id n1-20020a170902f60100b001870c495a1amr46280296plg.17.1671432209345; Sun, 18 Dec 2022 22:43:29 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1671432209; cv=pass; d=google.com; s=arc-20160816; b=iKcuMfXaDBndcistlWjlJTqfshF5HlLJRyMSab4paM6SBGO1GI6iV/TxeXqsx7PwUY TZnwXmehSYuNVPLptDajDrz/UP52z2xiAtHmFhtovkafY/XTcBFfbJga7s/iTd396S2j YJOjn9mZLZxm8bJcs3GzzPtbqRGgceXSiJq3OFzFXJ4LjGQDBgMuL2CVpgk8XJxyKJAA hGkYCmbHhTPAAVL/eXbJ9dOd3DWpJ2M6kwDqmYqS+r3eSWmjtwrrwoA3NWfudMiLJZrk sZtayrT/dTkZoCLU+ImDvLw3KSkS/TIc62V9xgRRbKxVGCJygQilpcuDzQMXQiPp+CNp uA3g== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=ItkWZS7N7TsFSYYznfiCZsZjwXt0F1NknfG+HEWWxsE=; b=FjltcUEpWMj6RXlyBjD41Fa1QlZnVEBQ2wVYkLbW6S303PQ4VV5z9W43E24cD3Wjbi p7NJmOEBf9HPqrrKQ2h2k12SeXOzqo0KmcQK7+KGr58by53xSjD+PULc2wNoH55fez8O GAYnr67jfwMR5hHKxtgjZuJQH09QyGfxavoX/O3i3hsd5jMMxfv8zezON5ckJkBWfOR4 WhEOz6fPfm1KBc6oeBe8ClDiF5IQckn9+8j0M16JNrshhEc6jJ4Z6S5oWPekAd0l7t6+ vLq5V63RljaO1AhsFvLwLBdY5ZHSpfZkHZvOTyQU6oUenY/Rlzh5ut+B8esGQmft4yXr NdPw== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amd.com header.s=selector1 header.b=qG6ODjgx; arc=pass (i=1 spf=pass spfdomain=amd.com dmarc=pass fromdomain=amd.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=amd.com Received: from out1.vger.email (out1.vger.email. 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Mon, 19 Dec 2022 00:41:14 -0600 From: Perry Yuan To: , , , CC: , , , , , , , , Subject: [PATCH v8 04/13] cpufreq: amd-pstate: fix kernel hang issue while amd-pstate unregistering Date: Mon, 19 Dec 2022 14:40:33 +0800 Message-ID: <20221219064042.661122-5-perry.yuan@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221219064042.661122-1-perry.yuan@amd.com> References: <20221219064042.661122-1-perry.yuan@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT101:EE_|MN0PR12MB6174:EE_ X-MS-Office365-Filtering-Correlation-Id: 3ccb2026-0b1c-44bc-6b54-08dae18c0847 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: qX856iBrS0kU9lq3g943XpndPLuATzzgrMXbdHCA2pB3f8kMohCHglKDnLTPwzOuAxh6mEx/PXzxaGB+eAB929ZjVpdThWqRyUCigjaL4awd2EApQGHo/fSEANMpU9FSQ/YW+J+8mFhEDNswVSWmHhIgnzlKEhXU6+wv1AccSi2IADv0lRtqZ9/78Bs1Wep0JbuUy0lsVml/84ZvT0fnxjdgueazJCFsI5c5HK5rITV4a23ugD6CIIvbsSRFmFOLXkiAIRXmAIv5+9r/SkAQUgF9laXV87OlZ3j09EMCMluwZ303CzdlVm9hzkhccL7eJljKCmv5bJTpGSrGhHzzRubE8gwfd7OXlGKcxa0Y6stozBQ/vlSsz7Erz2yLCIcoARzAWrZD5xUJ1V+3UhwWrEsgSF4anFaKhXB1WU0uwiBT+t9vXmfQIE/rVmdghUG4BK5Z4Lk1z0Asag8ktb83PcEKNOSFZhAIjxesCzralws5XYBtPFyyye/YhHUixIetYIwLEG23asvP+UMxTnQ+KNbrrYePcVYGxJfs9Tcda8bbouxFwXln8SGwUWV6ZwxkFLBJ4KNYhQTZbHjgAnMBC2m7nok78QdY9VzChLoR267NebzZfDjIXFl0sZd1tB+uaQ5HISap1P2R3FZo6QyrC5rdqkP7Yd8j7FlCY8OVetV78WNtGAu4Ptxw+lAfkWckM6IVOFbdcxfM7RjN1qvLIhun2nDicKdR9Fq8HQCx5cc= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230022)(4636009)(346002)(376002)(39860400002)(136003)(396003)(451199015)(46966006)(40470700004)(36840700001)(36756003)(478600001)(81166007)(86362001)(356005)(47076005)(426003)(40460700003)(336012)(83380400001)(82740400003)(7696005)(6666004)(1076003)(2616005)(16526019)(186003)(26005)(41300700001)(70586007)(70206006)(4744005)(5660300002)(4326008)(8676002)(316002)(2906002)(40480700001)(8936002)(36860700001)(110136005)(54906003)(82310400005)(44832011)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Dec 2022 06:41:17.6134 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3ccb2026-0b1c-44bc-6b54-08dae18c0847 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT101.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN0PR12MB6174 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1752623700362127201?= X-GMAIL-MSGID: =?utf-8?q?1752623700362127201?= In the amd_pstate_adjust_perf(), there is one cpufreq_cpu_get() call to increase increments the kobject reference count of policy and make it as busy. Therefore, a corresponding call to cpufreq_cpu_put() is needed to decrement the kobject reference count back, it will resolve the kernel hang issue when unregistering the amd-pstate driver and register the `amd_pstate_epp` driver instance. Signed-off-by: Perry Yuan Acked-by: Huang Rui Reviewed-by: Mario Limonciello --- drivers/cpufreq/amd-pstate.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index 204e39006dda..c17bd845f5fc 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -307,6 +307,7 @@ static void amd_pstate_adjust_perf(unsigned int cpu, max_perf = min_perf; amd_pstate_update(cpudata, min_perf, des_perf, max_perf, true); + cpufreq_cpu_put(policy); } static int amd_get_min_freq(struct amd_cpudata *cpudata) From patchwork Mon Dec 19 06:40:34 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Yuan, Perry" X-Patchwork-Id: 34411 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:e747:0:0:0:0:0 with SMTP id c7csp2229687wrn; Sun, 18 Dec 2022 22:43:27 -0800 (PST) X-Google-Smtp-Source: AMrXdXuI6Q+Q+E56+tNhBbEcbCkjJ8t8B5EAsg6PosrNyzZqKT3TqUh9iNx8c+asrw4frgmmAJXf X-Received: by 2002:a05:6a20:3ca2:b0:9f:3197:bfa1 with SMTP id b34-20020a056a203ca200b0009f3197bfa1mr12665328pzj.7.1671432207084; Sun, 18 Dec 2022 22:43:27 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1671432207; cv=pass; d=google.com; s=arc-20160816; b=CyDUTGac4K7bZ0U5SHAjz0DOMs+rbMnmFd03jvNPEnxl9Y4UJnAX7+a4MyDklsBW57 u/mlgXEEIuvKy3fVH2GR6vN4CiLd6UJgnikQpaODN9A8DU861LUBOEvQygkrU+ejeng7 AhMS8PJ64gJm/3d5cO7AY21uU47GjaJ8F971LbfuKhSezzirQwOp2i9OjiTaQ36qOCHp GBim0IuWmFB8dCNKYE2n3lonPMdVBhr5u0Oku4IcxaRUvQmfB71BilZ2Cj0eWKgYGiqt FRI987Q0hAfzZmhfDsnQQQjPs/EKXhPzKYzSBHU8Ay0C83Zi1iKgFLv6f+IQWZ0ndtq1 fcaw== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=g607Gbfc0wzy0Md7QQLevN5MlXbFDshEp6Ypr6gr+cI=; b=zdVg8ulDHaLKipiFdFygpxagdlZnps5oJ9QxuF2lM1lWiFsn24ywn/lN0lAHmsabec 1JKIlXXaByT1xjxXJRCJJbGQ2v/vS4qFEY1VPC0Jp9ONhiYD8OSahXhTK0q4KtcrAe8G JTn4z2Ej936eRVZFX5ay3urwAE2y9DdC1zzR71EXmr4fd6KIyh7U091V3xE/FGsswEn9 teThe8qxdSf0ggtQsXzrxsBTmBdrnkqlMgRRH4XIiraRNhi9vHOfk2jG3dyiVhs/8NtV R4Rp6+nMos6ulldQwQROMUxqACJP0EUQXHpwHPcmyuaLUC2/C9F/fVhJWEDzvPcNseNl 6bLA== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amd.com header.s=selector1 header.b=xxpr6ODF; arc=pass (i=1 spf=pass spfdomain=amd.com dmarc=pass fromdomain=amd.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=amd.com Received: from out1.vger.email (out1.vger.email. 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Mon, 19 Dec 2022 00:41:17 -0600 From: Perry Yuan To: , , , CC: , , , , , , , , Subject: [PATCH v8 05/13] cpufreq: amd-pstate: optimize driver working mode selection in amd_pstate_param() Date: Mon, 19 Dec 2022 14:40:34 +0800 Message-ID: <20221219064042.661122-6-perry.yuan@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221219064042.661122-1-perry.yuan@amd.com> References: <20221219064042.661122-1-perry.yuan@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT098:EE_|SJ0PR12MB6712:EE_ X-MS-Office365-Filtering-Correlation-Id: 35dca283-d606-4032-0025-08dae18c0a6b X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: rm8kHqBAVRfR+Z6X1bp3p3whQf2bPxcJMQU1IBzFerf+cOPJ4eUFmsDOnosBvyFY+ZAkMETEL6VKrjWIwHfQHCIDk/FzyjCNJDsKpfQdQqWCEgmVdT30o8JRsFR3fWad4PCKdN6ajuqiMLa4WoF2jWJT0Taqq5mVXtJKbz9bfH7VZ7JULXRHGeed74zLubQvD0KIslFTpZWdJ2+ecij27ppZKaKph0veIh0SOEjfYd5ZqJAzg8BTex5daqaMzp90ucG3WUKp5Mf1jg/51ChKQkjGqM9GfEEs7SNOYppY6WdcWHCDhY2HkYKEJj1jDOVUJSSN9yDARt2ddehoNkX05ib2R9MRfw2IwTZn5KvsAf1WdT67vCSSC7rBpPInFe2AlUJPEBBcoY4DOdEA4KbggfKEXlEE/DzGhO6a4D1UQtRjDMlSbmuchOqwJI91F5HxUxi0kOV3RzGiOi7ggUBgrv1ZGA4k1kZxL2kD2tgMAFRiaEqAKvi3fzaQ3bhB1xfcluw4eupbbnGbP0bAMIh67ELmZtNECSR5Nr9AcjgneqGd9HXJnwU92i6b5C7EKyWGwDF6FSXh5SkUj1TiOrV4wcABDT04DoKESbW3wUj1BvOVYbsYJswNoab0pRRF9q+mUS/tK0xmURnUjqjrP6QW0zDkNwsU/9lKoHER11Qgby94xdhBFptyRBkg/EsBH9xTLtnj6eLNE0JZiHOAwH8C1bBDkvh9TFqJEtKNdVXCu10= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230022)(4636009)(346002)(376002)(136003)(39860400002)(396003)(451199015)(46966006)(40470700004)(36840700001)(5660300002)(8676002)(4326008)(44832011)(54906003)(70586007)(70206006)(110136005)(2906002)(478600001)(6666004)(16526019)(26005)(186003)(7696005)(41300700001)(426003)(47076005)(86362001)(40480700001)(83380400001)(82310400005)(36860700001)(2616005)(1076003)(336012)(82740400003)(356005)(81166007)(36756003)(8936002)(316002)(40460700003)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Dec 2022 06:41:21.2020 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 35dca283-d606-4032-0025-08dae18c0a6b X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT098.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ0PR12MB6712 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1752623698129336127?= X-GMAIL-MSGID: =?utf-8?q?1752623698129336127?= There are some other amd pstate driver working mode to be supported. Here we use cppc_state var to indicate which mode is enabled. This change will help to simplify the the amd_pstate_param() to choose which mode used for the following driver registeration. Signed-off-by: Perry Yuan Signed-off-by: Wyes Karny --- drivers/cpufreq/amd-pstate.c | 35 +++++++++++++++++++++++++++-------- include/linux/amd-pstate.h | 29 +++++++++++++++++++++++++++++ 2 files changed, 56 insertions(+), 8 deletions(-) diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index c17bd845f5fc..861a905f9324 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -60,7 +60,18 @@ * module parameter to be able to enable it manually for debugging. */ static struct cpufreq_driver amd_pstate_driver; -static int cppc_load __initdata; +static int cppc_state = AMD_PSTATE_DISABLE; + +static inline int get_mode_idx_from_str(const char *str, size_t size) +{ + int i; + + for (i=0; i < AMD_PSTATE_MAX; i++) { + if (!strncmp(str, amd_pstate_mode_string[i], size)) + return i; + } + return -EINVAL; +} static inline int pstate_enable(bool enable) { @@ -628,7 +639,7 @@ static int __init amd_pstate_init(void) * enable the amd_pstate passive mode driver explicitly * with amd_pstate=passive in kernel command line */ - if (!cppc_load) { + if (cppc_state == AMD_PSTATE_DISABLE) { pr_debug("driver load is disabled, boot with amd_pstate=passive to enable this\n"); return -ENODEV; } @@ -671,16 +682,24 @@ device_initcall(amd_pstate_init); static int __init amd_pstate_param(char *str) { + size_t size; + int mode_idx; + if (!str) return -EINVAL; - if (!strcmp(str, "disable")) { - cppc_load = 0; - pr_info("driver is explicitly disabled\n"); - } else if (!strcmp(str, "passive")) - cppc_load = 1; + size = strlen(str); + mode_idx = get_mode_idx_from_str(str, size); - return 0; + if (mode_idx >= AMD_PSTATE_DISABLE && mode_idx < AMD_PSTATE_MAX) { + cppc_state = mode_idx; + if (cppc_state == AMD_PSTATE_DISABLE) + pr_info("driver is explicitly disabled\n"); + + return 0; + } + + return -EINVAL; } early_param("amd_pstate", amd_pstate_param); diff --git a/include/linux/amd-pstate.h b/include/linux/amd-pstate.h index 1c4b8659f171..922d05a13902 100644 --- a/include/linux/amd-pstate.h +++ b/include/linux/amd-pstate.h @@ -74,4 +74,33 @@ struct amd_cpudata { bool boost_supported; }; +/** + * enum amd_pstate_mode - driver working mode of amd pstate + */ + +enum amd_pstate_mode { + /** @AMD_PSTATE_DISABLE: Driver mode is disabled */ + AMD_PSTATE_DISABLE = 0, + + /** @AMD_PSTATE_PASSIVE: Drier mode is passive mode */ + AMD_PSTATE_PASSIVE = 1, + + /** @AMD_PSTATE_ACTIVE: Driver mode is active mode */ + AMD_PSTATE_ACTIVE = 2, + + /** @AMD_PSTATE_GUIDE: Driver mode is guided mode */ + AMD_PSTATE_GUIDE = 3, + + /** @AMD_PSTATE_MAX */ + AMD_PSTATE_MAX = 4, +}; + +static const char * const amd_pstate_mode_string[] = { + [AMD_PSTATE_DISABLE] = "disable", + [AMD_PSTATE_PASSIVE] = "passive", + [AMD_PSTATE_ACTIVE] = "active", + [AMD_PSTATE_GUIDE] = "guide", + NULL, +}; + #endif /* _LINUX_AMD_PSTATE_H */ From patchwork Mon Dec 19 06:40:35 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Yuan, Perry" X-Patchwork-Id: 34413 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:e747:0:0:0:0:0 with SMTP id c7csp2229882wrn; Sun, 18 Dec 2022 22:44:00 -0800 (PST) X-Google-Smtp-Source: AA0mqf5xRtf5/8XQWgvKtNfBMptFqRxCjG3YzKI/6/ka+43RUBLkBYvz6Un1FrDyP282nHP8Ti6B X-Received: by 2002:a05:6a20:320e:b0:aa:7548:883d with SMTP id y14-20020a056a20320e00b000aa7548883dmr72875979pzc.11.1671432240028; Sun, 18 Dec 2022 22:44:00 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1671432240; cv=pass; d=google.com; s=arc-20160816; b=qtFVzJp92V3LTTdjmcVlOft+7XOieTSZKPBkMHpWmD97ehMa8GfVjsz3zr4RuG//F5 PsF7nWfGYf+XxmD8DA/67P3RWCASGzIh2P89WmyO5+5foTsDqn1TXDwj9H0fh/gNvIa/ 4k90QxSS5W48ZQfP2SSgRmMuANLBpJ2TIZiMTWKZMnGO3lg5I47g2UsOY0mvi1jwiS19 XDRC7w7m1PffvGaDb0tzQFIhAGyj0YM50stx0NKLhemUURP8EOPShWaSsguHehBcUfuH raOO5CcQl8d72HJEon6GjRerC0/bqsBg7oiIiWOBmH8u4g5ywPOy397uxy3LRpywUdxs OXKg== ARC-Message-Signature: i=2; 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Mon, 19 Dec 2022 00:41:21 -0600 From: Perry Yuan To: , , , CC: , , , , , , , , Subject: [PATCH v8 06/13] cpufreq: amd-pstate: implement Pstate EPP support for the AMD processors Date: Mon, 19 Dec 2022 14:40:35 +0800 Message-ID: <20221219064042.661122-7-perry.yuan@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221219064042.661122-1-perry.yuan@amd.com> References: <20221219064042.661122-1-perry.yuan@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT098:EE_|CH0PR12MB5252:EE_ X-MS-Office365-Filtering-Correlation-Id: 3199ee32-38ed-48fc-be9e-08dae18c182e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: /It6wlW0oamWDOkIxnctFgaW0lRDKHL15ZItFAFCxJGot7MxZAdthOPHNdMQPOA+R9hwKLN1ekghqa4Ks54hh0xGMGtrjKgpPyewOH0aJSoqFeUoEQA0hLB/26FkDFxk3Ha7LoJW/XLasItG5IQSq6+0ji784xKYg+y9SYJFzdTyVxqMeE7y3t/N8bDrrqQabyOc+KJWVt7A8gOt62w8MblktdPw2VPciWjaHaoR0dz8y/lo6PYzijU45e2rb8t6RySe8pdX3nyhtlolzhfXYqy/ph/H80O7PlByGyXdfuCNGgqhWV9Q+P3658lzh9OQtGOZfoZe5lXPsuEGDEOQ13/hG8jmD6rdT++P4pQoG6QqHI0BiZX2PFwwbmVdF6TSS+Ldipoh4nUPwTcQkaai9MZwgGOMMMghASH6Uv7Q+4uhefLe+dTrpaktvrTL7KJsMy3/t+aGuAF/fSGmGErnqTd1L/oV5GBKJlR47s8mpa+9jR2MIcTZ5xr4O8H8fs0FQtoBkVYl7cCcPro8gwyqzb4ax/O+5uQ23nq/BwqbR99pBIvT/mCF9uaC6OyleU9AQjBa3wFzf1MZHniEKl7F5c8CbxMoZVWth7px5Qnoz9yJeM805D/kMdy7Vzc5X/nQtNZMLzrpp0NWfqL7l4VeRjTgU9jqVaolh0jIJKQudiOSVD/xxTjQrJxRbMazb9DaADI6xxV6bB9RwpXv7MMsE0EA9pBdvdb2q5kdYl3vSbw= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230022)(4636009)(396003)(136003)(376002)(346002)(39860400002)(451199015)(40470700004)(46966006)(36840700001)(40480700001)(2906002)(82310400005)(16526019)(316002)(40460700003)(4326008)(1076003)(70206006)(8676002)(70586007)(54906003)(110136005)(336012)(7696005)(2616005)(86362001)(36860700001)(36756003)(478600001)(5660300002)(81166007)(83380400001)(6666004)(26005)(8936002)(426003)(47076005)(82740400003)(41300700001)(186003)(356005)(44832011)(30864003)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Dec 2022 06:41:44.2952 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3199ee32-38ed-48fc-be9e-08dae18c182e X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT098.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH0PR12MB5252 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1752623732308173420?= X-GMAIL-MSGID: =?utf-8?q?1752623732308173420?= From: Perry Yuan Add EPP driver support for AMD SoCs which support a dedicated MSR for CPPC. EPP is used by the DPM controller to configure the frequency that a core operates at during short periods of activity. The SoC EPP targets are configured on a scale from 0 to 255 where 0 represents maximum performance and 255 represents maximum efficiency. The amd-pstate driver exports profile string names to userspace that are tied to specific EPP values. The balance_performance string (0x80) provides the best balance for efficiency versus power on most systems, but users can choose other strings to meet their needs as well. $ cat /sys/devices/system/cpu/cpufreq/policy0/energy_performance_available_preferences default performance balance_performance balance_power power $ cat /sys/devices/system/cpu/cpufreq/policy0/energy_performance_preference balance_performance To enable the driver,it needs to add `amd_pstate=active` to kernel command line and kernel will load the active mode epp driver Signed-off-by: Perry Yuan --- drivers/cpufreq/amd-pstate.c | 447 ++++++++++++++++++++++++++++++++++- include/linux/amd-pstate.h | 10 + 2 files changed, 451 insertions(+), 6 deletions(-) diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index 861a905f9324..66b39457a312 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -59,7 +59,10 @@ * we disable it by default to go acpi-cpufreq on these processors and add a * module parameter to be able to enable it manually for debugging. */ +static struct cpufreq_driver *default_pstate_driver; static struct cpufreq_driver amd_pstate_driver; +static struct cpufreq_driver amd_pstate_epp_driver; +static struct amd_cpudata **all_cpu_data; static int cppc_state = AMD_PSTATE_DISABLE; static inline int get_mode_idx_from_str(const char *str, size_t size) @@ -70,9 +73,128 @@ static inline int get_mode_idx_from_str(const char *str, size_t size) if (!strncmp(str, amd_pstate_mode_string[i], size)) return i; } + return -EINVAL; } +/** + * struct amd_pstate_params - global parameters for the performance control + * @ cppc_boost_disabled wheher the core performance boost disabled + */ +struct amd_pstate_params { + bool cppc_boost_disabled; +}; + +static struct amd_pstate_params global_params; + +static DEFINE_MUTEX(amd_pstate_limits_lock); +static DEFINE_MUTEX(amd_pstate_driver_lock); + +static s16 amd_pstate_get_epp(struct amd_cpudata *cpudata, u64 cppc_req_cached) +{ + u64 epp; + int ret; + + if (boot_cpu_has(X86_FEATURE_CPPC)) { + if (!cppc_req_cached) { + epp = rdmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ, + &cppc_req_cached); + if (epp) + return epp; + } + epp = (cppc_req_cached >> 24) & 0xFF; + } else { + ret = cppc_get_epp_perf(cpudata->cpu, &epp); + if (ret < 0) { + pr_debug("Could not retrieve energy perf value (%d)\n", ret); + return -EIO; + } + } + + return (s16)(epp & 0xff); +} + +static int amd_pstate_get_energy_pref_index(struct amd_cpudata *cpudata) +{ + s16 epp; + int index = -EINVAL; + + epp = amd_pstate_get_epp(cpudata, 0); + if (epp < 0) + return epp; + + switch (epp) { + case HWP_EPP_PERFORMANCE: + index = EPP_INDEX_PERFORMANCE; + break; + case HWP_EPP_BALANCE_PERFORMANCE: + index = EPP_INDEX_BALANCE_PERFORMANCE; + break; + case HWP_EPP_BALANCE_POWERSAVE: + index = EPP_INDEX_BALANCE_POWERSAVE; + break; + case HWP_EPP_POWERSAVE: + index = EPP_INDEX_POWERSAVE; + break; + default: + break; + } + + return index; +} + +static int amd_pstate_set_epp(struct amd_cpudata *cpudata, u32 epp) +{ + int ret; + struct cppc_perf_ctrls perf_ctrls; + + if (boot_cpu_has(X86_FEATURE_CPPC)) { + u64 value = READ_ONCE(cpudata->cppc_req_cached); + + value &= ~GENMASK_ULL(31, 24); + value |= (u64)epp << 24; + WRITE_ONCE(cpudata->cppc_req_cached, value); + + ret = wrmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ, value); + if (!ret) + cpudata->epp_cached = epp; + } else { + perf_ctrls.energy_perf = epp; + ret = cppc_set_epp_perf(cpudata->cpu, &perf_ctrls, 1); + if (ret) { + pr_debug("failed to set energy perf value (%d)\n", ret); + return ret; + } + cpudata->epp_cached = epp; + } + + return ret; +} + +static int amd_pstate_set_energy_pref_index(struct amd_cpudata *cpudata, + int pref_index) +{ + int epp = -EINVAL; + int ret; + + if (!pref_index) { + pr_debug("EPP pref_index is invalid\n"); + return -EINVAL; + } + + if (epp == -EINVAL) + epp = epp_values[pref_index]; + + if (epp > 0 && cpudata->policy == CPUFREQ_POLICY_PERFORMANCE) { + pr_debug("EPP cannot be set under performance policy\n"); + return -EBUSY; + } + + ret = amd_pstate_set_epp(cpudata, epp); + + return ret; +} + static inline int pstate_enable(bool enable) { return wrmsrl_safe(MSR_AMD_CPPC_ENABLE, enable); @@ -81,11 +203,21 @@ static inline int pstate_enable(bool enable) static int cppc_enable(bool enable) { int cpu, ret = 0; + struct cppc_perf_ctrls perf_ctrls; for_each_present_cpu(cpu) { ret = cppc_set_enable(cpu, enable); if (ret) return ret; + + /* Enable autonomous mode for EPP */ + if (cppc_state == AMD_PSTATE_ACTIVE) { + /* Set desired perf as zero to allow EPP firmware control */ + perf_ctrls.desired_perf = 0; + ret = cppc_set_perf(cpu, &perf_ctrls); + if (ret) + return ret; + } } return ret; @@ -429,7 +561,7 @@ static void amd_pstate_boost_init(struct amd_cpudata *cpudata) return; cpudata->boost_supported = true; - amd_pstate_driver.boost_enabled = true; + default_pstate_driver->boost_enabled = true; } static void amd_perf_ctl_reset(unsigned int cpu) @@ -603,10 +735,61 @@ static ssize_t show_amd_pstate_highest_perf(struct cpufreq_policy *policy, return sprintf(&buf[0], "%u\n", perf); } +static ssize_t show_energy_performance_available_preferences( + struct cpufreq_policy *policy, char *buf) +{ + int i = 0; + int offset = 0; + + while (energy_perf_strings[i] != NULL) + offset += sysfs_emit_at(buf, offset, "%s ", energy_perf_strings[i++]); + + sysfs_emit_at(buf, offset, "\n"); + + return offset; +} + +static ssize_t store_energy_performance_preference( + struct cpufreq_policy *policy, const char *buf, size_t count) +{ + struct amd_cpudata *cpudata = policy->driver_data; + char str_preference[21]; + ssize_t ret; + + ret = sscanf(buf, "%20s", str_preference); + if (ret != 1) + return -EINVAL; + + ret = match_string(energy_perf_strings, -1, str_preference); + if (ret < 0) + return -EINVAL; + + mutex_lock(&amd_pstate_limits_lock); + ret = amd_pstate_set_energy_pref_index(cpudata, ret); + mutex_unlock(&amd_pstate_limits_lock); + + return ret ?: count; +} + +static ssize_t show_energy_performance_preference( + struct cpufreq_policy *policy, char *buf) +{ + struct amd_cpudata *cpudata = policy->driver_data; + int preference; + + preference = amd_pstate_get_energy_pref_index(cpudata); + if (preference < 0) + return preference; + + return sysfs_emit(buf, "%s\n", energy_perf_strings[preference]); +} + cpufreq_freq_attr_ro(amd_pstate_max_freq); cpufreq_freq_attr_ro(amd_pstate_lowest_nonlinear_freq); cpufreq_freq_attr_ro(amd_pstate_highest_perf); +cpufreq_freq_attr_rw(energy_performance_preference); +cpufreq_freq_attr_ro(energy_performance_available_preferences); static struct freq_attr *amd_pstate_attr[] = { &amd_pstate_max_freq, @@ -615,6 +798,235 @@ static struct freq_attr *amd_pstate_attr[] = { NULL, }; +static struct freq_attr *amd_pstate_epp_attr[] = { + &amd_pstate_max_freq, + &amd_pstate_lowest_nonlinear_freq, + &amd_pstate_highest_perf, + &energy_performance_preference, + &energy_performance_available_preferences, + NULL, +}; + +static inline void update_boost_state(void) +{ + u64 misc_en; + struct amd_cpudata *cpudata; + + cpudata = all_cpu_data[0]; + rdmsrl(MSR_K7_HWCR, misc_en); + global_params.cppc_boost_disabled = misc_en & BIT_ULL(25); +} + +static int amd_pstate_init_cpu(unsigned int cpunum) +{ + struct amd_cpudata *cpudata; + + cpudata = all_cpu_data[cpunum]; + if (!cpudata) { + cpudata = kzalloc(sizeof(*cpudata), GFP_KERNEL); + if (!cpudata) + return -ENOMEM; + WRITE_ONCE(all_cpu_data[cpunum], cpudata); + + cpudata->cpu = cpunum; + } + + cpudata->epp_policy = 0; + pr_debug("controlling: cpu %d\n", cpunum); + return 0; +} + +static int amd_pstate_epp_cpu_init(struct cpufreq_policy *policy) +{ + int min_freq, max_freq, nominal_freq, lowest_nonlinear_freq, ret; + struct amd_cpudata *cpudata; + struct device *dev; + int rc; + u64 value; + + rc = amd_pstate_init_cpu(policy->cpu); + if (rc) + return rc; + + cpudata = all_cpu_data[policy->cpu]; + + dev = get_cpu_device(policy->cpu); + if (!dev) + goto free_cpudata1; + + rc = amd_pstate_init_perf(cpudata); + if (rc) + goto free_cpudata1; + + min_freq = amd_get_min_freq(cpudata); + max_freq = amd_get_max_freq(cpudata); + nominal_freq = amd_get_nominal_freq(cpudata); + lowest_nonlinear_freq = amd_get_lowest_nonlinear_freq(cpudata); + if (min_freq < 0 || max_freq < 0 || min_freq > max_freq) { + dev_err(dev, "min_freq(%d) or max_freq(%d) value is incorrect\n", + min_freq, max_freq); + ret = -EINVAL; + goto free_cpudata1; + } + + policy->min = min_freq; + policy->max = max_freq; + + policy->cpuinfo.min_freq = min_freq; + policy->cpuinfo.max_freq = max_freq; + /* It will be updated by governor */ + policy->cur = policy->cpuinfo.min_freq; + + /* Initial processor data capability frequencies */ + cpudata->max_freq = max_freq; + cpudata->min_freq = min_freq; + cpudata->nominal_freq = nominal_freq; + cpudata->lowest_nonlinear_freq = lowest_nonlinear_freq; + + policy->driver_data = cpudata; + + cpudata->epp_cached = amd_pstate_get_epp(cpudata, value); + + policy->min = policy->cpuinfo.min_freq; + policy->max = policy->cpuinfo.max_freq; + + /* + * Set the policy to powersave to provide a valid fallback value in case + * the default cpufreq governor is neither powersave nor performance. + */ + policy->policy = CPUFREQ_POLICY_POWERSAVE; + + if (boot_cpu_has(X86_FEATURE_CPPC)) { + policy->fast_switch_possible = true; + ret = rdmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ, &value); + if (ret) + return ret; + WRITE_ONCE(cpudata->cppc_req_cached, value); + + ret = rdmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_CAP1, &value); + if (ret) + return ret; + WRITE_ONCE(cpudata->cppc_cap1_cached, value); + } + amd_pstate_boost_init(cpudata); + + return 0; + +free_cpudata1: + kfree(cpudata); + return ret; +} + +static int amd_pstate_epp_cpu_exit(struct cpufreq_policy *policy) +{ + pr_debug("CPU %d exiting\n", policy->cpu); + policy->fast_switch_possible = false; + return 0; +} + +static void amd_pstate_update_max_freq(unsigned int cpu) +{ + struct cpufreq_policy *policy = cpufreq_cpu_get(cpu); + + if (!policy) + return; + + refresh_frequency_limits(policy); + cpufreq_cpu_put(policy); +} + +static void amd_pstate_epp_update_limits(unsigned int cpu) +{ + mutex_lock(&amd_pstate_driver_lock); + update_boost_state(); + if (global_params.cppc_boost_disabled) { + for_each_possible_cpu(cpu) + amd_pstate_update_max_freq(cpu); + } else { + cpufreq_update_policy(cpu); + } + mutex_unlock(&amd_pstate_driver_lock); +} + +static void amd_pstate_epp_init(unsigned int cpu) +{ + struct amd_cpudata *cpudata = all_cpu_data[cpu]; + u32 max_perf, min_perf; + u64 value; + s16 epp; + + max_perf = READ_ONCE(cpudata->highest_perf); + min_perf = READ_ONCE(cpudata->lowest_perf); + + value = READ_ONCE(cpudata->cppc_req_cached); + + if (cpudata->policy == CPUFREQ_POLICY_PERFORMANCE) + min_perf = max_perf; + + /* Initial min/max values for CPPC Performance Controls Register */ + value &= ~AMD_CPPC_MIN_PERF(~0L); + value |= AMD_CPPC_MIN_PERF(min_perf); + + value &= ~AMD_CPPC_MAX_PERF(~0L); + value |= AMD_CPPC_MAX_PERF(max_perf); + + /* CPPC EPP feature require to set zero to the desire perf bit */ + value &= ~AMD_CPPC_DES_PERF(~0L); + value |= AMD_CPPC_DES_PERF(0); + + if (cpudata->epp_policy == cpudata->policy) + goto skip_epp; + + cpudata->epp_policy = cpudata->policy; + + if (cpudata->policy == CPUFREQ_POLICY_PERFORMANCE) { + epp = amd_pstate_get_epp(cpudata, value); + if (epp < 0) + goto skip_epp; + /* force the epp value to be zero for performance policy */ + epp = 0; + } else { + /* Get BIOS pre-defined epp value */ + epp = amd_pstate_get_epp(cpudata, value); + if (epp) + goto skip_epp; + } + /* Set initial EPP value */ + if (boot_cpu_has(X86_FEATURE_CPPC)) { + value &= ~GENMASK_ULL(31, 24); + value |= (u64)epp << 24; + } + +skip_epp: + WRITE_ONCE(cpudata->cppc_req_cached, value); + amd_pstate_set_epp(cpudata, epp); +} + +static int amd_pstate_epp_set_policy(struct cpufreq_policy *policy) +{ + struct amd_cpudata *cpudata; + + if (!policy->cpuinfo.max_freq) + return -ENODEV; + + pr_debug("set_policy: cpuinfo.max %u policy->max %u\n", + policy->cpuinfo.max_freq, policy->max); + + cpudata = all_cpu_data[policy->cpu]; + cpudata->policy = policy->policy; + + amd_pstate_epp_init(policy->cpu); + + return 0; +} + +static int amd_pstate_epp_verify_policy(struct cpufreq_policy_data *policy) +{ + cpufreq_verify_within_cpu_limits(policy); + pr_debug("policy_max =%d, policy_min=%d\n", policy->max, policy->min); + return 0; +} + static struct cpufreq_driver amd_pstate_driver = { .flags = CPUFREQ_CONST_LOOPS | CPUFREQ_NEED_UPDATE_LIMITS, .verify = amd_pstate_verify, @@ -628,8 +1040,20 @@ static struct cpufreq_driver amd_pstate_driver = { .attr = amd_pstate_attr, }; +static struct cpufreq_driver amd_pstate_epp_driver = { + .flags = CPUFREQ_CONST_LOOPS, + .verify = amd_pstate_epp_verify_policy, + .setpolicy = amd_pstate_epp_set_policy, + .init = amd_pstate_epp_cpu_init, + .exit = amd_pstate_epp_cpu_exit, + .update_limits = amd_pstate_epp_update_limits, + .name = "amd_pstate_epp", + .attr = amd_pstate_epp_attr, +}; + static int __init amd_pstate_init(void) { + static struct amd_cpudata **cpudata; int ret; if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD) @@ -656,7 +1080,8 @@ static int __init amd_pstate_init(void) /* capability check */ if (boot_cpu_has(X86_FEATURE_CPPC)) { pr_debug("AMD CPPC MSR based functionality is supported\n"); - amd_pstate_driver.adjust_perf = amd_pstate_adjust_perf; + if (cppc_state == AMD_PSTATE_PASSIVE) + default_pstate_driver->adjust_perf = amd_pstate_adjust_perf; } else { pr_debug("AMD CPPC shared memory based functionality is supported\n"); static_call_update(amd_pstate_enable, cppc_enable); @@ -664,17 +1089,21 @@ static int __init amd_pstate_init(void) static_call_update(amd_pstate_update_perf, cppc_update_perf); } + cpudata = vzalloc(array_size(sizeof(void *), num_possible_cpus())); + if (!cpudata) + return -ENOMEM; + WRITE_ONCE(all_cpu_data, cpudata); + /* enable amd pstate feature */ ret = amd_pstate_enable(true); if (ret) { - pr_err("failed to enable amd-pstate with return %d\n", ret); + pr_err("failed to enable with return %d\n", ret); return ret; } - ret = cpufreq_register_driver(&amd_pstate_driver); + ret = cpufreq_register_driver(default_pstate_driver); if (ret) - pr_err("failed to register amd_pstate_driver with return %d\n", - ret); + pr_err("failed to register with return %d\n", ret); return ret; } @@ -696,6 +1125,12 @@ static int __init amd_pstate_param(char *str) if (cppc_state == AMD_PSTATE_DISABLE) pr_info("driver is explicitly disabled\n"); + if (cppc_state == AMD_PSTATE_ACTIVE) + default_pstate_driver = &amd_pstate_epp_driver; + + if (cppc_state == AMD_PSTATE_PASSIVE) + default_pstate_driver = &amd_pstate_driver; + return 0; } diff --git a/include/linux/amd-pstate.h b/include/linux/amd-pstate.h index 922d05a13902..fe1aef743c09 100644 --- a/include/linux/amd-pstate.h +++ b/include/linux/amd-pstate.h @@ -47,6 +47,10 @@ struct amd_aperf_mperf { * @prev: Last Aperf/Mperf/tsc count value read from register * @freq: current cpu frequency value * @boost_supported: check whether the Processor or SBIOS supports boost mode + * @epp_policy: Last saved policy used to set energy-performance preference + * @epp_cached: Cached CPPC energy-performance preference value + * @policy: Cpufreq policy value + * @cppc_cap1_cached Cached MSR_AMD_CPPC_CAP1 register value * * The amd_cpudata is key private data for each CPU thread in AMD P-State, and * represents all the attributes and goals that AMD P-State requests at runtime. @@ -72,6 +76,12 @@ struct amd_cpudata { u64 freq; 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Mon, 19 Dec 2022 00:41:40 -0600 From: Perry Yuan To: , , , CC: , , , , , , , , Subject: [PATCH v8 07/13] cpufreq: amd-pstate: implement amd pstate cpu online and offline callback Date: Mon, 19 Dec 2022 14:40:36 +0800 Message-ID: <20221219064042.661122-8-perry.yuan@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221219064042.661122-1-perry.yuan@amd.com> References: <20221219064042.661122-1-perry.yuan@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT056:EE_|SJ1PR12MB6219:EE_ X-MS-Office365-Filtering-Correlation-Id: 58f1e912-7c53-4708-0fe1-08dae18c187a X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: f6DQ5lFX9NknbZOZr8ZtfiUXNsbi6H15VsS0KMy8q2oTXFbZNW7fOp1JNkFDpQ/BWzr05m9DKIDeDtbKBEuRpXpiRn5+cvWaTtcLloOHBvj3+c6xRL2r+VAanpQi89xYW8UYs6CG1lnERJj4yro1BXevOpA3G1mx81IHKOX/6q2mfuonCfK6hm2779Cm9CjTlHV9OcXsEQkkdF/5EBpMkq4im3KkccF6OkpuO5cLWzwRVZ3i2cfg0ILHjY0UmpJu2/Y58ZakjHsoanwJaXkN9iQAkowUlq4bOxu9lQZyi/Y15dq7x46MHs8enlD1ATOf3td0w7dXjmIfCi2kp9ksemh9BvPhNAqKI8pnsoyBnVV/GhNDQu9Yb7tinOvet2QDAeIyKnebNrlKVA8WmMO4iNWc59DiB5keWNMgz5lxd5qmN2NNhIWr7sWz7jXAEA3JBK9qoSJTaIU8XkLZnc/AzYOCSPKL6RRgXeYOX6WoYcCiP6Rt1+ECTp4wmj6rL8DZ3Z9Jx5V4Gwow1smmtO/6EiN+EAmqtH7rqjmP977UKW8iL5OQ1kzWO4NC4/BjN3Mbg5vbGn4HXGwLbTce9DrRSaDPd0uEMLxKW2lVIXTy3yY7oLQMQdDa/tkWHD8xKDvXTTkOIRrAw9jx6P5zLYg4s1+hae5B6r94uvNKKQgajRGo7iB2WkOpsReAoCips7uW8s/iUW/09OjzAiVu58h/Yn5Z9AMoCAS4/O5H54SXKdY= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230022)(4636009)(396003)(39860400002)(346002)(376002)(136003)(451199015)(36840700001)(40470700004)(46966006)(44832011)(83380400001)(2906002)(336012)(41300700001)(356005)(8936002)(426003)(5660300002)(47076005)(82310400005)(40480700001)(86362001)(36860700001)(36756003)(40460700003)(81166007)(316002)(7696005)(54906003)(110136005)(478600001)(82740400003)(186003)(26005)(70586007)(16526019)(70206006)(2616005)(6666004)(4326008)(1076003)(8676002)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Dec 2022 06:41:44.7888 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 58f1e912-7c53-4708-0fe1-08dae18c187a X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT056.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ1PR12MB6219 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1752623736565194920?= X-GMAIL-MSGID: =?utf-8?q?1752623736565194920?= From: Perry Yuan Adds online and offline driver callback support to allow cpu cores go offline and help to restore the previous working states when core goes back online later for EPP driver mode. Reviewed-by: Mario Limonciello Signed-off-by: Perry Yuan Acked-by: Huang Rui --- drivers/cpufreq/amd-pstate.c | 82 ++++++++++++++++++++++++++++++++++++ include/linux/amd-pstate.h | 1 + 2 files changed, 83 insertions(+) diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index 66b39457a312..cb647f55a169 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -1020,6 +1020,86 @@ static int amd_pstate_epp_set_policy(struct cpufreq_policy *policy) return 0; } +static void amd_pstate_epp_reenable(struct amd_cpudata *cpudata) +{ + struct cppc_perf_ctrls perf_ctrls; + u64 value, max_perf; + int ret; + + ret = amd_pstate_enable(true); + if (ret) + pr_err("failed to enable amd pstate during resume, return %d\n", ret); + + value = READ_ONCE(cpudata->cppc_req_cached); + max_perf = READ_ONCE(cpudata->highest_perf); + + if (boot_cpu_has(X86_FEATURE_CPPC)) { + wrmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ, value); + } else { + perf_ctrls.max_perf = max_perf; + perf_ctrls.energy_perf = AMD_CPPC_ENERGY_PERF_PREF(cpudata->epp_cached); + cppc_set_perf(cpudata->cpu, &perf_ctrls); + } +} + +static int amd_pstate_epp_cpu_online(struct cpufreq_policy *policy) +{ + struct amd_cpudata *cpudata = all_cpu_data[policy->cpu]; + + pr_debug("AMD CPU Core %d going online\n", cpudata->cpu); + + if (cppc_state == AMD_PSTATE_ACTIVE) { + amd_pstate_epp_reenable(cpudata); + cpudata->suspended = false; + } + + return 0; +} + +static void amd_pstate_epp_offline(struct cpufreq_policy *policy) +{ + struct amd_cpudata *cpudata = all_cpu_data[policy->cpu]; + struct cppc_perf_ctrls perf_ctrls; + int min_perf; + u64 value; + + min_perf = READ_ONCE(cpudata->lowest_perf); + value = READ_ONCE(cpudata->cppc_req_cached); + + mutex_lock(&amd_pstate_limits_lock); + if (boot_cpu_has(X86_FEATURE_CPPC)) { + cpudata->epp_policy = CPUFREQ_POLICY_UNKNOWN; + + /* Set max perf same as min perf */ + value &= ~AMD_CPPC_MAX_PERF(~0L); + value |= AMD_CPPC_MAX_PERF(min_perf); + value &= ~AMD_CPPC_MIN_PERF(~0L); + value |= AMD_CPPC_MIN_PERF(min_perf); + wrmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ, value); + } else { + perf_ctrls.desired_perf = 0; + perf_ctrls.max_perf = min_perf; + perf_ctrls.energy_perf = AMD_CPPC_ENERGY_PERF_PREF(HWP_EPP_BALANCE_POWERSAVE); + cppc_set_perf(cpudata->cpu, &perf_ctrls); + } + mutex_unlock(&amd_pstate_limits_lock); +} + +static int amd_pstate_epp_cpu_offline(struct cpufreq_policy *policy) +{ + struct amd_cpudata *cpudata = all_cpu_data[policy->cpu]; + + pr_debug("AMD CPU Core %d going offline\n", cpudata->cpu); + + if (cpudata->suspended) + return 0; + + if (cppc_state == AMD_PSTATE_ACTIVE) + amd_pstate_epp_offline(policy); + + return 0; +} + static int amd_pstate_epp_verify_policy(struct cpufreq_policy_data *policy) { cpufreq_verify_within_cpu_limits(policy); @@ -1047,6 +1127,8 @@ static struct cpufreq_driver amd_pstate_epp_driver = { .init = amd_pstate_epp_cpu_init, .exit = amd_pstate_epp_cpu_exit, .update_limits = amd_pstate_epp_update_limits, + .offline = amd_pstate_epp_cpu_offline, + .online = amd_pstate_epp_cpu_online, .name = "amd_pstate_epp", .attr = amd_pstate_epp_attr, }; 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Mon, 19 Dec 2022 00:41:44 -0600 From: Perry Yuan To: , , , CC: , , , , , , , , Subject: [PATCH v8 08/13] cpufreq: amd-pstate: implement suspend and resume callbacks Date: Mon, 19 Dec 2022 14:40:37 +0800 Message-ID: <20221219064042.661122-9-perry.yuan@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221219064042.661122-1-perry.yuan@amd.com> References: <20221219064042.661122-1-perry.yuan@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT056:EE_|BL1PR12MB5923:EE_ X-MS-Office365-Filtering-Correlation-Id: 831b0681-0571-4787-c7a6-08dae18c1a62 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: AIuCZXfkwo8mTdpPZocjgj3zGMYIucEPxe6uxRG1l2WJq37qbq5powH7g6kaD2Z/LRLr0MEBgKfOmGLyFmSZEBa6n9GepB5l6KBER9Rq5XlrAnn/isD8I3Otfyi1D3O7kWGTX4iAr1meza3B5fNECXkYPJLqUQxUn3HS0WSSclaydyPst0Ec6XsP+D1u7IxlCGDnsLbW9IjRoF34+E86XzcEXvbv9waVEdzQQ/AhFjiNf3MvrcLb7xQpuM+rZX7ocAaVAKiO34yPmmPlDxqoVXP2uSyQ5EomGV4lDQixbZ1SZLZz43Azfhc9EvaHB97yiRnwFaMD9l0Ock9B0MxQ5urtncGTUkG3IeHy753uz0CBqbkYuu2VmocDbbooHQBq1FntF9K0kjuRDdRrlwFG2itO/2vBEXwQtAhFBRIXeZ2lrfDv2Ib8uS8/4km+YcyFQ5SK8QEmrujcGkzSFdiZ5Qgof7KrR1U+wKbUYJ7AAZeqLt09DVitz2Y46Gosj59WEI/7VgQRrPp5pqZ7r9/TdoiZRe8YBkQ4jXJ/4y5fYBxCpSv9k+3Kj7SeVjsSxrQatRBp51VNFlENqcim4MBM8U7fpOYmAYJL8mLisq/Ao6EMdaLIrpKIArgcussplBWldDjTMqV+8MoT6PjV4UN+E1XI2AgM2mczsTwd9QKEO5aN7d0A4bJ1SEBLpXxq7bA2kqGOC91+Lv/f0b6wyVt4mGlN1YQ4jYf1uQDq+e9otfY= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230022)(4636009)(396003)(376002)(39860400002)(136003)(346002)(451199015)(46966006)(36840700001)(40470700004)(54906003)(36860700001)(110136005)(336012)(44832011)(15650500001)(41300700001)(4326008)(47076005)(40460700003)(86362001)(426003)(36756003)(8936002)(5660300002)(83380400001)(2906002)(316002)(8676002)(40480700001)(2616005)(16526019)(70586007)(70206006)(1076003)(82310400005)(6666004)(26005)(186003)(82740400003)(81166007)(478600001)(356005)(7696005)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Dec 2022 06:41:47.9917 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 831b0681-0571-4787-c7a6-08dae18c1a62 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT056.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL1PR12MB5923 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1752623739025387910?= X-GMAIL-MSGID: =?utf-8?q?1752623739025387910?= From: Perry Yuan add suspend and resume support for the AMD processors by amd_pstate_epp driver instance. When the CPPC is suspended, EPP driver will set EPP profile to 'power' profile and set max/min perf to lowest perf value. When resume happens, it will restore the MSR registers with previous cached value. Reviewed-by: Mario Limonciello Signed-off-by: Perry Yuan Acked-by: Huang Rui --- drivers/cpufreq/amd-pstate.c | 41 ++++++++++++++++++++++++++++++++++++ 1 file changed, 41 insertions(+) diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index cb647f55a169..fc12d35bc7bd 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -1107,6 +1107,45 @@ static int amd_pstate_epp_verify_policy(struct cpufreq_policy_data *policy) return 0; } +static int amd_pstate_epp_suspend(struct cpufreq_policy *policy) +{ + struct amd_cpudata *cpudata = all_cpu_data[policy->cpu]; + int ret; + + /* avoid suspending when EPP is not enabled */ + if (cppc_state != AMD_PSTATE_ACTIVE) + return 0; + + /* set this flag to avoid setting core offline*/ + cpudata->suspended = true; + + /* disable CPPC in lowlevel firmware */ + ret = amd_pstate_enable(false); + if (ret) + pr_err("failed to suspend, return %d\n", ret); + + return 0; +} + +static int amd_pstate_epp_resume(struct cpufreq_policy *policy) +{ + struct amd_cpudata *cpudata = all_cpu_data[policy->cpu]; + + if (cpudata->suspended) { + mutex_lock(&amd_pstate_limits_lock); + + /* enable amd pstate from suspend state*/ + amd_pstate_epp_reenable(cpudata); + + mutex_unlock(&amd_pstate_limits_lock); + + cpudata->suspended = false; + } + + return 0; +} + + static struct cpufreq_driver amd_pstate_driver = { .flags = CPUFREQ_CONST_LOOPS | CPUFREQ_NEED_UPDATE_LIMITS, .verify = amd_pstate_verify, @@ -1129,6 +1168,8 @@ static struct cpufreq_driver amd_pstate_epp_driver = { .update_limits = amd_pstate_epp_update_limits, .offline = amd_pstate_epp_cpu_offline, .online = amd_pstate_epp_cpu_online, + .suspend = amd_pstate_epp_suspend, + .resume = amd_pstate_epp_resume, .name = "amd_pstate_epp", .attr = amd_pstate_epp_attr, }; From patchwork Mon Dec 19 06:40:38 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Yuan, Perry" X-Patchwork-Id: 34417 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:e747:0:0:0:0:0 with SMTP id c7csp2230023wrn; Sun, 18 Dec 2022 22:44:24 -0800 (PST) X-Google-Smtp-Source: AMrXdXtmtFPy/qANIpqgS/9RqtZW9wkXt+JciVK9geQKqCaD/dt+szsrETo2eRizqjzRu3gxhW4K X-Received: by 2002:aa7:9e06:0:b0:566:94d0:8c83 with SMTP id y6-20020aa79e06000000b0056694d08c83mr8269986pfq.7.1671432263809; Sun, 18 Dec 2022 22:44:23 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1671432263; cv=pass; d=google.com; s=arc-20160816; b=ZHmcEpttC1Yw6DfRqu3qd29p1crxSAJfhrUvv14/wSq/lSNfSvtkrtnK6G9oW12B+2 Tgvyh464uKVORKMNl7517DehkiqX8p5WtPjVpdEuLP+0ec2HVc3QpKEu4t5PIciFx8fG GSZPikv+xBCu7kWIyv7DxUqLWzDbq6vVlEAgQtzNKC6LgiVhMG/MsLjDisoPJ/dp1UiE sEy9ZBPmIWzn5SXEfaddEzky8hat+kgPWVpzTh+8WriVod/m/NplW9TnN5eMLKDI6Pfl HEfpNilNF7poSKYA2QXPo8mzWN4/Ow9vLNGaMeShYZo80+t6q2laMhIXw6w/FQ08YHqq OxEg== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=W2ZqHGdaWG++QejFv0qF0mLadsspFPKdlGH9QjkoDS4=; b=baFQNydAtaX2nljV96cdE/4aKYx4ZzU4FBeIFHPKyOpuSOrGpwP3dQmKGjkO/0Q73x nLUADizo3A5nZbJx0nks9/2zi3Df/z83oZIFkgjBfRs4lRortjS6/9Fqk8IWcJDBwIuP Fc82fzxc/ydwcGLT8DatZI3wSxZ+VDkpgFm4J8BZxn3Kj2e62W41i9VJrkRLJRpGHN0R M7mgvhZ0yI2WFkRqoSPywmc0Vo8oPSlqZDnRJ0PWYG6zhOHG1oFP3ita7gsmtLKSEwiA nC5N8axaTSaXxbLgEFsmOvo8LvRrvHt8T2HkhQ8aoBqdqyw4XLp0hnlLBR7toHBq4Lne NPKw== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amd.com header.s=selector1 header.b="kKL13/5G"; arc=pass (i=1 spf=pass spfdomain=amd.com dmarc=pass fromdomain=amd.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=amd.com Received: from out1.vger.email (out1.vger.email. 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Mon, 19 Dec 2022 00:41:48 -0600 From: Perry Yuan To: , , , CC: , , , , , , , , Subject: [PATCH v8 09/13] cpufreq: amd-pstate: add driver working mode switch support Date: Mon, 19 Dec 2022 14:40:38 +0800 Message-ID: <20221219064042.661122-10-perry.yuan@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221219064042.661122-1-perry.yuan@amd.com> References: <20221219064042.661122-1-perry.yuan@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT050:EE_|SA1PR12MB7245:EE_ X-MS-Office365-Filtering-Correlation-Id: dfde6600-fa56-4c48-18f9-08dae18c1c7d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: r5clV4acaRKPaC3eabGYYwYkwOfU+ovsC9HSRf8m6YMqkm5ORLkZyi7fs1BSV6nPj1ALP3cXgdV2sFXPe6EkLjTNyv4J0g2pNKBlWSGH2xqVnF+ao0Rq4DC2mSo6LM+Q4Q5GnNGxyFieFlhS1J4QFa+bcCteqhIJcY+6UDH/+IIxYp8PGygAbpmb5lUthT5otzhPZ9JWQL33lKeHClUFkiWw4JPiCYjDTuxMzRkEp5Xq+AYJEZAeq/on6ZA9NvO04rAR/o9KvK8YAvB7oEObHKknMHISDBezyeShwCmLJaB86QcNrOV3Da0kHA/KZwgze5BCD+7nwmGL+Woy4P+Djc4r3CWajp5ikFkEE4FnkTCnHUscmCYdBeSn08b8bfv4+ralv7nxB3GumRAs1i+/+txrA5eT/1buStzHB123T5OYXGiDdRQ78f36rZAXhmoSf46dJ2T6oWpm3tMVO+qX9g8hG49KM2UOxWpqZyiQLVLNMHDHQ8QjSmnZsLWdrOkaIIP8kikJj7BxY/PEa7CVnHL674J0U96BnLTnwzQLk64UyjXc2RQD6p2vUCsHhs2ySjSKXNsdVWgCUJDXHZQVt5tEXympElLeoWwU+z0FqV1GZ02VSL27MWHEf+1fnaNupJXBiC9zadjtQA1kAIFpYY93aeGqoO+eoRkMUK7NPpUM0LmQIBGip6H1Sx09FxqC2lOtHxTjkR358RJYXw91l146m4Vxhv5gqUQOaUgx30w= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230022)(4636009)(346002)(39860400002)(136003)(376002)(396003)(451199015)(46966006)(40470700004)(36840700001)(70586007)(70206006)(40460700003)(86362001)(8676002)(4326008)(316002)(5660300002)(36756003)(8936002)(2616005)(41300700001)(1076003)(82310400005)(7696005)(16526019)(6666004)(186003)(36860700001)(26005)(83380400001)(426003)(336012)(47076005)(356005)(54906003)(40480700001)(82740400003)(81166007)(110136005)(478600001)(44832011)(2906002)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Dec 2022 06:41:51.5196 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: dfde6600-fa56-4c48-18f9-08dae18c1c7d X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT050.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB7245 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1752623757357419237?= X-GMAIL-MSGID: =?utf-8?q?1752623757357419237?= From: Perry Yuan While amd-pstate driver was loaded with specific driver mode, it will need to check which mode is enabled for the pstate driver,add this sysfs entry to show the current status $ cat /sys/devices/system/cpu/amd-pstate/status active Meanwhile, user can switch the pstate driver mode with writing mode string to sysfs entry as below. Enable passive mode: $ sudo bash -c "echo passive > /sys/devices/system/cpu/amd-pstate/status" Enable active mode (EPP driver mode): $ sudo bash -c "echo active > /sys/devices/system/cpu/amd-pstate/status" Signed-off-by: Perry Yuan --- drivers/cpufreq/amd-pstate.c | 128 +++++++++++++++++++++++++++++++++++ 1 file changed, 128 insertions(+) diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index fc12d35bc7bd..e8996e937e63 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -64,6 +64,7 @@ static struct cpufreq_driver amd_pstate_driver; static struct cpufreq_driver amd_pstate_epp_driver; static struct amd_cpudata **all_cpu_data; static int cppc_state = AMD_PSTATE_DISABLE; +struct kobject *amd_pstate_kobj; static inline int get_mode_idx_from_str(const char *str, size_t size) { @@ -90,6 +91,8 @@ static struct amd_pstate_params global_params; static DEFINE_MUTEX(amd_pstate_limits_lock); static DEFINE_MUTEX(amd_pstate_driver_lock); +static DEFINE_SPINLOCK(cppc_notify_lock); + static s16 amd_pstate_get_epp(struct amd_cpudata *cpudata, u64 cppc_req_cached) { u64 epp; @@ -644,6 +647,8 @@ static int amd_pstate_cpu_init(struct cpufreq_policy *policy) policy->driver_data = cpudata; amd_pstate_boost_init(cpudata); + if (!default_pstate_driver->adjust_perf) + default_pstate_driver->adjust_perf = amd_pstate_adjust_perf; return 0; @@ -784,12 +789,106 @@ static ssize_t show_energy_performance_preference( return sysfs_emit(buf, "%s\n", energy_perf_strings[preference]); } +static ssize_t amd_pstate_show_status(char *buf) +{ + if (!default_pstate_driver) + return sysfs_emit(buf, "off\n"); + + return sysfs_emit(buf, "%s\n", default_pstate_driver == &amd_pstate_epp_driver ? + "active" : "passive"); +} + +static void amd_pstate_driver_cleanup(void) +{ + unsigned int cpu; + + cpus_read_lock(); + for_each_online_cpu(cpu) { + if (all_cpu_data[cpu]) { + spin_lock(&cppc_notify_lock); + kfree(all_cpu_data[cpu]); + WRITE_ONCE(all_cpu_data[cpu], NULL); + spin_unlock(&cppc_notify_lock); + } + } + cpus_read_unlock(); + + default_pstate_driver = NULL; +} + +static int amd_pstate_update_status(const char *buf, size_t size) +{ + if (size == 3 && !strncmp(buf, "off", size)) { + if (!default_pstate_driver) + return -EINVAL; + + if (cppc_state == AMD_PSTATE_ACTIVE) + return -EBUSY; + + cpufreq_unregister_driver(default_pstate_driver); + amd_pstate_driver_cleanup(); + return 0; + } + + if (size == 6 && !strncmp(buf, "active", size)) { + if (default_pstate_driver) { + if (default_pstate_driver == &amd_pstate_epp_driver) + return 0; + cpufreq_unregister_driver(default_pstate_driver); + default_pstate_driver = &amd_pstate_epp_driver; + cppc_state = AMD_PSTATE_ACTIVE; + } + + return cpufreq_register_driver(default_pstate_driver); + } + + if (size == 7 && !strncmp(buf, "passive", size)) { + if (default_pstate_driver) { + if (default_pstate_driver == &amd_pstate_driver) + return 0; + cpufreq_unregister_driver(default_pstate_driver); + cppc_state = AMD_PSTATE_PASSIVE; + default_pstate_driver = &amd_pstate_driver; + } + + return cpufreq_register_driver(default_pstate_driver); + } + + return -EINVAL; +} + +static ssize_t show_status(struct kobject *kobj, + struct kobj_attribute *attr, char *buf) +{ + ssize_t ret; + + mutex_lock(&amd_pstate_driver_lock); + ret = amd_pstate_show_status(buf); + mutex_unlock(&amd_pstate_driver_lock); + + return ret; +} + +static ssize_t store_status(struct kobject *a, struct kobj_attribute *b, + const char *buf, size_t count) +{ + char *p = memchr(buf, '\n', count); + int ret; + + mutex_lock(&amd_pstate_driver_lock); + ret = amd_pstate_update_status(buf, p ? p - buf : count); + mutex_unlock(&amd_pstate_driver_lock); + + return ret < 0 ? ret : count; +} + cpufreq_freq_attr_ro(amd_pstate_max_freq); cpufreq_freq_attr_ro(amd_pstate_lowest_nonlinear_freq); cpufreq_freq_attr_ro(amd_pstate_highest_perf); cpufreq_freq_attr_rw(energy_performance_preference); cpufreq_freq_attr_ro(energy_performance_available_preferences); +define_one_global_rw(status); static struct freq_attr *amd_pstate_attr[] = { &amd_pstate_max_freq, @@ -807,6 +906,15 @@ static struct freq_attr *amd_pstate_epp_attr[] = { NULL, }; +static struct attribute *pstate_global_attributes[] = { + &status.attr, + NULL +}; + +static const struct attribute_group amd_pstate_global_attr_group = { + .attrs = pstate_global_attributes, +}; + static inline void update_boost_state(void) { u64 misc_en; @@ -1228,6 +1336,26 @@ static int __init amd_pstate_init(void) if (ret) pr_err("failed to register with return %d\n", ret); + amd_pstate_kobj = kobject_create_and_add("amd-pstate", &cpu_subsys.dev_root->kobj); + if (!amd_pstate_kobj) { + ret = -EINVAL; + pr_err("global sysfs registration failed.\n"); + goto kobject_free; + } + + ret = sysfs_create_group(amd_pstate_kobj, &amd_pstate_global_attr_group); + if (ret) { + pr_err("sysfs attribute export failed with error %d.\n", ret); + goto global_attr_free; + } + + return ret; + +global_attr_free: + kobject_put(amd_pstate_kobj); +kobject_free: + kfree(cpudata); + cpufreq_unregister_driver(default_pstate_driver); return ret; } device_initcall(amd_pstate_init); From patchwork Mon Dec 19 06:40:39 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Yuan, Perry" X-Patchwork-Id: 34418 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:e747:0:0:0:0:0 with SMTP id c7csp2230039wrn; Sun, 18 Dec 2022 22:44:27 -0800 (PST) X-Google-Smtp-Source: AA0mqf7n4m+paYTRfcnZ8aukZZRvtklWZCfsKzsVJPVQIJhJTqTnFPo7GC9ozLdcsfkyqviVEqcm X-Received: by 2002:a05:6a20:6d04:b0:ac:706e:178c with SMTP id fv4-20020a056a206d0400b000ac706e178cmr45618476pzb.26.1671432267112; Sun, 18 Dec 2022 22:44:27 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1671432267; cv=pass; d=google.com; s=arc-20160816; b=zRIUkxHLRT1QP54JAXx/MiUBW22MHSIEHQ/47X3wJglCM7BkATGetekI+Ul+I2BgOD 5aJ2a6G4vHC0OQJOMEKgSSim3lA8K8+7cnFA0haqLDXFWYiAllvhn3Tqa1wfQLj+h59C mpMOjJxwxBFhfbDeXVcmoAvWaP6NfZn6VCSbp1IqFkfieTEzkkjE8iOQXC7owZh7KBKw G1BpOGYvmXCslT8y0m/DWImVTj2nHiuc93EXsoF3Lw1/oRNd6F2tEG77LucYWyAoDFPm hdsG375FrFVYjgcq/WKhfZ1fWRmS/c3G3UVsD6hSCPiTsZllPFeLQEoe6Q3MgYTXen2X ZYRg== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=7iLNwCDA2FPuXX0XbspH2ZQmIiCfHs2C+UB1BWc0KDM=; b=zINQn2v7M1zTynEj6L3dmg6fb44wnVPaXJAjR9MnPxjf/ycXFOZjZxilbaqZgHE3cg Nky5HwgaZ20tRpxbCsBZOU3aOG3RFDG7218MeNA17lDNhJaKLtHWdF9eYkAwGuP436yv NOkS6b0dTBIjMPsFQw71rtT3F7DzrPWCAmiIXEB3IswvfidNj8p+gTPLV9GMAleo67YS Rai/rSMPFz3krlw5wpuHY+7dGL/pAab2o2v9Ygx00K7BCm1vbG6t1BE2WuhMXP02n35O KhMtwVIJoh+1PlOrFR7PY91ynZnapoGBiv9Fh4o/rg3y8BEf18V+T2ffA7V8x+jbLfq6 JIfQ== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amd.com header.s=selector1 header.b=d0rVuGUP; arc=pass (i=1 spf=pass spfdomain=amd.com dmarc=pass fromdomain=amd.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=amd.com Received: from out1.vger.email (out1.vger.email. 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Mon, 19 Dec 2022 00:41:51 -0600 From: Perry Yuan To: , , , CC: , , , , , , , , Subject: [PATCH v8 10/13] Documentation: amd-pstate: add amd pstate driver mode introduction Date: Mon, 19 Dec 2022 14:40:39 +0800 Message-ID: <20221219064042.661122-11-perry.yuan@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221219064042.661122-1-perry.yuan@amd.com> References: <20221219064042.661122-1-perry.yuan@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT089:EE_|BL0PR12MB4915:EE_ X-MS-Office365-Filtering-Correlation-Id: 0a865751-2e29-451c-ac6e-08dae18c1e82 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: oOQkoWr3DSE/n2Pr2VqXhC70P0WWOvqoSAvekShiCNMy2HyUWEQP1rhKFHnjuharSSVPVfHi5PPl7Iy1y2tpCyuw7RqOAWiv1ADmLskvhvArlPvrnketFBJ1PFNHzGVEzb10bemP3IFIn7lDrsxBGnffb3bTFZht9G7Vm4SwzOF6ottRhwAPvBx9gRohM1rqwAbxbU7qMR00lotQ6YF/hqciFZIVckMvsd5oFez3UOmBpyLMd6GXc2WrKjuiT2SMVv23BdDJYa2SnlTzuKXvRAMi3NmhfyjnrEfb8WW0SAl10vm4jgqDcjSwqlY+btxCTiUqSNs4QxBAYzyCwawQlvLD3hjhsYq12qJeQkDbbKqevMAcpISVLcFIow9VM3/Um6SL0b015oIk9M+IJSJPCMAuMwM8T7vtKBtTztQ3/CMX4stydxnmEd8GupKRM4Nw/L1b38y6MBYANxtj7H9Ly0KTvXvNwYiVq7r8kgxQi6q7QiYfPQPCj1o1s7SmXlZX4CUAMb9bz2N01oOpi2yJlBgwhpBPYD9WP9RCVmsXbq6k81sKbjIknCqKFLAYYnFdeila9qJWkiIltMohaYvZ0CS7NZHWfWmZWPc5uTbP0DAuSXxdmsAslPvRWixUZHPL1UXCXxKcRfrDzUKg48RZg2u+Gx7pU/lW1QOmBZDs5heJ5dIRYN6fBelvy/TO+tKtYwRFTJHK1fWBVzyH+8kfN9jg77rlvmeUtcPCZCnYWVs= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230022)(4636009)(346002)(39860400002)(376002)(136003)(396003)(451199015)(46966006)(36840700001)(40470700004)(8676002)(40480700001)(2906002)(86362001)(336012)(4326008)(70206006)(186003)(26005)(41300700001)(16526019)(1076003)(478600001)(2616005)(40460700003)(7696005)(54906003)(110136005)(316002)(36860700001)(6666004)(81166007)(356005)(82740400003)(5660300002)(426003)(83380400001)(47076005)(44832011)(8936002)(82310400005)(36756003)(70586007)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Dec 2022 06:41:54.8960 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0a865751-2e29-451c-ac6e-08dae18c1e82 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT089.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL0PR12MB4915 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1752623760672276570?= X-GMAIL-MSGID: =?utf-8?q?1752623760672276570?= From: Perry Yuan Introduce ``amd-pstate`` CPPC has two operation modes: * CPPC Autonomous (active) mode * CPPC non-autonomous (passive) mode. active mode and passive mode can be chosen by different kernel parameters. Signed-off-by: Perry Yuan Reviewed-by: Mario Limonciello --- Documentation/admin-guide/pm/amd-pstate.rst | 26 +++++++++++++++++++-- 1 file changed, 24 insertions(+), 2 deletions(-) diff --git a/Documentation/admin-guide/pm/amd-pstate.rst b/Documentation/admin-guide/pm/amd-pstate.rst index 33ab8ec8fc2f..62744dae3c5f 100644 --- a/Documentation/admin-guide/pm/amd-pstate.rst +++ b/Documentation/admin-guide/pm/amd-pstate.rst @@ -299,8 +299,30 @@ module which supports the new AMD P-States mechanism on most of the future AMD platforms. The AMD P-States mechanism is the more performance and energy efficiency frequency management method on AMD processors. -Kernel Module Options for ``amd-pstate`` -========================================= + +AMD Pstate Driver Operation Modes +================================= + +``amd_pstate`` CPPC has two operation modes: CPPC Autonomous(active) mode and +CPPC non-autonomous(passive) mode. +active mode and passive mode can be chosen by different kernel parameters. +When in Autonomous mode, CPPC ignores requests done in the Desired Performance +Target register and takes into account only the values set to the Minimum requested +performance, Maximum requested performance, and Energy Performance Preference +registers. When Autonomous is disabled, it only considers the Desired Performance Target. + +Active Mode +------------ + +``amd_pstate=active`` + +This is the low-level firmware control mode which is implemented by ``amd_pstate_epp`` +driver with ``amd_pstate=active`` passed to the kernel in the command line. +In this mode, ``amd_pstate_epp`` driver provides a hint to the hardware if software +wants to bias toward performance (0x0) or energy efficiency (0xff) to the CPPC firmware. +then CPPC power algorithm will calculate the runtime workload and adjust the realtime +cores frequency according to the power supply and thermal, core voltage and some other +hardware conditions. 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Mon, 19 Dec 2022 00:41:54 -0600 From: Perry Yuan To: , , , CC: , , , , , , , , Subject: [PATCH v8 11/13] Documentation: introduce amd pstate active mode kernel command line options Date: Mon, 19 Dec 2022 14:40:40 +0800 Message-ID: <20221219064042.661122-12-perry.yuan@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221219064042.661122-1-perry.yuan@amd.com> References: <20221219064042.661122-1-perry.yuan@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT084:EE_|MN2PR12MB4222:EE_ X-MS-Office365-Filtering-Correlation-Id: 3508d86c-3934-4fa4-ec25-08dae18c2fe6 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 8hkQRXK0GaWEzFPGIMwFpEjAWrpHiCdxuJxA8ei25pvcRzrNpeO1UZCVKU7AQg92aoZhfNiPQw7U0nG0uG8okM4x+ONdlh9eUW8sylE4EVGLwCJV1oBTA70wRkx+F7EmHqszxHd+sDsiWJ4bP4cHHmYBFDOLd7U9qjtF07jbUkUJykycbHfQ1V83PfTOwguUFouZNHngf1JvkLzKk+MnQucCBp8oL60InYvNO3qCA1mqoOi89flgFDUmoQZ220zod1FL+fjloCh7EqsInIhktoUGj6X4YpFYNGDBbyo+7Tni8EJC2j/mmMmAAmMjGi5awK7zmWDvWzfA0FtZdcwv3dQkyObeew27nF3id+IMkv7XEl4Ach9oJpNQ2nEus6E6f+wimNHRbbI6RjDJ+siBz3USd84iWxzrG0V1FcvB9kVNq/Gh9g1kA8Bi9vnafsEv80SoeKuDOGn+p5+Ab8DjDwsm1Ydv4VpBVuD4jHaz3JOLQ2/oUjXddybcXjJ7JgO9ybLZK/4C/XZeWGb7KEDXu7IeXmNs0dJP/yiS0asCHPTgOBo1wntVA8R13XMn43PpQVQ3EjQnzHioAkGM+X+bEeJoQnekNjc0fl6euAvCTQHsF58KVBhBWnzyrFkGDBOh7zuW9RhPSF3dtydRX5mqJsSuzk1yYticC9LZfz0Qz0IrG3sssbZrUDdEYdDsaThZzXow0HIvBzEsydmQMjnVxWxbi/J5j2ISyugelnbCHgc= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230022)(4636009)(136003)(346002)(376002)(396003)(39860400002)(451199015)(36840700001)(46966006)(40470700004)(41300700001)(336012)(81166007)(8676002)(1076003)(4326008)(82740400003)(2906002)(82310400005)(44832011)(8936002)(36756003)(40460700003)(36860700001)(47076005)(83380400001)(5660300002)(426003)(356005)(7696005)(6666004)(478600001)(110136005)(86362001)(54906003)(316002)(70206006)(70586007)(26005)(186003)(16526019)(2616005)(40480700001)(36900700001);DIR:OUT;SFP:1101; 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In autonomous mode SMU firmware decides frequencies at 1 ms timescale based on workload utilization, usage in other IPs, infrastructure limits such as power, thermals and so on. Signed-off-by: Perry Yuan Reviewed-by: Mario Limonciello --- Documentation/admin-guide/kernel-parameters.txt | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt index 42af9ca0127e..73a02816f6f8 100644 --- a/Documentation/admin-guide/kernel-parameters.txt +++ b/Documentation/admin-guide/kernel-parameters.txt @@ -6970,3 +6970,10 @@ management firmware translates the requests into actual hardware states (core frequency, data fabric and memory clocks etc.) + active + Use amd_pstate_epp driver instance as the scaling driver, + driver provides a hint to the hardware if software wants + to bias toward performance (0x0) or energy efficiency (0xff) + to the CPPC firmware. then CPPC power algorithm will + calculate the runtime workload and adjust the realtime cores + frequency. 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Mon, 19 Dec 2022 00:42:24 -0600 From: Perry Yuan To: , , , CC: , , , , , , , , Subject: [PATCH v8 12/13] cpufreq: amd-pstate: convert sprintf with sysfs_emit() Date: Mon, 19 Dec 2022 14:40:41 +0800 Message-ID: <20221219064042.661122-13-perry.yuan@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221219064042.661122-1-perry.yuan@amd.com> References: <20221219064042.661122-1-perry.yuan@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT088:EE_|CH2PR12MB4230:EE_ X-MS-Office365-Filtering-Correlation-Id: 46896717-ff0d-4c4d-e725-08dae18c325f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 5pO1T1wd/dAnX38nmgkVw30ePisYJ8TfhMvZLMvu3S2nJfMk29eTPi80KIIxYpMH9GlZX+w/mY/6wn2EEA9yW4xua1U5w/vS5CpnHjCE8sOoms2h/HC5por4Zu99WQpSY1Tombhrrxe/gd2ReGljRfrRT1Dv1LNwe8ZIDcrkqOpoxeA7wi7nU9AAqWvlrj/VXu3DDrq+W3tPJF7nHX9ojD2GFakca+wmqRq11uQx1j07cgjLKmU1tUzOJmz/0oo28Pv+tXU1HFSocdTGyRA/qjSWwuPQktKAm0ElOo9SS3hvHK4jjGBwAJX/qRS1Tm1Uz8K2COOW72tZsLN2OPUzU6DiBitIKbVYNnonWX/OntT0QxIKHsw6fBahDksr+dOPp1Wit9nSCs3/rcVAGfrhRqkIrzMm/QLygr59mUZxUTx8NEQptxxcrP/atpDAM8AUudyshXGLvgxbsoia8tbLojKkmjkmQY1T1ToZ/OyfLXGG9lOj+QBO3UYukrc2v/a81uBjaeG4DxPnvl2mX5nu4WBQbKaPJkRpzqJ8hklPdf9//kI5WN4udse0Bd/4t0/XxQMSBfdH/rAsuv+djdD7AmfYZYy/PDv5XWoo7zJ+FNvIeNdChdMf9M+JKlQBos2J/FPTqvbCX4LA4juYCh7npbhip1IScoDlyNZqyVVmSioz1zRnC8hQgaOR9JTjHpxUj/Lx1PPR3dXCvKENomIEAa0jXhT30JVl0UJ7xbZWO18= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230022)(4636009)(346002)(136003)(376002)(39860400002)(396003)(451199015)(46966006)(36840700001)(40470700004)(47076005)(426003)(110136005)(36756003)(54906003)(316002)(2906002)(44832011)(83380400001)(478600001)(40460700003)(7696005)(86362001)(40480700001)(6666004)(16526019)(2616005)(1076003)(336012)(186003)(26005)(36860700001)(8936002)(82740400003)(41300700001)(82310400005)(4326008)(5660300002)(70586007)(70206006)(356005)(81166007)(8676002)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Dec 2022 06:42:28.2538 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 46896717-ff0d-4c4d-e725-08dae18c325f X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT088.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH2PR12MB4230 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1752623839240461746?= X-GMAIL-MSGID: =?utf-8?q?1752623839240461746?= replace the sprintf with a more generic sysfs_emit function No potential function impact Signed-off-by: Perry Yuan Reviewed-by: Mario Limonciello Acked-by: Huang Rui --- drivers/cpufreq/amd-pstate.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index e8996e937e63..d8b182614c18 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -709,7 +709,7 @@ static ssize_t show_amd_pstate_max_freq(struct cpufreq_policy *policy, if (max_freq < 0) return max_freq; - return sprintf(&buf[0], "%u\n", max_freq); + return sysfs_emit(buf, "%u\n", max_freq); } static ssize_t show_amd_pstate_lowest_nonlinear_freq(struct cpufreq_policy *policy, @@ -722,7 +722,7 @@ static ssize_t show_amd_pstate_lowest_nonlinear_freq(struct cpufreq_policy *poli if (freq < 0) return freq; - return sprintf(&buf[0], "%u\n", freq); + return sysfs_emit(buf, "%u\n", freq); } /* @@ -737,7 +737,7 @@ static ssize_t show_amd_pstate_highest_perf(struct cpufreq_policy *policy, perf = READ_ONCE(cpudata->highest_perf); - return sprintf(&buf[0], "%u\n", perf); + return sysfs_emit(buf, "%u\n", perf); } static ssize_t show_energy_performance_available_preferences( From patchwork Mon Dec 19 06:40:42 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Yuan, Perry" X-Patchwork-Id: 34421 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:e747:0:0:0:0:0 with SMTP id c7csp2230488wrn; Sun, 18 Dec 2022 22:45:46 -0800 (PST) X-Google-Smtp-Source: AMrXdXupbBLrs8VlZjrc87Jp9kBgNMcIuKHiv+i3wGKdjRyoBEnb5eWslIHrGHkmKu+F0mifIjRi X-Received: by 2002:a17:902:e149:b0:186:5f5a:5842 with SMTP id d9-20020a170902e14900b001865f5a5842mr7976746pla.11.1671432345745; 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Mon, 19 Dec 2022 00:42:27 -0600 From: Perry Yuan To: , , , CC: , , , , , , , , Subject: [PATCH v8 13/13] Documentation: amd-pstate: introduce new global sysfs attributes Date: Mon, 19 Dec 2022 14:40:42 +0800 Message-ID: <20221219064042.661122-14-perry.yuan@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221219064042.661122-1-perry.yuan@amd.com> References: <20221219064042.661122-1-perry.yuan@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT079:EE_|SA0PR12MB4432:EE_ X-MS-Office365-Filtering-Correlation-Id: 634f4576-0d32-43bc-feb8-08dae18c347f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: OAtiWyiGcaqrZm8Z0cUyY6trbuSVAcS5MmOgGNoeiP1Efn2VbUKJGDjQqkf3baRX01ze0HuEEsrntcc7Z6b8K5cqKv606aIJd7E6aM6QHzh3mKSjscdtayMej8WWx/UW018079Rncp+QVK3MpEyQflSm3wpjS6aRO50e3BWXEUHtrrLCNcMuEV15rOUrpzSl7uusg+a2/y+KwIsoyz6bgi2kJ0oW4o00PHLAHsn09ZuMcn4ZXVFJmelpY4XzmxtRaI/Qo5xkx3YV6AFXA4EPmeWpgeMKbndfGuJP50y2sgV9AeGsBBeXs80X1wKmsVSbe4+BkIYNJAdb9kKALm7au3IrFzzA2j67w5Rm/gakMsW0v8bXG9suC0g72QbRbY7NQwI7Oig+698Rgy0CEzX4aSdxeuAiJnh3geu2EMiIloPbSdkmbfhesJDIqdcVgYn6i4r6LNMFE196nY+dSQgA7cvZkvP0uLX6nPdaPhrXd3rWdWQhFqxdPEypA2fTLgKZXZZQ3wUw5H9yWxeDcuZZO/9sKLpqP30juKc+oeWRdcL/e3M/1Z3Buvm4K+tcr8GaY2KYEH2IzRUAtSXJIPdOjP5nb8COMCD5LQlrYlM0n3PfJ77BxXx8Yutj3fKGrDNWAm/a+9nfoDZy05XcT9SLHsO+PNxxgvqkNYpvXmPzjsLgZ4ADoY2EcSuXlfL41dVKL4gAjyOnEETn9GTCY5ePGOKBsxjqVY6qV/SuNoL5kK8= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230022)(4636009)(346002)(396003)(39860400002)(376002)(136003)(451199015)(46966006)(40470700004)(36840700001)(2616005)(86362001)(82740400003)(36860700001)(6666004)(40460700003)(40480700001)(16526019)(2906002)(336012)(36756003)(186003)(26005)(81166007)(7696005)(478600001)(356005)(8936002)(110136005)(54906003)(316002)(70206006)(4326008)(8676002)(82310400005)(1076003)(41300700001)(44832011)(47076005)(5660300002)(426003)(70586007)(83380400001)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Dec 2022 06:42:31.8039 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 634f4576-0d32-43bc-feb8-08dae18c347f X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT079.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA0PR12MB4432 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1752623843742706245?= X-GMAIL-MSGID: =?utf-8?q?1752623843742706245?= The new amd-pstate driver support to switch the driver working mode and use can switch the driver mode within the sysfs attributes in the below path and check current mode $ cd /sys/devices/system/cpu/amd-pstate check driver mode: $ cat /sys/devices/system/cpu/amd-pstate/status switch mode: $ sudo bash -c "echo passive > /sys/devices/system/cpu/amd-pstate/status" or $ sudo bash -c "echo active > /sys/devices/system/cpu/amd-pstate/status" Signed-off-by: Perry Yuan --- Documentation/admin-guide/pm/amd-pstate.rst | 28 +++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/Documentation/admin-guide/pm/amd-pstate.rst b/Documentation/admin-guide/pm/amd-pstate.rst index 62744dae3c5f..f3a8f8a66783 100644 --- a/Documentation/admin-guide/pm/amd-pstate.rst +++ b/Documentation/admin-guide/pm/amd-pstate.rst @@ -339,6 +339,34 @@ processor must provide at least nominal performance requested and go higher if c operating conditions allow. +User Space Interface in ``sysfs`` +================================= + +Global Attributes +----------------- + +``amd-pstate`` exposes several global attributes (files) in ``sysfs`` to +control its functionality at the system level. They are located in the +``/sys/devices/system/cpu/amd-pstate/`` directory and affect all CPUs. + +``status`` + Operation mode of the driver: "active", "passive" or "off". + + "active" + The driver is functional and in the ``active mode`` + + "passive" + The driver is functional and in the ``passive mode`` + + "off" + The driver is unregistered and not functional now. + + This attribute can be written to in order to change the driver's + operation mode or to unregister it. The string written to it must be + one of the possible values of it and, if successful, the write will + cause the driver to switch over to the operation mode represented by + that string - or to be unregistered in the "off" case. + ``cpupower`` tool support for ``amd-pstate`` ===============================================