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Unfortunately, it looks like the SMMU integration in the NXP LS1028A has wrongly tied the cfg_cttw signal to 0, even though the SoC documentation specifies that "The SMMU supports cache coherency for page table walks and DVM transactions for page table cache maintenance operations." Device tree provides the option of overriding the ID register via the dma-coherent property since commit bae2c2d421cd ("iommu/arm-smmu: Sort out coherency"), and that's what we do here. Telling struct io_pgtable_cfg that the SMMU page table walks are coherent with the CPU caches brings performance benefits, because it avoids certain operations such as __arm_lpae_sync_pte() for PTE updates. Link: https://lore.kernel.org/linux-iommu/3f3112e4-65ff-105d-8cd7-60495ec9054a@arm.com/ Suggested-by: Robin Murphy Signed-off-by: Vladimir Oltean --- v1->v2: reword commit message, drop Fixes: tag vfio's problem with arm_smmu_capable(IOMMU_CAP_CACHE_COHERENCY) should be resolved independently, I'm not claiming that this is the only fix for that. v1 at: https://lore.kernel.org/linux-iommu/20221208151514.3840720-1-vladimir.oltean@nxp.com/ arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi index ac1c3a7e5f7a..9be0b4b7babf 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi @@ -712,6 +712,7 @@ smmu: iommu@5000000 { reg = <0 0x5000000 0 0x800000>; #global-interrupts = <8>; #iommu-cells = <1>; + dma-coherent; stream-match-mask = <0x7c00>; /* global secure fault */ interrupts = , From patchwork Thu Dec 15 13:56:36 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vladimir Oltean X-Patchwork-Id: 33651 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:e747:0:0:0:0:0 with SMTP id c7csp369596wrn; Thu, 15 Dec 2022 06:00:35 -0800 (PST) X-Google-Smtp-Source: AA0mqf79blL67chwZoe2rh9IBWo+cA+ougETZPfvCRnZqPy0eGJMFKKvGIA8s6J2V74IryAjyM6B X-Received: by 2002:a17:907:d0e:b0:7c0:a4e9:615b with SMTP id gn14-20020a1709070d0e00b007c0a4e9615bmr31936678ejc.61.1671112835012; Thu, 15 Dec 2022 06:00:35 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1671112834; cv=pass; d=google.com; s=arc-20160816; b=zu0ox+2F8ZHT1Th91GspqIhTQotMEmFyc82K88vbyn8eHVlIbJDn6paP+txPcx2yQK EvHs61NfthyokOU0PQw0y3oYq/gCynSod4zKLbC7yifcFh2BYdxsD1XWY5q84GukJY3i fndZ7RA5OnBtMguPG3Nzmk8Y86vyLWfgdBD9HukdiUa8zWDH1olHvAhOP+AUHrL7ChNg FQ5BkNkF3enf2AF2Edc4HXQQUBLMLAeLumtZfK6EXU9kaS5TCFjj0iTH6mXXnTlhCjXx 2Z2bHfqN18gpASIhVxu12iCCmCwtv6QKyxBCD6UW/pTE0Xi9MFYGnIYIJjyYNsgysC0A QCVg== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:content-transfer-encoding :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=jrT0Ja4gT0OblzbqwCqLKJLffImZD4+knJNuGhNnmB4=; b=e0jvY39l5cIutQ4aL/5yWcMJPOiyG0NDFDyJudm7DKGbo1UnJ5VJfs+hzCNs9vqIpA opLOtvQG2DRA+UKnc/UVfrIfevvcbu3rCEZpB/gW7hUrsapYeH2Ml35dOBNPYCcGtwQ7 nLfObX3/Om4Z4x+T586I4R8gAgaVanFQBz9PO7p146n51ma2rRvVAsKJxucGs2LSYpnB ThvVBmmcfI1vkhja8vdSb72FlUxUj7u3rsaXXMgeK5a/RWlpyeFrEuRFEy0vA1Uw39hR K/6fs3G99YLMCiHCbIu+Tx7qQW8c0RSj8jn+FtTVPQKEQ0Q6tcfTDrbs1zp1toO/lRdT gHtQ== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@nxp.com header.s=selector2 header.b=g0JOQD0z; arc=pass (i=1 spf=pass spfdomain=nxp.com dkim=pass dkdomain=nxp.com dmarc=pass fromdomain=nxp.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=nxp.com Received: from out1.vger.email (out1.vger.email. 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Unfortunately, it looks like the SMMU integration in the NXP LS1088A has wrongly tied the cfg_cttw signal to 0, even though the SoC documentation specifies that "The SMMU supports cache coherency for page table walks and DVM transactions for page table cache maintenance operations." Device tree provides the option of overriding the ID register via the dma-coherent property since commit bae2c2d421cd ("iommu/arm-smmu: Sort out coherency"), and that's what we do here. Telling struct io_pgtable_cfg that the SMMU page table walks are coherent with the CPU caches brings performance benefits, because it avoids certain operations such as __arm_lpae_sync_pte() for PTE updates. Link: https://lore.kernel.org/linux-iommu/3f3112e4-65ff-105d-8cd7-60495ec9054a@arm.com/ Suggested-by: Robin Murphy Signed-off-by: Vladimir Oltean --- v1->v2: patch is new arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi index 260d045dbd9a..e5fb137ac02b 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi @@ -674,6 +674,7 @@ smmu: iommu@5000000 { reg = <0 0x5000000 0 0x800000>; #iommu-cells = <1>; stream-match-mask = <0x7C00>; + dma-coherent; #global-interrupts = <12>; // global secure fault interrupts = ,