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Bottomley" , Krzysztof Kozlowski , Jinyoung Choi , Keoseong Park , linux-kernel@vger.kernel.org (open list) Subject: [PATCH v3 1/3] ufs: core: Add Event Specific Interrupt configuration vendor specific ops Date: Wed, 14 Dec 2022 19:06:20 -0800 Message-Id: <1671073583-10065-2-git-send-email-quic_cang@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1671073583-10065-1-git-send-email-quic_cang@quicinc.com> References: <1671073583-10065-1-git-send-email-quic_cang@quicinc.com> X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: 6xb9QM55TSW3DImuz7vet65zswn_yJ-2 X-Proofpoint-GUID: 6xb9QM55TSW3DImuz7vet65zswn_yJ-2 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.923,Hydra:6.0.545,FMLib:17.11.122.1 definitions=2022-12-14_12,2022-12-14_01,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 adultscore=0 priorityscore=1501 clxscore=1011 phishscore=0 malwarescore=0 mlxlogscore=999 spamscore=0 suspectscore=0 impostorscore=0 mlxscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2212070000 definitions=main-2212150019 X-Spam-Status: No, score=-1.7 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,SPF_HELO_NONE, SPF_NONE autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1752247821832612196?= X-GMAIL-MSGID: =?utf-8?q?1752247821832612196?= As Event Specific Interrupt message format is not defined in UFSHCI JEDEC specs, and the ESI handling highly depends on how the format is designed, hence add a vendor specific ops such that SoC vendors can configure their own ESI handlers. If ESI vops is not provided or returning error, go with the legacy (central) interrupt way. Signed-off-by: Can Guo Reviewed-by: Bart Van Assche --- drivers/ufs/core/ufshcd-priv.h | 8 ++++++++ drivers/ufs/core/ufshcd.c | 5 +++++ include/ufs/ufshcd.h | 2 ++ 3 files changed, 15 insertions(+) diff --git a/drivers/ufs/core/ufshcd-priv.h b/drivers/ufs/core/ufshcd-priv.h index ff03aa5..802029e 100644 --- a/drivers/ufs/core/ufshcd-priv.h +++ b/drivers/ufs/core/ufshcd-priv.h @@ -276,6 +276,14 @@ static inline int ufshcd_vops_get_outstanding_cqs(struct ufs_hba *hba, return -EOPNOTSUPP; } +static inline int ufshcd_mcq_vops_config_esi(struct ufs_hba *hba) +{ + if (hba->vops && hba->vops->config_esi) + return hba->vops->config_esi(hba); + + return -EOPNOTSUPP; +} + extern const struct ufs_pm_lvl_states ufs_pm_lvl_states[]; /** diff --git a/drivers/ufs/core/ufshcd.c b/drivers/ufs/core/ufshcd.c index e9d6891..3762dca 100644 --- a/drivers/ufs/core/ufshcd.c +++ b/drivers/ufs/core/ufshcd.c @@ -8375,6 +8375,11 @@ static int ufshcd_alloc_mcq(struct ufs_hba *hba) static void ufshcd_config_mcq(struct ufs_hba *hba) { + int ret; + + ret = ufshcd_mcq_vops_config_esi(hba); + dev_info(hba->dev, "ESI %sconfigured\n", ret ? "is not " : ""); + ufshcd_enable_intr(hba, UFSHCD_ENABLE_MCQ_INTRS); ufshcd_mcq_make_queues_operational(hba); ufshcd_mcq_config_mac(hba, hba->nutrs); diff --git a/include/ufs/ufshcd.h b/include/ufs/ufshcd.h index f20557b..7f0139b 100644 --- a/include/ufs/ufshcd.h +++ b/include/ufs/ufshcd.h @@ -302,6 +302,7 @@ struct ufs_pwr_mode_info { * @get_hba_mac: called to get vendor specific mac value, mandatory for mcq mode * @op_runtime_config: called to config Operation and runtime regs Pointers * @get_outstanding_cqs: called to get outstanding completion queues + * @config_esi: called to config Event Specific Interrupt */ struct ufs_hba_variant_ops { const char *name; @@ -345,6 +346,7 @@ struct ufs_hba_variant_ops { int (*op_runtime_config)(struct ufs_hba *hba); int (*get_outstanding_cqs)(struct ufs_hba *hba, unsigned long *ocqs); + int (*config_esi)(struct ufs_hba *hba); }; /* clock gating state */ From patchwork Thu Dec 15 03:06:21 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Can Guo X-Patchwork-Id: 33463 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:e747:0:0:0:0:0 with SMTP id c7csp112476wrn; Wed, 14 Dec 2022 19:16:34 -0800 (PST) X-Google-Smtp-Source: AA0mqf6O4YzeHiU0Hzo2gLYZiFd/too5N1RKK4EU8Xw0WBmxnZzM0ybh6ZPXu7fzy2A5gms64xxY X-Received: by 2002:a05:6a20:939e:b0:ac:36bd:3f74 with SMTP id x30-20020a056a20939e00b000ac36bd3f74mr35904147pzh.34.1671074194084; Wed, 14 Dec 2022 19:16:34 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1671074194; cv=none; d=google.com; s=arc-20160816; b=e5DI/E0hXlhEq5x6ccqWOu3bdAhMsbOJWzndxi91S7aZ5rUeNd6TGnylFHfA8rpTKR CvJSBjmHvL/ySbzcOo7Tf0rxEzJuKK9GNIm1GYZQNi1+3FK5UQ4ELIZzLtbhBevnQtOh hS3ckL/ZXjLEOSWl0WzVoWOUDAKfPxUMdoo0SbjagAe7p3X0xRu+vupYwO/Y4PgCvwlK n6sIBrp7ILrMi9dTF3WO5sg45EPZ9ZlsrRMfkKMssSUyr6+o0fOhhimPxqzn9edpZNkU bQI1OQzWI6D047oFkMxUVVgzQNnjvanyo/XvIsjPqHriYZl6+f2X+JLkgZW5ebGdwDo7 ufLw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from:dkim-signature; bh=I8sFfArgA28fxxpoGe/I6RezTQ7Hqvhu32IadG6BIWw=; b=l2BKVV6Y9OrFYT0JTLBLhNIbrplqng6VkTCh2zQ1eNWlB0Pu4gHjWcL0TwyC2nd68I lb8fmHsn/hBxv6npRVlnMov2TL2PWhPkhRlW5BXg+UDk9jg/TAJY4jxDNOidXGeDyQp4 WJHpBgBarFX4Az7e0ewo2EeVbMgsFUB5ZbHmbrqG7UIXD5jLjP5BsWz32mKoq9h8uLp3 4WFtB766YeIYc3wZVfh164ndrc2G47Mt8wI7JWs3necvZXJhtnZq0+OD5pzQrMCNmAHd 2au7YK7/I651LzuuGK8yncvQo76JghMun6Hx8oT1sFsfmLbICfy9uOOuYsmDNgaYTjdb SWBQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=gOe4q41y; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from out1.vger.email (out1.vger.email. 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Bottomley" , Keoseong Park , Yoshihiro Shimoda , Kiwoong Kim , linux-kernel@vger.kernel.org (open list) Subject: [PATCH v3 2/3] ufs: core: mcq: Add Event Specific Interrupt enable and config functions Date: Wed, 14 Dec 2022 19:06:21 -0800 Message-Id: <1671073583-10065-3-git-send-email-quic_cang@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1671073583-10065-1-git-send-email-quic_cang@quicinc.com> References: <1671073583-10065-1-git-send-email-quic_cang@quicinc.com> X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: W0T5sR2JuSp94dGhBI4hVEfMldKZW7_0 X-Proofpoint-ORIG-GUID: W0T5sR2JuSp94dGhBI4hVEfMldKZW7_0 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.923,Hydra:6.0.545,FMLib:17.11.122.1 definitions=2022-12-14_12,2022-12-14_01,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 spamscore=0 lowpriorityscore=0 phishscore=0 priorityscore=1501 bulkscore=0 adultscore=0 suspectscore=0 mlxlogscore=999 mlxscore=0 impostorscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2212070000 definitions=main-2212150019 X-Spam-Status: No, score=-1.7 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,SPF_HELO_NONE, SPF_NONE autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1752248294165285661?= X-GMAIL-MSGID: =?utf-8?q?1752248294165285661?= Add and export two functions to enable ESI and config ESI base addresses. The calls to these exported functions will be added by the next patch in this series. Signed-off-by: Can Guo Reviewed-by: Bart Van Assche --- drivers/ufs/core/ufs-mcq.c | 16 ++++++++++++++++ include/ufs/ufshcd.h | 6 ++++++ include/ufs/ufshci.h | 2 ++ 3 files changed, 24 insertions(+) diff --git a/drivers/ufs/core/ufs-mcq.c b/drivers/ufs/core/ufs-mcq.c index f99c912..c81e424 100644 --- a/drivers/ufs/core/ufs-mcq.c +++ b/drivers/ufs/core/ufs-mcq.c @@ -246,6 +246,7 @@ void ufshcd_mcq_write_cqis(struct ufs_hba *hba, u32 val, int i) { writel(val, mcq_opr_base(hba, OPR_CQIS, i) + REG_CQIS); } +EXPORT_SYMBOL_GPL(ufshcd_mcq_write_cqis); /* * Current MCQ specification doesn't provide a Task Tag or its equivalent in @@ -293,6 +294,7 @@ unsigned long ufshcd_mcq_poll_cqe_nolock(struct ufs_hba *hba, return completed_reqs; } +EXPORT_SYMBOL_GPL(ufshcd_mcq_poll_cqe_nolock); unsigned long ufshcd_mcq_poll_cqe_lock(struct ufs_hba *hba, struct ufs_hw_queue *hwq) @@ -370,6 +372,20 @@ void ufshcd_mcq_make_queues_operational(struct ufs_hba *hba) } } +void ufshcd_mcq_enable_esi(struct ufs_hba *hba) +{ + ufshcd_writel(hba, ufshcd_readl(hba, REG_UFS_MEM_CFG) | 0x2, + REG_UFS_MEM_CFG); +} +EXPORT_SYMBOL_GPL(ufshcd_mcq_enable_esi); + +void ufshcd_mcq_config_esi(struct ufs_hba *hba, struct msi_msg *msg) +{ + ufshcd_writel(hba, msg->address_lo, REG_UFS_ESILBA); + ufshcd_writel(hba, msg->address_hi, REG_UFS_ESIUBA); +} +EXPORT_SYMBOL_GPL(ufshcd_mcq_config_esi); + int ufshcd_mcq_init(struct ufs_hba *hba) { struct Scsi_Host *host = hba->host; diff --git a/include/ufs/ufshcd.h b/include/ufs/ufshcd.h index 7f0139b..660ccd3 100644 --- a/include/ufs/ufshcd.h +++ b/include/ufs/ufshcd.h @@ -16,6 +16,7 @@ #include #include #include +#include #include #include #include @@ -1201,6 +1202,11 @@ void ufshcd_parse_dev_ref_clk_freq(struct ufs_hba *hba, struct clk *refclk); void ufshcd_update_evt_hist(struct ufs_hba *hba, u32 id, u32 val); void ufshcd_hba_stop(struct ufs_hba *hba); void ufshcd_schedule_eh_work(struct ufs_hba *hba); +void ufshcd_mcq_write_cqis(struct ufs_hba *hba, u32 val, int i); +unsigned long ufshcd_mcq_poll_cqe_nolock(struct ufs_hba *hba, + struct ufs_hw_queue *hwq); +void ufshcd_mcq_enable_esi(struct ufs_hba *hba); +void ufshcd_mcq_config_esi(struct ufs_hba *hba, struct msi_msg *msg); /** * ufshcd_set_variant - set variant specific data to the hba diff --git a/include/ufs/ufshci.h b/include/ufs/ufshci.h index 1df8425..9b74194 100644 --- a/include/ufs/ufshci.h +++ b/include/ufs/ufshci.h @@ -59,6 +59,8 @@ enum { REG_UFS_MEM_CFG = 0x300, REG_UFS_MCQ_CFG = 0x380, + REG_UFS_ESILBA = 0x384, + REG_UFS_ESIUBA = 0x388, UFSHCI_CRYPTO_REG_SPACE_SIZE = 0x400, }; From patchwork Thu Dec 15 03:06:22 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Can Guo X-Patchwork-Id: 33462 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:e747:0:0:0:0:0 with SMTP id c7csp109667wrn; Wed, 14 Dec 2022 19:09:12 -0800 (PST) X-Google-Smtp-Source: AA0mqf4jOHvvTf1o9VHHQcONQAiJ1RRPwbAiFfYTGRKoLx9E4Gdj3yf80DLP+jejTR7ydygeiGP9 X-Received: by 2002:a17:906:2249:b0:7c0:e23d:12c4 with SMTP id 9-20020a170906224900b007c0e23d12c4mr23005491ejr.63.1671073752043; Wed, 14 Dec 2022 19:09:12 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1671073752; cv=none; d=google.com; s=arc-20160816; b=zLjSGztUR23g7j6kuol/WNgTwbvcRW4y6qHAmdSdsfGkgh0u8giHVFEKsFuf6yO3yr G0SdXHQPM8pWW/zj/YZb+B056xsPkwkSBnQ+F9XVZxYXTRweGjT5GHQRFTjBcvL4mD77 5x3DtJQqSVO2eTEb/uI4T5eI+L3nhhUasKSQZNxuO1qgS+uV5dcgS32eaCJmBIMximiD S3sHEHOBT8rU+j0kRTYnYxC995vdEm0x0zjQyJc10FQLJ+W6AtpfSZTCrgARxkNgX4KQ pDDbaRxmv+lKJzR64JYl6ztKZI7zJ4NgyhiGtNRu1YWKdCJfWzaJ4VA6c0h9qo5M4qrf lqlg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from:dkim-signature; bh=fc+/8vFSou4s5+MOccYvq7ute0TTCtlSbQeVttuawN4=; b=exdfgg2qWCkE8YzMFzocghuqXjnVi+VmczTiyaOzFStPeNiF9YhQqczRa0nnzcV3Eb 4i4GROmfhXhRR1GG7fKyCXT+o0re1fUezbMGi55iIBLk4cRxYIdqPOggwzU4PGt1YHT7 ly/nJw1emdthlurHjDR80dnZk/3MZR2GNh6iHDYAqDVRalXWPYBgiFxvbKYuZWgvy/Yx Hlkbxx9ejdN1w+DmpF8vd/R05FK8kqOploVmvMMJrI/TzILCWvOJlluoKO0Bzs7ELCg4 IjewZ8Mrkn7x5VWTsSpZ4JIH8BmbRSQHTmvE8HEbJxLrpsrioOFQb+on9GXQKszULar1 6k5g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcdkim header.b="d6/x1t6K"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from out1.vger.email (out1.vger.email. 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Bottomley" , linux-arm-msm@vger.kernel.org (open list:ARM/QUALCOMM SUPPORT), linux-kernel@vger.kernel.org (open list) Subject: [PATCH v3 3/3] ufs-host: qcom: Add MCQ ESI config vendor specific ops Date: Wed, 14 Dec 2022 19:06:22 -0800 Message-Id: <1671073583-10065-4-git-send-email-quic_cang@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1671073583-10065-1-git-send-email-quic_cang@quicinc.com> References: <1671073583-10065-1-git-send-email-quic_cang@quicinc.com> X-Spam-Status: No, score=-4.0 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, RCVD_IN_DNSWL_MED,SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1752247830502946953?= X-GMAIL-MSGID: =?utf-8?q?1752247830502946953?= Add MCQ ESI config vendor specific ops. Co-developed-by: Asutosh Das Signed-off-by: Asutosh Das Signed-off-by: Can Guo Reviewed-by: Bart Van Assche --- drivers/ufs/host/ufs-qcom.c | 97 +++++++++++++++++++++++++++++++++++++++++++++ drivers/ufs/host/ufs-qcom.h | 5 +++ 2 files changed, 102 insertions(+) diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c index 96a58b4..ea5b5f7 100644 --- a/drivers/ufs/host/ufs-qcom.c +++ b/drivers/ufs/host/ufs-qcom.c @@ -1568,6 +1568,101 @@ static int ufs_qcom_get_outstanding_cqs(struct ufs_hba *hba, return 0; } +#ifdef CONFIG_GENERIC_MSI_IRQ_DOMAIN +static void ufs_qcom_write_msi_msg(struct msi_desc *desc, struct msi_msg *msg) +{ + struct device *dev = msi_desc_to_dev(desc); + struct ufs_hba *hba = dev_get_drvdata(dev); + + ufshcd_mcq_config_esi(hba, msg); +} + +static irqreturn_t ufs_qcom_mcq_esi_handler(int irq, void *__hba) +{ + struct ufs_hba *hba = __hba; + struct ufs_qcom_host *host = ufshcd_get_variant(hba); + u32 id = irq - host->esi_base; + struct ufs_hw_queue *hwq = &hba->uhq[id]; + + ufshcd_mcq_write_cqis(hba, 0x1, id); + ufshcd_mcq_poll_cqe_nolock(hba, hwq); + + return IRQ_HANDLED; +} + +static int ufs_qcom_config_esi(struct ufs_hba *hba) +{ + struct ufs_qcom_host *host = ufshcd_get_variant(hba); + struct msi_desc *desc; + struct msi_desc *failed_desc = NULL; + int nr_irqs, ret; + + if (host->esi_enabled) + return 0; + else if (host->esi_base < 0) + return -EINVAL; + + /* + * 1. We only handle CQs as of now. + * 2. Poll queues do not need ESI. + */ + nr_irqs = hba->nr_hw_queues - hba->nr_queues[HCTX_TYPE_POLL]; + ret = platform_msi_domain_alloc_irqs(hba->dev, nr_irqs, + ufs_qcom_write_msi_msg); + if (ret) + goto out; + + msi_for_each_desc(desc, hba->dev, MSI_DESC_ALL) { + if (!desc->msi_index) + host->esi_base = desc->irq; + + ret = devm_request_irq(hba->dev, desc->irq, + ufs_qcom_mcq_esi_handler, + IRQF_SHARED, "qcom-mcq-esi", hba); + if (ret) { + dev_err(hba->dev, "%s: Fail to request IRQ for %d, err = %d\n", + __func__, desc->irq, ret); + failed_desc = desc; + break; + } + } + + if (ret) { + /* Rewind */ + msi_for_each_desc(desc, hba->dev, MSI_DESC_ALL) { + if (desc == failed_desc) + break; + devm_free_irq(hba->dev, desc->irq, hba); + } + platform_msi_domain_free_irqs(hba->dev); + } else { + if (host->hw_ver.major == 6 && host->hw_ver.minor == 0 && + host->hw_ver.step == 0) { + ufshcd_writel(hba, + ufshcd_readl(hba, REG_UFS_CFG3) | 0x1F000, + REG_UFS_CFG3); + } + ufshcd_mcq_enable_esi(hba); + } + +out: + if (ret) { + host->esi_base = -1; + dev_warn(hba->dev, "Failed to request Platform MSI %d\n", ret); + } else { + host->esi_enabled = true; + } + + return ret; +} + +#else +static int ufs_qcom_config_esi(struct ufs_hba *hba) +{ + return -EOPNOTSUPP; +} +#endif + /* * struct ufs_hba_qcom_vops - UFS QCOM specific variant operations * @@ -1595,6 +1690,7 @@ static const struct ufs_hba_variant_ops ufs_hba_qcom_vops = { .get_hba_mac = ufs_qcom_get_hba_mac, .op_runtime_config = ufs_qcom_op_runtime_config, .get_outstanding_cqs = ufs_qcom_get_outstanding_cqs, + .config_esi = ufs_qcom_config_esi, }; /** @@ -1628,6 +1724,7 @@ static int ufs_qcom_remove(struct platform_device *pdev) pm_runtime_get_sync(&(pdev)->dev); ufshcd_remove(hba); + platform_msi_domain_free_irqs(hba->dev); return 0; } diff --git a/drivers/ufs/host/ufs-qcom.h b/drivers/ufs/host/ufs-qcom.h index 6912bdf..7937b41 100644 --- a/drivers/ufs/host/ufs-qcom.h +++ b/drivers/ufs/host/ufs-qcom.h @@ -54,6 +54,8 @@ enum { * added in HW Version 3.0.0 */ UFS_AH8_CFG = 0xFC, + + REG_UFS_CFG3 = 0x271C, }; /* QCOM UFS host controller vendor specific debug registers */ @@ -226,6 +228,9 @@ struct ufs_qcom_host { struct reset_controller_dev rcdev; struct gpio_desc *device_reset; + + int esi_base; + bool esi_enabled; }; static inline u32