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[2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id sa17-20020a1709076d1100b007b99436026dsi10921548ejc.968.2022.12.13.22.58.23 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 13 Dec 2022 22:58:23 -0800 (PST) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 00A2B384C349 for ; Wed, 14 Dec 2022 06:58:20 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from smtpbgeu2.qq.com (smtpbgeu2.qq.com [18.194.254.142]) by sourceware.org (Postfix) with ESMTPS id A0E3E384F953 for ; Wed, 14 Dec 2022 06:57:52 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org A0E3E384F953 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai X-QQ-mid: bizesmtp85t1671001066tnfnjfx6 Received: from rios-cad5.localdomain ( [58.60.1.11]) by bizesmtp.qq.com (ESMTP) with id ; Wed, 14 Dec 2022 14:57:45 +0800 (CST) X-QQ-SSF: 01400000000000D0L000000A0000000 X-QQ-FEAT: Rf1s/nWaRtuDP72CtDPU3rcv7CRAj6xVDMeKJDyWoYdSTus1VioMoDu7N43F2 EpqQW8LjalgrBkm/Fps3XSv2TkhKupIjXH5YuqwE9MHCRUhP3Ou7h7/n0QB5C7uXVvFXvue 8XAVgkiN2YLyAZVvt8eZ41wGQVG7+/PurygjO+tzPc04lDN9hBEXtc9HkH9Ww9hUyQihMAS J3mX4VepGe0Ak/2syrxnTVHEd+W6LbJVSOvXYB+XqoRB1rwy9kB4+IQamMwoSDD/WUMEsi2 rPCnS6uTM9+hI3q6Ia0ID9anR4K7IkUNtxaEKBhl0Gqi7j1Bj40d2j6bo26NQq0DbhTlNcV nNoGeW28PI8FI68isrhWc5qBCNZj+5+e4zib/LzkLg0mxfkZV4nCvtnsJ3ZDVM+7VaLjAmf X-QQ-GoodBg: 2 From: juzhe.zhong@rivai.ai To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, palmer@dabbelt.com, Ju-Zhe Zhong Subject: [PATCH] RISC-V: Change vlmul printing rule Date: Wed, 14 Dec 2022 14:57:44 +0800 Message-Id: <20221214065744.124007-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.3 MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvr:qybglogicsvr7 X-Spam-Status: No, score=-12.7 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_PASS, TXREP, T_SPF_HELO_TEMPERROR autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1752171652661826619?= X-GMAIL-MSGID: =?utf-8?q?1752171652661826619?= From: Ju-Zhe Zhong This patch is preparing patch for the following patch (VSETVL PASS) support since the current vlmul printing rule is not appropriate information for VSETVL PASS. I split this fix in a single patch. gcc/ChangeLog: * config/riscv/riscv-v.cc (emit_vlmax_vsetvl): Pass through VLMUL enum instead of machine mode. * config/riscv/riscv-vector-builtins-bases.cc: Ditto. * config/riscv/riscv.cc (riscv_print_operand): Print LMUL by enum vlmul instead of machine mode. --- gcc/config/riscv/riscv-v.cc | 2 +- .../riscv/riscv-vector-builtins-bases.cc | 2 +- gcc/config/riscv/riscv.cc | 52 ++++++++++--------- 3 files changed, 30 insertions(+), 26 deletions(-) diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc index 4992ff2470c..13ee33938bb 100644 --- a/gcc/config/riscv/riscv-v.cc +++ b/gcc/config/riscv/riscv-v.cc @@ -115,7 +115,7 @@ emit_vlmax_vsetvl (machine_mode vmode) emit_insn ( gen_vsetvl_no_side_effects (Pmode, vl, RVV_VLMAX, gen_int_mode (sew, Pmode), - gen_int_mode ((unsigned int) vmode, Pmode), + gen_int_mode (get_vlmul (vmode), Pmode), const1_rtx, const1_rtx)); return vl; } diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc b/gcc/config/riscv/riscv-vector-builtins-bases.cc index 231b63a610d..ffeb1b25fbc 100644 --- a/gcc/config/riscv/riscv-vector-builtins-bases.cc +++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc @@ -73,7 +73,7 @@ public: gen_int_mode (GET_MODE_BITSIZE (inner_mode), Pmode)); /* LMUL. */ - e.add_input_operand (Pmode, gen_int_mode ((unsigned int) mode, Pmode)); + e.add_input_operand (Pmode, gen_int_mode (get_vlmul (mode), Pmode)); /* TA. */ e.add_input_operand (Pmode, gen_int_mode (1, Pmode)); diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 2d380aa42cb..ff07d4a3843 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -4272,30 +4272,34 @@ riscv_print_operand (FILE *file, rtx op, int letter) } else if (code == CONST_INT) { - /* The value in the operand is the unsigned int value - converted from (enum machine_mode). - This RTX is generated as follows: - - machine_mode mode = XXXmode; - operand = gen_int_mode ((unsigned int)mode, Pmode); - - So we convert it back into machine_mode and then calculate - the LMUL according to GET_MODE_SIZE. */ - - machine_mode rvv_mode = (machine_mode) UINTVAL (op); - /* For rvv mask modes, we can not calculate LMUL simpily according - to BYTES_PER_RISCV_VECTOR. When rvv_mode = VNx4BImode. - Set SEW = 8, LMUL = 1 by default if TARGET_MIN_VLEN == 32. - Set SEW = 8, LMUL = 1 / 2 by default if TARGET_MIN_VLEN > 32. */ - bool bool_p = GET_MODE_CLASS (rvv_mode) == MODE_VECTOR_BOOL; - poly_int64 m1_size = BYTES_PER_RISCV_VECTOR; - poly_int64 rvv_size - = bool_p ? GET_MODE_NUNITS (rvv_mode) : GET_MODE_SIZE (rvv_mode); - bool fractional_p = known_lt (rvv_size, BYTES_PER_RISCV_VECTOR); - unsigned int factor - = fractional_p ? exact_div (m1_size, rvv_size).to_constant () - : exact_div (rvv_size, m1_size).to_constant (); - asm_fprintf (file, "%s%d", fractional_p ? "mf" : "m", factor); + /* If it is a const_int value, it denotes the VLMUL field enum. */ + unsigned int vlmul = UINTVAL (op); + switch (vlmul) + { + case riscv_vector::LMUL_1: + asm_fprintf (file, "%s", "m1"); + break; + case riscv_vector::LMUL_2: + asm_fprintf (file, "%s", "m2"); + break; + case riscv_vector::LMUL_4: + asm_fprintf (file, "%s", "m4"); + break; + case riscv_vector::LMUL_8: + asm_fprintf (file, "%s", "m8"); + break; + case riscv_vector::LMUL_F8: + asm_fprintf (file, "%s", "mf8"); + break; + case riscv_vector::LMUL_F4: + asm_fprintf (file, "%s", "mf4"); + break; + case riscv_vector::LMUL_F2: + asm_fprintf (file, "%s", "mf2"); + break; + default: + gcc_unreachable (); + } } else output_operand_lossage ("invalid vector constant");