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Tue, 13 Dec 2022 04:49:10 -0800 (PST) Received: from LAP568U.mistral.in ([106.51.227.150]) by smtp.gmail.com with ESMTPSA id y15-20020aa7942f000000b0057622e8e82csm7605485pfo.191.2022.12.13.04.49.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 13 Dec 2022 04:49:09 -0800 (PST) From: Sinthu Raja X-Google-Original-From: Sinthu Raja To: Vinod Koul , Ravi Gunasekaran , Siddharth Vadapalli Cc: Vignesh Raghavendra , Roger Quadros , linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, Sinthu Raja Subject: [PATCH 1/2] phy: ti: j721e-wiz: Manage TypeC lane swap if typec-gpio-dir not specified Date: Tue, 13 Dec 2022 18:18:53 +0530 Message-Id: <20221213124854.3779-2-sinthu.raja@ti.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20221213124854.3779-1-sinthu.raja@ti.com> References: <20221213124854.3779-1-sinthu.raja@ti.com> MIME-Version: 1.0 X-BESS-ID: 1670935751-305367-5380-5821-1 X-BESS-VER: 2019.1_20221212.2317 X-BESS-Apparent-Source-IP: 209.85.210.197 X-BESS-Outbound-Spam-Score: 0.00 X-BESS-Outbound-Spam-Report: Code version 3.2, rules version 3.2.2.244774 [from cloudscan15-235.eu-central-1a.ess.aws.cudaops.com] Rule breakdown below pts rule name description ---- ---------------------- -------------------------------- 0.00 BSF_BESS_OUTBOUND META: BESS Outbound 0.00 BSF_SC0_MISMATCH_TO META: Envelope rcpt doesn't match header X-BESS-Outbound-Spam-Status: SCORE=0.00 using account:ESS91090 scores of KILL_LEVEL=7.0 tests=BSF_BESS_OUTBOUND, BSF_SC0_MISMATCH_TO X-BESS-BRTS-Status: 1 X-Spam-Status: No, score=-2.8 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_LOW, RCVD_IN_MSPIKE_H2,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1752103696059685813?= X-GMAIL-MSGID: =?utf-8?q?1752103696059685813?= It's possible that the Type-C plug orientation on the DIR line will be implemented through hardware design. In that situation, there won't be an external GPIO line available, but the driver still needs to address this since the DT won't use the typec-gpio-dir property. Add code to handle LN10 Type-C swap if typec-gpio-dir property is not specified in DT. Remove typec-gpio-dir check to use minimum debounce from Type-C spec if it is not provided in DT Signed-off-by: Sinthu Raja --- drivers/phy/ti/phy-j721e-wiz.c | 65 +++++++++++++++++++++------------- 1 file changed, 40 insertions(+), 25 deletions(-) diff --git a/drivers/phy/ti/phy-j721e-wiz.c b/drivers/phy/ti/phy-j721e-wiz.c index 141b51af4427..b17eec632d49 100644 --- a/drivers/phy/ti/phy-j721e-wiz.c +++ b/drivers/phy/ti/phy-j721e-wiz.c @@ -375,6 +375,7 @@ struct wiz { struct gpio_desc *gpio_typec_dir; int typec_dir_delay; u32 lane_phy_type[WIZ_MAX_LANES]; + u32 lane_phy_reg[WIZ_MAX_LANES]; struct clk *input_clks[WIZ_MAX_INPUT_CLOCKS]; struct clk *output_clks[WIZ_MAX_OUTPUT_CLOCKS]; struct clk_onecell_data clk_data; @@ -1231,14 +1232,28 @@ static int wiz_phy_reset_deassert(struct reset_controller_dev *rcdev, int ret; /* if typec-dir gpio was specified, set LN10 SWAP bit based on that */ - if (id == 0 && wiz->gpio_typec_dir) { - if (wiz->typec_dir_delay) - msleep_interruptible(wiz->typec_dir_delay); - - if (gpiod_get_value_cansleep(wiz->gpio_typec_dir)) - regmap_field_write(wiz->typec_ln10_swap, 1); - else - regmap_field_write(wiz->typec_ln10_swap, 0); + if (id == 0 && wiz->typec_dir_delay) { + msleep_interruptible(wiz->typec_dir_delay); + + if (wiz->gpio_typec_dir) { + if (gpiod_get_value_cansleep(wiz->gpio_typec_dir)) + regmap_field_write(wiz->typec_ln10_swap, 1); + else + regmap_field_write(wiz->typec_ln10_swap, 0); + } else { + /* if no typec-dir gpio was specified, and USB lines + * are connected to Lane 0 then set LN10 SWAP bit to 1. + */ + u32 num_lanes = wiz->num_lanes; + int i; + + for (i = 0; i < num_lanes; i++) { + if ((wiz->lane_phy_type[i] == PHY_TYPE_USB3) \ + && wiz->lane_phy_reg[i] == 0) { + regmap_field_write(wiz->typec_ln10_swap, 1); + } + } + } } if (id == 0) { @@ -1370,8 +1385,10 @@ static int wiz_get_lane_phy_types(struct device *dev, struct wiz *wiz) dev_dbg(dev, "%s: Lanes %u-%u have phy-type %u\n", __func__, reg, reg + num_lanes - 1, phy_type); - for (i = reg; i < reg + num_lanes; i++) + for (i = reg; i < reg + num_lanes; i++) { + wiz->lane_phy_reg[i] = reg; wiz->lane_phy_type[i] = phy_type; + } } return 0; @@ -1464,24 +1481,22 @@ static int wiz_probe(struct platform_device *pdev) goto err_addr_to_resource; } - if (wiz->gpio_typec_dir) { - ret = of_property_read_u32(node, "typec-dir-debounce-ms", - &wiz->typec_dir_delay); - if (ret && ret != -EINVAL) { - dev_err(dev, "Invalid typec-dir-debounce property\n"); - goto err_addr_to_resource; - } + ret = of_property_read_u32(node, "typec-dir-debounce-ms", + &wiz->typec_dir_delay); + if (ret && ret != -EINVAL) { + dev_err(dev, "Invalid typec-dir-debounce property\n"); + goto err_addr_to_resource; + } - /* use min. debounce from Type-C spec if not provided in DT */ - if (ret == -EINVAL) - wiz->typec_dir_delay = WIZ_TYPEC_DIR_DEBOUNCE_MIN; + /* use min. debounce from Type-C spec if not provided in DT */ + if (ret == -EINVAL) + wiz->typec_dir_delay = WIZ_TYPEC_DIR_DEBOUNCE_MIN; - if (wiz->typec_dir_delay < WIZ_TYPEC_DIR_DEBOUNCE_MIN || - wiz->typec_dir_delay > WIZ_TYPEC_DIR_DEBOUNCE_MAX) { - ret = -EINVAL; - dev_err(dev, "Invalid typec-dir-debounce property\n"); - goto err_addr_to_resource; - } + if (wiz->typec_dir_delay < WIZ_TYPEC_DIR_DEBOUNCE_MIN || + wiz->typec_dir_delay > WIZ_TYPEC_DIR_DEBOUNCE_MAX) { + ret = -EINVAL; + dev_err(dev, "Invalid typec-dir-debounce property\n"); + goto err_addr_to_resource; } ret = wiz_get_lane_phy_types(dev, wiz); From patchwork Tue Dec 13 12:48:54 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sinthu Raja X-Patchwork-Id: 32805 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:e747:0:0:0:0:0 with SMTP id c7csp100712wrn; Tue, 13 Dec 2022 04:58:07 -0800 (PST) X-Google-Smtp-Source: AA0mqf5z9e40VJ5nKzLRI5dxff3TNvp9yv851j+yBCKst6iqh3hirQkyas9J1EwwsMXrkXs8XtxQ X-Received: by 2002:a05:6a00:1687:b0:56b:f566:600f with SMTP id k7-20020a056a00168700b0056bf566600fmr26395254pfc.12.1670936287060; Tue, 13 Dec 2022 04:58:07 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1670936287; 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Tue, 13 Dec 2022 04:49:13 -0800 (PST) Received: from LAP568U.mistral.in ([106.51.227.150]) by smtp.gmail.com with ESMTPSA id y15-20020aa7942f000000b0057622e8e82csm7605485pfo.191.2022.12.13.04.49.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 13 Dec 2022 04:49:12 -0800 (PST) From: Sinthu Raja X-Google-Original-From: Sinthu Raja To: Vinod Koul , Ravi Gunasekaran , Siddharth Vadapalli Cc: Vignesh Raghavendra , Roger Quadros , linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, Sinthu Raja Subject: [PATCH 2/2] phy: ti: j721e-wiz: Add support to enable LN23 Type-C swap Date: Tue, 13 Dec 2022 18:18:54 +0530 Message-Id: <20221213124854.3779-3-sinthu.raja@ti.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20221213124854.3779-1-sinthu.raja@ti.com> References: <20221213124854.3779-1-sinthu.raja@ti.com> MIME-Version: 1.0 X-BESS-ID: 1670935754-312012-5635-5406-1 X-BESS-VER: 2019.1_20221212.2317 X-BESS-Apparent-Source-IP: 209.85.214.199 X-BESS-Outbound-Spam-Score: 0.50 X-BESS-Outbound-Spam-Report: Code version 3.2, rules version 3.2.2.244774 [from cloudscan15-174.eu-central-1a.ess.aws.cudaops.com] Rule breakdown below pts rule name description ---- ---------------------- -------------------------------- 0.50 BSF_RULE7568M META: Custom Rule 7568M 0.00 BSF_BESS_OUTBOUND META: BESS Outbound 0.00 BSF_SC0_MISMATCH_TO META: Envelope rcpt doesn't match header X-BESS-Outbound-Spam-Status: SCORE=0.50 using account:ESS91090 scores of KILL_LEVEL=7.0 tests=BSF_RULE7568M, BSF_BESS_OUTBOUND, BSF_SC0_MISMATCH_TO X-BESS-BRTS-Status: 1 X-Spam-Status: No, score=-2.8 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_LOW, RCVD_IN_MSPIKE_H2,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1752103688236192930?= X-GMAIL-MSGID: =?utf-8?q?1752103688236192930?= Serdes wiz supports both LN23 and LN10 Type-C swap. Add support to configure LN23 bit to swap between lane2 or lane3 if required. Signed-off-by: Sinthu Raja --- drivers/phy/ti/phy-j721e-wiz.c | 33 +++++++++++++++++++++++++++++---- 1 file changed, 29 insertions(+), 4 deletions(-) diff --git a/drivers/phy/ti/phy-j721e-wiz.c b/drivers/phy/ti/phy-j721e-wiz.c index b17eec632d49..0091892af0b0 100644 --- a/drivers/phy/ti/phy-j721e-wiz.c +++ b/drivers/phy/ti/phy-j721e-wiz.c @@ -58,6 +58,11 @@ enum wiz_lane_standard_mode { LANE_MODE_GEN4, }; +enum wiz_lane_typec_swap_mode { + LANE10_SWAP = 0, + LANE23_SWAP = 2, +}; + enum wiz_refclk_mux_sel { PLL0_REFCLK, PLL1_REFCLK, @@ -194,6 +199,9 @@ static const struct reg_field p_mac_div_sel1[WIZ_MAX_LANES] = { static const struct reg_field typec_ln10_swap = REG_FIELD(WIZ_SERDES_TYPEC, 30, 30); +static const struct reg_field typec_ln23_swap = + REG_FIELD(WIZ_SERDES_TYPEC, 31, 31); + struct wiz_clk_mux { struct clk_hw hw; struct regmap_field *field; @@ -366,6 +374,7 @@ struct wiz { struct regmap_field *mux_sel_field[WIZ_MUX_NUM_CLOCKS]; struct regmap_field *div_sel_field[WIZ_DIV_NUM_CLOCKS_16G]; struct regmap_field *typec_ln10_swap; + struct regmap_field *typec_ln23_swap; struct regmap_field *sup_legacy_clk_override; struct device *dev; @@ -675,6 +684,13 @@ static int wiz_regfield_init(struct wiz *wiz) return PTR_ERR(wiz->typec_ln10_swap); } + wiz->typec_ln23_swap = devm_regmap_field_alloc(dev, regmap, + typec_ln23_swap); + if (IS_ERR(wiz->typec_ln23_swap)) { + dev_err(dev, "LN23_SWAP reg field init failed\n"); + return PTR_ERR(wiz->typec_ln23_swap); + } + wiz->phy_en_refclk = devm_regmap_field_alloc(dev, regmap, phy_en_refclk); if (IS_ERR(wiz->phy_en_refclk)) { dev_err(dev, "PHY_EN_REFCLK reg field init failed\n"); @@ -1242,15 +1258,24 @@ static int wiz_phy_reset_deassert(struct reset_controller_dev *rcdev, regmap_field_write(wiz->typec_ln10_swap, 0); } else { /* if no typec-dir gpio was specified, and USB lines - * are connected to Lane 0 then set LN10 SWAP bit to 1. + * are connected to SWAP lanes '0' or '2' then set LN10 SWAP + * or LN23 bit to 1 respectively. */ u32 num_lanes = wiz->num_lanes; int i; for (i = 0; i < num_lanes; i++) { - if ((wiz->lane_phy_type[i] == PHY_TYPE_USB3) \ - && wiz->lane_phy_reg[i] == 0) { - regmap_field_write(wiz->typec_ln10_swap, 1); + if (wiz->lane_phy_type[i] == PHY_TYPE_USB3) { + switch (wiz->lane_phy_reg[i]) { + case LANE10_SWAP: + regmap_field_write(wiz->typec_ln10_swap, 1); + break; + case LANE23_SWAP: + regmap_field_write(wiz->typec_ln23_swap, 1); + break; + default: + break; + } } } }