From patchwork Tue Dec 13 09:00:24 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Victor Shih X-Patchwork-Id: 32694 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:8188:b0:89:790f:f786 with SMTP id m8csp3856905dye; Tue, 13 Dec 2022 01:02:46 -0800 (PST) X-Google-Smtp-Source: AA0mqf5Igm0zDnerz8y2+C/Yiy/DEzJBmPaKGfmFaOZisE+PO1qkjpVnxGrVSgEYq8Ftuoxls/2o X-Received: by 2002:a17:90a:f3c2:b0:219:38b7:4809 with SMTP id ha2-20020a17090af3c200b0021938b74809mr20303509pjb.39.1670922165926; Tue, 13 Dec 2022 01:02:45 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1670922165; cv=none; d=google.com; s=arc-20160816; b=EZAjr9l4ul0QPU1fXIZPrrYEkZzMXLSBscWnEXc6bh22vvTSaNjngMtG8+cF8lp78I GNbjdYGktT8goQDxdBv6+i9dRm2qRgFF2DiHK5IxouW0xkY3XuxQ3crv6I+OGHtD1234 6VG29f4gYdwllcxRezV65tBNq5BbGqThz7YDA7LYTsCBIL6BIFG2S/ujEL//D9sOMOYg rptRLTbZao1ri30jly1VgHBUHp9WtN/0HA+Qzq9wYGzvncPmyBWlgcnTFg+q/H4U4+mU DDcyCTeE+a1RSvmliMJMACzzCNPJn8Rt+glct699ersxI7xQvQxmRcK132ENoHUHrHhv 0rLg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=OnZ14x+Cd+TEg+zucSh/Nr19nBP6U3yPYDLuptGj0yU=; b=V99gDfWt0czLJRfShuL16pZmh9NZm90X32ZjFrG8R8LmVjgLUtRzcVECPwLkugq4ds ju92TuVvNrLFxO9FgCcOyBZ0yAY5RI4YGh0UfeW2hH6U1JL+3BMe9O+O1LtuoWeDGFU6 zcAbD3sBDPt4koQ8FN009dR+OZwX1yZS3b2RS7AuNHhnA7JtdHBJQAN0Kfheny3Oqpof w28NAf0m80d834qutaAmo6GM3+eIVL+IvA3DPnbN5vd0jlEgekZYWYbg4/bYSyP7SYu/ gnBwGbMsFS3tBv4niJDeOz6j4cyDmWQqZ34giCrPGmW8RoTENI1qpvtUEgYus86Zjtd4 wiUA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20210112 header.b=qUTiEHNy; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id 131-20020a630589000000b00478a09699f8si12273140pgf.126.2022.12.13.01.02.33; Tue, 13 Dec 2022 01:02:45 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@gmail.com header.s=20210112 header.b=qUTiEHNy; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234748AbiLMJBM (ORCPT + 99 others); Tue, 13 Dec 2022 04:01:12 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35838 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234733AbiLMJBI (ORCPT ); Tue, 13 Dec 2022 04:01:08 -0500 Received: from mail-pg1-x529.google.com (mail-pg1-x529.google.com [IPv6:2607:f8b0:4864:20::529]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BFF3562E1; Tue, 13 Dec 2022 01:01:07 -0800 (PST) Received: by mail-pg1-x529.google.com with SMTP id 62so9966439pgb.13; Tue, 13 Dec 2022 01:01:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=OnZ14x+Cd+TEg+zucSh/Nr19nBP6U3yPYDLuptGj0yU=; b=qUTiEHNy4ETosFcpfvdfkl5YygjNK3pfz1KiVstmSGIsMF4rqVrBI60aPcZZqzkAPZ To8u7kWzviFjCrW1xbuoJG0FJjowUeDiVmzXW/5o5D1Zd5WJhZY3UbIsBr4rIWK++Rqf LjfQCn94uIEufBDNz+M6QH+aPXDO6nlxbWQzorcB6DaPSXZO4vaO50JTCHo+gozNSMWF JbnRQmDZcW8q0sr6YMiz3uVH96XQ9CU6Qng4xPM+hENqg9sY9UuqDRVgOske8Fzt5qsv 847sAcQuNlDIuCUnWJMtQ4XbdSjIUH/gcGJJmqtFodZr9athZC9ZfmR6WDbYnsXx1Z6+ Lguw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=OnZ14x+Cd+TEg+zucSh/Nr19nBP6U3yPYDLuptGj0yU=; b=FbO5CrArAeTHbf+KXG81fVRcHKxxsn/smSaP/VhA5mqkQmI235zq4fl9rpu74nkEcQ f7xqWN9eQCBv8Pg86AOvBq+5cMhuuL7hJkXL4kp6RigxSS6j0KLBGkMJgeVHN/ropled ZFNOn4ibQx8hxuyGDRr638I1+/TonBymK13CGYrhfr5cDefgCf4eA4B91UQdN162QGfJ EmyXGVju1znfd8uVrqtXt4GePvDQK4DFGfKEIvQy0FX7oQju/ZAoLcs4sfpnrjzbj+fT jruhlHkkD/UNPOeToMJidaxN8BfgHN8iCUnmgrnOuJ8ZNaPUlNpbC6dIzI0LezoZNOKs uYKQ== X-Gm-Message-State: ANoB5plt7wWqBNssT0x8ygYWub6lWCjO949ilqZv4/MZIa/rS2SOVdt0 dSVDxn4+hmYqxve8D5du06o= X-Received: by 2002:a05:6a00:26c5:b0:576:fb7c:7aa3 with SMTP id p5-20020a056a0026c500b00576fb7c7aa3mr18291570pfw.14.1670922067266; Tue, 13 Dec 2022 01:01:07 -0800 (PST) Received: from localhost.localdomain (2001-b400-e2dc-5c03-264b-f684-a8c9-21ae.emome-ip6.hinet.net. [2001:b400:e2dc:5c03:264b:f684:a8c9:21ae]) by smtp.gmail.com with ESMTPSA id 81-20020a621954000000b0056b9ec7e2desm7141682pfz.125.2022.12.13.01.01.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 13 Dec 2022 01:01:06 -0800 (PST) From: Victor Shih X-Google-Original-From: Victor Shih To: ulf.hansson@linaro.org, adrian.hunter@intel.com Cc: linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, benchuanggli@gmail.com, HL.Liu@genesyslogic.com.tw, Greg.tu@genesyslogic.com.tw, takahiro.akashi@linaro.org, dlunev@chromium.org, Victor Shih Subject: [PATCH V6 01/24] mmc: core: Cleanup printing of speed mode at card insertion Date: Tue, 13 Dec 2022 17:00:24 +0800 Message-Id: <20221213090047.3805-2-victor.shih@genesyslogic.com.tw> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221213090047.3805-1-victor.shih@genesyslogic.com.tw> References: <20221213090047.3805-1-victor.shih@genesyslogic.com.tw> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM, RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1752088881183086465?= X-GMAIL-MSGID: =?utf-8?q?1752088881183086465?= The current print of the bus speed mode in mmc_add_card() has grown over the years and is now difficult to parse. Let's clean up the code and also take the opportunity to properly announce "DDR" for eMMCs as "high speed DDR", which is according to the eMMC spec. Signed-off-by: Ulf Hansson Signed-off-by: Victor Shih --- drivers/mmc/core/bus.c | 35 ++++++++++++++++++++--------------- 1 file changed, 20 insertions(+), 15 deletions(-) diff --git a/drivers/mmc/core/bus.c b/drivers/mmc/core/bus.c index 36679f4e9acc..bbbbdbca5366 100644 --- a/drivers/mmc/core/bus.c +++ b/drivers/mmc/core/bus.c @@ -299,6 +299,7 @@ int mmc_add_card(struct mmc_card *card) { int ret; const char *type; + const char *speed_mode = ""; const char *uhs_bus_speed_mode = ""; static const char *const uhs_speeds[] = { [UHS_SDR12_BUS_SPEED] = "SDR12 ", @@ -337,25 +338,29 @@ int mmc_add_card(struct mmc_card *card) break; } + if (mmc_card_hs(card)) + speed_mode = "high speed "; + else if (mmc_card_uhs(card)) + speed_mode = "ultra high speed "; + else if (mmc_card_ddr52(card)) + speed_mode = "high speed DDR "; + else if (mmc_card_hs200(card)) + speed_mode = "HS200 "; + else if (mmc_card_hs400es(card)) + speed_mode = "HS400 Enhanced strobe "; + else if (mmc_card_hs400(card)) + speed_mode = "HS400 "; + if (mmc_card_uhs(card) && (card->sd_bus_speed < ARRAY_SIZE(uhs_speeds))) uhs_bus_speed_mode = uhs_speeds[card->sd_bus_speed]; - if (mmc_host_is_spi(card->host)) { - pr_info("%s: new %s%s%s card on SPI\n", - mmc_hostname(card->host), - mmc_card_hs(card) ? "high speed " : "", - mmc_card_ddr52(card) ? "DDR " : "", - type); - } else { - pr_info("%s: new %s%s%s%s%s%s card at address %04x\n", - mmc_hostname(card->host), - mmc_card_uhs(card) ? "ultra high speed " : - (mmc_card_hs(card) ? "high speed " : ""), - mmc_card_hs400(card) ? "HS400 " : - (mmc_card_hs200(card) ? "HS200 " : ""), - mmc_card_hs400es(card) ? "Enhanced strobe " : "", - mmc_card_ddr52(card) ? "DDR " : "", + if (mmc_host_is_spi(card->host)) + pr_info("%s: new %s%s card on SPI\n", + mmc_hostname(card->host), speed_mode, type); + else { + pr_info("%s: new %s%s%s card at address %04x\n", + mmc_hostname(card->host), speed_mode, uhs_bus_speed_mode, type, card->rca); } From patchwork Tue Dec 13 09:00:25 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Victor Shih X-Patchwork-Id: 32695 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:8188:b0:89:790f:f786 with SMTP id m8csp3857167dye; Tue, 13 Dec 2022 01:03:07 -0800 (PST) X-Google-Smtp-Source: AA0mqf7UEpOZVEeajW//jXuUjpqJ0V7GWeDJYijb9D1KbVldBFwk9vUpG2X4cu255Eux+1SoXYXV X-Received: by 2002:a17:90b:1207:b0:219:5bd1:a32d with SMTP id gl7-20020a17090b120700b002195bd1a32dmr19681634pjb.39.1670922186898; Tue, 13 Dec 2022 01:03:06 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1670922186; cv=none; d=google.com; s=arc-20160816; b=D2QV/Q5ZfhNnZ7zQsYrXRmvaovjoro03fwyLRxS49qQynHVBzqu0RANW5i89Y4NKl0 EWnAAUx6WALe1yznwW/Yi+e8Y7Gyj8dr//1gBPnZFQYiLzD3Dybp9UnwyazqX5j9tHoZ oBRTn1ikLQmu2Mv4IVS/XOoS/GPkC0LXmW2BiUMw4F0ZdDqgihFSOFDNtmp697sHuv0G MuTN0ZbnXCjwr6qhFI6MoTZ/nGw2oioPybd0zN5vp4L2fUUievl7O6CpLQk8hVfW6gdH 6V/7J0wl/rmfBn/x57gvnLjEF5GqE2vifwV5tAI9vXdqpIsqIfYrVZM+rpRvrQTvbLuu ruVQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=8/2aPR5cjL3Xw9e4fZnl97FHWpptrNy6HVYitqVGsm4=; b=ZFWyVnKlN5TQCR3ttJJTQLoJFpXT2lE3Cbhd0Jx3sEQ3yLjf+Rr1kwfMiu0umAQqIL PW+TOdnjLmKZKYBwcSzSYR8I6FVp2Y9f4abJkCe2DyJ+AiSerPKES5KmtuSO/kLmWoLl 4CWjPrwrjLG+u/5VLyXy6XQ5rHTkNNNaqPtDsZs5kSZAwL59HSLCI3SqwimhPN2Xqq9s M9ziKCZU5BKU8/eQMYdOkmuGQzF7fkgKMoQqEG9f1D3wsSFS3jTvAT+UsjEknF7sbzvY Bh829XmZgwnpXXGB+koDclrKWeVfXgNxhHsKfdbPH9lnYYRvYS4BVlhQ2EOfVqb+XzrH UrSA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20210112 header.b=LiPopkNa; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id r23-20020a632b17000000b00476e8fca283si12752860pgr.725.2022.12.13.01.02.51; Tue, 13 Dec 2022 01:03:06 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@gmail.com header.s=20210112 header.b=LiPopkNa; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234795AbiLMJBY (ORCPT + 99 others); Tue, 13 Dec 2022 04:01:24 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35884 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234704AbiLMJBM (ORCPT ); Tue, 13 Dec 2022 04:01:12 -0500 Received: from mail-pg1-x529.google.com (mail-pg1-x529.google.com [IPv6:2607:f8b0:4864:20::529]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id ED37AE0B2; Tue, 13 Dec 2022 01:01:10 -0800 (PST) Received: by mail-pg1-x529.google.com with SMTP id 62so9966532pgb.13; Tue, 13 Dec 2022 01:01:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=8/2aPR5cjL3Xw9e4fZnl97FHWpptrNy6HVYitqVGsm4=; b=LiPopkNaDxqb2IJ8L5m6SNs1oLB83nlrjDAKea8zANqNMxbejIRClFsWJNX1JF0gk3 gD+sf6OaTS3NyPWj7DSdTQsA9fRPS1vLMoBFg7WCk+yIvo38zPLBPA59/ze5YO9I0iV8 +FSRPP/VNd8GyW/q7R29YczEN4ukTCm2e2Ek2qyk86EHysDK/YhVSIUJjhw/7lR45ZC1 01KUwZueV29W9Pt6vgh7m7UkC3aQNuED9vSWlSuxo3hsWinEqZscKhS70b0IIB4zkjeb nj2GnIYVT1/VqCjwzRT8GUFEvzPNVfNOPHjS6WFYBSIIvRgqPX6yaRvT8o10Dx2xE47+ 7SvA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=8/2aPR5cjL3Xw9e4fZnl97FHWpptrNy6HVYitqVGsm4=; b=XHyo0yDqOjHDRv8c2RkhAMPBfmxodX3LZAci2P17l2z7OVJ1Pge/Bfa2OR/9Q3mOGr y7omb/WK6PHCHNLTLIAnUDuO+xp7jbAZ9hJ9f8Pl3x3bcN237wLy63UvdxwVzxCA9Nsx TPuAE7+jhVZ8Zkcb038tMBMQtM9KJeL40tSyVBhEovgaFXpr1dsWqggkmu2+V6Fkz+t5 u6fwZ/GFQiLKDsVn5E4yIIst1aP18s1t1bB7syWO1Q002SCkvsfKzH5S3yvjwt8Lslvl gleNp+TvRIp+gvVkVdryZp/fewnOUL+1uQFReuQQKg2YoseL/vv6LIWwqTNZ+n1GIq9J RJdA== X-Gm-Message-State: ANoB5pnRdOZEtd0JxMin/F2gxle6OMnCAZqHLUyVtpW6Xtdx6jCpsre1 vL9hzO1WcGmjystNSKHdRVwVZWU6TuMKLw== X-Received: by 2002:a05:6a00:1c95:b0:578:8864:b25c with SMTP id y21-20020a056a001c9500b005788864b25cmr5918348pfw.25.1670922070259; Tue, 13 Dec 2022 01:01:10 -0800 (PST) Received: from localhost.localdomain (2001-b400-e2dc-5c03-264b-f684-a8c9-21ae.emome-ip6.hinet.net. [2001:b400:e2dc:5c03:264b:f684:a8c9:21ae]) by smtp.gmail.com with ESMTPSA id 81-20020a621954000000b0056b9ec7e2desm7141682pfz.125.2022.12.13.01.01.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 13 Dec 2022 01:01:09 -0800 (PST) From: Victor Shih X-Google-Original-From: Victor Shih To: ulf.hansson@linaro.org, adrian.hunter@intel.com Cc: linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, benchuanggli@gmail.com, HL.Liu@genesyslogic.com.tw, Greg.tu@genesyslogic.com.tw, takahiro.akashi@linaro.org, dlunev@chromium.org, Victor Shih Subject: [PATCH V6 02/24] mmc: core: Prepare to support SD UHS-II cards Date: Tue, 13 Dec 2022 17:00:25 +0800 Message-Id: <20221213090047.3805-3-victor.shih@genesyslogic.com.tw> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221213090047.3805-1-victor.shih@genesyslogic.com.tw> References: <20221213090047.3805-1-victor.shih@genesyslogic.com.tw> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM, RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1752088903253938253?= X-GMAIL-MSGID: =?utf-8?q?1752088903253938253?= From: Ulf Hansson Updates in V4: - Re-based, updated a comment and removed white-space. - Moved MMC_VQMMC2_VOLTAGE_180 into a later patch in the series. Update in previous version: The SD UHS-II interface was introduced to the SD spec v4.00 several years ago. The interface is fundamentally different from an electrical and a protocol point of view, comparing to the legacy SD interface. However, the legacy SD protocol is supported through a specific transport layer (SD-TRAN) defined in the UHS-II addendum of the spec. This allows the SD card to be managed in a very similar way as a legacy SD card, hence a lot of code can be re-used to support these new types of cards through the mmc subsystem. Moreover, an SD card that supports the UHS-II interface shall also be backwards compatible with the legacy SD interface, which allows a UHS-II card to be inserted into a legacy slot. As a matter of fact, this is already supported by mmc subsystem as of today. To prepare to add support for UHS-II, this change puts the basic foundation in the mmc core in place, allowing it to be more easily reviewed before subsequent changes implements the actual support. Basically, the approach here adds a new UHS-II bus_ops type and adds a separate initialization path for the UHS-II card. The intent is to avoid us from sprinkling the legacy initialization path, but also to simplify implementation of the UHS-II specific bits. At this point, there is only one new host ops added to manage the various ios settings needed for UHS-II. Additional host ops that are needed, are being added from subsequent changes. Signed-off-by: Ulf Hansson --- drivers/mmc/core/Makefile | 2 +- drivers/mmc/core/core.c | 17 ++- drivers/mmc/core/core.h | 1 + drivers/mmc/core/sd_uhs2.c | 289 +++++++++++++++++++++++++++++++++++++ include/linux/mmc/card.h | 7 + include/linux/mmc/host.h | 19 +++ 6 files changed, 333 insertions(+), 2 deletions(-) create mode 100644 drivers/mmc/core/sd_uhs2.c diff --git a/drivers/mmc/core/Makefile b/drivers/mmc/core/Makefile index 6a907736cd7a..15b067e8b0d1 100644 --- a/drivers/mmc/core/Makefile +++ b/drivers/mmc/core/Makefile @@ -7,7 +7,7 @@ obj-$(CONFIG_MMC) += mmc_core.o mmc_core-y := core.o bus.o host.o \ mmc.o mmc_ops.o sd.o sd_ops.o \ sdio.o sdio_ops.o sdio_bus.o \ - sdio_cis.o sdio_io.o sdio_irq.o \ + sdio_cis.o sdio_io.o sdio_irq.o sd_uhs2.o\ slot-gpio.o regulator.o mmc_core-$(CONFIG_OF) += pwrseq.o obj-$(CONFIG_PWRSEQ_SIMPLE) += pwrseq_simple.o diff --git a/drivers/mmc/core/core.c b/drivers/mmc/core/core.c index c04f5016807b..ad1a40446813 100644 --- a/drivers/mmc/core/core.c +++ b/drivers/mmc/core/core.c @@ -2244,6 +2244,18 @@ void mmc_rescan(struct work_struct *work) goto out; } + /* + * Ideally we should favor initialization of legacy SD cards and defer + * UHS-II enumeration. However, it seems like cards doesn't reliably + * announce their support for UHS-II in the response to the ACMD41, + * while initializing the legacy SD interface. Therefore, let's start + * with UHS-II for now. + */ + if (!mmc_attach_sd_uhs2(host)) { + mmc_release_host(host); + goto out; + } + for (i = 0; i < ARRAY_SIZE(freqs); i++) { unsigned int freq = freqs[i]; if (freq > host->f_max) { @@ -2271,10 +2283,13 @@ void mmc_rescan(struct work_struct *work) void mmc_start_host(struct mmc_host *host) { + bool power_up = !(host->caps2 & + (MMC_CAP2_NO_PRESCAN_POWERUP | MMC_CAP2_SD_UHS2)); + host->f_init = max(min(freqs[0], host->f_max), host->f_min); host->rescan_disable = 0; - if (!(host->caps2 & MMC_CAP2_NO_PRESCAN_POWERUP)) { + if (power_up) { mmc_claim_host(host); mmc_power_up(host, host->ocr_avail); mmc_release_host(host); diff --git a/drivers/mmc/core/core.h b/drivers/mmc/core/core.h index 37091a6589ed..920323faa834 100644 --- a/drivers/mmc/core/core.h +++ b/drivers/mmc/core/core.h @@ -81,6 +81,7 @@ int mmc_detect_card_removed(struct mmc_host *host); int mmc_attach_mmc(struct mmc_host *host); int mmc_attach_sd(struct mmc_host *host); int mmc_attach_sdio(struct mmc_host *host); +int mmc_attach_sd_uhs2(struct mmc_host *host); /* Module parameters */ extern bool use_spi_crc; diff --git a/drivers/mmc/core/sd_uhs2.c b/drivers/mmc/core/sd_uhs2.c new file mode 100644 index 000000000000..800957f74632 --- /dev/null +++ b/drivers/mmc/core/sd_uhs2.c @@ -0,0 +1,289 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2021 Linaro Ltd + * + * Author: Ulf Hansson + * + * Support for SD UHS-II cards + */ +#include + +#include +#include + +#include "core.h" +#include "bus.h" +#include "sd.h" +#include "mmc_ops.h" + +static const unsigned int sd_uhs2_freqs[] = { 52000000, 26000000 }; + +static int sd_uhs2_set_ios(struct mmc_host *host) +{ + struct mmc_ios *ios = &host->ios; + + return host->ops->uhs2_set_ios(host, ios); +} + +static int sd_uhs2_power_up(struct mmc_host *host) +{ + host->ios.vdd = fls(host->ocr_avail) - 1; + host->ios.clock = host->f_init; + host->ios.timing = MMC_TIMING_SD_UHS2; + host->ios.power_mode = MMC_POWER_UP; + + return sd_uhs2_set_ios(host); +} + +static void sd_uhs2_power_off(struct mmc_host *host) +{ + host->ios.vdd = 0; + host->ios.clock = 0; + host->ios.timing = MMC_TIMING_LEGACY; + host->ios.power_mode = MMC_POWER_OFF; + + sd_uhs2_set_ios(host); +} + +/* + * Run the phy initialization sequence, which mainly relies on the UHS-II host + * to check that we reach the expected electrical state, between the host and + * the card. + */ +static int sd_uhs2_phy_init(struct mmc_host *host) +{ + return 0; +} + +/* + * Do the early initialization of the card, by sending the device init broadcast + * command and wait for the process to be completed. + */ +static int sd_uhs2_dev_init(struct mmc_host *host) +{ + return 0; +} + +/* + * Run the enumeration process by sending the enumerate command to the card. + * Note that, we currently support only the point to point connection, which + * means only one card can be attached per host/slot. + */ +static int sd_uhs2_enum(struct mmc_host *host, u32 *node_id) +{ + return 0; +} + +/* + * Read the UHS-II configuration registers (CFG_REG) of the card, by sending it + * commands and by parsing the responses. Store a copy of the relevant data in + * card->uhs2_config. + */ +static int sd_uhs2_config_read(struct mmc_host *host, struct mmc_card *card) +{ + return 0; +} + +/* + * Based on the card's and host's UHS-II capabilities, let's update the + * configuration of the card and the host. This may also include to move to a + * greater speed range/mode. Depending on the updated configuration, we may need + * to do a soft reset of the card via sending it a GO_DORMANT_STATE command. + * + * In the final step, let's check if the card signals "config completion", which + * indicates that the card has moved from config state into active state. + */ +static int sd_uhs2_config_write(struct mmc_host *host, struct mmc_card *card) +{ + return 0; +} + +/* + * Initialize the UHS-II card through the SD-TRAN transport layer. This enables + * commands/requests to be backwards compatible through the legacy SD protocol. + * UHS-II cards has a specific power limit specified for VDD1/VDD2, that should + * be set through a legacy CMD6. Note that, the power limit that becomes set, + * survives a soft reset through the GO_DORMANT_STATE command. + */ +static int sd_uhs2_legacy_init(struct mmc_host *host, struct mmc_card *card) +{ + return 0; +} + +/* + * Allocate the data structure for the mmc_card and run the UHS-II specific + * initialization sequence. + */ +static int sd_uhs2_init_card(struct mmc_host *host) +{ + struct mmc_card *card; + u32 node_id; + int err; + + err = sd_uhs2_dev_init(host); + if (err) + return err; + + err = sd_uhs2_enum(host, &node_id); + if (err) + return err; + + card = mmc_alloc_card(host, &sd_type); + if (IS_ERR(card)) + return PTR_ERR(card); + + card->uhs2_config.node_id = node_id; + card->type = MMC_TYPE_SD; + + err = sd_uhs2_config_read(host, card); + if (err) + goto err; + + err = sd_uhs2_config_write(host, card); + if (err) + goto err; + + err = sd_uhs2_legacy_init(host, card); + if (err) + goto err; + + host->card = card; + return 0; + +err: + mmc_remove_card(card); + return err; +} + +static void sd_uhs2_remove(struct mmc_host *host) +{ + mmc_remove_card(host->card); + host->card = NULL; +} + +static int sd_uhs2_alive(struct mmc_host *host) +{ + return mmc_send_status(host->card, NULL); +} + +static void sd_uhs2_detect(struct mmc_host *host) +{ + int err; + + mmc_get_card(host->card, NULL); + err = _mmc_detect_card_removed(host); + mmc_put_card(host->card, NULL); + + if (err) { + sd_uhs2_remove(host); + + mmc_claim_host(host); + mmc_detach_bus(host); + sd_uhs2_power_off(host); + mmc_release_host(host); + } +} + +static int sd_uhs2_suspend(struct mmc_host *host) +{ + return 0; +} + +static int sd_uhs2_resume(struct mmc_host *host) +{ + return 0; +} + +static int sd_uhs2_runtime_suspend(struct mmc_host *host) +{ + return 0; +} + +static int sd_uhs2_runtime_resume(struct mmc_host *host) +{ + return 0; +} + +static int sd_uhs2_shutdown(struct mmc_host *host) +{ + return 0; +} + +static int sd_uhs2_hw_reset(struct mmc_host *host) +{ + return 0; +} + +static const struct mmc_bus_ops sd_uhs2_ops = { + .remove = sd_uhs2_remove, + .alive = sd_uhs2_alive, + .detect = sd_uhs2_detect, + .suspend = sd_uhs2_suspend, + .resume = sd_uhs2_resume, + .runtime_suspend = sd_uhs2_runtime_suspend, + .runtime_resume = sd_uhs2_runtime_resume, + .shutdown = sd_uhs2_shutdown, + .hw_reset = sd_uhs2_hw_reset, +}; + +static int sd_uhs2_attach(struct mmc_host *host) +{ + int err; + + err = sd_uhs2_power_up(host); + if (err) + goto err; + + err = sd_uhs2_phy_init(host); + if (err) + goto err; + + err = sd_uhs2_init_card(host); + if (err) + goto err; + + mmc_attach_bus(host, &sd_uhs2_ops); + + mmc_release_host(host); + + err = mmc_add_card(host->card); + if (err) + goto remove_card; + + mmc_claim_host(host); + return 0; + +remove_card: + mmc_remove_card(host->card); + host->card = NULL; + mmc_claim_host(host); + mmc_detach_bus(host); +err: + sd_uhs2_power_off(host); + return err; +} + +int mmc_attach_sd_uhs2(struct mmc_host *host) +{ + int i, err = 0; + + if (!(host->caps2 & MMC_CAP2_SD_UHS2)) + return -EOPNOTSUPP; + + /* Turn off the legacy SD interface before trying with UHS-II. */ + mmc_power_off(host); + + /* + * Start UHS-II initialization at 52MHz and possibly make a retry at + * 26MHz according to the spec. It's required that the host driver + * validates ios->clock, to set a rate within the correct range. + */ + for (i = 0; i < ARRAY_SIZE(sd_uhs2_freqs); i++) { + host->f_init = sd_uhs2_freqs[i]; + err = sd_uhs2_attach(host); + if (!err) + break; + } + + return err; +} diff --git a/include/linux/mmc/card.h b/include/linux/mmc/card.h index c726ea781255..4a42f31b7bb0 100644 --- a/include/linux/mmc/card.h +++ b/include/linux/mmc/card.h @@ -211,6 +211,11 @@ struct sd_ext_reg { #define SD_EXT_PERF_CMD_QUEUE (1<<4) }; +struct sd_uhs2_config { + u32 node_id; + /* TODO: Extend with more register configs. */ +}; + struct sdio_cccr { unsigned int sdio_vsn; unsigned int sd_vsn; @@ -317,6 +322,8 @@ struct mmc_card { struct sd_ext_reg ext_power; /* SD extension reg for PM */ struct sd_ext_reg ext_perf; /* SD extension reg for PERF */ + struct sd_uhs2_config uhs2_config; /* SD UHS-II config */ + unsigned int sdio_funcs; /* number of SDIO functions */ atomic_t sdio_funcs_probed; /* number of probed SDIO funcs */ struct sdio_cccr cccr; /* common card info */ diff --git a/include/linux/mmc/host.h b/include/linux/mmc/host.h index 8fdd3cf971a3..150d10d5e6f8 100644 --- a/include/linux/mmc/host.h +++ b/include/linux/mmc/host.h @@ -63,6 +63,7 @@ struct mmc_ios { #define MMC_TIMING_MMC_HS400 10 #define MMC_TIMING_SD_EXP 11 #define MMC_TIMING_SD_EXP_1_2V 12 +#define MMC_TIMING_SD_UHS2 13 unsigned char signal_voltage; /* signalling voltage (1.8V or 3.3V) */ @@ -91,6 +92,10 @@ struct mmc_clk_phase_map { struct mmc_clk_phase phase[MMC_NUM_CLK_PHASES]; }; +struct sd_uhs2_caps { + /* TODO: Add UHS-II capabilities for the host. */ +}; + struct mmc_host; enum mmc_err_stat { @@ -145,6 +150,17 @@ struct mmc_host_ops { */ void (*set_ios)(struct mmc_host *host, struct mmc_ios *ios); + /* + * The uhs2_set_ios callback is mandatory to implement for hosts that + * supports the SD UHS-II interface (MMC_CAP2_SD_UHS2), while the + * callback is unused for the other cases. Note that, the struct + * mmc_ios is being re-used for this as well. + * + * Expected return values for the uhs2_set_ios callback are a negative + * errno in case of a failure or zero for success. + */ + int (*uhs2_set_ios)(struct mmc_host *host, struct mmc_ios *ios); + /* * Return values for the get_ro callback should be: * 0 for a read/write card @@ -396,6 +412,7 @@ struct mmc_host { MMC_CAP2_HS200_1_2V_SDR) #define MMC_CAP2_SD_EXP (1 << 7) /* SD express via PCIe */ #define MMC_CAP2_SD_EXP_1_2V (1 << 8) /* SD express 1.2V */ +#define MMC_CAP2_SD_UHS2 (1 << 9) /* SD UHS-II support */ #define MMC_CAP2_CD_ACTIVE_HIGH (1 << 10) /* Card-detect signal active high */ #define MMC_CAP2_RO_ACTIVE_HIGH (1 << 11) /* Write-protect signal active high */ #define MMC_CAP2_NO_PRESCAN_POWERUP (1 << 14) /* Don't power up before scan */ @@ -422,6 +439,8 @@ struct mmc_host { #endif #define MMC_CAP2_ALT_GPT_TEGRA (1 << 28) /* Host with eMMC that has GPT entry at a non-standard location */ + struct sd_uhs2_caps uhs2_caps; /* Host UHS-II capabilities */ + int fixed_drv_type; /* fixed driver type for non-removable media */ mmc_pm_flag_t pm_caps; /* supported pm features */ From patchwork Tue Dec 13 09:00:26 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Victor Shih X-Patchwork-Id: 32696 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:8188:b0:89:790f:f786 with SMTP id m8csp3857263dye; Tue, 13 Dec 2022 01:03:18 -0800 (PST) X-Google-Smtp-Source: AA0mqf7VeN259MDsFnvDek4JuOtXszvyjvb2cz9TNE9xSpR6kU2q+uOYIpioGykbJa18i9kCOhGM X-Received: by 2002:a17:906:704d:b0:7b9:62ab:dc3f with SMTP id r13-20020a170906704d00b007b962abdc3fmr21883888ejj.1.1670922198555; Tue, 13 Dec 2022 01:03:18 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1670922198; cv=none; d=google.com; s=arc-20160816; b=FYMz3Zyvwhc0McIfuR5RwlgkG/WQ1dxtDQFtsV3gr1qEDlcS6Yq11Ujgufj6R2MTLX Hiyg+Y/OMaz5PvFm1L5nPG53OTYP+vWftswUASmXhCCMue7UZivVVdi7WcYymAH7LHZ5 PDe2T2NtbNh2W+a7hzKhUDS2LITwuPdSDGabb7c5yb2upAuWstTlftC25oTF/n8LBhgy AGqBngUhnMoFqrJrH3DZB5RTdMm6x5/u7iav4Mdebyhv0QCjeT/EEF7rI0zjo74LLpi7 WyKwHp0jmKEPwzF5hHMmhvc+n+ojO+BKfky0ooTGQRAtnsjG92qa6sE8uZk2aRsBEmJ5 v2Iw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=SzyMjrzMGxa/F0kJlX9UhW9e9/tXGWF/5HYdrk5JCcw=; b=n0LniF0ow6dPNWsfwe3xDMenGvmOnMv960RUM3JU/82M44o/5VEK9o6BIT915HnBhw uLWXcT5ULIOlxGQwYue8niB1BEjaev2JaxYHgC5Ei4J7+/bMA3aDIVumyGlgrn5/Vepn m5mOhLyplmVhrX3W6IxGCcU/0Og0M8RUUHakqs3ZawPKi+SOmakiXboZEobICBmdc7Hn gYY+lNz4PYz8aI6BPGhrj3NubBjQjImw1VpnSLBuMMasZmb73z6BLvVZkQKjqs675jAi aMfi7D6fpwr0BjoD8lxcYg9bG4mdk4xkfqSBWBYvXoeMWfxuzx3qiGU5YNvjtpu6aEtC suVw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20210112 header.b=c7qHtaWD; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id dn3-20020a17090794c300b007c1727f7c6fsi3940190ejc.261.2022.12.13.01.02.54; Tue, 13 Dec 2022 01:03:18 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@gmail.com header.s=20210112 header.b=c7qHtaWD; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234839AbiLMJB1 (ORCPT + 99 others); Tue, 13 Dec 2022 04:01:27 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35920 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234771AbiLMJBP (ORCPT ); Tue, 13 Dec 2022 04:01:15 -0500 Received: from mail-pg1-x52f.google.com (mail-pg1-x52f.google.com [IPv6:2607:f8b0:4864:20::52f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 224F0F02E; Tue, 13 Dec 2022 01:01:14 -0800 (PST) Received: by mail-pg1-x52f.google.com with SMTP id 36so3062681pgp.10; Tue, 13 Dec 2022 01:01:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=SzyMjrzMGxa/F0kJlX9UhW9e9/tXGWF/5HYdrk5JCcw=; b=c7qHtaWDFJSSeLTu+g4gi4qiNcnIB/XU+cmyxqm4GfzvF2eyPpAAapSKEvexdqdcOs EgEgUbIFlc2lo72F/hO9GJPq2JpUB4iM5D8mAfykXx7gXUui39d0dUyiZzI/J8EPbT2y pk/h0A847WDMlhoQq5T0l9PWUshxUKXZDg99kf+XrCfuMnnzriMOo48Rzya0GDYA0O/s I/2dE38d91Syf+wACem6cp/55zqDvU7OZi2tzOVdqwSHjI/v9hkssuumhIF3C8u9b055 SG4wGOKfHsDCa2YCxXF7daCKeRqaxj915/ZSUiRL7Ma4/EvcaDUVw+iA1IDgtuciZA2I WDMw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=SzyMjrzMGxa/F0kJlX9UhW9e9/tXGWF/5HYdrk5JCcw=; b=Qr43Qf4uMavfqYFi13la1oB4OgKo/puFy9mHvLMtImL5zO4W65U5SsDyluMKfzsAS7 6dN4awo9WMdwxYxcYgVZ8HIl4nm7CtxaZJi7mQBRGHUd+EbS4sFq4PxFAFSenvhUrONJ lsExWhlAfGT+gTjnq2uD4gwPjBu8jqF0jpTgmtBYXhbOlpDZoBOSTJklZuzptuT8JULW 1z4hVsotuZKTNkVTfCW9jL9o6d9F7/wckaE3WOPZysPALEQGhkoUU/GoU2TkfYik6u79 V7l9RsjN28beQOUv+ScOlRo4mmIt0zijQX2s35pXFA/U1vvnVnM0Ygf/NZ2owO6O2Kwi Q3yQ== X-Gm-Message-State: ANoB5pnpMpTJiQ4J7LMdO+bh3cMIFl36Qs9eVbJlP13sYyBC/P/6aC2N rW+VjH+9IvBCTl2LSjtRAaPrfbsSaldzAw== X-Received: by 2002:a62:52d5:0:b0:577:6525:fc98 with SMTP id g204-20020a6252d5000000b005776525fc98mr19540945pfb.3.1670922073697; Tue, 13 Dec 2022 01:01:13 -0800 (PST) Received: from localhost.localdomain (2001-b400-e2dc-5c03-264b-f684-a8c9-21ae.emome-ip6.hinet.net. [2001:b400:e2dc:5c03:264b:f684:a8c9:21ae]) by smtp.gmail.com with ESMTPSA id 81-20020a621954000000b0056b9ec7e2desm7141682pfz.125.2022.12.13.01.01.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 13 Dec 2022 01:01:12 -0800 (PST) From: Victor Shih X-Google-Original-From: Victor Shih To: ulf.hansson@linaro.org, adrian.hunter@intel.com Cc: linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, benchuanggli@gmail.com, HL.Liu@genesyslogic.com.tw, Greg.tu@genesyslogic.com.tw, takahiro.akashi@linaro.org, dlunev@chromium.org, Victor Shih Subject: [PATCH V6 03/24] mmc: core: Announce successful insertion of an SD UHS-II card Date: Tue, 13 Dec 2022 17:00:26 +0800 Message-Id: <20221213090047.3805-4-victor.shih@genesyslogic.com.tw> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221213090047.3805-1-victor.shih@genesyslogic.com.tw> References: <20221213090047.3805-1-victor.shih@genesyslogic.com.tw> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM, RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1752088915527218843?= X-GMAIL-MSGID: =?utf-8?q?1752088915527218843?= From: Ulf Hansson Updates in V4: - Make mmc_card_uhs2() take struct mmc_host* as in-param. Update in previous version: To inform the users about SD UHS-II cards, let's extend the print at card insertion with a "UHS-II" substring. Within this change, it seems reasonable to convert from using "ultra high speed" into "UHS-I speed", for the UHS-I type, as it should makes it more clear. Note that, the new print for UHS-II cards doesn't include the actual selected speed mode. Instead, this is going to be added from subsequent change. Signed-off-by: Ulf Hansson --- drivers/mmc/core/bus.c | 4 +++- drivers/mmc/core/host.h | 4 ++++ 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/core/bus.c b/drivers/mmc/core/bus.c index bbbbdbca5366..c8d51fc7d5bb 100644 --- a/drivers/mmc/core/bus.c +++ b/drivers/mmc/core/bus.c @@ -341,7 +341,9 @@ int mmc_add_card(struct mmc_card *card) if (mmc_card_hs(card)) speed_mode = "high speed "; else if (mmc_card_uhs(card)) - speed_mode = "ultra high speed "; + speed_mode = "UHS-I speed "; + else if (mmc_card_uhs2(card->host)) + speed_mode = "UHS-II speed "; else if (mmc_card_ddr52(card)) speed_mode = "high speed DDR "; else if (mmc_card_hs200(card)) diff --git a/drivers/mmc/core/host.h b/drivers/mmc/core/host.h index 48c4952512a5..ba6a80e9b360 100644 --- a/drivers/mmc/core/host.h +++ b/drivers/mmc/core/host.h @@ -89,5 +89,9 @@ static inline bool mmc_card_sd_express(struct mmc_host *host) host->ios.timing == MMC_TIMING_SD_EXP_1_2V; } +static inline bool mmc_card_uhs2(struct mmc_host *host) +{ + return host->ios.timing == MMC_TIMING_SD_UHS2; +} #endif From patchwork Tue Dec 13 09:00:27 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Victor Shih X-Patchwork-Id: 32710 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:8188:b0:89:790f:f786 with SMTP id m8csp3858158dye; Tue, 13 Dec 2022 01:04:46 -0800 (PST) X-Google-Smtp-Source: AA0mqf738SILzzjSPwOIJSt2Ck9/pcFb9xqHneeYZElMWPdhOckYXFWdHNXuYCAPhZa111zUzTLW X-Received: by 2002:a17:902:9696:b0:189:cf92:6f5c with SMTP id n22-20020a170902969600b00189cf926f5cmr19711744plp.52.1670922286726; Tue, 13 Dec 2022 01:04:46 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1670922286; cv=none; d=google.com; s=arc-20160816; b=atsM3WhWpKzR/aS0lfMLyAXEXi4tk+lm5NomCbGf/t65BnbwjxRHEFdiBNInmPEd5g //vr8bLmZuhDVLKE1GlRWhql461ag+r/fJ0LLQJnp4f7J2mBDmhYm21V+kCA0NJBcCRR EGTMEdntQo5/Svkw0Pz2SiHtmPZlMT9onX151azIzXeeZyveT+MtC6ggLYDmq1srXH8q B7VfenLsH01en2B79XUqUCEsVoLIJm+7kiW4ExT2S/0T4SjGRG1jI1g/ibfTIn/BE+Am UPZyKf64WuqEBPkWN0EYHbN1e2ewOmiOju1IitlCm79HBkvbriA+YR8xa2G62Tl4X5Zk BOrA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=e/VYYTH35eMukzyNpI36t8nzdr9tycZ4oeZLcYIOrT8=; b=mGVf4FNoWulTyC34m1kTBIbK8OADA6faZ12lNE5jhFpN/YgYkj46i5L+4SOG4UAjms s78dygEd8iTfaACCzQP85A001VY20Di4rleWeqawvfGSLqAY1E8gM4wQyQnd+hakvIRS AHOry0yVUU9rJvBKnhl9aspwVQwisJ8qZzjm9molj7Zaj3JWQ0hXtMB47DKEc6BXuuNZ XWX3KxnII6nrEBLOxfdNDFU56tyk+/PGZAq1ypMUubMXV5gGXKkzl1FDzNNNNxDzF2+7 gPmN1In1jaiSJJ6iEtlmZfR8BFIX3TR+PJr6B9hx+Sp4SDhYGl0ajSFxrvz+j5xrNrQx BsEQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20210112 header.b=UQXvkCRy; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id y188-20020a6364c5000000b004779a46d07csi12046689pgb.183.2022.12.13.01.04.34; Tue, 13 Dec 2022 01:04:46 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@gmail.com header.s=20210112 header.b=UQXvkCRy; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234861AbiLMJBh (ORCPT + 99 others); Tue, 13 Dec 2022 04:01:37 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36076 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234803AbiLMJBY (ORCPT ); Tue, 13 Dec 2022 04:01:24 -0500 Received: from mail-pg1-x52e.google.com (mail-pg1-x52e.google.com [IPv6:2607:f8b0:4864:20::52e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 720ECF01E; Tue, 13 Dec 2022 01:01:17 -0800 (PST) Received: by mail-pg1-x52e.google.com with SMTP id 82so10019096pgc.0; Tue, 13 Dec 2022 01:01:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=e/VYYTH35eMukzyNpI36t8nzdr9tycZ4oeZLcYIOrT8=; b=UQXvkCRykSmhhm2/6D0LbCPixYNY2zizGMDSgkX71YKlPOefvpf5wphXCXpwnqfJqe KgMI0l/cWlYJJmhaZjGMZgz9zzYsR1DP7HLNKxRgcDBI3e3Hrz8vR1e0ezMU4Uaaig+O UVGM+4l12hwO7xGrkTkF0Lhh66FC8sjH2XRxRVnuq2V/NFvsmDWv+ApATRGLRbMoXzoY HyYvbsDx/JK7pUWAHdy5Xy56mppQtRIf3Kok5/Ah1w1qgMd+Vc0bBpvDzfEBttFuW5+K COnTwp0wxcIgwldQEGnO1U9POjbJY3XOHLFl1kZXB8qMt2Ei44sKbwjO0GRdxTKDVtNk wnMQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=e/VYYTH35eMukzyNpI36t8nzdr9tycZ4oeZLcYIOrT8=; b=F5uXb+AqDLxv+ItdOfP0B06AMFR0Nu2C8rc/+Z8Jv6GYiP1p6LtFlwKJC1QkOQmUtw j1sEwCLBPH3vdlVjgOtnP4IDXsSbW3G3+M3yJmVPCZwjNEinp2L0QxfNKClpwS67NA64 7AEEYlgNWVRAx6Ea6gcD057s0pY3hIs+seA5rcd09axlPCEBAelQ+dB0fEht68UMyjDl mo43ojKWprNjoQ+QypzruAG93cbmdVEJbxfJl/0FgiaOs2E+PaklNHv+84DfkYftxbNK Z1Lqchezv+Td6xKN1fBlZBIh1uYCxAkNWD4nNgmKxFgZnA68bPBU6ROs487S/VkRfYMG etyg== X-Gm-Message-State: ANoB5pmda1JQqRRALHXAktyi33q9Ew///5hCrt1A+4h44/iQow/l7oMH 1B+BgGxFz/8E/bO5mOwqOns= X-Received: by 2002:a62:4ece:0:b0:577:3126:704d with SMTP id c197-20020a624ece000000b005773126704dmr20021853pfb.17.1670922076920; Tue, 13 Dec 2022 01:01:16 -0800 (PST) Received: from localhost.localdomain (2001-b400-e2dc-5c03-264b-f684-a8c9-21ae.emome-ip6.hinet.net. [2001:b400:e2dc:5c03:264b:f684:a8c9:21ae]) by smtp.gmail.com with ESMTPSA id 81-20020a621954000000b0056b9ec7e2desm7141682pfz.125.2022.12.13.01.01.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 13 Dec 2022 01:01:15 -0800 (PST) From: Victor Shih X-Google-Original-From: Victor Shih To: ulf.hansson@linaro.org, adrian.hunter@intel.com Cc: linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, benchuanggli@gmail.com, HL.Liu@genesyslogic.com.tw, Greg.tu@genesyslogic.com.tw, takahiro.akashi@linaro.org, dlunev@chromium.org, Victor Shih Subject: [PATCH V6 04/24] mmc: core: Extend support for mmc regulators with a vqmmc2 Date: Tue, 13 Dec 2022 17:00:27 +0800 Message-Id: <20221213090047.3805-5-victor.shih@genesyslogic.com.tw> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221213090047.3805-1-victor.shih@genesyslogic.com.tw> References: <20221213090047.3805-1-victor.shih@genesyslogic.com.tw> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM, RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1752089008026624748?= X-GMAIL-MSGID: =?utf-8?q?1752089008026624748?= From: Ulf Hansson Updates in V4: - Moved the voltage defines into this patch. Update in previous version: To allow an additional external regulator to be controlled by an mmc host driver, let's add support for a vqmmc2 regulator to the mmc core. For an SD UHS-II interface the vqmmc2 regulator may correspond to the so called vdd2 supply, as described by the SD spec. Initially, only 1.8V is needed, hence limit the new helper function, mmc_regulator_set_vqmmc2() to this too. Note that, to allow for flexibility mmc host drivers need to manage the enable/disable of the vqmmc2 regulator themselves, while the regulator is looked up through the common mmc_regulator_get_supply(). Signed-off-by: Ulf Hansson --- drivers/mmc/core/regulator.c | 34 ++++++++++++++++++++++++++++++++++ include/linux/mmc/host.h | 11 +++++++++++ 2 files changed, 45 insertions(+) diff --git a/drivers/mmc/core/regulator.c b/drivers/mmc/core/regulator.c index 609201a467ef..3c189682797c 100644 --- a/drivers/mmc/core/regulator.c +++ b/drivers/mmc/core/regulator.c @@ -223,6 +223,33 @@ int mmc_regulator_set_vqmmc(struct mmc_host *mmc, struct mmc_ios *ios) } EXPORT_SYMBOL_GPL(mmc_regulator_set_vqmmc); +/** + * mmc_regulator_set_vqmmc2 - Set vqmmc2 as per the ios->vqmmc2_voltage + * @mmc: The mmc host to regulate + * @ios: The io bus settings + * + * Sets a new voltage level for the vqmmc2 regulator, which may correspond to + * the vdd2 regulator for an SD UHS-II interface. This function is expected to + * be called by mmc host drivers. + * + * Returns a negative error code on failure, zero if the voltage level was + * changed successfully or a positive value if the level didn't need to change. + */ +int mmc_regulator_set_vqmmc2(struct mmc_host *mmc, struct mmc_ios *ios) +{ + if (IS_ERR(mmc->supply.vqmmc2)) + return -EINVAL; + + switch (ios->vqmmc2_voltage) { + case MMC_VQMMC2_VOLTAGE_180: + return mmc_regulator_set_voltage_if_supported( + mmc->supply.vqmmc2, 1700000, 1800000, 1950000); + default: + return -EINVAL; + } +} +EXPORT_SYMBOL_GPL(mmc_regulator_set_vqmmc2); + #else static inline int mmc_regulator_get_ocrmask(struct regulator *supply) @@ -249,6 +276,7 @@ int mmc_regulator_get_supply(struct mmc_host *mmc) mmc->supply.vmmc = devm_regulator_get_optional(dev, "vmmc"); mmc->supply.vqmmc = devm_regulator_get_optional(dev, "vqmmc"); + mmc->supply.vqmmc2 = devm_regulator_get_optional(dev, "vqmmc2"); if (IS_ERR(mmc->supply.vmmc)) { if (PTR_ERR(mmc->supply.vmmc) == -EPROBE_DEFER) @@ -268,6 +296,12 @@ int mmc_regulator_get_supply(struct mmc_host *mmc) dev_dbg(dev, "No vqmmc regulator found\n"); } + if (IS_ERR(mmc->supply.vqmmc2)) { + if (PTR_ERR(mmc->supply.vqmmc2) == -EPROBE_DEFER) + return -EPROBE_DEFER; + dev_dbg(dev, "No vqmmc2 regulator found\n"); + } + return 0; } EXPORT_SYMBOL_GPL(mmc_regulator_get_supply); diff --git a/include/linux/mmc/host.h b/include/linux/mmc/host.h index 150d10d5e6f8..895bcf7f80b7 100644 --- a/include/linux/mmc/host.h +++ b/include/linux/mmc/host.h @@ -71,6 +71,9 @@ struct mmc_ios { #define MMC_SIGNAL_VOLTAGE_180 1 #define MMC_SIGNAL_VOLTAGE_120 2 + unsigned char vqmmc2_voltage; +#define MMC_VQMMC2_VOLTAGE_180 0 + unsigned char drv_type; /* driver type (A, B, C, D) */ #define MMC_SET_DRIVER_TYPE_B 0 @@ -321,6 +324,7 @@ struct mmc_pwrseq; struct mmc_supply { struct regulator *vmmc; /* Card power supply */ struct regulator *vqmmc; /* Optional Vccq supply */ + struct regulator *vqmmc2; /* Optional supply for phy */ }; struct mmc_ctx { @@ -600,6 +604,7 @@ int mmc_regulator_set_ocr(struct mmc_host *mmc, struct regulator *supply, unsigned short vdd_bit); int mmc_regulator_set_vqmmc(struct mmc_host *mmc, struct mmc_ios *ios); +int mmc_regulator_set_vqmmc2(struct mmc_host *mmc, struct mmc_ios *ios); #else static inline int mmc_regulator_set_ocr(struct mmc_host *mmc, struct regulator *supply, @@ -613,6 +618,12 @@ static inline int mmc_regulator_set_vqmmc(struct mmc_host *mmc, { return -EINVAL; } + +static inline int mmc_regulator_set_vqmmc2(struct mmc_host *mmc, + struct mmc_ios *ios) +{ + return -EINVAL; +} #endif int mmc_regulator_get_supply(struct mmc_host *mmc); From patchwork Tue Dec 13 09:00:28 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Victor Shih X-Patchwork-Id: 32698 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:8188:b0:89:790f:f786 with SMTP id m8csp3857486dye; Tue, 13 Dec 2022 01:03:35 -0800 (PST) X-Google-Smtp-Source: AA0mqf6Z0WYPlYcGzafhrHaiqQo/cHc8ljo5OoB/TKJGbDvcpy7tbVFhVQtLrHr4zPpQTbgQKI11 X-Received: by 2002:a17:907:2dab:b0:7c0:eba9:cf0f with SMTP id gt43-20020a1709072dab00b007c0eba9cf0fmr22384573ejc.30.1670922215383; Tue, 13 Dec 2022 01:03:35 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1670922215; cv=none; d=google.com; s=arc-20160816; b=E1AsphAuanTOrfusilP4lWezjugxtqC+kI2ek91XwHy1BfbUczx8pgyHF3aUra+nDp thwik5JmSG6SR+wkOPG9Ied3AqRXvSMKJrs6yOyzgni7GSU3xbOz8WtPL4UIRAsRD0DT yFfKD8ZR4JC/T8Nmy3CoqULgwm0Ip9BXeXMgsNAa6lDh1NRqAlrukSfZAuM9nKxUNEnJ cbmajpVBAMHKLXiP01PgMZnSXLQz6UsFleELP0zmNgjmI3MdlKA7H7EuZB3oTh+01eZG LP4NjRIkIk1/wxXK9SEdRaTbr4aNzRL4n2RWxPpJUYbI4YGSoKw2M++1FWf1OzwKcZ1N 5rSQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=wgVVTOfj/uMlHDB7VZ60DFJ+2dh2bQuFiHjxAdjEHqQ=; b=bu9iP3u6m9jO7ociVt9hW22O5pjJdzMKcUBMlDYQYqriJul5GjV2D88kjUg0MTH0tO YnOBAmI8lnbJ0r2hlBy89aATQiDmiIh5Gu3ShdpgM9wuDkrrTf87k7DRzWfSBp7AiZdr o+p0OHh5wYeu8tspV82EV3fzlxWBYtDV0GGMX/fLI6lpn3BFxjmEGHqBZ/ev3J+bMITH RnxslFIdUm+tgNDaQN1FT393rqTEH7evoyg6eQHVVwMKgl3avzAD636ypDyXFW3ExiEN +uDhNZpVs4VhReCV/5dvPQuorlKTNQkVMnqsqG10L7JnF+BJh+26MGsBlJwP4Hk+oKfg ot2A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20210112 header.b=JHyPZaVo; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id g20-20020a170906595400b0078d4cf8de04si6276327ejr.380.2022.12.13.01.03.10; Tue, 13 Dec 2022 01:03:35 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@gmail.com header.s=20210112 header.b=JHyPZaVo; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234793AbiLMJB4 (ORCPT + 99 others); Tue, 13 Dec 2022 04:01:56 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36124 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234737AbiLMJB1 (ORCPT ); Tue, 13 Dec 2022 04:01:27 -0500 Received: from mail-pj1-x102d.google.com (mail-pj1-x102d.google.com [IPv6:2607:f8b0:4864:20::102d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D3069E0B2; Tue, 13 Dec 2022 01:01:22 -0800 (PST) Received: by mail-pj1-x102d.google.com with SMTP id u15-20020a17090a3fcf00b002191825cf02so2856527pjm.2; Tue, 13 Dec 2022 01:01:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=wgVVTOfj/uMlHDB7VZ60DFJ+2dh2bQuFiHjxAdjEHqQ=; b=JHyPZaVoxt7VxxmNih0KgeavO8YAKTptVYfZzG5Z4ibEeaa96TpVdz1gm8LKCEp01Q zrVH+NqpiU4zNc71wwWDSt42tcaur1xbpyyg3esAHe0SkOXEMrZaTNYUKDwRuqnCFwOC /MuAgPS4FywaHrYqQ3Aa/EtxZXVO8gT0Q99ZeMdlvGRIlrLW+il92QVl6W812gVKErLs oM1XvhS89Fr2rRFqrBJNjfbhOLcnPgwPi24DNkK2dx6vwNu3HioiAmGc0o0vPpVm10mW NDqhH270zmFJtfIFxkbjE9OclySyL066rlQj8iGS1hUsv8nicBTMRs5MaS2er5XlByGw PNJQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=wgVVTOfj/uMlHDB7VZ60DFJ+2dh2bQuFiHjxAdjEHqQ=; b=zFTOLJ0if9+qJoBXzQKWLenul6zeLtEZq9szfc9mmgaCQSV/08qQLms+oe/LE1Mb0F lB51P6G7b4217fgzy/UFWsFnn/RWVXRUEsvImOxnXCGzZdE/Ibh5szm3wA+dXfu0bwUp weu1/U99KF6JUf266RLE05Z00tzvs0qj1bx0Fhkia73rmtjJNYB9S7Gvw+aVDnNytM4X MTKrXLfvP2AGiT5ipGEk+HXHACFXWpBhpiUv+iVv9SHbTzaL4ubNgv+td71EuTZcdsNp mw1RXBzGsT6kbwg+HWZqdPScNMKvk7SE1/+mhopotflfGzyNc6TPuARLOtfqx8v7LciB tpFw== X-Gm-Message-State: ANoB5pla77UexWTII+zxE2UxRsixDedsxiOXhTxfib+cfn+Br11FODXw GEvNAasZa6f22oCG/PAKZ8Q= X-Received: by 2002:a05:6a21:6d9c:b0:aa:4010:2789 with SMTP id wl28-20020a056a216d9c00b000aa40102789mr31765363pzb.53.1670922081398; Tue, 13 Dec 2022 01:01:21 -0800 (PST) Received: from localhost.localdomain (2001-b400-e2dc-5c03-264b-f684-a8c9-21ae.emome-ip6.hinet.net. [2001:b400:e2dc:5c03:264b:f684:a8c9:21ae]) by smtp.gmail.com with ESMTPSA id 81-20020a621954000000b0056b9ec7e2desm7141682pfz.125.2022.12.13.01.01.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 13 Dec 2022 01:01:19 -0800 (PST) From: Victor Shih X-Google-Original-From: Victor Shih To: ulf.hansson@linaro.org, adrian.hunter@intel.com Cc: linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, benchuanggli@gmail.com, HL.Liu@genesyslogic.com.tw, Greg.tu@genesyslogic.com.tw, takahiro.akashi@linaro.org, dlunev@chromium.org, Victor Shih , Jason Lai Subject: [PATCH V6 05/24] mmc: core: Add definitions for SD UHS-II cards Date: Tue, 13 Dec 2022 17:00:28 +0800 Message-Id: <20221213090047.3805-6-victor.shih@genesyslogic.com.tw> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221213090047.3805-1-victor.shih@genesyslogic.com.tw> References: <20221213090047.3805-1-victor.shih@genesyslogic.com.tw> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM, RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1752088932450696387?= X-GMAIL-MSGID: =?utf-8?q?1752088932450696387?= Add UHS-II specific data structures for commands and defines for registers, as described in Part 1 UHS-II Addendum Version 1.01. UHS-II related definitions are listed below: 1. UHS-II card capability: sd_uhs2_caps{} 2. UHS-II configuration: sd_uhs2_config{} 3. UHS-II Command structure: uhs2_command{} 4. UHS-II register I/O address and register field definitions: sd_uhs2.h Signed-off-by: Ulf Hansson Signed-off-by: Jason Lai Signed-off-by: Victor Shih --- include/linux/mmc/card.h | 42 +++++- include/linux/mmc/core.h | 13 ++ include/linux/mmc/host.h | 63 ++++++++- include/linux/mmc/sd_uhs2.h | 263 ++++++++++++++++++++++++++++++++++++ 4 files changed, 379 insertions(+), 2 deletions(-) create mode 100644 include/linux/mmc/sd_uhs2.h diff --git a/include/linux/mmc/card.h b/include/linux/mmc/card.h index 4a42f31b7bb0..d638a2c689cf 100644 --- a/include/linux/mmc/card.h +++ b/include/linux/mmc/card.h @@ -190,6 +190,13 @@ struct sd_switch_caps { #define SD_MAX_CURRENT_400 (1 << SD_SET_CURRENT_LIMIT_400) #define SD_MAX_CURRENT_600 (1 << SD_SET_CURRENT_LIMIT_600) #define SD_MAX_CURRENT_800 (1 << SD_SET_CURRENT_LIMIT_800) + unsigned int sd4_curr_limit; +#define SD4_SET_POWER_LIMIT_0_72W 0 +#define SD4_SET_POWER_LIMIT_1_44W 1 +#define SD4_SET_POWER_LIMIT_2_16W 2 +#define SD4_SET_POWER_LIMIT_2_88W 3 +#define SD4_SET_POWER_LIMIT_1_80W 4 +#define SD4_SET_POWER_NO_CHANGE (-1) }; struct sd_ext_reg { @@ -213,7 +220,35 @@ struct sd_ext_reg { struct sd_uhs2_config { u32 node_id; - /* TODO: Extend with more register configs. */ + + u32 dap; + u32 gap; + u32 n_fcu; + u32 maxblk_len; + u8 n_lanes; + u8 dadr_len; + u8 app_type; + u8 phy_minor_rev; + u8 phy_major_rev; + u8 can_hibernate; + u8 n_lss_sync; + u8 n_lss_dir; + u8 link_minor_rev; + u8 link_major_rev; + u8 dev_type; + u8 n_data_gap; + + u32 n_fcu_set; + u32 maxblk_len_set; + u8 n_lanes_set; + u8 speed_range_set; + u8 n_lss_sync_set; + u8 n_lss_dir_set; + u8 n_data_gap_set; + u8 pwrctrl_mode_set; + u8 max_retry_set; + + u8 cfg_complete; }; struct sdio_cccr { @@ -323,6 +358,9 @@ struct mmc_card { struct sd_ext_reg ext_perf; /* SD extension reg for PERF */ struct sd_uhs2_config uhs2_config; /* SD UHS-II config */ + u8 uhs2_state; /* SD UHS-II states */ +#define MMC_UHS2_INITIALIZED BIT(1) +#define MMC_UHS2_SPEED_B BIT(2) unsigned int sdio_funcs; /* number of SDIO functions */ atomic_t sdio_funcs_probed; /* number of probed SDIO funcs */ @@ -364,4 +402,6 @@ bool mmc_card_is_blockaddr(struct mmc_card *card); #define mmc_card_sdio(c) ((c)->type == MMC_TYPE_SDIO) #define mmc_card_sd_combo(c) ((c)->type == MMC_TYPE_SD_COMBO) +#define mmc_card_can_poweroff_notify(c) ((c)->ext_power.feature_support & SD_EXT_POWER_OFF_NOTIFY) + #endif /* LINUX_MMC_CARD_H */ diff --git a/include/linux/mmc/core.h b/include/linux/mmc/core.h index 6efec0b9820c..2a0581d87706 100644 --- a/include/linux/mmc/core.h +++ b/include/linux/mmc/core.h @@ -23,6 +23,14 @@ enum mmc_blk_status { MMC_BLK_NEW_REQUEST, }; +struct uhs2_command { + u16 header; + u16 arg; + __be32 *payload; + u32 payload_len; + u32 packet_len; +}; + struct mmc_command { u32 opcode; u32 arg; @@ -109,6 +117,11 @@ struct mmc_command { unsigned int busy_timeout; /* busy detect timeout in ms */ struct mmc_data *data; /* data segment associated with cmd */ struct mmc_request *mrq; /* associated request */ + + struct uhs2_command *uhs2_cmd; /* UHS2 command */ + u8 *uhs2_resp; /* UHS2 native cmd resp */ + u8 uhs2_resp_len; /* UHS2 native cmd resp len */ + u8 uhs2_tmode0_flag; /* UHS2 transfer mode flag */ }; struct mmc_data { diff --git a/include/linux/mmc/host.h b/include/linux/mmc/host.h index 895bcf7f80b7..ca1026ac85de 100644 --- a/include/linux/mmc/host.h +++ b/include/linux/mmc/host.h @@ -16,6 +16,7 @@ #include #include #include +#include struct mmc_ios { unsigned int clock; /* clock rate */ @@ -96,7 +97,48 @@ struct mmc_clk_phase_map { }; struct sd_uhs2_caps { - /* TODO: Add UHS-II capabilities for the host. */ + u32 dap; + u32 gap; + u32 group_desc; + u32 maxblk_len; + u32 n_fcu; + u8 n_lanes; + u8 addr64; + u8 card_type; + u8 phy_rev; + u8 speed_range; + u8 can_hibernate; + u8 n_lss_sync; + u8 n_lss_dir; + u8 link_rev; + u8 host_type; + u8 n_data_gap; + + u32 maxblk_len_set; + u32 n_fcu_set; + u8 n_lanes_set; + u8 n_lss_sync_set; + u8 n_lss_dir_set; + u8 n_data_gap_set; + u8 max_retry_set; +}; + +struct sd_uhs2_ios { + bool is_2L_HD_mode; + bool is_APP_CMD; + unsigned int power_delay_ms; /* waiting for stable power */ +}; + +enum sd_uhs2_operation { + UHS2_PHY_INIT = 0, + UHS2_SET_CONFIG, + UHS2_ENABLE_INT, + UHS2_DISABLE_INT, + UHS2_ENABLE_CLK, + UHS2_DISABLE_CLK, + UHS2_CHECK_DORMANT, + UHS2_SET_SPEED_B, + UHS2_POST_ATTACH_SD, }; struct mmc_host; @@ -231,6 +273,14 @@ struct mmc_host_ops { /* Initialize an SD express card, mandatory for MMC_CAP2_SD_EXP. */ int (*init_sd_express)(struct mmc_host *host, struct mmc_ios *ios); + + /* + * The uhs2_control callback is used to execute SD UHS-II specific + * operations. It's mandatory to implement for hosts that supports the + * SD UHS-II interface (MMC_CAP2_SD_UHS2). Expected return values are a + * negative errno in case of a failure or zero for success. + */ + int (*uhs2_control)(struct mmc_host *host, enum sd_uhs2_operation op); }; struct mmc_cqe_ops { @@ -323,6 +373,7 @@ struct mmc_pwrseq; struct mmc_supply { struct regulator *vmmc; /* Card power supply */ + struct regulator *vmmc2; /* UHS2 VDD2 power supply */ struct regulator *vqmmc; /* Optional Vccq supply */ struct regulator *vqmmc2; /* Optional supply for phy */ }; @@ -344,10 +395,12 @@ struct mmc_host { u32 ocr_avail_sdio; /* SDIO-specific OCR */ u32 ocr_avail_sd; /* SD-specific OCR */ u32 ocr_avail_mmc; /* MMC-specific OCR */ + u32 ocr_avail_uhs2; /* UHS2-specific OCR */ struct wakeup_source *ws; /* Enable consume of uevents */ u32 max_current_330; u32 max_current_300; u32 max_current_180; + u32 max_current_180_vdd2; /* UHS2 vdd2 max curt. */ #define MMC_VDD_165_195 0x00000080 /* VDD voltage 1.65 - 1.95 */ #define MMC_VDD_20_21 0x00000100 /* VDD voltage 2.0 ~ 2.1 */ @@ -366,6 +419,7 @@ struct mmc_host { #define MMC_VDD_33_34 0x00200000 /* VDD voltage 3.3 ~ 3.4 */ #define MMC_VDD_34_35 0x00400000 /* VDD voltage 3.4 ~ 3.5 */ #define MMC_VDD_35_36 0x00800000 /* VDD voltage 3.5 ~ 3.6 */ +#define MMC_VDD2_165_195 0x00000080 /* UHS2 VDD2 1.65 ~ 1.95 */ u32 caps; /* Host capabilities */ @@ -443,7 +497,11 @@ struct mmc_host { #endif #define MMC_CAP2_ALT_GPT_TEGRA (1 << 28) /* Host with eMMC that has GPT entry at a non-standard location */ + int flags; +#define MMC_UHS2_SUPPORT (1 << 0) + struct sd_uhs2_caps uhs2_caps; /* Host UHS-II capabilities */ + struct sd_uhs2_ios uhs2_ios; /* Host UHS-II capabilities */ int fixed_drv_type; /* fixed driver type for non-removable media */ @@ -695,4 +753,7 @@ int mmc_send_tuning(struct mmc_host *host, u32 opcode, int *cmd_error); int mmc_send_abort_tuning(struct mmc_host *host, u32 opcode); int mmc_get_ext_csd(struct mmc_card *card, u8 **new_ext_csd); +#define mmc_uhs2_2L_HD_mode(h) ((h)->uhs2_ios.is_2L_HD_mode) +#define mmc_uhs2_APP_cmd(h) ((h)->uhs2_ios.is_APP_CMD) + #endif /* LINUX_MMC_HOST_H */ diff --git a/include/linux/mmc/sd_uhs2.h b/include/linux/mmc/sd_uhs2.h new file mode 100644 index 000000000000..8fcf702cf4a5 --- /dev/null +++ b/include/linux/mmc/sd_uhs2.h @@ -0,0 +1,263 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Header file for UHS-II packets, Host Controller registers and I/O + * accessors. + * + * Copyright (C) 2014 Intel Corp, All Rights Reserved. + */ +#ifndef LINUX_MMC_UHS2_H +#define LINUX_MMC_UHS2_H + +/* LINK Layer definition */ +/* + * UHS2 Header: + * Refer to UHS-II Addendum Version 1.02 Figure 5-2, the format of CCMD Header is described below: + * bit [3:0] : DID(Destination ID = Node ID of UHS2 card) + * bit [6:4] : TYP(Packet Type) + * 000b: CCMD(Control command packet) + * 001b: DCMD(Data command packet) + * 010b: RES(Response packet) + * 011b: DATA(Data payload packet) + * 111b: MSG(Message packet) + * Others: Reserved + * bit [7] : NP(Native Packet) + * bit [10:8] : TID(Transaction ID) + * bit [11] : Reserved + * bit [15:12]: SID(Source ID 0: Node ID of Host) + * + * Broadcast CCMD issued by Host is represented as DID=SID=0. + */ +/* + * UHS2 Argument: + * Refer to UHS-II Addendum Version 1.02 Figure 6-5, the format of CCMD Argument is described below: + * bit [3:0] : MSB of IOADR + * bit [5:4] : PLEN(Payload Length) + * 00b: 0 byte + * 01b: 4 bytes + * 10b: 8 bytes + * 11b: 16 bytes + * bit [6] : Reserved + * bit [7] : R/W(Read/Write) + * 0: Control read command + * 1: Control write command + * bit [15:8] : LSB of IOADR + * + * I/O Address specifies the address of register in UHS-II I/O space accessed by CCMD. + * The unit of I/O Address is 4 Bytes. It is transmitted in MSB first, LSB last. + */ +#define UHS2_NATIVE_PACKET_POS 7 +#define UHS2_NATIVE_PACKET (1 << UHS2_NATIVE_PACKET_POS) + +#define UHS2_PACKET_TYPE_POS 4 +#define UHS2_PACKET_TYPE_CCMD (0 << UHS2_PACKET_TYPE_POS) +#define UHS2_PACKET_TYPE_DCMD (1 << UHS2_PACKET_TYPE_POS) +#define UHS2_PACKET_TYPE_RES (2 << UHS2_PACKET_TYPE_POS) +#define UHS2_PACKET_TYPE_DATA (3 << UHS2_PACKET_TYPE_POS) +#define UHS2_PACKET_TYPE_MSG (7 << UHS2_PACKET_TYPE_POS) + +#define UHS2_DEST_ID_MASK 0x0F +#define UHS2_DEST_ID 0x1 + +#define UHS2_SRC_ID_POS 12 +#define UHS2_SRC_ID_MASK 0xF000 + +#define UHS2_TRANS_ID_POS 8 +#define UHS2_TRANS_ID_MASK 0x0700 + +/* UHS2 MSG */ +#define UHS2_MSG_CTG_POS 5 +#define UHS2_MSG_CTG_LMSG 0x00 +#define UHS2_MSG_CTG_INT 0x60 +#define UHS2_MSG_CTG_AMSG 0x80 + +#define UHS2_MSG_CTG_FCREQ 0x00 +#define UHS2_MSG_CTG_FCRDY 0x01 +#define UHS2_MSG_CTG_STAT 0x02 + +#define UHS2_MSG_CODE_POS 8 +#define UHS2_MSG_CODE_FC_UNRECOVER_ERR 0x8 +#define UHS2_MSG_CODE_STAT_UNRECOVER_ERR 0x8 +#define UHS2_MSG_CODE_STAT_RECOVER_ERR 0x1 + +/* TRANS Layer definition */ + +/* Native packets*/ +#define UHS2_NATIVE_CMD_RW_POS 7 +#define UHS2_NATIVE_CMD_WRITE (1 << UHS2_NATIVE_CMD_RW_POS) +#define UHS2_NATIVE_CMD_READ (0 << UHS2_NATIVE_CMD_RW_POS) + +#define UHS2_NATIVE_CMD_PLEN_POS 4 +#define UHS2_NATIVE_CMD_PLEN_4B (1 << UHS2_NATIVE_CMD_PLEN_POS) +#define UHS2_NATIVE_CMD_PLEN_8B (2 << UHS2_NATIVE_CMD_PLEN_POS) +#define UHS2_NATIVE_CMD_PLEN_16B (3 << UHS2_NATIVE_CMD_PLEN_POS) + +#define UHS2_NATIVE_CCMD_GET_MIOADR_MASK 0xF00 +#define UHS2_NATIVE_CCMD_MIOADR_MASK 0x0F + +#define UHS2_NATIVE_CCMD_LIOADR_POS 8 +#define UHS2_NATIVE_CCMD_GET_LIOADR_MASK 0x0FF + +#define UHS2_CCMD_DEV_INIT_COMPLETE_FLAG BIT(11) +#define UHS2_DEV_INIT_PAYLOAD_LEN 1 +#define UHS2_DEV_INIT_RESP_LEN 6 +#define UHS2_DEV_ENUM_PAYLOAD_LEN 1 +#define UHS2_DEV_ENUM_RESP_LEN 8 +#define UHS2_CFG_WRITE_PAYLOAD_LEN 2 +#define UHS2_CFG_WRITE_PHY_SET_RESP_LEN 4 +#define UHS2_CFG_WRITE_GENERIC_SET_RESP_LEN 5 +#define UHS2_GO_DORMANT_PAYLOAD_LEN 1 + +/* + * UHS2 Argument: + * Refer to UHS-II Addendum Version 1.02 Figure 6-8, the format of DCMD Argument is described below: + * bit [3:0] : Reserved + * bit [6:3] : TMODE(Transfer Mode) + * bit 3: DAM(Data Access Mode) + * bit 4: TLUM(TLEN Unit Mode) + * bit 5: LM(Length Mode) + * bit 6: DM(Duplex Mode) + * bit [7] : R/W(Read/Write) + * 0: Control read command + * 1: Control write command + * bit [15:8] : Reserved + * + * I/O Address specifies the address of register in UHS-II I/O space accessed by CCMD. + * The unit of I/O Address is 4 Bytes. It is transmitted in MSB first, LSB last. + */ +#define UHS2_DCMD_DM_POS 6 +#define UHS2_DCMD_2L_HD_MODE (1 << UHS2_DCMD_DM_POS) +#define UHS2_DCMD_LM_POS 5 +#define UHS2_DCMD_LM_TLEN_EXIST (1 << UHS2_DCMD_LM_POS) +#define UHS2_DCMD_TLUM_POS 4 +#define UHS2_DCMD_TLUM_BYTE_MODE (1 << UHS2_DCMD_TLUM_POS) +#define UHS2_NATIVE_DCMD_DAM_POS 3 +#define UHS2_NATIVE_DCMD_DAM_IO (1 << UHS2_NATIVE_DCMD_DAM_POS) + +/* + * Per UHS2 spec, DCMD payload should be MSB first. There may be + * two types of data be assembled to MSB: + * 1. TLEN: Input block size for single read/write and number of blocks + * for multiple read/write to calculate TLEN as MSB first per spec. + * 2. SD command argument. + */ +static inline __be32 uhs2_dcmd_convert_msb(u32 input) +{ + u32 ret = 0; + + ret = ((input & 0xFF) << 24) | + (((input >> 8) & 0xFF) << 16) | + (((input >> 16) & 0xFF) << 8) | + ((input >> 24) & 0xFF); + return cpu_to_be32(ret); +} + +#define UHS2_RES_NACK_POS 7 +#define UHS2_RES_NACK_MASK (0x1 << UHS2_RES_NACK_POS) + +#define UHS2_RES_ECODE_POS 4 +#define UHS2_RES_ECODE_MASK 0x7 +#define UHS2_RES_ECODE_COND 1 +#define UHS2_RES_ECODE_ARG 2 +#define UHS2_RES_ECODE_GEN 3 + +/* IOADR of device registers */ +#define UHS2_IOADR_GENERIC_CAPS 0x00 +#define UHS2_IOADR_PHY_CAPS 0x02 +#define UHS2_IOADR_LINK_CAPS 0x04 +#define UHS2_IOADR_RSV_CAPS 0x06 +#define UHS2_IOADR_GENERIC_SETTINGS 0x08 +#define UHS2_IOADR_PHY_SETTINGS 0x0A +#define UHS2_IOADR_LINK_SETTINGS 0x0C +#define UHS2_IOADR_PRESET 0x40 + +/* SD application packets */ +#define UHS2_SD_CMD_INDEX_POS 8 + +#define UHS2_SD_CMD_APP_POS 14 +#define UHS2_SD_CMD_APP (1 << UHS2_SD_CMD_APP_POS) + +/* UHS-II Device Registers */ +#define UHS2_DEV_CONFIG_REG 0x000 + +/* General Caps and Settings registers */ +#define UHS2_DEV_CONFIG_GEN_CAPS (UHS2_DEV_CONFIG_REG + 0x000) +#define UHS2_DEV_CONFIG_N_LANES_POS 8 +#define UHS2_DEV_CONFIG_N_LANES_MASK 0x3F +#define UHS2_DEV_CONFIG_2L_HD_FD 0x1 +#define UHS2_DEV_CONFIG_2D1U_FD 0x2 +#define UHS2_DEV_CONFIG_1D2U_FD 0x4 +#define UHS2_DEV_CONFIG_2D2U_FD 0x8 +#define UHS2_DEV_CONFIG_DADR_POS 14 +#define UHS2_DEV_CONFIG_DADR_MASK 0x1 +#define UHS2_DEV_CONFIG_APP_POS 16 +#define UHS2_DEV_CONFIG_APP_MASK 0xFF +#define UHS2_DEV_CONFIG_APP_SD_MEM 0x1 + +#define UHS2_DEV_CONFIG_GEN_SET (UHS2_DEV_CONFIG_REG + 0x008) +#define UHS2_DEV_CONFIG_GEN_SET_N_LANES_POS 8 +#define UHS2_DEV_CONFIG_GEN_SET_2L_FD_HD 0x0 +#define UHS2_DEV_CONFIG_GEN_SET_2D1U_FD 0x2 +#define UHS2_DEV_CONFIG_GEN_SET_1D2U_FD 0x3 +#define UHS2_DEV_CONFIG_GEN_SET_2D2U_FD 0x4 +#define UHS2_DEV_CONFIG_GEN_SET_CFG_COMPLETE BIT(31) + +/* PHY Caps and Settings registers */ +#define UHS2_DEV_CONFIG_PHY_CAPS (UHS2_DEV_CONFIG_REG + 0x002) +#define UHS2_DEV_CONFIG_PHY_MINOR_MASK 0xF +#define UHS2_DEV_CONFIG_PHY_MAJOR_POS 4 +#define UHS2_DEV_CONFIG_PHY_MAJOR_MASK 0x3 +#define UHS2_DEV_CONFIG_CAN_HIBER_POS 15 +#define UHS2_DEV_CONFIG_CAN_HIBER_MASK 0x1 +#define UHS2_DEV_CONFIG_PHY_CAPS1 (UHS2_DEV_CONFIG_REG + 0x003) +#define UHS2_DEV_CONFIG_N_LSS_SYN_MASK 0xF +#define UHS2_DEV_CONFIG_N_LSS_DIR_POS 4 +#define UHS2_DEV_CONFIG_N_LSS_DIR_MASK 0xF + +#define UHS2_DEV_CONFIG_PHY_SET (UHS2_DEV_CONFIG_REG + 0x00A) +#define UHS2_DEV_CONFIG_PHY_SET_SPEED_POS 6 +#define UHS2_DEV_CONFIG_PHY_SET_SPEED_A 0x0 +#define UHS2_DEV_CONFIG_PHY_SET_SPEED_B 0x1 + +/* LINK-TRAN Caps and Settings registers */ +#define UHS2_DEV_CONFIG_LINK_TRAN_CAPS (UHS2_DEV_CONFIG_REG + 0x004) +#define UHS2_DEV_CONFIG_LT_MINOR_MASK 0xF +#define UHS2_DEV_CONFIG_LT_MAJOR_POS 4 +#define UHS2_DEV_CONFIG_LT_MAJOR_MASK 0x3 +#define UHS2_DEV_CONFIG_N_FCU_POS 8 +#define UHS2_DEV_CONFIG_N_FCU_MASK 0xFF +#define UHS2_DEV_CONFIG_DEV_TYPE_POS 16 +#define UHS2_DEV_CONFIG_DEV_TYPE_MASK 0x7 +#define UHS2_DEV_CONFIG_MAX_BLK_LEN_POS 20 +#define UHS2_DEV_CONFIG_MAX_BLK_LEN_MASK 0xFFF +#define UHS2_DEV_CONFIG_LINK_TRAN_CAPS1 (UHS2_DEV_CONFIG_REG + 0x005) +#define UHS2_DEV_CONFIG_N_DATA_GAP_MASK 0xFF + +#define UHS2_DEV_CONFIG_LINK_TRAN_SET (UHS2_DEV_CONFIG_REG + 0x00C) +#define UHS2_DEV_CONFIG_LT_SET_MAX_BLK_LEN 0x200 +#define UHS2_DEV_CONFIG_LT_SET_MAX_RETRY_POS 16 + +/* Preset register */ +#define UHS2_DEV_CONFIG_PRESET (UHS2_DEV_CONFIG_REG + 0x040) + +#define UHS2_DEV_INT_REG 0x100 + +#define UHS2_DEV_STATUS_REG 0x180 + +#define UHS2_DEV_CMD_REG 0x200 +#define UHS2_DEV_CMD_FULL_RESET (UHS2_DEV_CMD_REG + 0x000) +#define UHS2_DEV_CMD_GO_DORMANT_STATE (UHS2_DEV_CMD_REG + 0x001) +#define UHS2_DEV_CMD_DORMANT_HIBER BIT(7) +#define UHS2_DEV_CMD_DEVICE_INIT (UHS2_DEV_CMD_REG + 0x002) +#define UHS2_DEV_INIT_COMPLETE_FLAG BIT(11) +#define UHS2_DEV_CMD_ENUMERATE (UHS2_DEV_CMD_REG + 0x003) +#define UHS2_DEV_CMD_TRANS_ABORT (UHS2_DEV_CMD_REG + 0x004) + +#define UHS2_RCLK_MAX 52000000 +#define UHS2_RCLK_MIN 26000000 + +struct sd_uhs2_wait_active_state_data { + struct mmc_host *host; + struct mmc_command *cmd; +}; + +#endif /* LINUX_MMC_UHS2_H */ From patchwork Tue Dec 13 09:00:29 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Victor Shih X-Patchwork-Id: 32697 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:8188:b0:89:790f:f786 with SMTP id m8csp3857398dye; Tue, 13 Dec 2022 01:03:28 -0800 (PST) X-Google-Smtp-Source: AA0mqf7H/KaCBev/V8LwyQQ5dbRGMnDj1BCuvZqaLHdlYioBNECVtdQXHKjw/UsW3UgaePZbXv5l X-Received: by 2002:a05:6a20:8ba5:b0:aa:7ed0:fcf3 with SMTP id m37-20020a056a208ba500b000aa7ed0fcf3mr20927786pzh.1.1670922208070; Tue, 13 Dec 2022 01:03:28 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1670922208; cv=none; d=google.com; s=arc-20160816; b=FaqNbKPSUtkqtgJjPC9G1TRekiSBmd3PJcQNlNJyypXhlT/iQy4D3HbUN+V3QRJrUm ++vo7iapzFhdTe1l8ZHnv+unhrrOT+LeF0Er3FC+XcScZks08ygmbsXHftOpzTk4kkjJ rGh+4UUcXxFJmOXfzaV35ONiY3Td9aW0vYw4PCscFCQhomNQKvaWS4q6WZQCb8Uug+mQ cE3UmdcBxYhy9k9CeyYSdwPjWJAHm81L1mX2Nr32PEePPr2GJW5dWnMNrZ79m7PCGLau AQVwiR8NyFeA1cZxW3OTVgSmw03tTB7jdwNy8CayVlmY+br8/TkU+6VCx5/b+vmnGv7b 2AYQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=u0gi8O1uS7hu3absW7bU2WmBKEECmCexNng/mlIBJBA=; b=I9oCfJHISk19M8ztwxLmgynkkkuzr8Bh1SYMpjSEiDkLIF6HDuJKwP0PlTnkM/06Mk Le2LdDbap5t1s80GKcbjgQyghLQLVUwvCqAl2JJNnow6cMI4CxL4UpyJqnuAtkU3K/2+ pewTc+quF/Y44x/vTztj1HMwIMbrUQlEkBCy+iqylQRf3Su+jmr3a8FDGlv21WYhvp7g DQj9YP8A3vgPmpL+BZNIga8iDXvAlmmbbHYBnXBkYFP62rpNIbQxHhnZ+zAEGEVHCWce MuUr89IMZoRHISb1OOyf5veL3F8X9MsusA/7LiWAyaltevBPavR2K9ACYn6CsxH7CN64 2Llg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20210112 header.b=MgvSgFVF; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id d4-20020a170902cec400b001868a25da0dsi351416plg.40.2022.12.13.01.03.15; Tue, 13 Dec 2022 01:03:28 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@gmail.com header.s=20210112 header.b=MgvSgFVF; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234806AbiLMJCP (ORCPT + 99 others); Tue, 13 Dec 2022 04:02:15 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36036 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234720AbiLMJBt (ORCPT ); Tue, 13 Dec 2022 04:01:49 -0500 Received: from mail-pf1-x42d.google.com (mail-pf1-x42d.google.com [IPv6:2607:f8b0:4864:20::42d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A2A5CBCA6; Tue, 13 Dec 2022 01:01:26 -0800 (PST) Received: by mail-pf1-x42d.google.com with SMTP id d82so1718597pfd.11; Tue, 13 Dec 2022 01:01:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=u0gi8O1uS7hu3absW7bU2WmBKEECmCexNng/mlIBJBA=; b=MgvSgFVFPKCjEMTqASc/CSE5sQZtTm6lYthX6oFfydJxL7Zt542qj9WE4t7ts4Md2e 4VCMzJOBnBfFyyZUnZZcSzg3ohlKlJHGVdEq6yZNsWwZEZOSwHNdVWl/3l99Y10vChH/ JWTiQZBUvaA9gsOZrnBUS/fck2srTQHuEXHSXEj02MJWd8EyaXd2SHLFWNxpe5s0fXnX /Ka0niY71tl3DiJHyosHLoyczxGkJL2yqhx9tkQ5N8afnJCfges7nmWByn9Gbh20rhXY wQ51t3QuzVGo/qJDoo5SDAgQjJZf4cFkJrBSCIuj+MqdP5u3msWBxWyh8qPymIidSZSq 688A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=u0gi8O1uS7hu3absW7bU2WmBKEECmCexNng/mlIBJBA=; b=hJ+xLdMZldWhFXC5T1sPnTAn3TqQsu9mmaR87ZIRexXXeuslYv87AVpJwRi3eY3Fxg S20tccWfMGD4Xu1GikEq24mOfhRjSqSDiBLWi04nsCmuTUGvfLm5U4wXsqpJGxqmFzGQ YQz7wUZSHxWZFFpJvtGXFdAWxsCI3NtywvRsNtLLabZG6taxejmEs9c7rcVxmhBtdnnp O75GdJemKDfSQz3vWW5n4kVXjjpeYbTzNpLCQIoNWXFe014GFhey96DckiyNZ5rN+nZn Ap/H//9RIqgQ0kT0Z1IuKYqnUL1WPApAjCvQkYKRb0sHRkDTMgCThQDXD1MCicVdUbIo jPDg== X-Gm-Message-State: ANoB5plqYtsd/qn7eU/7F4Ft9pc3qKJwBjEYHL9k4vH8p6PAdC9/VE91 +lN0oOuwQufT6CYn6QQ403o= X-Received: by 2002:aa7:87ca:0:b0:56c:5e2:3064 with SMTP id i10-20020aa787ca000000b0056c05e23064mr15633827pfo.0.1670922085623; Tue, 13 Dec 2022 01:01:25 -0800 (PST) Received: from localhost.localdomain (2001-b400-e2dc-5c03-264b-f684-a8c9-21ae.emome-ip6.hinet.net. [2001:b400:e2dc:5c03:264b:f684:a8c9:21ae]) by smtp.gmail.com with ESMTPSA id 81-20020a621954000000b0056b9ec7e2desm7141682pfz.125.2022.12.13.01.01.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 13 Dec 2022 01:01:24 -0800 (PST) From: Victor Shih X-Google-Original-From: Victor Shih To: ulf.hansson@linaro.org, adrian.hunter@intel.com Cc: linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, benchuanggli@gmail.com, HL.Liu@genesyslogic.com.tw, Greg.tu@genesyslogic.com.tw, takahiro.akashi@linaro.org, dlunev@chromium.org, Victor Shih , Jason Lai Subject: [PATCH V6 06/24] mmc: core: Support UHS-II card control and access Date: Tue, 13 Dec 2022 17:00:29 +0800 Message-Id: <20221213090047.3805-7-victor.shih@genesyslogic.com.tw> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221213090047.3805-1-victor.shih@genesyslogic.com.tw> References: <20221213090047.3805-1-victor.shih@genesyslogic.com.tw> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM, RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1752088925427255240?= X-GMAIL-MSGID: =?utf-8?q?1752088925427255240?= Embed UHS-II access/control functionality into the MMC request processing flow. Signed-off-by: Ulf Hansson Signed-off-by: Jason Lai Signed-off-by: Victor Shih --- drivers/mmc/core/block.c | 6 +- drivers/mmc/core/core.c | 20 + drivers/mmc/core/mmc_ops.c | 25 +- drivers/mmc/core/mmc_ops.h | 1 + drivers/mmc/core/sd.c | 11 +- drivers/mmc/core/sd.h | 3 + drivers/mmc/core/sd_ops.c | 13 + drivers/mmc/core/sd_ops.h | 3 + drivers/mmc/core/sd_uhs2.c | 1171 +++++++++++++++++++++++++++++++++++- 9 files changed, 1206 insertions(+), 47 deletions(-) diff --git a/drivers/mmc/core/block.c b/drivers/mmc/core/block.c index 20da7ed43e6d..d3e8ec43cdd5 100644 --- a/drivers/mmc/core/block.c +++ b/drivers/mmc/core/block.c @@ -1596,6 +1596,9 @@ static void mmc_blk_rw_rq_prep(struct mmc_queue_req *mqrq, struct request *req = mmc_queue_req_to_req(mqrq); struct mmc_blk_data *md = mq->blkdata; bool do_rel_wr, do_data_tag; + bool do_multi; + + do_multi = (card->uhs2_state & MMC_UHS2_INITIALIZED) ? true : false; mmc_blk_data_prep(mq, mqrq, recovery_mode, &do_rel_wr, &do_data_tag); @@ -1606,7 +1609,7 @@ static void mmc_blk_rw_rq_prep(struct mmc_queue_req *mqrq, brq->cmd.arg <<= 9; brq->cmd.flags = MMC_RSP_SPI_R1 | MMC_RSP_R1 | MMC_CMD_ADTC; - if (brq->data.blocks > 1 || do_rel_wr) { + if (brq->data.blocks > 1 || do_rel_wr || do_multi) { /* SPI multiblock writes terminate using a special * token, not a STOP_TRANSMISSION request. */ @@ -1619,6 +1622,7 @@ static void mmc_blk_rw_rq_prep(struct mmc_queue_req *mqrq, brq->mrq.stop = NULL; readcmd = MMC_READ_SINGLE_BLOCK; writecmd = MMC_WRITE_BLOCK; + brq->cmd.uhs2_tmode0_flag = 1; } brq->cmd.opcode = rq_data_dir(req) == READ ? readcmd : writecmd; diff --git a/drivers/mmc/core/core.c b/drivers/mmc/core/core.c index ad1a40446813..01f8216885ad 100644 --- a/drivers/mmc/core/core.c +++ b/drivers/mmc/core/core.c @@ -334,6 +334,8 @@ static int mmc_mrq_prep(struct mmc_host *host, struct mmc_request *mrq) int mmc_start_request(struct mmc_host *host, struct mmc_request *mrq) { + struct uhs2_command uhs2_cmd; + __be32 payload[4]; /* for maximum size */ int err; init_completion(&mrq->cmd_completion); @@ -351,6 +353,14 @@ int mmc_start_request(struct mmc_host *host, struct mmc_request *mrq) if (err) return err; + if (host->card) { + if (host->card->uhs2_state & MMC_UHS2_INITIALIZED) { + uhs2_cmd.payload = payload; + mrq->cmd->uhs2_cmd = &uhs2_cmd; + mmc_uhs2_prepare_cmd(host, mrq); + } + } + led_trigger_event(host->led, LED_FULL); __mmc_start_request(host, mrq); @@ -430,6 +440,8 @@ EXPORT_SYMBOL(mmc_wait_for_req_done); */ int mmc_cqe_start_req(struct mmc_host *host, struct mmc_request *mrq) { + struct uhs2_command uhs2_cmd; + __be32 payload[4]; /* for maximum size */ int err; /* @@ -450,6 +462,14 @@ int mmc_cqe_start_req(struct mmc_host *host, struct mmc_request *mrq) if (err) goto out_err; + if (host->card) { + if (host->card->uhs2_state & MMC_UHS2_INITIALIZED) { + uhs2_cmd.payload = payload; + mrq->cmd->uhs2_cmd = &uhs2_cmd; + mmc_uhs2_prepare_cmd(host, mrq); + } + } + err = host->cqe_ops->cqe_request(host, mrq); if (err) goto out_err; diff --git a/drivers/mmc/core/mmc_ops.c b/drivers/mmc/core/mmc_ops.c index 81c55bfd6e0c..daa1f4ccd99a 100644 --- a/drivers/mmc/core/mmc_ops.c +++ b/drivers/mmc/core/mmc_ops.c @@ -144,10 +144,24 @@ int mmc_set_dsr(struct mmc_host *host) return mmc_wait_for_cmd(host, &cmd, MMC_CMD_RETRIES); } +int __mmc_go_idle(struct mmc_host *host) +{ + struct mmc_command cmd = {}; + int err; + + cmd.opcode = MMC_GO_IDLE_STATE; + cmd.arg = 0; + cmd.flags = MMC_RSP_SPI_R1 | MMC_RSP_NONE | MMC_CMD_BC; + + err = mmc_wait_for_cmd(host, &cmd, 0); + mmc_delay(1); + + return err; +} + int mmc_go_idle(struct mmc_host *host) { int err; - struct mmc_command cmd = {}; /* * Non-SPI hosts need to prevent chipselect going active during @@ -163,13 +177,7 @@ int mmc_go_idle(struct mmc_host *host) mmc_delay(1); } - cmd.opcode = MMC_GO_IDLE_STATE; - cmd.arg = 0; - cmd.flags = MMC_RSP_SPI_R1 | MMC_RSP_NONE | MMC_CMD_BC; - - err = mmc_wait_for_cmd(host, &cmd, 0); - - mmc_delay(1); + err = __mmc_go_idle(host); if (!mmc_host_is_spi(host)) { mmc_set_chip_select(host, MMC_CS_DONTCARE); @@ -300,6 +308,7 @@ int mmc_send_adtc_data(struct mmc_card *card, struct mmc_host *host, u32 opcode, * not R1 plus a data block. */ cmd.flags = MMC_RSP_SPI_R1 | MMC_RSP_R1 | MMC_CMD_ADTC; + cmd.uhs2_tmode0_flag = 1; data.blksz = len; data.blocks = 1; diff --git a/drivers/mmc/core/mmc_ops.h b/drivers/mmc/core/mmc_ops.h index 09ffbc00908b..abda7492d578 100644 --- a/drivers/mmc/core/mmc_ops.h +++ b/drivers/mmc/core/mmc_ops.h @@ -25,6 +25,7 @@ struct mmc_command; int mmc_select_card(struct mmc_card *card); int mmc_deselect_cards(struct mmc_host *host); int mmc_set_dsr(struct mmc_host *host); +int __mmc_go_idle(struct mmc_host *host); int mmc_go_idle(struct mmc_host *host); int mmc_send_op_cond(struct mmc_host *host, u32 ocr, u32 *rocr); int mmc_set_relative_addr(struct mmc_card *card); diff --git a/drivers/mmc/core/sd.c b/drivers/mmc/core/sd.c index 72b664ed90cf..4de4914c5ced 100644 --- a/drivers/mmc/core/sd.c +++ b/drivers/mmc/core/sd.c @@ -207,7 +207,7 @@ static int mmc_decode_csd(struct mmc_card *card) /* * Given a 64-bit response, decode to our card SCR structure. */ -static int mmc_decode_scr(struct mmc_card *card) +int mmc_decode_scr(struct mmc_card *card) { struct sd_scr *scr = &card->scr; unsigned int scr_struct; @@ -1616,11 +1616,6 @@ static void mmc_sd_detect(struct mmc_host *host) } } -static int sd_can_poweroff_notify(struct mmc_card *card) -{ - return card->ext_power.feature_support & SD_EXT_POWER_OFF_NOTIFY; -} - static int sd_busy_poweroff_notify_cb(void *cb_data, bool *busy) { struct sd_busy_data *data = cb_data; @@ -1644,7 +1639,7 @@ static int sd_busy_poweroff_notify_cb(void *cb_data, bool *busy) return 0; } -static int sd_poweroff_notify(struct mmc_card *card) +int sd_poweroff_notify(struct mmc_card *card) { struct sd_busy_data cb_data; u8 *reg_buf; @@ -1692,7 +1687,7 @@ static int _mmc_sd_suspend(struct mmc_host *host) if (mmc_card_suspended(card)) goto out; - if (sd_can_poweroff_notify(card)) + if (mmc_card_can_poweroff_notify(card)) err = sd_poweroff_notify(card); else if (!mmc_host_is_spi(host)) err = mmc_deselect_cards(host); diff --git a/drivers/mmc/core/sd.h b/drivers/mmc/core/sd.h index 1af5a038bae9..b573a809a0f4 100644 --- a/drivers/mmc/core/sd.h +++ b/drivers/mmc/core/sd.h @@ -17,4 +17,7 @@ int mmc_sd_setup_card(struct mmc_host *host, struct mmc_card *card, unsigned mmc_sd_get_max_clock(struct mmc_card *card); int mmc_sd_switch_hs(struct mmc_card *card); +/* These call back functions were also used by UHS2 sd card */ +int sd_poweroff_notify(struct mmc_card *card); + #endif diff --git a/drivers/mmc/core/sd_ops.c b/drivers/mmc/core/sd_ops.c index ef8d1dce5af1..44a47a373b04 100644 --- a/drivers/mmc/core/sd_ops.c +++ b/drivers/mmc/core/sd_ops.c @@ -27,6 +27,17 @@ int mmc_app_cmd(struct mmc_host *host, struct mmc_card *card) if (WARN_ON(card && card->host != host)) return -EINVAL; + /* + * UHS2 packet has APP bit so only set APP_CMD flag here. + * Will set the APP bit when assembling UHS2 packet. + */ + if (host->card) { + if (host->card->uhs2_state & MMC_UHS2_INITIALIZED) { + host->uhs2_ios.is_APP_CMD = true; + return 0; + } + } + cmd.opcode = MMC_APP_CMD; if (card) { @@ -281,6 +292,7 @@ int mmc_app_send_scr(struct mmc_card *card) cmd.opcode = SD_APP_SEND_SCR; cmd.arg = 0; cmd.flags = MMC_RSP_SPI_R1 | MMC_RSP_R1 | MMC_CMD_ADTC; + cmd.uhs2_tmode0_flag = 1; data.blksz = 8; data.blocks = 1; @@ -344,6 +356,7 @@ int mmc_app_sd_status(struct mmc_card *card, void *ssr) cmd.opcode = SD_APP_SD_STATUS; cmd.arg = 0; cmd.flags = MMC_RSP_SPI_R2 | MMC_RSP_R1 | MMC_CMD_ADTC; + cmd.uhs2_tmode0_flag = 1; data.blksz = 64; data.blocks = 1; diff --git a/drivers/mmc/core/sd_ops.h b/drivers/mmc/core/sd_ops.h index 3ba7b3cf4652..29c802dec988 100644 --- a/drivers/mmc/core/sd_ops.h +++ b/drivers/mmc/core/sd_ops.h @@ -11,6 +11,7 @@ #include struct mmc_card; +struct mmc_command; struct mmc_host; int mmc_app_set_bus_width(struct mmc_card *card, int width); @@ -19,10 +20,12 @@ int mmc_send_if_cond(struct mmc_host *host, u32 ocr); int mmc_send_if_cond_pcie(struct mmc_host *host, u32 ocr); int mmc_send_relative_addr(struct mmc_host *host, unsigned int *rca); int mmc_app_send_scr(struct mmc_card *card); +int mmc_decode_scr(struct mmc_card *card); int mmc_sd_switch(struct mmc_card *card, int mode, int group, u8 value, u8 *resp); int mmc_app_sd_status(struct mmc_card *card, void *ssr); int mmc_app_cmd(struct mmc_host *host, struct mmc_card *card); +void mmc_uhs2_prepare_cmd(struct mmc_host *host, struct mmc_request *mrq); #endif diff --git a/drivers/mmc/core/sd_uhs2.c b/drivers/mmc/core/sd_uhs2.c index 800957f74632..a79eb08ec540 100644 --- a/drivers/mmc/core/sd_uhs2.c +++ b/drivers/mmc/core/sd_uhs2.c @@ -1,48 +1,125 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (C) 2021 Linaro Ltd - * * Author: Ulf Hansson * + * Copyright (C) 2014 Intel Corp, All Rights Reserved. + * Author: Yi Sun + * + * Copyright (C) 2020 Genesys Logic, Inc. + * Authors: Ben Chuang + * + * Copyright (C) 2020 Linaro Limited + * Author: AKASHI Takahiro + * + * Copyright (C) 2022 Genesys Logic, Inc. + * Authors: Jason Lai + * * Support for SD UHS-II cards */ #include +#include #include #include +#include +#include +#include +#include "card.h" #include "core.h" #include "bus.h" #include "sd.h" +#include "sd_ops.h" #include "mmc_ops.h" +#define UHS2_WAIT_CFG_COMPLETE_PERIOD_US (1 * 1000) /* 1ms */ +#define UHS2_WAIT_CFG_COMPLETE_TIMEOUT_MS 100 /* 100ms */ + static const unsigned int sd_uhs2_freqs[] = { 52000000, 26000000 }; +int sd_uhs2_reinit(struct mmc_host *host); -static int sd_uhs2_set_ios(struct mmc_host *host) +/* + * Internal function that does the actual ios call to the host driver, + * optionally printing some debug output. + */ +static inline int sd_uhs2_set_ios(struct mmc_host *host) { struct mmc_ios *ios = &host->ios; + pr_debug("%s: clock %uHz powermode %u Vdd %u timing %u\n", + mmc_hostname(host), ios->clock, ios->power_mode, ios->vdd, ios->timing); + return host->ops->uhs2_set_ios(host, ios); } static int sd_uhs2_power_up(struct mmc_host *host) { + int err; + + if (host->ios.power_mode == MMC_POWER_ON) + return 0; + host->ios.vdd = fls(host->ocr_avail) - 1; host->ios.clock = host->f_init; host->ios.timing = MMC_TIMING_SD_UHS2; - host->ios.power_mode = MMC_POWER_UP; + host->ios.power_mode = MMC_POWER_ON; - return sd_uhs2_set_ios(host); + err = sd_uhs2_set_ios(host); + + mmc_delay(host->uhs2_ios.power_delay_ms); + + return err; } -static void sd_uhs2_power_off(struct mmc_host *host) +static int sd_uhs2_power_off(struct mmc_host *host) { + if (host->ios.power_mode == MMC_POWER_OFF) + return 0; + host->ios.vdd = 0; host->ios.clock = 0; host->ios.timing = MMC_TIMING_LEGACY; host->ios.power_mode = MMC_POWER_OFF; - sd_uhs2_set_ios(host); + return sd_uhs2_set_ios(host); +} + +/** + * sd_uhs2_cmd_assemble() - build up UHS-II command packet which is embedded in + * mmc_command structure + * @cmd: MMC command to executed + * @uhs2_cmd: UHS2 command corresponded to MMC command + * @header: Header field of UHS-II command cxpacket + * @arg: Argument field of UHS-II command packet + * @payload: Payload field of UHS-II command packet + * @plen: Payload length + * @resp: Response buffer is allocated by caller and it is used to keep + * the response of CM-TRAN command. For SD-TRAN command, uhs2_resp + * should be null and SD-TRAN command response should be stored in + * resp of mmc_command. + * @resp_len: Response buffer length + * + * The uhs2_command structure contains message packets which are transmited/ + * received on UHS-II bus. This function fills in the contents of uhs2_command + * structure and embededs UHS2 command into mmc_command structure, which is used + * in legacy SD operation functions. + * + */ +static void sd_uhs2_cmd_assemble(struct mmc_command *cmd, + struct uhs2_command *uhs2_cmd, + u16 header, u16 arg, __be32 *payload, + u8 plen, u8 *resp, u8 resp_len) +{ + uhs2_cmd->header = header; + uhs2_cmd->arg = arg; + uhs2_cmd->payload = payload; + uhs2_cmd->payload_len = plen * sizeof(u32); + uhs2_cmd->packet_len = uhs2_cmd->payload_len + 4; + + cmd->uhs2_cmd = uhs2_cmd; + cmd->uhs2_resp = resp; + cmd->uhs2_resp_len = resp_len; } /* @@ -52,7 +129,15 @@ static void sd_uhs2_power_off(struct mmc_host *host) */ static int sd_uhs2_phy_init(struct mmc_host *host) { - return 0; + int err = 0; + + err = host->ops->uhs2_control(host, UHS2_PHY_INIT); + if (err) { + pr_err("%s: failed to initial phy for UHS-II!\n", + mmc_hostname(host)); + } + + return err; } /* @@ -61,6 +146,88 @@ static int sd_uhs2_phy_init(struct mmc_host *host) */ static int sd_uhs2_dev_init(struct mmc_host *host) { + struct mmc_command cmd = {0}; + struct uhs2_command uhs2_cmd = {}; + u32 cnt; + u32 dap, gap, resp_gap; + u16 header, arg; + __be32 payload[UHS2_DEV_INIT_PAYLOAD_LEN]; + u8 gd = 0; + u8 resp[UHS2_DEV_ENUM_RESP_LEN] = {0}; + int err; + + dap = host->uhs2_caps.dap; + gap = host->uhs2_caps.gap; + + /* + * Refer to UHS-II Addendum Version 1.02 Figure 6-21 to see DEVICE_INIT CCMD format. + * Head: + * - Control Write(R/W=1) with 4-Byte payload(PLEN=01b). + * - IOADR = CMD_BASE + 002h + * Payload: + * - bit [3:0] : GAP(Group Allocated Power) + * - bit [7:4] : GD(Group Descriptor) + * - bit [11] : Complete Flag + * - bit [15:12]: DAP(Device Allocated Power) + */ + header = UHS2_NATIVE_PACKET | UHS2_PACKET_TYPE_CCMD; + arg = ((UHS2_DEV_CMD_DEVICE_INIT & 0xFF) << 8) | + UHS2_NATIVE_CMD_WRITE | + UHS2_NATIVE_CMD_PLEN_4B | + (UHS2_DEV_CMD_DEVICE_INIT >> 8); + + /* + * Refer to UHS-II Addendum Version 1.02 section 6.3.1. + * Max. time from DEVICE_INIT CCMD EOP reception on Device + * Rx to its SOP transmission on Device Tx(Tfwd_init_cmd) is + * 1 second. + */ + cmd.busy_timeout = 1000; + + /* + * Refer to UHS-II Addendum Version 1.02 section 6.2.6.3. + * When the number of the DEVICE_INIT commands is reach to + * 30 tiems, Host shall stop issuing DEVICE_INIT command + * and regard it as an error. + */ + for (cnt = 0; cnt < 30; cnt++) { + payload[0] = ((dap & 0xF) << 12) | + UHS2_DEV_INIT_COMPLETE_FLAG | + ((gd & 0xF) << 4) | + (gap & 0xF); + + sd_uhs2_cmd_assemble(&cmd, &uhs2_cmd, header, arg, + payload, UHS2_DEV_INIT_PAYLOAD_LEN, + resp, UHS2_DEV_INIT_RESP_LEN); + + err = mmc_wait_for_cmd(host, &cmd, 0); + + if (err) { + pr_err("%s: %s: UHS2 CMD send fail, err= 0x%x!\n", + mmc_hostname(host), __func__, err); + return err; + } + + if (resp[3] != (UHS2_DEV_CMD_DEVICE_INIT & 0xFF)) { + pr_err("%s: DEVICE_INIT response is wrong!\n", + mmc_hostname(host)); + return -EIO; + } + + if (resp[5] & 0x8) { + host->uhs2_caps.group_desc = gd; + return 0; + } + resp_gap = resp[4] & 0x0F; + if (gap == resp_gap) + gd++; + } + if (cnt == 30) { + pr_err("%s: DEVICE_INIT fail, already 30 times!\n", + mmc_hostname(host)); + return -EIO; + } + return 0; } @@ -71,6 +238,52 @@ static int sd_uhs2_dev_init(struct mmc_host *host) */ static int sd_uhs2_enum(struct mmc_host *host, u32 *node_id) { + struct mmc_command cmd = {0}; + struct uhs2_command uhs2_cmd = {}; + u16 header, arg; + __be32 payload[UHS2_DEV_ENUM_PAYLOAD_LEN]; + u8 id_f = 0xF, id_l = 0x0; + u8 resp[UHS2_DEV_ENUM_RESP_LEN] = {0}; + int err; + + /* + * Refer to UHS-II Addendum Version 1.02 Figure 6-28 to see ENUMERATE CCMD format. + * Header: + * - Control Write(R/W=1) with 4-Byte payload(PLEN=01b). + * - IOADR = CMD_BASE + 003h + * Payload: + * - bit [3:0]: ID_L(Last Node ID) + * - bit [7:4]: ID_F(First Node ID) + */ + header = UHS2_NATIVE_PACKET | UHS2_PACKET_TYPE_CCMD; + arg = ((UHS2_DEV_CMD_ENUMERATE & 0xFF) << 8) | + UHS2_NATIVE_CMD_WRITE | + UHS2_NATIVE_CMD_PLEN_4B | + (UHS2_DEV_CMD_ENUMERATE >> 8); + + payload[0] = (id_f << 4) | id_l; + payload[0] = cpu_to_be32(payload[0]); + + sd_uhs2_cmd_assemble(&cmd, &uhs2_cmd, header, arg, payload, UHS2_DEV_ENUM_PAYLOAD_LEN, + resp, UHS2_DEV_ENUM_RESP_LEN); + + err = mmc_wait_for_cmd(host, &cmd, 0); + if (err) { + pr_err("%s: %s: UHS2 CMD send fail, err= 0x%x!\n", + mmc_hostname(host), __func__, err); + return err; + } + + if (resp[3] != (UHS2_DEV_CMD_ENUMERATE & 0xFF)) { + pr_err("%s: ENUMERATE response is wrong!\n", + mmc_hostname(host)); + return -EIO; + } + + id_f = (resp[4] >> 4) & 0xF; + id_l = resp[4] & 0xF; + *node_id = id_f; + return 0; } @@ -81,6 +294,181 @@ static int sd_uhs2_enum(struct mmc_host *host, u32 *node_id) */ static int sd_uhs2_config_read(struct mmc_host *host, struct mmc_card *card) { + struct mmc_command cmd = {0}; + struct uhs2_command uhs2_cmd = {}; + u16 header, arg; + u32 cap; + int err; + + /* + * Use Control Read CCMD to read Generic Capability from Configuration Register. + * - Control Write(R/W=1) with 4-Byte payload(PLEN=01b). + * - IOADR = Generic Capability Register(CFG_BASE + 000h) + */ + header = UHS2_NATIVE_PACKET | UHS2_PACKET_TYPE_CCMD | card->uhs2_config.node_id; + arg = ((UHS2_DEV_CONFIG_GEN_CAPS & 0xFF) << 8) | + UHS2_NATIVE_CMD_READ | + UHS2_NATIVE_CMD_PLEN_4B | + (UHS2_DEV_CONFIG_GEN_CAPS >> 8); + + /* + * There is no payload because per spec, there should be + * no payload field for read CCMD. + * Plen is set in arg. Per spec, plen for read CCMD + * represents the len of read data which is assigned in payload + * of following RES (p136). + */ + sd_uhs2_cmd_assemble(&cmd, &uhs2_cmd, header, arg, NULL, 0, NULL, 0); + + err = mmc_wait_for_cmd(host, &cmd, 0); + if (err) { + pr_err("%s: %s: UHS2 CMD send fail, err= 0x%x!\n", + mmc_hostname(host), __func__, err); + return err; + } + + /* + * Generic Capability Register: + * bit [7:0] : Reserved + * bit [13:8] : Device-Specific Number of Lanes and Functionality + * bit 8: 2L-HD + * bit 9: 2D-1U FD + * bit 10: 1D-2U FD + * bit 11: 2D-2U FD + * Others: Reserved + * bit [14] : DADR Length + * 0: 4 bytes + * 1: Reserved + * bit [23:16]: Application Type + * bit 16: 0=Non-SD memory, 1=SD memory + * bit 17: 0=Non-SDIO, 1=SDIO + * bit 18: 0=Card, 1=Embedded + * bit [63:24]: Reserved + */ + cap = cmd.resp[0]; + card->uhs2_config.n_lanes = + (cap >> UHS2_DEV_CONFIG_N_LANES_POS) & + UHS2_DEV_CONFIG_N_LANES_MASK; + card->uhs2_config.dadr_len = + (cap >> UHS2_DEV_CONFIG_DADR_POS) & + UHS2_DEV_CONFIG_DADR_MASK; + card->uhs2_config.app_type = + (cap >> UHS2_DEV_CONFIG_APP_POS) & + UHS2_DEV_CONFIG_APP_MASK; + + /* + * Use Control Read CCMD to read PHY Capability from Configuration Register. + * - Control Write(R/W=1) with 8-Byte payload(PLEN=10b). + * - IOADR = PHY Capability Register(CFG_BASE + 002h) + */ + arg = ((UHS2_DEV_CONFIG_PHY_CAPS & 0xFF) << 8) | + UHS2_NATIVE_CMD_READ | + UHS2_NATIVE_CMD_PLEN_8B | + (UHS2_DEV_CONFIG_PHY_CAPS >> 8); + + sd_uhs2_cmd_assemble(&cmd, &uhs2_cmd, header, arg, NULL, 0, NULL, 0); + + err = mmc_wait_for_cmd(host, &cmd, 0); + if (err) { + pr_err("%s: %s: UHS2 CMD send fail, err= 0x%x!\n", + mmc_hostname(host), __func__, err); + return err; + } + + /* + * PHY Capability Register: + * bit [3:0] : PHY Minor Revision + * bit [5:4] : PHY Major Revision + * bit [15] : Support Hibernate Mode + * 0: Not support Hibernate Mode + * 1: Support Hibernate Mode + * bit [31:16]: Reserved + * bit [35:32]: Device-Specific N_LSS_SYN + * bit [39:36]: Device-Specific N_LSS_DIR + * bit [63:40]: Reserved + */ + cap = cmd.resp[0]; + card->uhs2_config.phy_minor_rev = + cap & UHS2_DEV_CONFIG_PHY_MINOR_MASK; + card->uhs2_config.phy_major_rev = + (cap >> UHS2_DEV_CONFIG_PHY_MAJOR_POS) & + UHS2_DEV_CONFIG_PHY_MAJOR_MASK; + card->uhs2_config.can_hibernate = + (cap >> UHS2_DEV_CONFIG_CAN_HIBER_POS) & + UHS2_DEV_CONFIG_CAN_HIBER_MASK; + + cap = cmd.resp[1]; + card->uhs2_config.n_lss_sync = + cap & UHS2_DEV_CONFIG_N_LSS_SYN_MASK; + card->uhs2_config.n_lss_dir = + (cap >> UHS2_DEV_CONFIG_N_LSS_DIR_POS) & + UHS2_DEV_CONFIG_N_LSS_DIR_MASK; + if (card->uhs2_config.n_lss_sync == 0) + card->uhs2_config.n_lss_sync = 16 << 2; + else + card->uhs2_config.n_lss_sync <<= 2; + + if (card->uhs2_config.n_lss_dir == 0) + card->uhs2_config.n_lss_dir = 16 << 3; + else + card->uhs2_config.n_lss_dir <<= 3; + + /* + * Use Control Read CCMD to read LINK/TRAN Capability from Configuration Register. + * - Control Write(R/W=1) with 8-Byte payload(PLEN=10b). + * - IOADR = LINK/TRAN Capability Register(CFG_BASE + 004h) + */ + arg = ((UHS2_DEV_CONFIG_LINK_TRAN_CAPS & 0xFF) << 8) | + UHS2_NATIVE_CMD_READ | + UHS2_NATIVE_CMD_PLEN_8B | + (UHS2_DEV_CONFIG_LINK_TRAN_CAPS >> 8); + + sd_uhs2_cmd_assemble(&cmd, &uhs2_cmd, header, arg, NULL, 0, NULL, 0); + + err = mmc_wait_for_cmd(host, &cmd, 0); + if (err) { + pr_err("%s: %s: UHS2 CMD send fail, err= 0x%x!\n", + mmc_hostname(host), __func__, err); + return err; + } + + /* + * LINK/TRAN Capability Register: + * bit [3:0] : LINK_TRAN Minor Revision + * bit [5:4] : LINK/TRAN Major Revision + * bit [7:6] : Reserved + * bit [15:8] : Device-Specific N_FCU + * bit [18:16]: Device Type + * 001b=Host + * 010b=Device + * 011b=Reserved for CMD issuable Device + * bit [19] : Reserved + * bit [31:20]: Device-Specific MAX_BLKLEN + * bit [39:32]: Device-Specific N_DATA_GAP + * bit [63:40]: Reserved + */ + cap = cmd.resp[0]; + card->uhs2_config.link_minor_rev = + cap & UHS2_DEV_CONFIG_LT_MINOR_MASK; + card->uhs2_config.link_major_rev = + (cap >> UHS2_DEV_CONFIG_LT_MAJOR_POS) & + UHS2_DEV_CONFIG_LT_MAJOR_MASK; + card->uhs2_config.n_fcu = + (cap >> UHS2_DEV_CONFIG_N_FCU_POS) & + UHS2_DEV_CONFIG_N_FCU_MASK; + card->uhs2_config.dev_type = + (cap >> UHS2_DEV_CONFIG_DEV_TYPE_POS) & + UHS2_DEV_CONFIG_DEV_TYPE_MASK; + card->uhs2_config.maxblk_len = + (cap >> UHS2_DEV_CONFIG_MAX_BLK_LEN_POS) & + UHS2_DEV_CONFIG_MAX_BLK_LEN_MASK; + + cap = cmd.resp[1]; + card->uhs2_config.n_data_gap = + cap & UHS2_DEV_CONFIG_N_DATA_GAP_MASK; + if (card->uhs2_config.n_fcu == 0) + card->uhs2_config.n_fcu = 256; + return 0; } @@ -95,9 +483,407 @@ static int sd_uhs2_config_read(struct mmc_host *host, struct mmc_card *card) */ static int sd_uhs2_config_write(struct mmc_host *host, struct mmc_card *card) { + struct mmc_command cmd = {0}; + struct uhs2_command uhs2_cmd = {}; + u16 header, arg; + __be32 payload[UHS2_CFG_WRITE_PAYLOAD_LEN]; + u8 nMinDataGap; + int err; + u8 resp[5] = {0}; + + /* + * Use Control Write CCMD to set Generic Setting in Configuration Register. + * - Control Write(R/W=1) with 8-Byte payload(PLEN=10b). + * - IOADR = Generic Setting Register(CFG_BASE + 008h) + * - Payload = New contents to be written to Generic Setting Register + */ + header = UHS2_NATIVE_PACKET | UHS2_PACKET_TYPE_CCMD | card->uhs2_config.node_id; + arg = ((UHS2_DEV_CONFIG_GEN_SET & 0xFF) << 8) | + UHS2_NATIVE_CMD_WRITE | + UHS2_NATIVE_CMD_PLEN_8B | + (UHS2_DEV_CONFIG_GEN_SET >> 8); + + if (card->uhs2_config.n_lanes == UHS2_DEV_CONFIG_2L_HD_FD && + host->uhs2_caps.n_lanes == UHS2_DEV_CONFIG_2L_HD_FD) { + /* Support HD */ + host->uhs2_ios.is_2L_HD_mode = true; + nMinDataGap = 1; + } else { + /* Only support 2L-FD so far */ + host->uhs2_ios.is_2L_HD_mode = false; + nMinDataGap = 3; + } + + /* + * Most UHS-II cards only support FD and 2L-HD mode. Other lane numbers + * defined in UHS-II addendem Ver1.01 are optional. + */ + host->uhs2_caps.n_lanes_set = UHS2_DEV_CONFIG_GEN_SET_2L_FD_HD; + card->uhs2_config.n_lanes_set = UHS2_DEV_CONFIG_GEN_SET_2L_FD_HD; + + payload[0] = card->uhs2_config.n_lanes_set << UHS2_DEV_CONFIG_N_LANES_POS; + payload[1] = 0; + payload[0] = cpu_to_be32(payload[0]); + payload[1] = cpu_to_be32(payload[1]); + + /* + * There is no payload because per spec, there should be + * no payload field for read CCMD. + * Plen is set in arg. Per spec, plen for read CCMD + * represents the len of read data which is assigned in payload + * of following RES (p136). + */ + sd_uhs2_cmd_assemble(&cmd, &uhs2_cmd, header, arg, payload, UHS2_CFG_WRITE_PAYLOAD_LEN, + NULL, 0); + + err = mmc_wait_for_cmd(host, &cmd, 0); + if (err) { + pr_err("%s: %s: UHS2 CMD send fail, err= 0x%x!\n", + mmc_hostname(host), __func__, err); + return err; + } + + /* + * Use Control Write CCMD to set PHY Setting in Configuration Register. + * - Control Write(R/W=1) with 8-Byte payload(PLEN=10b). + * - IOADR = PHY Setting Register(CFG_BASE + 00Ah) + * - Payload = New contents to be written to PHY Setting Register + */ + arg = ((UHS2_DEV_CONFIG_PHY_SET & 0xFF) << 8) | + UHS2_NATIVE_CMD_WRITE | + UHS2_NATIVE_CMD_PLEN_8B | + (UHS2_DEV_CONFIG_PHY_SET >> 8); + + if (host->uhs2_caps.speed_range == UHS2_DEV_CONFIG_PHY_SET_SPEED_B) { + card->uhs2_state |= MMC_UHS2_SPEED_B; + card->uhs2_config.speed_range_set = + UHS2_DEV_CONFIG_PHY_SET_SPEED_B; + } else { + card->uhs2_config.speed_range_set = UHS2_DEV_CONFIG_PHY_SET_SPEED_A; + card->uhs2_state &= ~MMC_UHS2_SPEED_B; + } + + payload[0] = card->uhs2_config.speed_range_set << UHS2_DEV_CONFIG_PHY_SET_SPEED_POS; + + card->uhs2_config.n_lss_sync_set = (max(card->uhs2_config.n_lss_sync, + host->uhs2_caps.n_lss_sync) >> 2) & + UHS2_DEV_CONFIG_N_LSS_SYN_MASK; + host->uhs2_caps.n_lss_sync_set = card->uhs2_config.n_lss_sync_set; + + card->uhs2_config.n_lss_dir_set = (max(card->uhs2_config.n_lss_dir, + host->uhs2_caps.n_lss_dir) >> 3) & + UHS2_DEV_CONFIG_N_LSS_DIR_MASK; + host->uhs2_caps.n_lss_dir_set = card->uhs2_config.n_lss_dir_set; + + payload[1] = (card->uhs2_config.n_lss_dir_set << UHS2_DEV_CONFIG_N_LSS_DIR_POS) | + card->uhs2_config.n_lss_sync_set; + payload[0] = cpu_to_be32(payload[0]); + payload[1] = cpu_to_be32(payload[1]); + + memset(resp, 0, sizeof(resp)); + + sd_uhs2_cmd_assemble(&cmd, &uhs2_cmd, header, arg, payload, UHS2_CFG_WRITE_PAYLOAD_LEN, + resp, UHS2_CFG_WRITE_PHY_SET_RESP_LEN); + + err = mmc_wait_for_cmd(host, &cmd, 0); + if (err) { + pr_err("%s: %s: UHS2 CMD send fail, err= 0x%x!\n", + mmc_hostname(host), __func__, err); + return err; + } + + if ((resp[2] & 0x80)) { + pr_err("%s: %s: UHS2 CMD not accepted, resp= 0x%x!\n", + mmc_hostname(host), __func__, resp[2]); + return -EIO; + } + + /* + * Use Control Write CCMD to set LINK/TRAN Setting in Configuration Register. + * - Control Write(R/W=1) with 8-Byte payload(PLEN=10b). + * - IOADR = LINK/TRAN Setting Register(CFG_BASE + 00Ch) + * - Payload = New contents to be written to LINK/TRAN Setting Register + */ + arg = ((UHS2_DEV_CONFIG_LINK_TRAN_SET & 0xFF) << 8) | + UHS2_NATIVE_CMD_WRITE | + UHS2_NATIVE_CMD_PLEN_8B | + (UHS2_DEV_CONFIG_LINK_TRAN_SET >> 8); + + if (card->uhs2_config.app_type == UHS2_DEV_CONFIG_APP_SD_MEM) + card->uhs2_config.maxblk_len_set = UHS2_DEV_CONFIG_LT_SET_MAX_BLK_LEN; + else + card->uhs2_config.maxblk_len_set = min(card->uhs2_config.maxblk_len, + host->uhs2_caps.maxblk_len); + host->uhs2_caps.maxblk_len_set = card->uhs2_config.maxblk_len_set; + + card->uhs2_config.n_fcu_set = min(card->uhs2_config.n_fcu, host->uhs2_caps.n_fcu); + host->uhs2_caps.n_fcu_set = card->uhs2_config.n_fcu_set; + + card->uhs2_config.n_data_gap_set = max(nMinDataGap, card->uhs2_config.n_data_gap); + host->uhs2_caps.n_data_gap_set = card->uhs2_config.n_data_gap_set; + + host->uhs2_caps.max_retry_set = 3; + card->uhs2_config.max_retry_set = host->uhs2_caps.max_retry_set; + + payload[0] = (card->uhs2_config.maxblk_len_set << UHS2_DEV_CONFIG_MAX_BLK_LEN_POS) | + (card->uhs2_config.max_retry_set << UHS2_DEV_CONFIG_LT_SET_MAX_RETRY_POS) | + (card->uhs2_config.n_fcu_set << UHS2_DEV_CONFIG_N_FCU_POS); + payload[1] = card->uhs2_config.n_data_gap_set; + payload[0] = cpu_to_be32(payload[0]); + payload[1] = cpu_to_be32(payload[1]); + + sd_uhs2_cmd_assemble(&cmd, &uhs2_cmd, header, arg, payload, UHS2_CFG_WRITE_PAYLOAD_LEN, + NULL, 0); + + err = mmc_wait_for_cmd(host, &cmd, 0); + if (err) { + pr_err("%s: %s: UHS2 CMD send fail, err= 0x%x!\n", + mmc_hostname(host), __func__, err); + return err; + } + + /* + * Use Control Write CCMD to set Config Completion(payload bit 63) in Generic Setting + * Register. + * Header: + * - Control Write(R/W=1) with 8-Byte payload(PLEN=10b). + * - IOADR = PGeneric Setting Register(CFG_BASE + 008h) + * Payload: + * - bit [63]: Config Completion + * + * DLSM transits to Active state immediately when Config Completion is set to 1. + */ + arg = ((UHS2_DEV_CONFIG_GEN_SET & 0xFF) << 8) | + UHS2_NATIVE_CMD_WRITE | + UHS2_NATIVE_CMD_PLEN_8B | + (UHS2_DEV_CONFIG_GEN_SET >> 8); + + payload[0] = 0; + payload[1] = UHS2_DEV_CONFIG_GEN_SET_CFG_COMPLETE; + payload[0] = cpu_to_be32(payload[0]); + payload[1] = cpu_to_be32(payload[1]); + + memset(resp, 0, sizeof(resp)); + sd_uhs2_cmd_assemble(&cmd, &uhs2_cmd, header, arg, payload, UHS2_CFG_WRITE_PAYLOAD_LEN, + resp, UHS2_CFG_WRITE_GENERIC_SET_RESP_LEN); + + err = mmc_wait_for_cmd(host, &cmd, 0); + if (err) { + pr_err("%s: %s: UHS2 CMD send fail, err= 0x%x!\n", + mmc_hostname(host), __func__, err); + return err; + } + + /* Set host Config Setting registers */ + err = host->ops->uhs2_control(host, UHS2_SET_CONFIG); + if (err) { + pr_err("%s: %s: UHS2 SET_CONFIG fail!\n", mmc_hostname(host), __func__); + return err; + } + + return 0; +} + +static int sd_uhs2_go_dormant(struct mmc_host *host, u32 node_id) +{ + struct mmc_command cmd = {0}; + struct uhs2_command uhs2_cmd = {}; + u16 header, arg; + __be32 payload[1]; + int err; + + /* Disable Normal INT */ + err = host->ops->uhs2_control(host, UHS2_DISABLE_INT); + if (err) { + pr_err("%s: %s: UHS2 DISABLE_INT fail!\n", + mmc_hostname(host), __func__); + return err; + } + + /* + * Refer to UHS-II Addendum Version 1.02 Figure 6-17 to see GO_DORMANT_STATE CCMD format. + * Header: + * - Control Write(R/W=1) with 4-Byte payload(PLEN=01b). + * - IOADR = CMD_BASE + 001h + * Payload: + * - bit [7]: HBR(Entry to Hibernate Mode) + * 1: Host intends to enter Hibernate mode during Dormant state. + * The default setting is 0 because hibernate is currently not supported. + */ + header = UHS2_NATIVE_PACKET | UHS2_PACKET_TYPE_CCMD | node_id; + arg = ((UHS2_DEV_CMD_GO_DORMANT_STATE & 0xFF) << 8) | + UHS2_NATIVE_CMD_WRITE | + UHS2_NATIVE_CMD_PLEN_4B | + (UHS2_DEV_CMD_GO_DORMANT_STATE >> 8); + + sd_uhs2_cmd_assemble(&cmd, &uhs2_cmd, header, arg, payload, UHS2_GO_DORMANT_PAYLOAD_LEN, + NULL, 0); + + err = mmc_wait_for_cmd(host, &cmd, 0); + if (err) { + pr_err("%s: %s: UHS2 CMD send fail, err= 0x%x!\n", + mmc_hostname(host), __func__, err); + return err; + } + + /* Check Dormant State in Present */ + err = host->ops->uhs2_control(host, UHS2_CHECK_DORMANT); + if (err) + return err; + + /* Disable UHS2 card clock */ + err = host->ops->uhs2_control(host, UHS2_DISABLE_CLK); + if (err) + return err; + + /* Restore sd clock */ + mmc_delay(5); + err = host->ops->uhs2_control(host, UHS2_ENABLE_CLK); + if (err) + return err; + + /* Enable Normal INT */ + err = host->ops->uhs2_control(host, UHS2_ENABLE_INT); + if (err) + return err; + + /* Detect UHS2 */ + err = host->ops->uhs2_control(host, UHS2_PHY_INIT); + if (err) + return err; + + return 0; +} + +static int __sd_uhs2_wait_active_state_cb(void *cb_data, bool *busy) +{ + struct sd_uhs2_wait_active_state_data *data = cb_data; + struct mmc_host *host = data->host; + struct mmc_command *cmd = data->cmd; + int err; + + err = mmc_wait_for_cmd(host, cmd, 0); + if (err) + return err; + + if (cmd->resp[1] & UHS2_DEV_CONFIG_GEN_SET_CFG_COMPLETE) + *busy = false; + else + *busy = true; + return 0; } +static int sd_uhs2_change_speed(struct mmc_host *host, u32 node_id) +{ + struct mmc_command cmd = {0}; + struct uhs2_command uhs2_cmd = {}; + u16 header, arg; + int err; + struct sd_uhs2_wait_active_state_data cb_data = { + .host = host, + .cmd = &cmd + }; + + /* Change Speed Range at controller side. */ + err = host->ops->uhs2_control(host, UHS2_SET_SPEED_B); + if (err) { + pr_err("%s: %s: UHS2 SET_SPEED fail!\n", mmc_hostname(host), __func__); + return err; + } + + err = sd_uhs2_go_dormant(host, node_id); + if (err) { + pr_err("%s: %s: UHS2 GO_DORMANT_STATE fail, err= 0x%x!\n", + mmc_hostname(host), __func__, err); + return err; + } + + /* + * Use Control Read CCMD to check Config Completion(bit 63) in Generic Setting Register. + * - Control Read(R/W=0) with 8-Byte payload(PLEN=10b). + * - IOADR = Generic Setting Register(CFG_BASE + 008h) + * + * When UHS-II card been switched to new speed mode, it will set Config Completion to 1. + */ + header = UHS2_NATIVE_PACKET | UHS2_PACKET_TYPE_CCMD | node_id; + arg = ((UHS2_DEV_CONFIG_GEN_SET & 0xFF) << 8) | + UHS2_NATIVE_CMD_READ | + UHS2_NATIVE_CMD_PLEN_8B | + (UHS2_DEV_CONFIG_GEN_SET >> 8); + + sd_uhs2_cmd_assemble(&cmd, &uhs2_cmd, header, arg, NULL, 0, NULL, 0); + err = __mmc_poll_for_busy(host, UHS2_WAIT_CFG_COMPLETE_PERIOD_US, + UHS2_WAIT_CFG_COMPLETE_TIMEOUT_MS, + &__sd_uhs2_wait_active_state_cb, &cb_data); + if (err) { + pr_err("%s: %s: Not switch to Active in 100 ms\n", mmc_hostname(host), __func__); + return err; + } + + return 0; +} + +static int sd_uhs2_get_ro(struct mmc_host *host) +{ + /* + * Some systems don't feature a write-protect pin and don't need one. + * E.g. because they only have micro-SD card slot. For those systems + * assume that the SD card is always read-write. + */ + if (host->caps2 & MMC_CAP2_NO_WRITE_PROTECT) + return 0; + + if (!host->ops->get_ro) + return -1; + + return host->ops->get_ro(host); +} + +/* + * Mask off any voltages we don't support and select + * the lowest voltage + */ +u32 sd_uhs2_select_voltage(struct mmc_host *host, u32 ocr) +{ + int bit; + int err; + + /* + * Sanity check the voltages that the card claims to + * support. + */ + if (ocr & 0x7F) { + dev_warn(mmc_dev(host), "card claims to support voltages below defined range\n"); + ocr &= ~0x7F; + } + + ocr &= host->ocr_avail; + if (!ocr) { + dev_warn(mmc_dev(host), "no support for card's volts\n"); + return 0; + } + + if (host->caps2 & MMC_CAP2_FULL_PWR_CYCLE) { + bit = ffs(ocr) - 1; + ocr &= 3 << bit; + /* Power cycle */ + err = sd_uhs2_power_off(host); + if (err) + return 0; + err = sd_uhs2_reinit(host); + if (err) + return 0; + } else { + bit = fls(ocr) - 1; + ocr &= 3 << bit; + if (bit != host->ios.vdd) + dev_warn(mmc_dev(host), "exceeding card's volts\n"); + } + + return ocr; +} + /* * Initialize the UHS-II card through the SD-TRAN transport layer. This enables * commands/requests to be backwards compatible through the legacy SD protocol. @@ -107,14 +893,149 @@ static int sd_uhs2_config_write(struct mmc_host *host, struct mmc_card *card) */ static int sd_uhs2_legacy_init(struct mmc_host *host, struct mmc_card *card) { + int err; + u32 cid[4]; + u32 ocr; + u32 rocr; + u8 *status; + int ro; + + /* Send CMD0 to reset SD card */ + err = __mmc_go_idle(host); + if (err) + return err; + + mmc_delay(1); + + /* Send CMD8 to communicate SD interface operation condition */ + err = mmc_send_if_cond(host, host->ocr_avail); + if (err) { + dev_warn(mmc_dev(host), "CMD8 error\n"); + return err; + } + + /* + * Probe SD card working voltage. + */ + err = mmc_send_app_op_cond(host, 0, &ocr); + if (err) + return err; + + card->ocr = ocr; + + /* + * Some SD cards claims an out of spec VDD voltage range. Let's treat + * these bits as being in-valid and especially also bit7. + */ + ocr &= ~0x7FFF; + rocr = sd_uhs2_select_voltage(host, ocr); + /* + * Some cards have zero value of rocr in UHS-II mode. Assign host's + * ocr value to rocr. + */ + if (!rocr) + rocr = host->ocr_avail; + + rocr |= (SD_OCR_CCS | SD_OCR_XPC); + + /* Wait SD power on ready */ + ocr = rocr; + + err = mmc_send_app_op_cond(host, ocr, &rocr); + if (err) + return err; + + err = mmc_send_cid(host, cid); + if (err) + return err; + + memcpy(card->raw_cid, cid, sizeof(card->raw_cid)); + mmc_decode_cid(card); + + /* + * For native busses: get card RCA and quit open drain mode. + */ + err = mmc_send_relative_addr(host, &card->rca); + if (err) + return err; + + err = mmc_sd_get_csd(card); + if (err) + return err; + + /* + * Select card, as all following commands rely on that. + */ + err = mmc_select_card(card); + if (err) + return err; + + /* + * Fetch SCR from card. + */ + err = mmc_app_send_scr(card); + if (err) + return err; + + err = mmc_decode_scr(card); + if (err) + return err; + + /* + * Switch to high power consumption mode. + * Even switch failed, sd card can still work at lower power consumption mode, but + * performance will be lower than high power consumption mode. + */ + status = kmalloc(64, GFP_KERNEL); + if (!status) + return -ENOMEM; + + if (!(card->csd.cmdclass & CCC_SWITCH)) { + pr_warn("%s: card lacks mandatory switch function, performance might suffer\n", + mmc_hostname(card->host)); + } else { + /* send CMD6 to set Maximum Power Consumption to get better performance */ + err = mmc_sd_switch(card, 0, 3, SD4_SET_POWER_LIMIT_1_80W, status); + if (!err) + err = mmc_sd_switch(card, 1, 3, SD4_SET_POWER_LIMIT_1_80W, status); + + err = 0; + } + + /* + * Check if read-only switch is active. + */ + ro = sd_uhs2_get_ro(host); + if (ro < 0) { + pr_warn("%s: host does not support read-only switch, assuming write-enable\n", + mmc_hostname(host)); + } else if (ro > 0) { + mmc_card_set_readonly(card); + } + + /* + * NOTE: + * Should we read Externsion Register to check power notification feature here? + */ + + kfree(status); + return 0; } +static void sd_uhs2_remove(struct mmc_host *host) +{ + mmc_remove_card(host->card); + host->card = NULL; + if (host->flags & MMC_UHS2_INITIALIZED) + host->flags &= ~MMC_UHS2_INITIALIZED; +} + /* * Allocate the data structure for the mmc_card and run the UHS-II specific * initialization sequence. */ -static int sd_uhs2_init_card(struct mmc_host *host) +static int sd_uhs2_init_card(struct mmc_host *host, struct mmc_card *oldcard) { struct mmc_card *card; u32 node_id; @@ -128,9 +1049,14 @@ static int sd_uhs2_init_card(struct mmc_host *host) if (err) return err; - card = mmc_alloc_card(host, &sd_type); - if (IS_ERR(card)) - return PTR_ERR(card); + if (oldcard) { + card = oldcard; + } else { + card = mmc_alloc_card(host, &sd_type); + if (IS_ERR(card)) + return PTR_ERR(card); + } + host->card = card; card->uhs2_config.node_id = node_id; card->type = MMC_TYPE_SD; @@ -143,22 +1069,47 @@ static int sd_uhs2_init_card(struct mmc_host *host) if (err) goto err; + /* Change to Speed Range B if it is supported */ + if (card->uhs2_state & MMC_UHS2_SPEED_B) { + err = sd_uhs2_change_speed(host, node_id); + if (err) + return err; + } + + host->card->uhs2_state |= MMC_UHS2_INITIALIZED; + host->flags |= MMC_UHS2_INITIALIZED; + err = sd_uhs2_legacy_init(host, card); if (err) goto err; - host->card = card; return 0; err: - mmc_remove_card(card); + if (host->card->uhs2_state & MMC_UHS2_INITIALIZED) + host->card->uhs2_state &= ~MMC_UHS2_INITIALIZED; + if (host->flags & MMC_UHS2_INITIALIZED) + host->flags &= ~MMC_UHS2_INITIALIZED; + sd_uhs2_remove(host); return err; } -static void sd_uhs2_remove(struct mmc_host *host) +int sd_uhs2_reinit(struct mmc_host *host) { - mmc_remove_card(host->card); - host->card = NULL; + struct mmc_card *card = host->card; + int err; + + sd_uhs2_power_up(host); + err = sd_uhs2_phy_init(host); + if (err) + return err; + + err = sd_uhs2_init_card(host, card); + if (err) + return err; + + mmc_card_set_present(card); + return err; } static int sd_uhs2_alive(struct mmc_host *host) @@ -184,34 +1135,176 @@ static void sd_uhs2_detect(struct mmc_host *host) } } +static int _sd_uhs2_suspend(struct mmc_host *host) +{ + struct mmc_card *card = host->card; + int err = 0; + + mmc_claim_host(host); + + if (mmc_card_suspended(card)) + goto out; + + if (mmc_card_can_poweroff_notify(card)) + err = sd_poweroff_notify(card); + + if (!err) { + sd_uhs2_power_off(host); + mmc_card_set_suspended(card); + } + +out: + mmc_release_host(host); + return err; +} + +/* + * Callback for suspend + */ static int sd_uhs2_suspend(struct mmc_host *host) { - return 0; + int err; + + err = _sd_uhs2_suspend(host); + if (!err) { + pm_runtime_disable(&host->card->dev); + pm_runtime_set_suspended(&host->card->dev); + } + + return err; +} + +/* + * This function tries to determine if the same card is still present + * and, if so, restore all state to it. + */ +static int _mmc_sd_uhs2_resume(struct mmc_host *host) +{ + int err = 0; + + mmc_claim_host(host); + + if (!mmc_card_suspended(host->card)) + goto out; + + /* Power up UHS2 SD card and re-initialize it. */ + err = sd_uhs2_reinit(host); + mmc_card_clr_suspended(host->card); + +out: + mmc_release_host(host); + return err; } +/* + * Callback for resume + */ static int sd_uhs2_resume(struct mmc_host *host) { + pm_runtime_enable(&host->card->dev); return 0; } +/* + * Callback for runtime_suspend. + */ static int sd_uhs2_runtime_suspend(struct mmc_host *host) { - return 0; + int err; + + if (!(host->caps & MMC_CAP_AGGRESSIVE_PM)) + return 0; + + err = _sd_uhs2_suspend(host); + if (err) + pr_err("%s: error %d doing aggressive suspend\n", mmc_hostname(host), err); + + return err; } static int sd_uhs2_runtime_resume(struct mmc_host *host) { - return 0; + int err; + + err = _mmc_sd_uhs2_resume(host); + if (err && err != -ENOMEDIUM) + pr_err("%s: error %d doing runtime resume\n", mmc_hostname(host), err); + + return err; } -static int sd_uhs2_shutdown(struct mmc_host *host) +static int sd_uhs2_hw_reset(struct mmc_host *host) { - return 0; + int err; + + sd_uhs2_power_off(host); + /* Wait at least 1 ms according to SD spec */ + mmc_delay(1); + sd_uhs2_power_up(host); + + err = sd_uhs2_reinit(host); + + return err; } -static int sd_uhs2_hw_reset(struct mmc_host *host) +/* + * mmc_uhs2_prepare_cmd - prepare for SD command packet + * @host: MMC host + * @mrq: MMC request + * + * Initialize and fill in a header and a payload of SD command packet. + * The caller should allocate uhs2_command in host->cmd->uhs2_cmd in + * advance. + * + * Return: 0 on success, non-zero error on failure + */ +void mmc_uhs2_prepare_cmd(struct mmc_host *host, struct mmc_request *mrq) { - return 0; + struct mmc_command *cmd; + struct uhs2_command *uhs2_cmd; + u16 header, arg; + __be32 *payload; + u8 plen; + + cmd = mrq->cmd; + header = host->card->uhs2_config.node_id; + if ((cmd->flags & MMC_CMD_MASK) == MMC_CMD_ADTC) + header |= UHS2_PACKET_TYPE_DCMD; + else + header |= UHS2_PACKET_TYPE_CCMD; + + arg = cmd->opcode << UHS2_SD_CMD_INDEX_POS; + if (host->uhs2_ios.is_APP_CMD) { + arg |= UHS2_SD_CMD_APP; + host->uhs2_ios.is_APP_CMD = false; + } + + uhs2_cmd = cmd->uhs2_cmd; + payload = uhs2_cmd->payload; + plen = 2; /* at the maximum */ + + if ((cmd->flags & MMC_CMD_MASK) == MMC_CMD_ADTC && + !cmd->uhs2_tmode0_flag) { + if (host->uhs2_ios.is_2L_HD_mode) + arg |= UHS2_DCMD_2L_HD_MODE; + + arg |= UHS2_DCMD_LM_TLEN_EXIST; + + if (cmd->data->blocks == 1 && + cmd->data->blksz != 512 && + cmd->opcode != MMC_READ_SINGLE_BLOCK && + cmd->opcode != MMC_WRITE_BLOCK) { + arg |= UHS2_DCMD_TLUM_BYTE_MODE; + payload[1] = cpu_to_be32(cmd->data->blksz); + } else { + payload[1] = cpu_to_be32(cmd->data->blocks); + } + } else { + plen = 1; + } + + payload[0] = cpu_to_be32(cmd->arg); + sd_uhs2_cmd_assemble(cmd, uhs2_cmd, header, arg, payload, plen, NULL, 0); } static const struct mmc_bus_ops sd_uhs2_ops = { @@ -222,7 +1315,7 @@ static const struct mmc_bus_ops sd_uhs2_ops = { .resume = sd_uhs2_resume, .runtime_suspend = sd_uhs2_runtime_suspend, .runtime_resume = sd_uhs2_runtime_resume, - .shutdown = sd_uhs2_shutdown, + .shutdown = sd_uhs2_suspend, .hw_reset = sd_uhs2_hw_reset, }; @@ -230,6 +1323,8 @@ static int sd_uhs2_attach(struct mmc_host *host) { int err; + host->flags |= MMC_UHS2_SUPPORT; + err = sd_uhs2_power_up(host); if (err) goto err; @@ -238,7 +1333,7 @@ static int sd_uhs2_attach(struct mmc_host *host) if (err) goto err; - err = sd_uhs2_init_card(host); + err = sd_uhs2_init_card(host, NULL); if (err) goto err; @@ -251,21 +1346,34 @@ static int sd_uhs2_attach(struct mmc_host *host) goto remove_card; mmc_claim_host(host); + + host->ops->uhs2_control(host, UHS2_POST_ATTACH_SD); + return 0; remove_card: - mmc_remove_card(host->card); - host->card = NULL; + sd_uhs2_remove(host); mmc_claim_host(host); - mmc_detach_bus(host); + err: + mmc_detach_bus(host); sd_uhs2_power_off(host); - return err; + host->flags &= ~MMC_UHS2_SUPPORT; + return 1; } +/** + * mmc_attach_sd_uhs2 - select UHS2 interface + * @host: MMC host + * + * Try to select UHS2 interface and initialize the bus for a given + * frequency, @freq. + * + * Return: 0 on success, non-zero error on failure + */ int mmc_attach_sd_uhs2(struct mmc_host *host) { - int i, err = 0; + int i, err; if (!(host->caps2 & MMC_CAP2_SD_UHS2)) return -EOPNOTSUPP; @@ -280,6 +1388,9 @@ int mmc_attach_sd_uhs2(struct mmc_host *host) */ for (i = 0; i < ARRAY_SIZE(sd_uhs2_freqs); i++) { host->f_init = sd_uhs2_freqs[i]; + pr_info("%s: %s: trying to init UHS-II card at %u Hz\n", + mmc_hostname(host), __func__, host->f_init); + err = sd_uhs2_attach(host); if (!err) break; From patchwork Tue Dec 13 09:00:30 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Victor Shih X-Patchwork-Id: 32701 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:8188:b0:89:790f:f786 with SMTP id m8csp3857584dye; Tue, 13 Dec 2022 01:03:44 -0800 (PST) X-Google-Smtp-Source: AA0mqf4fL172r3biXmHhAkPPPP1S4ZIyx7RUse3BgCZ5gQ9GOJKhWJ5jAxmd6eJPupdG+9YBiap/ X-Received: by 2002:a17:907:a80e:b0:7c1:7b39:faae with SMTP id vo14-20020a170907a80e00b007c17b39faaemr5032530ejc.58.1670922224558; Tue, 13 Dec 2022 01:03:44 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1670922224; cv=none; d=google.com; s=arc-20160816; b=HNQ4E3Y7e96rgvKpP72fNjfCyuvlg31oUTCDd2XAQcN/fGsuMcwyV0Qs9n0vW+nVDP 9+JCXVarG2DjuUP0FA3PnDURgmLX+i06GqvLq3x0bGsJOCwBXCQXc0GWbHYGQ5qC4srD NQ4hEoPL2YH1jbhE8qoVb3Ka08YVukd+6IOdjIgC27xzuqipq0rYsGSgrcOM27fKfUcA JB6kDDNiYzfu51MFN5y2bfSJaP+PMjxAQJ7vEZ0gu6c/YH92EXtAKaiW8r75JRxe7OOL m/YQeqyneZflhEFalqHwc5zK1XKb1WNdOkFSUwi/ow7WSPGKIy/FY0i4w/+fS7UeGhD2 eSVg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=ytvk6Xz9kzifECNnDPGurVJw5tqFf6L6QTQqC+AmSqc=; b=zWhgBbXYYShfF3H2aJsYyQuJDAdjQaIP4hzAo9H4wqJjbIwF9pFqnPylHMs/cSgk3q 0pRnZ9V6URwIlPQYAelKLAxumkbdzqm/57XSg8757nwoD3W+Kdq7rJCaEY0Hsl7Stwj9 HN6rrcaOHnrzTy3hV+V5PHDSe3m6XeGLPwEdHCiDjw0FydkfRCHkSp7+6rIyuRuB9qBh WDu5MFet5nur1nsez8uDiImsnsOCCNBZm9YFHb1pTMV1IjjuKd1ljcuhX/U/AlqOgqPQ OOHVk1Er3dgKTerts1Q5+j3SGCAd0RwVu4E8DgbRnKaK3R7Qd/CnGacWkKnKxxuLkHUw ijig== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20210112 header.b=CIhUIq5U; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id gs10-20020a1709072d0a00b007c0ef00a04fsi9058337ejc.434.2022.12.13.01.03.21; Tue, 13 Dec 2022 01:03:44 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@gmail.com header.s=20210112 header.b=CIhUIq5U; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234876AbiLMJCW (ORCPT + 99 others); Tue, 13 Dec 2022 04:02:22 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36064 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234831AbiLMJBv (ORCPT ); Tue, 13 Dec 2022 04:01:51 -0500 Received: from mail-pj1-x102d.google.com (mail-pj1-x102d.google.com [IPv6:2607:f8b0:4864:20::102d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5AFCA1114F; Tue, 13 Dec 2022 01:01:29 -0800 (PST) Received: by mail-pj1-x102d.google.com with SMTP id u15-20020a17090a3fcf00b002191825cf02so2856879pjm.2; Tue, 13 Dec 2022 01:01:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ytvk6Xz9kzifECNnDPGurVJw5tqFf6L6QTQqC+AmSqc=; b=CIhUIq5UhniYIgZQ4DL4hMT3qpylxnODQ6fABScb3Dv6rkXn7F90ZsliExUURmsNW2 6DIXgxRfo8IBXnodQq0xYI3UgxpX69vS86zlAK8lDUwJB2ZA2ZjOxz41wXCdzyh2d/B3 ot3lwDMiHV9kMJZwK76SHRB4C09/YJBAHztQAinOm3OuHolEZcvJ43gz4aGkgsZwmBc7 LKulGra0/u2/SgMzlY4XzYk9npwmYSki3VcdXQBpewwa9KQKsGHy2LJL3w3c+wa8W7Pn //L7cg1TnrXNmdgKQzvuibOfgTGQQBpKQWi2yGEY/pAbEhCdXEAGQbWt8c1lGCBA5S0W SeIQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ytvk6Xz9kzifECNnDPGurVJw5tqFf6L6QTQqC+AmSqc=; b=Kd2St/LxtsXCMuqnAWV7ux1E9Koa84n8ziG63m/wqNEn3ofVgeX5w3+tkHiyy79A8t SrohI0Dv7WQJJ9HwoPGQ8Mnd795Q6+QjTl0lSKKG8FhYw8r4tkJjYijkcoqm16JYAsNI 3Sa92pMwMFpTeR7AC/5M8OgT7q6IBobQXVx358Ynlv/obqeIANSBEulifBVuuLug1KtE 63hVugTOXt9g+8yqwaJOm+gAptT5Z4eIHTguHBxNRFwJUl0ZTGcgLYUpg0ap8hHsv6VQ tWtVi90PUMR49m1YX8sX5x6VE/e2rgLarf038UbdAVocdSN2xoNm19q6uCVWrJgE5LTd kqWQ== X-Gm-Message-State: ANoB5pmXLowo3DJxt0kt8uJpYQv4iivpMW0vUQmXv1cqYubc/qMknSLD 08+tflI/9MCApSpl2NzqBA0= X-Received: by 2002:a05:6a20:3f26:b0:ad:5cde:5beb with SMTP id az38-20020a056a203f2600b000ad5cde5bebmr9539213pzb.47.1670922088956; Tue, 13 Dec 2022 01:01:28 -0800 (PST) Received: from localhost.localdomain (2001-b400-e2dc-5c03-264b-f684-a8c9-21ae.emome-ip6.hinet.net. [2001:b400:e2dc:5c03:264b:f684:a8c9:21ae]) by smtp.gmail.com with ESMTPSA id 81-20020a621954000000b0056b9ec7e2desm7141682pfz.125.2022.12.13.01.01.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 13 Dec 2022 01:01:28 -0800 (PST) From: Victor Shih X-Google-Original-From: Victor Shih To: ulf.hansson@linaro.org, adrian.hunter@intel.com Cc: linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, benchuanggli@gmail.com, HL.Liu@genesyslogic.com.tw, Greg.tu@genesyslogic.com.tw, takahiro.akashi@linaro.org, dlunev@chromium.org, Victor Shih , Ben Chuang Subject: [PATCH V6 07/24] mmc: sdhci: add UHS-II related definitions in headers Date: Tue, 13 Dec 2022 17:00:30 +0800 Message-Id: <20221213090047.3805-8-victor.shih@genesyslogic.com.tw> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221213090047.3805-1-victor.shih@genesyslogic.com.tw> References: <20221213090047.3805-1-victor.shih@genesyslogic.com.tw> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM, RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,UPPERCASE_50_75 autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1752088942403986263?= X-GMAIL-MSGID: =?utf-8?q?1752088942403986263?= Add UHS-II related definitions in shdci.h and sdhci-uhs2.h. Signed-off-by: Ben Chuang Signed-off-by: AKASHI Takahiro Signed-off-by: Victor Shih --- drivers/mmc/host/sdhci-uhs2.h | 175 ++++++++++++++++++++++++++++++++++ drivers/mmc/host/sdhci.h | 62 +++++++++++- 2 files changed, 236 insertions(+), 1 deletion(-) create mode 100644 drivers/mmc/host/sdhci-uhs2.h diff --git a/drivers/mmc/host/sdhci-uhs2.h b/drivers/mmc/host/sdhci-uhs2.h new file mode 100644 index 000000000000..29cd91f12b9e --- /dev/null +++ b/drivers/mmc/host/sdhci-uhs2.h @@ -0,0 +1,175 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * linux/drivers/mmc/host/sdhci-uhs2.h - Secure Digital Host Controller + * Interface driver + * + * Header file for Host Controller UHS2 related registers. + * + * Copyright (C) 2014 Intel Corp, All Rights Reserved. + */ +#ifndef __SDHCI_UHS2_H +#define __SDHCI_UHS2_H + +#include + +/* SDHCI Category B registers : UHS2 only */ +#define SDHCI_UHS2_CM_TRAN_RESP 0x10 +#define SDHCI_UHS2_SD_TRAN_RESP 0x18 +#define SDHCI_UHS2_SD_TRAN_RESP_1 0x1C + +#define SDHCI_UHS2_BLOCK_SIZE 0x80 +#define SDHCI_UHS2_MAKE_BLKSZ(dma, blksz) ((((dma) & 0x7) << 12) | ((blksz) & 0xFFF)) + +#define SDHCI_UHS2_BLOCK_COUNT 0x84 + +#define SDHCI_UHS2_CMD_PACKET 0x88 +#define SDHCI_UHS2_CMD_PACK_MAX_LEN 20 + +#define SDHCI_UHS2_TRANS_MODE 0x9C +#define SDHCI_UHS2_TRNS_DMA BIT(0) +#define SDHCI_UHS2_TRNS_BLK_CNT_EN BIT(1) +#define SDHCI_UHS2_TRNS_DATA_TRNS_WRT BIT(4) +#define SDHCI_UHS2_TRNS_BLK_BYTE_MODE BIT(5) +#define SDHCI_UHS2_TRNS_RES_R5 BIT(6) +#define SDHCI_UHS2_TRNS_RES_ERR_CHECK_EN BIT(7) +#define SDHCI_UHS2_TRNS_RES_INT_DIS BIT(8) +#define SDHCI_UHS2_TRNS_WAIT_EBSY BIT(14) +#define SDHCI_UHS2_TRNS_2L_HD BIT(15) + +#define SDHCI_UHS2_CMD 0x9E +#define SDHCI_UHS2_CMD_SUB_CMD BIT(2) +#define SDHCI_UHS2_CMD_DATA BIT(5) +#define SDHCI_UHS2_CMD_TRNS_ABORT BIT(6) +#define SDHCI_UHS2_CMD_CMD12 BIT(7) +#define SDHCI_UHS2_CMD_DORMANT GENMASK(7, 6) +#define SDHCI_UHS2_CMD_PACK_LEN_MASK GENMASK(12, 8) + +#define SDHCI_UHS2_RESPONSE 0xA0 +#define SDHCI_UHS2_RESPONSE_MAX_LEN 20 + +#define SDHCI_UHS2_MSG_SELECT 0xB4 +#define SDHCI_UHS2_MSG_SELECT_CURR 0x0 +#define SDHCI_UHS2_MSG_SELECT_ONE 0x1 +#define SDHCI_UHS2_MSG_SELECT_TWO 0x2 +#define SDHCI_UHS2_MSG_SELECT_THREE 0x3 + +#define SDHCI_UHS2_MSG 0xB8 + +#define SDHCI_UHS2_DEV_INT_STATUS 0xBC + +#define SDHCI_UHS2_DEV_SELECT 0xBE +#define SDHCI_UHS2_DEV_SEL_MASK GENMASK(3, 0) +#define SDHCI_UHS2_DEV_SEL_INT_MSG_EN BIT(7) + +#define SDHCI_UHS2_DEV_INT_CODE 0xBF + +#define SDHCI_UHS2_SW_RESET 0xC0 +#define SDHCI_UHS2_SW_RESET_FULL BIT(0) +#define SDHCI_UHS2_SW_RESET_SD BIT(1) + +#define SDHCI_UHS2_TIMER_CTRL 0xC2 +#define SDHCI_UHS2_TIMER_CTRL_DEADLOCK_MASK GENMASK(7, 4) + +#define SDHCI_UHS2_INT_STATUS 0xC4 +#define SDHCI_UHS2_INT_STATUS_ENABLE 0xC8 +#define SDHCI_UHS2_INT_SIGNAL_ENABLE 0xCC +#define SDHCI_UHS2_INT_HEADER_ERR BIT(0) +#define SDHCI_UHS2_INT_RES_ERR BIT(1) +#define SDHCI_UHS2_INT_RETRY_EXP BIT(2) +#define SDHCI_UHS2_INT_CRC BIT(3) +#define SDHCI_UHS2_INT_FRAME_ERR BIT(4) +#define SDHCI_UHS2_INT_TID_ERR BIT(5) +#define SDHCI_UHS2_INT_UNRECOVER BIT(7) +#define SDHCI_UHS2_INT_EBUSY_ERR BIT(8) +#define SDHCI_UHS2_INT_ADMA_ERROR BIT(15) +#define SDHCI_UHS2_INT_CMD_TIMEOUT BIT(16) +#define SDHCI_UHS2_INT_DEADLOCK_TIMEOUT BIT(17) +#define SDHCI_UHS2_INT_VENDOR_ERR BIT(27) +#define SDHCI_UHS2_INT_ERROR_MASK \ + (SDHCI_UHS2_INT_HEADER_ERR | \ + SDHCI_UHS2_INT_RES_ERR | \ + SDHCI_UHS2_INT_RETRY_EXP | \ + SDHCI_UHS2_INT_CRC | \ + SDHCI_UHS2_INT_FRAME_ERR | \ + SDHCI_UHS2_INT_TID_ERR | \ + SDHCI_UHS2_INT_UNRECOVER | \ + SDHCI_UHS2_INT_EBUSY_ERR | \ + SDHCI_UHS2_INT_ADMA_ERROR | \ + SDHCI_UHS2_INT_CMD_TIMEOUT | \ + SDHCI_UHS2_INT_DEADLOCK_TIMEOUT) +#define SDHCI_UHS2_INT_CMD_ERR_MASK \ + (SDHCI_UHS2_INT_HEADER_ERR | \ + SDHCI_UHS2_INT_RES_ERR | \ + SDHCI_UHS2_INT_FRAME_ERR | \ + SDHCI_UHS2_INT_TID_ERR | \ + SDHCI_UHS2_INT_CMD_TIMEOUT) +/* CRC Error occurs during a packet receiving */ +#define SDHCI_UHS2_INT_DATA_ERR_MASK \ + (SDHCI_UHS2_INT_RETRY_EXP | \ + SDHCI_UHS2_INT_CRC | \ + SDHCI_UHS2_INT_UNRECOVER | \ + SDHCI_UHS2_INT_EBUSY_ERR | \ + SDHCI_UHS2_INT_ADMA_ERROR | \ + SDHCI_UHS2_INT_DEADLOCK_TIMEOUT) + +#define SDHCI_UHS2_SETTINGS_PTR 0xE0 +#define SDHCI_UHS2_GEN_SETTINGS_POWER_LOW BIT(0) +#define SDHCI_UHS2_GEN_SETTINGS_N_LANES_MASK GENMASK(11, 8) +#define SDHCI_UHS2_FD_OR_2L_HD 0x0 /* 2 lanes */ +#define SDHCI_UHS2_2D1U_FD 0x2 /* 3 lanes, 2 down, 1 up, full duplex */ +#define SDHCI_UHS2_1D2U_FD 0x3 /* 3 lanes, 1 down, 2 up, full duplex */ +#define SDHCI_UHS2_2D2U_FD 0x4 /* 4 lanes, 2 down, 2 up, full duplex */ + +#define SDHCI_UHS2_PHY_SET_SPEED_B BIT(6) +#define SDHCI_UHS2_PHY_HIBERNATE_EN BIT(12) +#define SDHCI_UHS2_PHY_N_LSS_SYN_MASK GENMASK(19, 16) +#define SDHCI_UHS2_PHY_N_LSS_DIR_MASK GENMASK(23, 20) + +#define SDHCI_UHS2_TRAN_N_FCU_MASK GENMASK(15, 8) +#define SDHCI_UHS2_TRAN_RETRY_CNT_MASK GENMASK(17, 16) +#define SDHCI_UHS2_TRAN_1_N_DAT_GAP_MASK GENMASK(7, 0) + +#define SDHCI_UHS2_CAPS_PTR 0xE2 +#define SDHCI_UHS2_CAPS_OFFSET 0 +#define SDHCI_UHS2_CAPS_DAP_MASK GENMASK(3, 0) +#define SDHCI_UHS2_CAPS_GAP_MASK GENMASK(7, 4) +#define SDHCI_UHS2_CAPS_GAP(gap) ((gap) * 360) +#define SDHCI_UHS2_CAPS_LANE_MASK GENMASK(13, 8) +#define SDHCI_UHS2_CAPS_2L_HD_FD 1 +#define SDHCI_UHS2_CAPS_2D1U_FD 2 +#define SDHCI_UHS2_CAPS_1D2U_FD 4 +#define SDHCI_UHS2_CAPS_2D2U_FD 8 +#define SDHCI_UHS2_CAPS_ADDR_64 BIT(14) +#define SDHCI_UHS2_CAPS_BOOT BIT(15) +#define SDHCI_UHS2_CAPS_DEV_TYPE_MASK GENMASK(17, 16) +#define SDHCI_UHS2_CAPS_DEV_TYPE_RMV 0 +#define SDHCI_UHS2_CAPS_DEV_TYPE_EMB 1 +#define SDHCI_UHS2_CAPS_DEV_TYPE_EMB_RMV 2 +#define SDHCI_UHS2_CAPS_NUM_DEV_MASK GENMASK(21, 18) +#define SDHCI_UHS2_CAPS_BUS_TOPO_MASK GENMASK(23, 22) +#define SDHCI_UHS2_CAPS_BUS_TOPO_SHIFT 22 +#define SDHCI_UHS2_CAPS_BUS_TOPO_P2P 0 +#define SDHCI_UHS2_CAPS_BUS_TOPO_RING 1 +#define SDHCI_UHS2_CAPS_BUS_TOPO_HUB 2 +#define SDHCI_UHS2_CAPS_BUS_TOPO_HUB_RING 3 + +#define SDHCI_UHS2_CAPS_PHY_OFFSET 4 +#define SDHCI_UHS2_CAPS_PHY_REV_MASK GENMASK(5, 0) +#define SDHCI_UHS2_CAPS_PHY_RANGE_MASK GENMASK(7, 6) +#define SDHCI_UHS2_CAPS_PHY_RANGE_A 0 +#define SDHCI_UHS2_CAPS_PHY_RANGE_B 1 +#define SDHCI_UHS2_CAPS_PHY_N_LSS_SYN_MASK GENMASK(19, 16) +#define SDHCI_UHS2_CAPS_PHY_N_LSS_DIR_MASK GENMASK(23, 20) +#define SDHCI_UHS2_CAPS_TRAN_OFFSET 8 +#define SDHCI_UHS2_CAPS_TRAN_LINK_REV_MASK GENMASK(5, 0) +#define SDHCI_UHS2_CAPS_TRAN_N_FCU_MASK GENMASK(15, 8) +#define SDHCI_UHS2_CAPS_TRAN_HOST_TYPE_MASK GENMASK(18, 16) +#define SDHCI_UHS2_CAPS_TRAN_BLK_LEN_MASK GENMASK(31, 20) + +#define SDHCI_UHS2_CAPS_TRAN_1_OFFSET 12 +#define SDHCI_UHS2_CAPS_TRAN_1_N_DATA_GAP_MASK GENMASK(7, 0) + +#define SDHCI_UHS2_EMBED_CTRL_PTR 0xE6 +#define SDHCI_UHS2_VENDOR_PTR 0xE8 + +#endif /* __SDHCI_UHS2_H */ diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h index 605eaee805f7..40125ecd4e3f 100644 --- a/drivers/mmc/host/sdhci.h +++ b/drivers/mmc/host/sdhci.h @@ -43,8 +43,23 @@ #define SDHCI_TRNS_READ 0x10 #define SDHCI_TRNS_MULTI 0x20 +/* + * Defined in Host Version 4.0. + */ +#define SDHCI_TRNS_RES_TYPE 0x40 +#define SDHCI_TRNS_RES_ERR_CHECK 0x80 +#define SDHCI_TRNS_RES_INT_DIS 0x0100 + #define SDHCI_COMMAND 0x0E #define SDHCI_CMD_RESP_MASK 0x03 + +/* + * Host Version 4.10 adds this bit to distinguish a main command or + * sub command. + * For example with SDIO, CMD52 (sub command) issued during CMD53 (main command). + */ +#define SDHCI_CMD_SUB_CMD 0x04 + #define SDHCI_CMD_CRC 0x08 #define SDHCI_CMD_INDEX 0x10 #define SDHCI_CMD_DATA 0x20 @@ -65,6 +80,9 @@ #define SDHCI_PRESENT_STATE 0x24 #define SDHCI_CMD_INHIBIT 0x00000001 #define SDHCI_DATA_INHIBIT 0x00000002 + +#define SDHCI_DAT_4_TO_7_LVL_MASK 0x000000F0 + #define SDHCI_DOING_WRITE 0x00000100 #define SDHCI_DOING_READ 0x00000200 #define SDHCI_SPACE_AVAILABLE 0x00000400 @@ -80,6 +98,15 @@ #define SDHCI_DATA_0_LVL_MASK 0x00100000 #define SDHCI_CMD_LVL 0x01000000 +/* Host Version 4.10 */ + +#define SDHCI_HOST_REGULATOR_STABLE 0x02000000 +#define SDHCI_CMD_NOT_ISSUED_ERR 0x08000000 +#define SDHCI_SUB_CMD_STATUS 0x10000000 +#define SDHCI_UHS2_IN_DORMANT_STATE 0x20000000 +#define SDHCI_UHS2_LANE_SYNC 0x40000000 +#define SDHCI_UHS2_IF_DETECT 0x80000000 + #define SDHCI_HOST_CONTROL 0x28 #define SDHCI_CTRL_LED 0x01 #define SDHCI_CTRL_4BITBUS 0x02 @@ -100,6 +127,14 @@ #define SDHCI_POWER_300 0x0C #define SDHCI_POWER_330 0x0E +/* + * VDD2 - UHS2 + * VDD2 power on/off and voltage select (UHS2) + */ +#define SDHCI_VDD2_POWER_ON 0x10 +#define SDHCI_VDD2_POWER_120 0x80 +#define SDHCI_VDD2_POWER_180 0xA0 + #define SDHCI_BLOCK_GAP_CONTROL 0x2A #define SDHCI_WAKE_UP_CONTROL 0x2B @@ -110,7 +145,7 @@ #define SDHCI_CLOCK_CONTROL 0x2C #define SDHCI_DIVIDER_SHIFT 8 #define SDHCI_DIVIDER_HI_SHIFT 6 -#define SDHCI_DIV_MASK 0xFF +#define SDHCI_DIV_MASK 0xFF #define SDHCI_DIV_MASK_LEN 8 #define SDHCI_DIV_HI_MASK 0x300 #define SDHCI_PROG_CLOCK_MODE 0x0020 @@ -139,6 +174,10 @@ #define SDHCI_INT_CARD_REMOVE 0x00000080 #define SDHCI_INT_CARD_INT 0x00000100 #define SDHCI_INT_RETUNE 0x00001000 + +/* Host Version 4.10 */ +#define SDHCI_INT_FX_EVENT 0x00002000 + #define SDHCI_INT_CQE 0x00004000 #define SDHCI_INT_ERROR 0x00008000 #define SDHCI_INT_TIMEOUT 0x00010000 @@ -152,6 +191,9 @@ #define SDHCI_INT_AUTO_CMD_ERR 0x01000000 #define SDHCI_INT_ADMA_ERROR 0x02000000 +/* Host Version 4.0 */ +#define SDHCI_INT_RESP_ERR 0x08000000 + #define SDHCI_INT_NORMAL_MASK 0x00007FFF #define SDHCI_INT_ERROR_MASK 0xFFFF8000 @@ -178,6 +220,9 @@ #define SDHCI_AUTO_CMD_END_BIT 0x00000008 #define SDHCI_AUTO_CMD_INDEX 0x00000010 +/* Host Version 4.10 */ +#define SDHCI_AUTO_CMD_RESP_ERR 0x0020 + #define SDHCI_HOST_CONTROL2 0x3E #define SDHCI_CTRL_UHS_MASK 0x0007 #define SDHCI_CTRL_UHS_SDR12 0x0000 @@ -186,6 +231,7 @@ #define SDHCI_CTRL_UHS_SDR104 0x0003 #define SDHCI_CTRL_UHS_DDR50 0x0004 #define SDHCI_CTRL_HS400 0x0005 /* Non-standard */ +#define SDHCI_CTRL_UHS2 0x0007 #define SDHCI_CTRL_VDD_180 0x0008 #define SDHCI_CTRL_DRV_TYPE_MASK 0x0030 #define SDHCI_CTRL_DRV_TYPE_B 0x0000 @@ -194,9 +240,12 @@ #define SDHCI_CTRL_DRV_TYPE_D 0x0030 #define SDHCI_CTRL_EXEC_TUNING 0x0040 #define SDHCI_CTRL_TUNED_CLK 0x0080 +#define SDHCI_CTRL_UHS2_ENABLE 0x0100 +#define SDHCI_CTRL_ADMA2_LEN_MODE 0x0400 #define SDHCI_CMD23_ENABLE 0x0800 #define SDHCI_CTRL_V4_MODE 0x1000 #define SDHCI_CTRL_64BIT_ADDR 0x2000 +#define SDHCI_CTRL_ASYNC_INT_ENABLE 0x4000 #define SDHCI_CTRL_PRESET_VAL_ENABLE 0x8000 #define SDHCI_CAPABILITIES 0x40 @@ -219,11 +268,13 @@ #define SDHCI_CAN_VDD_180 0x04000000 #define SDHCI_CAN_64BIT_V4 0x08000000 #define SDHCI_CAN_64BIT 0x10000000 +#define SDHCI_CAN_ASYNC_INT 0x20000000 #define SDHCI_CAPABILITIES_1 0x44 #define SDHCI_SUPPORT_SDR50 0x00000001 #define SDHCI_SUPPORT_SDR104 0x00000002 #define SDHCI_SUPPORT_DDR50 0x00000004 +#define SDHCI_SUPPORT_UHS2 0x00000008 #define SDHCI_DRIVER_TYPE_A 0x00000010 #define SDHCI_DRIVER_TYPE_C 0x00000020 #define SDHCI_DRIVER_TYPE_D 0x00000040 @@ -232,6 +283,7 @@ #define SDHCI_RETUNING_MODE_MASK GENMASK(15, 14) #define SDHCI_CLOCK_MUL_MASK GENMASK(23, 16) #define SDHCI_CAN_DO_ADMA3 0x08000000 +#define SDHCI_CAN_VDD2_180 0x10000000 /* UHS-2 1.8V VDD2 */ #define SDHCI_SUPPORT_HS400 0x80000000 /* Non-standard */ #define SDHCI_MAX_CURRENT 0x48 @@ -239,11 +291,14 @@ #define SDHCI_MAX_CURRENT_330_MASK GENMASK(7, 0) #define SDHCI_MAX_CURRENT_300_MASK GENMASK(15, 8) #define SDHCI_MAX_CURRENT_180_MASK GENMASK(23, 16) +#define SDHCI_MAX_CURRENT_1 0x4C +#define SDHCI_MAX_CURRENT_VDD2_180_MASK GENMASK(7, 0) /* UHS2 */ #define SDHCI_MAX_CURRENT_MULTIPLIER 4 /* 4C-4F reserved for more max current */ #define SDHCI_SET_ACMD12_ERROR 0x50 +/* Host Version 4.10 */ #define SDHCI_SET_INT_ERROR 0x52 #define SDHCI_ADMA_ERROR 0x54 @@ -262,10 +317,15 @@ #define SDHCI_PRESET_FOR_SDR104 0x6C #define SDHCI_PRESET_FOR_DDR50 0x6E #define SDHCI_PRESET_FOR_HS400 0x74 /* Non-standard */ + +/* UHS2 */ +#define SDHCI_PRESET_FOR_UHS2 0x74 #define SDHCI_PRESET_DRV_MASK GENMASK(15, 14) #define SDHCI_PRESET_CLKGEN_SEL BIT(10) #define SDHCI_PRESET_SDCLK_FREQ_MASK GENMASK(9, 0) +#define SDHCI_ADMA3_ADDRESS 0x78 + #define SDHCI_SLOT_INT_STATUS 0xFC #define SDHCI_HOST_VERSION 0xFE From patchwork Tue Dec 13 09:00:31 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Victor Shih X-Patchwork-Id: 32699 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:8188:b0:89:790f:f786 with SMTP id m8csp3857542dye; Tue, 13 Dec 2022 01:03:40 -0800 (PST) X-Google-Smtp-Source: AA0mqf4BjjlOTAJfcnR8EWRU4UyS+kydwwQsHmXAa1Kcs3uvaMswXFZ+siiyYiHBkHmrqTP7NDFG X-Received: by 2002:a17:902:d706:b0:189:e55d:ec72 with SMTP id w6-20020a170902d70600b00189e55dec72mr21353423ply.20.1670922219951; Tue, 13 Dec 2022 01:03:39 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1670922219; cv=none; d=google.com; s=arc-20160816; b=pIpwyCJB+eiNGPYyrzZqe/8EuSDLOamfn1mp73w3O1wwWf7Qq54lb953bgPtdzatVD tC6pq2VaI6vEkWn2L32gqo8D8D9ScyWWQrJHM770YF6olwo9BJridDaCv3uHljliqd1z CnBJes/a0Yy+amHTbJD9LALXyDQ4MHG3Qu1rEqahX1AxwGPfSQTUlBuKdYNgCxzXVVOv pIqXe2sreLfkh12Sx25+0MDZ2XkTHvVSYKzajxk5BgdLElZq/kiK6x1nC6r56/2u4MYk 4W5OnQFYc68ooCFJpB45NVgpEm7bYfhICEr4dtHvN7PqH6m+ontaBGI1Omw3u/hi4ix3 ZMmg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=2sXYhJoMzlxiwjXEZUM0Ha5ReBVwS6vY1uXLUoOzHOc=; b=RdG0kKhG4yPi5q3QA775I6v9PJ9TeVmK2zVQCUqflGz+mqTITUUvo/YFS7fPK2qyZ/ RwTly/YXwnGdNydJEwGCzhdWntXyantvYEWjGcyYQKEic5chqP/B/ZROl4bEyjn8gCXm GlUIPIQyfbbYE+MLzxYvz17X5XHtSHJYn/oA1wWDZDQQb+47yKXE9NOtG3Dpm6LoBUby UMHV0QBnAf09oGtyRoxy74JC5iNKxpUQFVIiS0Fo8m0vMJyyigELsVuFAZR4bJVazXUH n/7YM7t0PFO2RDXuBTVJt8HUp1ZrwUTLRioMu1+wQmVpOBI2Z5bsX32fpZXackUz043N OgMg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20210112 header.b="S/OM8wgc"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id u14-20020a170903124e00b001836e510540si13058367plh.114.2022.12.13.01.03.26; Tue, 13 Dec 2022 01:03:39 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@gmail.com header.s=20210112 header.b="S/OM8wgc"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234909AbiLMJC3 (ORCPT + 99 others); Tue, 13 Dec 2022 04:02:29 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36130 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234916AbiLMJBw (ORCPT ); Tue, 13 Dec 2022 04:01:52 -0500 Received: from mail-pj1-x102e.google.com (mail-pj1-x102e.google.com [IPv6:2607:f8b0:4864:20::102e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CEE59186EE; Tue, 13 Dec 2022 01:01:32 -0800 (PST) Received: by mail-pj1-x102e.google.com with SMTP id w4-20020a17090ac98400b002186f5d7a4cso2903998pjt.0; Tue, 13 Dec 2022 01:01:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=2sXYhJoMzlxiwjXEZUM0Ha5ReBVwS6vY1uXLUoOzHOc=; b=S/OM8wgcUV6b12rVdm+rLyNcWnPdg461uEV9DLlcAK2tAT2OylxVZKWYow7/A8iS/t IsxnaY84X+0MF6ZmEVaczan3YLH0IiVeN+ceuafYrpBySNtsHUXFhTfOBXM+e+ChBvsz TB1JvN6ZQ7w++VuOIC7uXt0m0c3J1+BOXPCzexKt0jfdfs8sc/2YFsOX3YtiWX899lkb uH16WPVSun34z1GOB5GLOP25nvJzArenMlpEeJKbZSZkSI78/1ATf62Qv/NTEZFOIIal t3H705Tdwz+8VGr3s/pxOkLEGyCGHLXCIuCWH/W9tT224MVKvDgeYOiwSFf72HxWMSsf us0A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=2sXYhJoMzlxiwjXEZUM0Ha5ReBVwS6vY1uXLUoOzHOc=; b=B0mhJ2qNTL4dLJjgLG5Qxe85B36/DgOAbPXYyYIAtQfDLs6iZieUJYIFqYRqi9OVqB hI9XiHYK/ByMSl/nWtj5leHRkZ+8u/Y7pjfF/o1344HSE48/a8FRGyHhAzqb2W1et6sL QE+l8qTmB/7D4x7Gv6GvnSEQ+7nLMI5+sdd2NQccF+5OKQ9rmEdtniC1UHobh04yJERz v5jieCYz4WOxYva0KYd7TXX7s7Rj4RK0hFa0esM+Wkayp9jURr1VSRa9F/qD/I/MJcO3 HWsoPI5hDkOuhYi0rXgvoCnRz5KX08qKqPieCpNO7CkeJP8OmSS0lulUTS9c42cWPKiS 697g== X-Gm-Message-State: ANoB5pkvw6WsIwer1fzekbTbK+ypERyQU6JJOPr7EU4lGRdntnvlxlcC Mww4OfTrnYeagpTkfSrPzPU= X-Received: by 2002:a05:6a20:4e1c:b0:ac:82ff:9f88 with SMTP id gk28-20020a056a204e1c00b000ac82ff9f88mr23736903pzb.12.1670922092177; Tue, 13 Dec 2022 01:01:32 -0800 (PST) Received: from localhost.localdomain (2001-b400-e2dc-5c03-264b-f684-a8c9-21ae.emome-ip6.hinet.net. [2001:b400:e2dc:5c03:264b:f684:a8c9:21ae]) by smtp.gmail.com with ESMTPSA id 81-20020a621954000000b0056b9ec7e2desm7141682pfz.125.2022.12.13.01.01.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 13 Dec 2022 01:01:31 -0800 (PST) From: Victor Shih X-Google-Original-From: Victor Shih To: ulf.hansson@linaro.org, adrian.hunter@intel.com Cc: linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, benchuanggli@gmail.com, HL.Liu@genesyslogic.com.tw, Greg.tu@genesyslogic.com.tw, takahiro.akashi@linaro.org, dlunev@chromium.org, Victor Shih , Ben Chuang Subject: [PATCH V6 08/24] mmc: sdhci: add UHS-II module and add a kernel configuration Date: Tue, 13 Dec 2022 17:00:31 +0800 Message-Id: <20221213090047.3805-9-victor.shih@genesyslogic.com.tw> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221213090047.3805-1-victor.shih@genesyslogic.com.tw> References: <20221213090047.3805-1-victor.shih@genesyslogic.com.tw> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM, RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1752088937699806814?= X-GMAIL-MSGID: =?utf-8?q?1752088937699806814?= This patch adds sdhci-uhs2.c as a module for UHS-II support. This is a skelton for further development in this patch series. This kernel configuration, CONFIG_MMC_SDHCI_UHS2, will be used in the following commits to indicate UHS-II specific code in sdhci controllers. Signed-off-by: Ben Chuang Signed-off-by: AKASHI Takahiro Signed-off-by: Victor Shih --- drivers/mmc/host/Kconfig | 9 +++++++ drivers/mmc/host/Makefile | 1 + drivers/mmc/host/sdhci-uhs2.c | 46 +++++++++++++++++++++++++++++++++++ 3 files changed, 56 insertions(+) create mode 100644 drivers/mmc/host/sdhci-uhs2.c diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig index 5e19a961c34d..9c22370fb778 100644 --- a/drivers/mmc/host/Kconfig +++ b/drivers/mmc/host/Kconfig @@ -98,6 +98,15 @@ config MMC_SDHCI_BIG_ENDIAN_32BIT_BYTE_SWAPPER This is the case for the Nintendo Wii SDHCI. +config MMC_SDHCI_UHS2 + tristate "UHS2 support on SDHCI controller" + depends on MMC_SDHCI + help + This option is selected by SDHCI controller drivers that want to + support UHS2-capable devices. + + If you have a controller with this feature, say Y or M here. + config MMC_SDHCI_PCI tristate "SDHCI support on PCI bus" depends on MMC_SDHCI && PCI diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile index ba0c6d0cd85d..ac1dd27fca3a 100644 --- a/drivers/mmc/host/Makefile +++ b/drivers/mmc/host/Makefile @@ -11,6 +11,7 @@ obj-$(CONFIG_MMC_PXA) += pxamci.o obj-$(CONFIG_MMC_MXC) += mxcmmc.o obj-$(CONFIG_MMC_MXS) += mxs-mmc.o obj-$(CONFIG_MMC_SDHCI) += sdhci.o +obj-$(CONFIG_MMC_SDHCI_UHS2) += sdhci-uhs2.o obj-$(CONFIG_MMC_SDHCI_PCI) += sdhci-pci.o sdhci-pci-y += sdhci-pci-core.o sdhci-pci-o2micro.o sdhci-pci-arasan.o \ sdhci-pci-dwc-mshc.o sdhci-pci-gli.o diff --git a/drivers/mmc/host/sdhci-uhs2.c b/drivers/mmc/host/sdhci-uhs2.c new file mode 100644 index 000000000000..8e15bd0dadee --- /dev/null +++ b/drivers/mmc/host/sdhci-uhs2.c @@ -0,0 +1,46 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * linux/drivers/mmc/host/sdhci_uhs2.c - Secure Digital Host Controller + * Interface driver + * + * Copyright (C) 2014 Intel Corp, All Rights Reserved. + * Copyright (C) 2020 Genesys Logic, Inc. + * Authors: Ben Chuang + * Copyright (C) 2020 Linaro Limited + * Author: AKASHI Takahiro + */ + +#include + +#include "sdhci.h" +#include "sdhci-uhs2.h" + +#define DRIVER_NAME "sdhci_uhs2" +#define DBG(f, x...) \ + pr_debug(DRIVER_NAME " [%s()]: " f, __func__, ## x) + +/*****************************************************************************\ + * * + * Driver init/exit * + * * +\*****************************************************************************/ + +static int sdhci_uhs2_host_ops_init(struct sdhci_host *host) +{ + return 0; +} + +static int __init sdhci_uhs2_mod_init(void) +{ + return 0; +} +module_init(sdhci_uhs2_mod_init); + +static void __exit sdhci_uhs2_mod_exit(void) +{ +} +module_exit(sdhci_uhs2_mod_exit); + +MODULE_AUTHOR("Intel, Genesys Logic, Linaro"); +MODULE_DESCRIPTION("MMC UHS-II Support"); +MODULE_LICENSE("GPL v2"); From patchwork Tue Dec 13 09:00:32 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Victor Shih X-Patchwork-Id: 32703 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:8188:b0:89:790f:f786 with SMTP id m8csp3857642dye; Tue, 13 Dec 2022 01:03:51 -0800 (PST) X-Google-Smtp-Source: AA0mqf6ow4KQYY7rXEOGimnyhlnnJqbmrcG27bHJpA/9io82DOimEsWsEyv9AsHSzstu+SRMcYO3 X-Received: by 2002:a17:906:7808:b0:7c1:61a6:2cd2 with SMTP id u8-20020a170906780800b007c161a62cd2mr9343709ejm.9.1670922231544; Tue, 13 Dec 2022 01:03:51 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1670922231; cv=none; d=google.com; s=arc-20160816; b=uGNeCmv1QGt12AWTNb+x09dafPw5k6M3s3cTzgpPiMHPIuKylKJ2K1Xwsc5OrnYOt8 SfHFhTqNPd4rWwVi7yNGI1GePPRpQsuXry14LztcsB0lJc+8QGLlIZcUZbqzSwDSC3KC Shz24nqE6POdoMadf289kdB/w4N0jSygqiHWN9nfCypju4W0c43yw1NO7DGkNgSIVYlL jxNhQcBfWIXxzvOVO43pN1wnR9j4tTe/hbVQJHgh/NbO5SlWW6ynomLoZo9mIvlXxoed 1hvpqVjB1RKuCvz8CGipkdtOBLE9/7P0DIysqkwAWsytghV/e0tNzBee+xJXkRl4ne26 x/zQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=7XwvhZ+/VRqupa5ETJWo4Tptp3RsfHxQZbyoSduVWd8=; b=PzfN9xwkXMXY6XF0SPWzQHqNaf2sY3xJv21//SVR9C3Mar0wlhQ4LilglGa0HMCuk4 N78DcCTNqWWhlEu5O6qlfElaWeohUF7ZPREXfX5IIdJBI8S/jvkDt5OVp8SbPFjyZTml 8aNpjHKD3XMeGmJd3SSytWaLBERGCg/ywIQClkpb4pskpe6jMJ/WKb3AwtIe5Sp19RdK 9l8NLNZuyMZvOhvGta9ZLKylEnMtLStCsM51KVxcJzhi0qj6DTeijALgxQdfJOyL2KCw SnzyvB3lcuZgJvfNuH8vLblO2lxg+Cr6+v67XFMZ/AzrQrgs6rQd7X2eJN7fQehktrLG F4zw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20210112 header.b=gXxnyw1o; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id us11-20020a170906bfcb00b007add8160fd9si5908832ejb.765.2022.12.13.01.03.28; Tue, 13 Dec 2022 01:03:51 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@gmail.com header.s=20210112 header.b=gXxnyw1o; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234930AbiLMJCe (ORCPT + 99 others); Tue, 13 Dec 2022 04:02:34 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36534 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234947AbiLMJB6 (ORCPT ); Tue, 13 Dec 2022 04:01:58 -0500 Received: from mail-pf1-x42a.google.com (mail-pf1-x42a.google.com [IPv6:2607:f8b0:4864:20::42a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 017C3F5AE; Tue, 13 Dec 2022 01:01:37 -0800 (PST) Received: by mail-pf1-x42a.google.com with SMTP id 130so1726695pfu.8; Tue, 13 Dec 2022 01:01:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=7XwvhZ+/VRqupa5ETJWo4Tptp3RsfHxQZbyoSduVWd8=; b=gXxnyw1oTmLEcKfWZi0bHZ74hgNT9y0B5uFMwHE5WBnTeKkq+UcXXvYnObDvMzLX7e UqqN4QB+g4RFrRAZEduAtGrdxGYoaxqjADqb+nfBMe/BAgOMvG1pcfkJXkkJ6ta0nDxu slmAOOKy1FyIqAHQoSSdI9NOgjhA3vGoWCj1kD9iVHjkVGDwJ3poOHTUz6bHFatFI7zU XQ7N0zXAFfnihWKr92VZoke0cspgjGHYbF8Lu/dhQZG7mPWeehVt0Pb2JGAqrJ8u098E DRD7ENDgSfTagGMXV5NikvUlYYam5q34zu5DP78UAfqazjM0+JT1OWo/8nFRHULMNeXz O6eA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=7XwvhZ+/VRqupa5ETJWo4Tptp3RsfHxQZbyoSduVWd8=; b=oZ/oVzAbXDJBZNT6aczc/BobuEDNPdpl/5Yw8gPyeZWoGW49tgOctbWGm1jF9ojvM5 NEfjZ7Qrbcgn1pR+bRYLX1zzSQEiKBmLKeDW0iAVScmevKBJvOX7PlZAb5BtoeKqtLOe /k9jokciVaJSyaJ+vOfTQ+fUhGnzzWl9tc1ngqH5LMe8SAuEfK6GMdBnfFB5Sa3lRECE ey/1C4mEcA84GnecZJ5Cod7aqhHIhNhtwGFvR6K8Z+Db3zRFDUoYBe3JfgG1CBJzjhai 2VcpsyIZ7yHVb1INP8Z63EyRdsz1kEFtyolsT9xYCP2JkLba9BkVc7A4Z/tCJz/7mTkj V+Eg== X-Gm-Message-State: ANoB5pk/ZksusSqRKeZcOO6xPvoY0/mwXbZHs1TBstdTpTXtKok8k4HG kHWN78NmtS4UXrPqbWDRwd4= X-Received: by 2002:a05:6a00:1e:b0:576:e704:d8c3 with SMTP id h30-20020a056a00001e00b00576e704d8c3mr18880443pfk.23.1670922096504; Tue, 13 Dec 2022 01:01:36 -0800 (PST) Received: from localhost.localdomain (2001-b400-e2dc-5c03-264b-f684-a8c9-21ae.emome-ip6.hinet.net. [2001:b400:e2dc:5c03:264b:f684:a8c9:21ae]) by smtp.gmail.com with ESMTPSA id 81-20020a621954000000b0056b9ec7e2desm7141682pfz.125.2022.12.13.01.01.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 13 Dec 2022 01:01:34 -0800 (PST) From: Victor Shih X-Google-Original-From: Victor Shih To: ulf.hansson@linaro.org, adrian.hunter@intel.com Cc: linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, benchuanggli@gmail.com, HL.Liu@genesyslogic.com.tw, Greg.tu@genesyslogic.com.tw, takahiro.akashi@linaro.org, dlunev@chromium.org, Victor Shih , Ben Chuang Subject: [PATCH V6 09/24] mmc: sdhci-uhs2: dump UHS-II registers Date: Tue, 13 Dec 2022 17:00:32 +0800 Message-Id: <20221213090047.3805-10-victor.shih@genesyslogic.com.tw> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221213090047.3805-1-victor.shih@genesyslogic.com.tw> References: <20221213090047.3805-1-victor.shih@genesyslogic.com.tw> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM, RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1752088950036241154?= X-GMAIL-MSGID: =?utf-8?q?1752088950036241154?= Dump UHS-II specific registers, if available, in sdhci_dumpregs() for informative/debugging use. Signed-off-by: Ben Chuang Signed-off-by: AKASHI Takahiro Signed-off-by: Victor Shih --- drivers/mmc/host/sdhci-uhs2.c | 30 ++++++++++++++++++++++++++++++ drivers/mmc/host/sdhci-uhs2.h | 4 ++++ drivers/mmc/host/sdhci.c | 3 +++ drivers/mmc/host/sdhci.h | 1 + 4 files changed, 38 insertions(+) diff --git a/drivers/mmc/host/sdhci-uhs2.c b/drivers/mmc/host/sdhci-uhs2.c index 8e15bd0dadee..7ea15f06fa99 100644 --- a/drivers/mmc/host/sdhci-uhs2.c +++ b/drivers/mmc/host/sdhci-uhs2.c @@ -18,6 +18,36 @@ #define DRIVER_NAME "sdhci_uhs2" #define DBG(f, x...) \ pr_debug(DRIVER_NAME " [%s()]: " f, __func__, ## x) +#define SDHCI_UHS2_DUMP(f, x...) \ + pr_err("%s: " DRIVER_NAME ": " f, mmc_hostname(host->mmc), ## x) + +void sdhci_uhs2_dump_regs(struct sdhci_host *host) +{ + if (!(host->mmc->flags & MMC_UHS2_SUPPORT)) + return; + + SDHCI_UHS2_DUMP("==================== UHS2 ==================\n"); + SDHCI_UHS2_DUMP("Blk Size: 0x%08x | Blk Cnt: 0x%08x\n", + sdhci_readw(host, SDHCI_UHS2_BLOCK_SIZE), + sdhci_readl(host, SDHCI_UHS2_BLOCK_COUNT)); + SDHCI_UHS2_DUMP("Cmd: 0x%08x | Trn mode: 0x%08x\n", + sdhci_readw(host, SDHCI_UHS2_CMD), + sdhci_readw(host, SDHCI_UHS2_TRANS_MODE)); + SDHCI_UHS2_DUMP("Int Stat: 0x%08x | Dev Sel : 0x%08x\n", + sdhci_readw(host, SDHCI_UHS2_DEV_INT_STATUS), + sdhci_readb(host, SDHCI_UHS2_DEV_SELECT)); + SDHCI_UHS2_DUMP("Dev Int Code: 0x%08x\n", + sdhci_readb(host, SDHCI_UHS2_DEV_INT_CODE)); + SDHCI_UHS2_DUMP("Reset: 0x%08x | Timer: 0x%08x\n", + sdhci_readw(host, SDHCI_UHS2_SW_RESET), + sdhci_readw(host, SDHCI_UHS2_TIMER_CTRL)); + SDHCI_UHS2_DUMP("ErrInt: 0x%08x | ErrIntEn: 0x%08x\n", + sdhci_readl(host, SDHCI_UHS2_INT_STATUS), + sdhci_readl(host, SDHCI_UHS2_INT_STATUS_ENABLE)); + SDHCI_UHS2_DUMP("ErrSigEn: 0x%08x\n", + sdhci_readl(host, SDHCI_UHS2_INT_SIGNAL_ENABLE)); +} +EXPORT_SYMBOL_GPL(sdhci_uhs2_dump_regs); /*****************************************************************************\ * * diff --git a/drivers/mmc/host/sdhci-uhs2.h b/drivers/mmc/host/sdhci-uhs2.h index 29cd91f12b9e..a1fcd7899829 100644 --- a/drivers/mmc/host/sdhci-uhs2.h +++ b/drivers/mmc/host/sdhci-uhs2.h @@ -172,4 +172,8 @@ #define SDHCI_UHS2_EMBED_CTRL_PTR 0xE6 #define SDHCI_UHS2_VENDOR_PTR 0xE8 +struct sdhci_host; + +void sdhci_uhs2_dump_regs(struct sdhci_host *host); + #endif /* __SDHCI_UHS2_H */ diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c index f3af1bd0f7b9..9b66b9a32c72 100644 --- a/drivers/mmc/host/sdhci.c +++ b/drivers/mmc/host/sdhci.c @@ -110,6 +110,9 @@ void sdhci_dumpregs(struct sdhci_host *host) } } + if (host->ops->dump_uhs2_regs) + host->ops->dump_uhs2_regs(host); + if (host->ops->dump_vendor_regs) host->ops->dump_vendor_regs(host); diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h index 40125ecd4e3f..f41c19c76994 100644 --- a/drivers/mmc/host/sdhci.h +++ b/drivers/mmc/host/sdhci.h @@ -723,6 +723,7 @@ struct sdhci_ops { void (*request_done)(struct sdhci_host *host, struct mmc_request *mrq); void (*dump_vendor_regs)(struct sdhci_host *host); + void (*dump_uhs2_regs)(struct sdhci_host *host); }; #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS From patchwork Tue Dec 13 09:00:33 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Victor Shih X-Patchwork-Id: 32700 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:8188:b0:89:790f:f786 with SMTP id m8csp3857585dye; Tue, 13 Dec 2022 01:03:44 -0800 (PST) X-Google-Smtp-Source: AA0mqf4q+vxjSBfOTsTlYxR7tqcZezVpDSxXP0DKpkRC7qbZn80lk+uZuddoIBtjbcASGFW61zyi X-Received: by 2002:a17:90a:f3c2:b0:219:38b7:4809 with SMTP id ha2-20020a17090af3c200b0021938b74809mr20306950pjb.39.1670922224607; Tue, 13 Dec 2022 01:03:44 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1670922224; cv=none; d=google.com; s=arc-20160816; b=tjVu50x8dho8AQvrjzZ7NP+QFw2Bqvk1MahcPwfCkINyxvQ4Ssq+NzWoDYKXEhpuFV NfFAywUiKyNj2QoF0S3DeE5/JCrmqiT1MQYgGTgz57yYhuTT4S7YJUYMfEJb6p1OXwfV Nvai7fzEB+LLBk8H9uCI1JX6ViXvMyJsfZjCTwDpJjnq9Ht79Q2tvqaRoWlMxeEHXJEu AddVbrrxvzuWd0sIphSK27M2QjChPgALl23skwFtSTCrXIwIYk2rJUl7wdCj9CI3g9yE ivJIEBgyy2xFb8XMdXFztpU8EP0QxV5zExnNrCzyMSM/W8qPa/D/cAVHDJJE4n5ytsyb F2dw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=0e0Zz1TO8qYEsDMf3o3pWG/i9MXpgx+hqEniREfvFtU=; b=WfcZ0LU11wtx5vXj72MScQEVymc7LiMaHBB1B2J1U1O1+mytgnZ3YeIQIzHDp/9Xtu 8kDP1uz2hDP0NcdO9g5qOM1yWBX8L3Vw9NuySM6CkD0L/pvOaTflr3SD1P8SrazbcftY fZW65iUE3xhFE8WbxPyaR0C9cYBhY+F3Bu0sTKxM/FGBPn2AikmQUf1euvGlCpxtedRY ZmfoweG3CRzPcKiPnXYFRcLTo1wGqGmi7fm5Bjkib0b4vLEVlJ3Pecn0Y/ldCxPefiqQ DBZC4PEvqxoFnStfdTThOVa59RlQ2rJ6y9VJRsNDSU3iUag9TuIMcuc7TClInRbwWngV rUeA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20210112 header.b="T34PB8/8"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id y8-20020a17090a474800b0021904a75d86si11590890pjg.32.2022.12.13.01.03.31; Tue, 13 Dec 2022 01:03:44 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@gmail.com header.s=20210112 header.b="T34PB8/8"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234963AbiLMJCu (ORCPT + 99 others); Tue, 13 Dec 2022 04:02:50 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36026 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234969AbiLMJCC (ORCPT ); Tue, 13 Dec 2022 04:02:02 -0500 Received: from mail-pg1-x52e.google.com (mail-pg1-x52e.google.com [IPv6:2607:f8b0:4864:20::52e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BBD401AF02; Tue, 13 Dec 2022 01:01:40 -0800 (PST) Received: by mail-pg1-x52e.google.com with SMTP id 82so10019828pgc.0; Tue, 13 Dec 2022 01:01:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=0e0Zz1TO8qYEsDMf3o3pWG/i9MXpgx+hqEniREfvFtU=; b=T34PB8/8sh9lrWai2hPI6Jo3+AMebb4VsS0skYzisOmkUp1H3Ggcsg+jadp7MpW+gv ftN9aTZx6rSdudGOPr4jRvLL+gKyN5Wovu5JsyfPBaWhxfF6btIGvBxggrKd6Y1dlERK HrepvWLSyEeDyNWPtX/cmbg5hvXCMynnNKy1aNLxpEyBgcejRP2qJi6WTQefFCyF8qAi yMT0qtz+AlTT9NbryKrzRq1emJc6uymIq2PGCoUiACnXKI+16+cnYgD0brvH3VEP1ykD ktKebsoxydjNf58dt5lag4bCuAv9Ad4GTkEewhv+UNdGEDid26zbMMj3Qslf7D3lvosT VMAA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=0e0Zz1TO8qYEsDMf3o3pWG/i9MXpgx+hqEniREfvFtU=; b=GQOkwyvMHqxiOxjZzk4PdFmkhe5MdROz9mdDVn7uX8lLbz2n/jY7HA00uTtqIclN9T 7G+11dXIsKOjUQ3FWgbQ+96QlHK3qPFSA+M8F9t3idvAn6bKtk7sPbaqkgfoWLetUUGN Dt/VNa3p95/LsAtG8Dpz0wC0rOMIekuTgesvrE76n4ez/yF7eHnIXUX/f3cc+3smD/JF w4XRJcIAbfmU3UJG/7eaZIEZv1JTKec3nTxLbG7aUlm1dN2zcTTNr7o19eS8XLRfdN6k V6GFW0uylw8G2Lrsw992NnW28MouytGYmgMT4C8jasehS+IZKA152Cd8EDBW044Jlxr7 vcHA== X-Gm-Message-State: ANoB5pl4fgfhjgy1C4yes2DtGLkqY/2G22c6GHitVrG7ovcu9y+J9R4z zz3mNa+OElxtqz2DAItL4EQ= X-Received: by 2002:a05:6a00:188b:b0:576:9eed:61de with SMTP id x11-20020a056a00188b00b005769eed61demr25838723pfh.4.1670922100392; Tue, 13 Dec 2022 01:01:40 -0800 (PST) Received: from localhost.localdomain (2001-b400-e2dc-5c03-264b-f684-a8c9-21ae.emome-ip6.hinet.net. [2001:b400:e2dc:5c03:264b:f684:a8c9:21ae]) by smtp.gmail.com with ESMTPSA id 81-20020a621954000000b0056b9ec7e2desm7141682pfz.125.2022.12.13.01.01.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 13 Dec 2022 01:01:39 -0800 (PST) From: Victor Shih X-Google-Original-From: Victor Shih To: ulf.hansson@linaro.org, adrian.hunter@intel.com Cc: linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, benchuanggli@gmail.com, HL.Liu@genesyslogic.com.tw, Greg.tu@genesyslogic.com.tw, takahiro.akashi@linaro.org, dlunev@chromium.org, Victor Shih , Ben Chuang Subject: [PATCH V6 10/24] mmc: sdhci-uhs2: add reset function and uhs2_mode function Date: Tue, 13 Dec 2022 17:00:33 +0800 Message-Id: <20221213090047.3805-11-victor.shih@genesyslogic.com.tw> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221213090047.3805-1-victor.shih@genesyslogic.com.tw> References: <20221213090047.3805-1-victor.shih@genesyslogic.com.tw> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM, RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1752088942240458139?= X-GMAIL-MSGID: =?utf-8?q?1752088942240458139?= Sdhci_uhs2_reset() does a UHS-II specific reset operation. Signed-off-by: Ben Chuang Signed-off-by: AKASHI Takahiro Signed-off-by: Victor Shih --- drivers/mmc/host/sdhci-uhs2.c | 46 +++++++++++++++++++++++++++++++++++ drivers/mmc/host/sdhci-uhs2.h | 2 ++ 2 files changed, 48 insertions(+) diff --git a/drivers/mmc/host/sdhci-uhs2.c b/drivers/mmc/host/sdhci-uhs2.c index 7ea15f06fa99..ae862e1eadab 100644 --- a/drivers/mmc/host/sdhci-uhs2.c +++ b/drivers/mmc/host/sdhci-uhs2.c @@ -10,7 +10,9 @@ * Author: AKASHI Takahiro */ +#include #include +#include #include "sdhci.h" #include "sdhci-uhs2.h" @@ -49,6 +51,50 @@ void sdhci_uhs2_dump_regs(struct sdhci_host *host) } EXPORT_SYMBOL_GPL(sdhci_uhs2_dump_regs); +/*****************************************************************************\ + * * + * Low level functions * + * * +\*****************************************************************************/ + +bool sdhci_uhs2_mode(struct sdhci_host *host) +{ + return host->mmc->flags & MMC_UHS2_SUPPORT; +} + +/** + * sdhci_uhs2_reset - invoke SW reset + * @host: SDHCI host + * @mask: Control mask + * + * Invoke SW reset, depending on a bit in @mask and wait for completion. + */ +void sdhci_uhs2_reset(struct sdhci_host *host, u16 mask) +{ + unsigned long timeout; + u32 val; + + sdhci_writew(host, mask, SDHCI_UHS2_SW_RESET); + + if (mask & SDHCI_UHS2_SW_RESET_FULL) + host->clock = 0; + + /* Wait max 100 ms */ + timeout = 100000; + + /* hw clears the bit when it's done */ + if (read_poll_timeout_atomic(sdhci_readw, val, !(val & mask), 10, + timeout, true, host, SDHCI_UHS2_SW_RESET)) { + pr_err("%s: %s: Reset 0x%x never completed.\n", + __func__, mmc_hostname(host->mmc), (int)mask); + pr_err("%s: clean reset bit\n", + mmc_hostname(host->mmc)); + sdhci_writeb(host, 0, SDHCI_UHS2_SW_RESET); + return; + } +} +EXPORT_SYMBOL_GPL(sdhci_uhs2_reset); + /*****************************************************************************\ * * * Driver init/exit * diff --git a/drivers/mmc/host/sdhci-uhs2.h b/drivers/mmc/host/sdhci-uhs2.h index a1fcd7899829..03b9f6675cdc 100644 --- a/drivers/mmc/host/sdhci-uhs2.h +++ b/drivers/mmc/host/sdhci-uhs2.h @@ -175,5 +175,7 @@ struct sdhci_host; void sdhci_uhs2_dump_regs(struct sdhci_host *host); +bool sdhci_uhs2_mode(struct sdhci_host *host); +void sdhci_uhs2_reset(struct sdhci_host *host, u16 mask); #endif /* __SDHCI_UHS2_H */ From patchwork Tue Dec 13 09:00:34 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Victor Shih X-Patchwork-Id: 32702 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:8188:b0:89:790f:f786 with SMTP id m8csp3857607dye; Tue, 13 Dec 2022 01:03:46 -0800 (PST) X-Google-Smtp-Source: AA0mqf4zJE4c1oMyBiwBoAJKEWPmceaYJonJbL0HFniYbINH41E1sFPsvVN/QxSW1NOaqtBJlJAj X-Received: by 2002:a17:90b:4a8c:b0:219:e763:1d21 with SMTP id lp12-20020a17090b4a8c00b00219e7631d21mr20502099pjb.5.1670922226185; Tue, 13 Dec 2022 01:03:46 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1670922226; cv=none; d=google.com; s=arc-20160816; b=kwtA49A2yv9PutA4bXpzP7l9KAzaH6YhXBY+7oFzQd1pDWOr5UtLKBcibJPPjj/BZQ 6Xr1SzkAvJOegnod+BK0K9ObVB2J13v3fQfGJNO/i6iadgz6qslgrYL2T7cfj21NqfAS /zTAPdoNFVG7EsLuxB4o11tXr/Ytz6Qln/0eixhu9PL0HmDwBASHph5gPrxBmvPHIMHX UtByRlRy6Qr/5NS+lJiLkQR5Cwfx0afvxRUIy/bLKCZHI+HC/hSnYTU16rMs7bheHV4g anSNZ1Peg+HtP7s+FBCbsctR9SiNfSrzKoldl9I+qxH0uPVqTitsUK2TsFMiGszW4cqw 2AQQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=FLdW/4JhcA/FBpV6VuVkXlXWUSLT0iXj+6y89s8Gs48=; b=FEctEd06Ggu7Ma7WAWDCDxFztzGGQd8Emus5jV7+ZPEGskNQHePMI/+tF12Th+Wtk1 FYAs/S/HRCPha16p+datqFzNtk8HAbBDsOi6e6xMQWO9RnSNp/fJYDMb2gJchZhfHcnN KblY6+YO2mqcXseFE5YSwvnPUheOJ6T47OUciuAaIn0zVe+wK2SczenngIjPNMN1wDjp s1FrRq5+Jjc7ZNIYUn/kXYVld9cosECtcSySdaYY6N3RpwyPrAljvv2h0J/XHPaoLZwS fWaK+5gXLHQwWD7Q4WeQaxsJJFoVq01OeKHeXVRE4R47MSRoS0IgiCoUlAOv8+bU3DfG NqrQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20210112 header.b=VQk31gV2; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id b10-20020a17090a800a00b0021872a7d873si954839pjn.57.2022.12.13.01.03.33; Tue, 13 Dec 2022 01:03:46 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@gmail.com header.s=20210112 header.b=VQk31gV2; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234986AbiLMJDE (ORCPT + 99 others); Tue, 13 Dec 2022 04:03:04 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36106 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234980AbiLMJCE (ORCPT ); Tue, 13 Dec 2022 04:02:04 -0500 Received: from mail-pf1-x436.google.com (mail-pf1-x436.google.com [IPv6:2607:f8b0:4864:20::436]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 61B5B1B1DC; Tue, 13 Dec 2022 01:01:44 -0800 (PST) Received: by mail-pf1-x436.google.com with SMTP id a14so1749823pfa.1; Tue, 13 Dec 2022 01:01:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=FLdW/4JhcA/FBpV6VuVkXlXWUSLT0iXj+6y89s8Gs48=; b=VQk31gV22yzNYD9p5E9Nlo8U0EybYLZV/LMTt69a5IB0aYYhirBcj6tSTmEvsfPEKd JI7c99OYHYjJ4aVe3ffXAhvahC3o3XJUbBHE2pV6S9mz7KX3C4f3uhdqzw5UE3PowFjK exBX1eZBNOD8V1abSx4XdXZCdLx26/5j1S1J0N9qX+ieX+o/eyM2/JJBY8EDwvZq37l3 btMKad9Ikof42tPzd1D22wkptSt1qkaFfmlhwcbkW4jCO4ctO8neq+sZSZYcc08AWWzA mDPvk0iN/A5jUxuqAwe/MuSOtPtyaZZeRjwgHXT2t36dlaIbl/sR3iqy6nTh8vc9oFV7 N92Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=FLdW/4JhcA/FBpV6VuVkXlXWUSLT0iXj+6y89s8Gs48=; b=a0J6NKCcqZl3zQhmA+IOOgBIJaqx+E8OJqMF8aT4mALZbMLCXrWP8hAP3MCaFpMmmG XsJ9sSS1/qhsWk/hUcxb21SyGMrey/r+HDqSs04JH9qu6hXvPQURwkQXG0mpm35eeh77 JmqDwQbvYtB5EQRsYfQ+dxbqMq59plv2jAYEyPKre9qZ7ED+90aI0U1Eid7RLxzx8sgX 2G+dGu473nPxcgU50vFFl6tMotm965xu27kmP+wt7A0mQBEbZs9pvqG0QcF956zAD+K9 kgJ2End1IM1+VYDXJBVeoLpeWKNaNnADSu4Z1DYJbSJCtWFPUJgJGCyE4jwlv89htfUi XbjA== X-Gm-Message-State: ANoB5pmgKOZiPqELyHLm07glntZGz7YvGa/7xv+v6bifS56NfRv5lClM ufzrmKRzIoJ7YiXBAF6kfbI= X-Received: by 2002:aa7:920e:0:b0:566:900d:a1de with SMTP id 14-20020aa7920e000000b00566900da1demr18596953pfo.26.1670922103881; Tue, 13 Dec 2022 01:01:43 -0800 (PST) Received: from localhost.localdomain (2001-b400-e2dc-5c03-264b-f684-a8c9-21ae.emome-ip6.hinet.net. [2001:b400:e2dc:5c03:264b:f684:a8c9:21ae]) by smtp.gmail.com with ESMTPSA id 81-20020a621954000000b0056b9ec7e2desm7141682pfz.125.2022.12.13.01.01.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 13 Dec 2022 01:01:43 -0800 (PST) From: Victor Shih X-Google-Original-From: Victor Shih To: ulf.hansson@linaro.org, adrian.hunter@intel.com Cc: linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, benchuanggli@gmail.com, HL.Liu@genesyslogic.com.tw, Greg.tu@genesyslogic.com.tw, takahiro.akashi@linaro.org, dlunev@chromium.org, Victor Shih , Ben Chuang Subject: [PATCH V6 11/24] mmc: sdhci-uhs2: add set_power() to support vdd2 Date: Tue, 13 Dec 2022 17:00:34 +0800 Message-Id: <20221213090047.3805-12-victor.shih@genesyslogic.com.tw> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221213090047.3805-1-victor.shih@genesyslogic.com.tw> References: <20221213090047.3805-1-victor.shih@genesyslogic.com.tw> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM, RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1752088944224849173?= X-GMAIL-MSGID: =?utf-8?q?1752088944224849173?= This is a UHS-II version of sdhci's set_power operation. VDD2, as well as VDD, is handled here. Signed-off-by: Ben Chuang Signed-off-by: AKASHI Takahiro Signed-off-by: Victor Shih --- drivers/mmc/host/sdhci-uhs2.c | 46 +++++++++++++++++++++++++ drivers/mmc/host/sdhci.c | 63 +++++++++++++++++++---------------- drivers/mmc/host/sdhci.h | 1 + 3 files changed, 82 insertions(+), 28 deletions(-) diff --git a/drivers/mmc/host/sdhci-uhs2.c b/drivers/mmc/host/sdhci-uhs2.c index ae862e1eadab..780491781613 100644 --- a/drivers/mmc/host/sdhci-uhs2.c +++ b/drivers/mmc/host/sdhci-uhs2.c @@ -57,6 +57,13 @@ EXPORT_SYMBOL_GPL(sdhci_uhs2_dump_regs); * * \*****************************************************************************/ +static inline int mmc_opt_regulator_set_ocr(struct mmc_host *mmc, + struct regulator *supply, + unsigned short vdd_bit) +{ + return IS_ERR_OR_NULL(supply) ? 0 : mmc_regulator_set_ocr(mmc, supply, vdd_bit); +} + bool sdhci_uhs2_mode(struct sdhci_host *host) { return host->mmc->flags & MMC_UHS2_SUPPORT; @@ -95,6 +102,45 @@ void sdhci_uhs2_reset(struct sdhci_host *host, u16 mask) } EXPORT_SYMBOL_GPL(sdhci_uhs2_reset); +static void sdhci_uhs2_set_power(struct sdhci_host *host, unsigned char mode, + unsigned short vdd) +{ + struct mmc_host *mmc = host->mmc; + u8 pwr; + + if (mode != MMC_POWER_OFF) { + pwr = sdhci_get_vdd_value(vdd); + if (!pwr) + WARN(1, "%s: Invalid vdd %#x\n", + mmc_hostname(host->mmc), vdd); + pwr |= SDHCI_VDD2_POWER_180; + } + + if (host->pwr == pwr) + return; + host->pwr = pwr; + + if (pwr == 0) { + sdhci_writeb(host, 0, SDHCI_POWER_CONTROL); + + mmc_opt_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); + mmc_opt_regulator_set_ocr(mmc, mmc->supply.vmmc2, 0); + } else { + mmc_opt_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd); + /* support 1.8v only for now */ + mmc_opt_regulator_set_ocr(mmc, mmc->supply.vmmc2, fls(MMC_VDD2_165_195) - 1); + + /* vdd first */ + pwr |= SDHCI_POWER_ON; + sdhci_writeb(host, pwr & 0xf, SDHCI_POWER_CONTROL); + mdelay(5); + + pwr |= SDHCI_VDD2_POWER_ON; + sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL); + mdelay(5); + } +} + /*****************************************************************************\ * * * Driver init/exit * diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c index 9b66b9a32c72..99633a3ef549 100644 --- a/drivers/mmc/host/sdhci.c +++ b/drivers/mmc/host/sdhci.c @@ -23,7 +23,7 @@ #include #include #include - +#include #include #include @@ -2061,41 +2061,48 @@ static void sdhci_set_power_reg(struct sdhci_host *host, unsigned char mode, sdhci_writeb(host, 0, SDHCI_POWER_CONTROL); } +unsigned short sdhci_get_vdd_value(unsigned short vdd) +{ + u8 pwr; + + switch (1 << vdd) { + case MMC_VDD_165_195: + /* + * Without a regulator, SDHCI does not support 2.0v + * so we only get here if the driver deliberately + * added the 2.0v range to ocr_avail. Map it to 1.8v + * for the purpose of turning on the power. + */ + case MMC_VDD_20_21: + pwr = SDHCI_POWER_180; + break; + case MMC_VDD_29_30: + case MMC_VDD_30_31: + pwr = SDHCI_POWER_300; + break; + case MMC_VDD_32_33: + case MMC_VDD_33_34: + pwr = SDHCI_POWER_330; + break; + default: + pwr = 0; + break; + } + + return pwr; +} +EXPORT_SYMBOL_GPL(sdhci_get_vdd_value); + void sdhci_set_power_noreg(struct sdhci_host *host, unsigned char mode, unsigned short vdd) { u8 pwr = 0; if (mode != MMC_POWER_OFF) { - switch (1 << vdd) { - case MMC_VDD_165_195: - /* - * Without a regulator, SDHCI does not support 2.0v - * so we only get here if the driver deliberately - * added the 2.0v range to ocr_avail. Map it to 1.8v - * for the purpose of turning on the power. - */ - case MMC_VDD_20_21: - pwr = SDHCI_POWER_180; - break; - case MMC_VDD_29_30: - case MMC_VDD_30_31: - pwr = SDHCI_POWER_300; - break; - case MMC_VDD_32_33: - case MMC_VDD_33_34: - /* - * 3.4 ~ 3.6V are valid only for those platforms where it's - * known that the voltage range is supported by hardware. - */ - case MMC_VDD_34_35: - case MMC_VDD_35_36: - pwr = SDHCI_POWER_330; - break; - default: + pwr = sdhci_get_vdd_value(vdd); + if (!pwr) { WARN(1, "%s: Invalid vdd %#x\n", mmc_hostname(host->mmc), vdd); - break; } } diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h index f41c19c76994..df7fa0c0ebf8 100644 --- a/drivers/mmc/host/sdhci.h +++ b/drivers/mmc/host/sdhci.h @@ -840,6 +840,7 @@ void sdhci_set_power(struct sdhci_host *host, unsigned char mode, void sdhci_set_power_and_bus_voltage(struct sdhci_host *host, unsigned char mode, unsigned short vdd); +unsigned short sdhci_get_vdd_value(unsigned short vdd); void sdhci_set_power_noreg(struct sdhci_host *host, unsigned char mode, unsigned short vdd); int sdhci_get_cd_nogpio(struct mmc_host *mmc); From patchwork Tue Dec 13 09:00:35 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Victor Shih X-Patchwork-Id: 32704 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:8188:b0:89:790f:f786 with SMTP id m8csp3857710dye; Tue, 13 Dec 2022 01:04:00 -0800 (PST) X-Google-Smtp-Source: AA0mqf72trydU0bCeTvM8wtu3H26eYGUfDFG3hDnILnM6V0o2TZ7fqCWyEaP496JE7SXf9y8W70B X-Received: by 2002:a05:6a20:bc82:b0:ad:79bb:7487 with SMTP id fx2-20020a056a20bc8200b000ad79bb7487mr10348789pzb.50.1670922240082; Tue, 13 Dec 2022 01:04:00 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1670922240; cv=none; d=google.com; s=arc-20160816; b=WmUOpFArwXKqGE8C+UgQiw4KmLQP3hnwnhV4PMtN0HKmeCho4o7yAvxGFLRLS4uYI+ /UWMgXW9G9S7NblNAdABVffAokfF4wLrX73oIzLAHaqGdRTHBMXt3QxvHLCczVTLmgGp iIy//WyoQyghCXUBn/PUFW7a7PRk+aDgGWirKg8SHc5efxMr5kzCOT0vW+S4kImb/bRH 4zYASx1XrQujkv9y27XeknaYwt5clcKHNjuq5tNU6/9L/55Vq15fNOqmIM47kFSJX1j7 bY+go7rGyq+JrfWi3PRRcXRASUSBU7lPaNaE385cVWOdvsmrqgNrxttoBJOFxivkkcmc Urlg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=infOJYAuY6NmVdfocqokUhNUb9UCZ9ojC/z55HJcvas=; b=tS1kRgld/igcQ257x3LgyOAq1lEmapaCokr/pnM/1ZNDDFoneVJ5v9qCHaE4U+jhpe H4lTmHSO3flGZ3Rx9An7nXijgyJYpL2UDnt7QxHYdHGDkjvQANOCOEpqqmn1abHSbyMH 5uz5x1HFbUmB9429LJqSQTW75bde3J8WiCIHiahCtFWPti2fibk6O65COtqb0k99MJKW 0OlNK0UDfvkWBov/tfHbJPKTWBcDvMkVk1/lFZuDs357b0NJn+dVvW1HWRYtxaPBBOjR btip8Jf2v1f2qK/HPNYPRuhjeSyk5JDkdvU9z7rfKsGf8heyHixYBh9P6Ns8pLgyoSZq 0ZHw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20210112 header.b=Lnku68LJ; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id a38-20020a634d26000000b00476990d057asi11934629pgb.472.2022.12.13.01.03.46; Tue, 13 Dec 2022 01:04:00 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@gmail.com header.s=20210112 header.b=Lnku68LJ; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234998AbiLMJDK (ORCPT + 99 others); Tue, 13 Dec 2022 04:03:10 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36610 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234989AbiLMJCE (ORCPT ); Tue, 13 Dec 2022 04:02:04 -0500 Received: from mail-pf1-x429.google.com (mail-pf1-x429.google.com [IPv6:2607:f8b0:4864:20::429]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A7B26FD0B; Tue, 13 Dec 2022 01:01:47 -0800 (PST) Received: by mail-pf1-x429.google.com with SMTP id 124so1775654pfy.0; Tue, 13 Dec 2022 01:01:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=infOJYAuY6NmVdfocqokUhNUb9UCZ9ojC/z55HJcvas=; b=Lnku68LJeyCc6DpE9eI2IZL7Ilekiby90qbRRR7Gpri22Fwd0J8AwJS2lx2iBFhqBH OH3ByCj9HPZ/SuBj5s/sSWgN96hkBAeP8dKXze5ptC28RRJf74CbdQqkOtbHAfWgmYFu 5s78L6qY56pJNotAMI7fBsBdW3te++9/M31Bvo9G9NnsxNRYi6P0m5jtBRJhwJCwW5Tv fRrIgE6mnDtK5bBWXxTTNGPVhxHmQc/eDRYggOh8azTWSnS6npHFy/MrEf5LSkrVDH31 GZz+lNr7gaGCTpBRg5FW94sSXiQstyuD37lrI6q6sLpOxyF+aTpvRv0bZZ91Fy8vMGlB Np7g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=infOJYAuY6NmVdfocqokUhNUb9UCZ9ojC/z55HJcvas=; b=tfE5q0SQErcR4exlSfSmndPfYMwB/MHha0tnZibroXfA3TXnoCBkl8GJkxbFgHPJCQ ZQKq2IjV88dxknpB5MtjCEe4gEYO/A52oU5Rro4KlmYn8krd79PdH+Kn9CtWLDbWCvKv XCmNMFy09xqXH8VtG+FEsa3r2Voj+TWFLX3n5hiz2UzlDnLQ+iuaIDVVZl+frJ7Xylcn 9jzZfwwqq4vldmhNk/NZiK5GnL9MnHh7m+K0de8CshA6Iv/kSNWmRLf/DCxfF2bjw9mn 3rE11EcEa9VweNJDHKvhNq5NaUha/pFZvijtpBYBhLrFHSybeCU2c+IAsmuk5TXRuEnq hIEQ== X-Gm-Message-State: ANoB5pmMW8KS9AUXnqhCrEc3NmC9lQrEJFzX176uHZnY4N1PaJzaRXV2 fkoXT2xqhgLvjlTUaa/G1zQ4vjFxdgnTQw== X-Received: by 2002:a05:6a00:2787:b0:578:8864:7b24 with SMTP id bd7-20020a056a00278700b0057888647b24mr6416821pfb.12.1670922107172; Tue, 13 Dec 2022 01:01:47 -0800 (PST) Received: from localhost.localdomain (2001-b400-e2dc-5c03-264b-f684-a8c9-21ae.emome-ip6.hinet.net. [2001:b400:e2dc:5c03:264b:f684:a8c9:21ae]) by smtp.gmail.com with ESMTPSA id 81-20020a621954000000b0056b9ec7e2desm7141682pfz.125.2022.12.13.01.01.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 13 Dec 2022 01:01:46 -0800 (PST) From: Victor Shih X-Google-Original-From: Victor Shih To: ulf.hansson@linaro.org, adrian.hunter@intel.com Cc: linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, benchuanggli@gmail.com, HL.Liu@genesyslogic.com.tw, Greg.tu@genesyslogic.com.tw, takahiro.akashi@linaro.org, dlunev@chromium.org, Victor Shih , Ben Chuang Subject: [PATCH V6 12/24] mmc: sdhci-uhs2: skip signal_voltage_switch() Date: Tue, 13 Dec 2022 17:00:35 +0800 Message-Id: <20221213090047.3805-13-victor.shih@genesyslogic.com.tw> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221213090047.3805-1-victor.shih@genesyslogic.com.tw> References: <20221213090047.3805-1-victor.shih@genesyslogic.com.tw> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM, RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1752088959255143521?= X-GMAIL-MSGID: =?utf-8?q?1752088959255143521?= For UHS2, the signal voltage is supplied by vdd2 which is already 1.8v, so no voltage switch required. Signed-off-by: Ben Chuang Signed-off-by: AKASHI Takahiro Signed-off-by: Victor Shih --- drivers/mmc/host/sdhci-uhs2.c | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/drivers/mmc/host/sdhci-uhs2.c b/drivers/mmc/host/sdhci-uhs2.c index 780491781613..2342c05c4cdb 100644 --- a/drivers/mmc/host/sdhci-uhs2.c +++ b/drivers/mmc/host/sdhci-uhs2.c @@ -141,6 +141,27 @@ static void sdhci_uhs2_set_power(struct sdhci_host *host, unsigned char mode, } } +/*****************************************************************************\ + * * + * MMC callbacks * + * * +\*****************************************************************************/ + +static int sdhci_uhs2_start_signal_voltage_switch(struct mmc_host *mmc, + struct mmc_ios *ios) +{ + struct sdhci_host *host = mmc_priv(mmc); + + /* + * For UHS2, the signal voltage is supplied by vdd2 which is + * already 1.8v so no voltage switch required. + */ + if (sdhci_uhs2_mode(host)) + return 0; + + return sdhci_start_signal_voltage_switch(mmc, ios); +} + /*****************************************************************************\ * * * Driver init/exit * @@ -149,6 +170,9 @@ static void sdhci_uhs2_set_power(struct sdhci_host *host, unsigned char mode, static int sdhci_uhs2_host_ops_init(struct sdhci_host *host) { + host->mmc_host_ops.start_signal_voltage_switch = + sdhci_uhs2_start_signal_voltage_switch; + return 0; } From patchwork Tue Dec 13 09:00:36 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Victor Shih X-Patchwork-Id: 32707 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:8188:b0:89:790f:f786 with SMTP id m8csp3857996dye; Tue, 13 Dec 2022 01:04:30 -0800 (PST) X-Google-Smtp-Source: AA0mqf7fjFgL9Ql3XkZKQ0bV6CdpaDKywc1lEhGtf9wFzdw9pnU+X5XSA6cvBYKjwFqMrXmGyDzN X-Received: by 2002:a17:90a:f191:b0:21a:1b9b:139e with SMTP id bv17-20020a17090af19100b0021a1b9b139emr19688236pjb.8.1670922269932; Tue, 13 Dec 2022 01:04:29 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1670922269; cv=none; d=google.com; s=arc-20160816; b=bq14vPuOWr5mdsIY9C3MBouO+SeBfTCXs9wQ5bri7Q7pLtMqvV7O5KkEiORKlyxKOh f/aIzLJ3FKV55OQfPWt8pZvTzwoqY62iIR26COzzVzenSK5RTEOHPpnPCGAzMH8DV83I fdCroTVeJclsyc+BExD1YevmWEPL1J4KJUv4pjvecCuuJHK6UO5Q7N2+fdObyZ2kStCA qByvlDplsGDe/N+Vqt444wqSZGnI8/byKWTRF2k4bY0d9DQgKI0kLlIbCzVnHlQp4te6 DIffPvitR1ZipldSn03B0a2EpFsKv5v5zv8MaDZDhHBo4i5UH91x+cq87vHmo+SPPjEr 9G1A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=Z1PHj1yKWIH44nR4fbTVq49MHfutRoM7zbX96DEQIj4=; b=wWUj22I5RjN9VkQWz9Q1KntSxbeDhkYqYKKigcig8IONLY8+nJtuXHxIYWIJVlIRmJ HydE0YbmdCLJwbUSiV66ADloiW2joVCBdVukzGdu8545waZMXLXp5974HtL/a3p4XZKl aTJUEipLadRxbGPPuH4uo3ON3YLAss8WVPdBoCLZBsPPR7YEfPgV8y0nTet6UxMI+Wyt 194vhfoVChyEojUVqqyUWbiLV6aPJk91XTFMUsfy5VPbt5upnQUape4PQZURA4kpcky5 wyw77o4y2Kd2ipGp9M3CFXQ4lOLkIwL4S9sy6GibIwgW+P83W/WEBowAtEZGobhq19ag vVvw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20210112 header.b=ZAF9Ih4N; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id v9-20020a17090a898900b0021a14834b1asi11717183pjn.109.2022.12.13.01.04.17; Tue, 13 Dec 2022 01:04:29 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@gmail.com header.s=20210112 header.b=ZAF9Ih4N; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235030AbiLMJDN (ORCPT + 99 others); Tue, 13 Dec 2022 04:03:13 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36612 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234990AbiLMJCE (ORCPT ); Tue, 13 Dec 2022 04:02:04 -0500 Received: from mail-pj1-x102e.google.com (mail-pj1-x102e.google.com [IPv6:2607:f8b0:4864:20::102e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 07A79E09E; Tue, 13 Dec 2022 01:01:51 -0800 (PST) Received: by mail-pj1-x102e.google.com with SMTP id js9so2714832pjb.2; Tue, 13 Dec 2022 01:01:51 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Z1PHj1yKWIH44nR4fbTVq49MHfutRoM7zbX96DEQIj4=; b=ZAF9Ih4N1XWyBi7TVZ1sHgmxbPJOy+0mfDevrgZooL6PHNWz78STohjQWhoT36egFk dgnrSW2zVKbr+Xlpqhokd8AwE396nXsXs1EaIUdWMdON+sNvOjSGYwA3ueF+2otjLoYR oSbmvIOht6qgsnPE/A4llqRZT6hh9jvHWsIgBTKjJxw/7oemqrkbF37B/Y/tfsI6kMzG 5Z7CQQyJTiJ3GRXxac9SZVImHpoo2vHbwuCJBo00CFI3uFxL21rQ3uSYiVPZpD9LrcCB jTjLTHZRNyQ7RoU/uTdzrlks3lVCNWOB0i2IPb5JXrSj+FQM3FYTDtaZFWxsJ3cP6nvc Sr7Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Z1PHj1yKWIH44nR4fbTVq49MHfutRoM7zbX96DEQIj4=; b=Zdr5aC+c6Q7DKDYvju8R7fmN6rwSoAihvzV1/ilkNewzbfUS5ZekeQx2HS/iyE1VZ2 dy1IhhkBOLARCVE/kbMFyZuM1BKJB1o/z0iFPH4XVO+mXfAxSL03PELLdUTZCpNRotqV 0dXva8dGmQlt3GiOJG2oIApKL5hSsGb+YH9bLwKSdMnBC7pf58z/SjFkK3EG3RIZTtr+ 652IdcrLvWYmD/qJoG+A/QN20/uj+9ajaRgue1ChlUl79hU36lRy0Ucbek0oYOtUQynf URdO0EIoh4sFHKXHkVS1ozPbnzvPM1EJwyMV6U0pvVB0FimtJPszDAyOCSmqlgsHS8se 06Cw== X-Gm-Message-State: ANoB5pln8v8HNT+bVekSQ8jh4+9k/Mv43QgUoPf8y7t0Fm6hLSCSXpYb /AGcGtxXRbpSbhJZ/do8GLE= X-Received: by 2002:a05:6a20:9c89:b0:9d:efbf:7876 with SMTP id mj9-20020a056a209c8900b0009defbf7876mr23428798pzb.43.1670922110574; Tue, 13 Dec 2022 01:01:50 -0800 (PST) Received: from localhost.localdomain (2001-b400-e2dc-5c03-264b-f684-a8c9-21ae.emome-ip6.hinet.net. [2001:b400:e2dc:5c03:264b:f684:a8c9:21ae]) by smtp.gmail.com with ESMTPSA id 81-20020a621954000000b0056b9ec7e2desm7141682pfz.125.2022.12.13.01.01.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 13 Dec 2022 01:01:49 -0800 (PST) From: Victor Shih X-Google-Original-From: Victor Shih To: ulf.hansson@linaro.org, adrian.hunter@intel.com Cc: linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, benchuanggli@gmail.com, HL.Liu@genesyslogic.com.tw, Greg.tu@genesyslogic.com.tw, takahiro.akashi@linaro.org, dlunev@chromium.org, Victor Shih , Ben Chuang Subject: [PATCH V6 13/24] mmc: sdhci-uhs2: add set_timeout() Date: Tue, 13 Dec 2022 17:00:36 +0800 Message-Id: <20221213090047.3805-14-victor.shih@genesyslogic.com.tw> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221213090047.3805-1-victor.shih@genesyslogic.com.tw> References: <20221213090047.3805-1-victor.shih@genesyslogic.com.tw> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM, RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1752088990156321743?= X-GMAIL-MSGID: =?utf-8?q?1752088990156321743?= This is a UHS-II version of sdhci's set_timeout() operation. Signed-off-by: Ben Chuang Signed-off-by: AKASHI Takahiro Signed-off-by: Victor Shih --- drivers/mmc/host/sdhci-uhs2.c | 72 +++++++++++++++++++++++++++++++++++ drivers/mmc/host/sdhci-uhs2.h | 1 + 2 files changed, 73 insertions(+) diff --git a/drivers/mmc/host/sdhci-uhs2.c b/drivers/mmc/host/sdhci-uhs2.c index 2342c05c4cdb..00b1b69b49ea 100644 --- a/drivers/mmc/host/sdhci-uhs2.c +++ b/drivers/mmc/host/sdhci-uhs2.c @@ -13,6 +13,7 @@ #include #include #include +#include #include "sdhci.h" #include "sdhci-uhs2.h" @@ -141,6 +142,77 @@ static void sdhci_uhs2_set_power(struct sdhci_host *host, unsigned char mode, } } +static u8 sdhci_calc_timeout_uhs2(struct sdhci_host *host, u8 *cmd_res, u8 *dead_lock) +{ + u8 count; + unsigned int cmd_res_timeout, dead_lock_timeout, current_timeout; + /* timeout in us */ + cmd_res_timeout = 5 * 1000; + dead_lock_timeout = 1 * 1000 * 1000; + + /* + * Figure out needed cycles. + * We do this in steps in order to fit inside a 32 bit int. + * The first step is the minimum timeout, which will have a + * minimum resolution of 6 bits: + * (1) 2^13*1000 > 2^22, + * (2) host->timeout_clk < 2^16 + * => + * (1) / (2) > 2^6 + */ + count = 0; + current_timeout = (1 << 13) * 1000 / host->timeout_clk; + while (current_timeout < cmd_res_timeout) { + count++; + current_timeout <<= 1; + if (count >= 0xF) + break; + } + + if (count >= 0xF) { + DBG("%s: Too large timeout 0x%x requested for CMD_RES!\n", + mmc_hostname(host->mmc), count); + count = 0xE; + } + *cmd_res = count; + + count = 0; + current_timeout = (1 << 13) * 1000 / host->timeout_clk; + while (current_timeout < dead_lock_timeout) { + count++; + current_timeout <<= 1; + if (count >= 0xF) + break; + } + + if (count >= 0xF) { + DBG("%s: Too large timeout 0x%x requested for DEADLOCK!\n", + mmc_hostname(host->mmc), count); + count = 0xE; + } + *dead_lock = count; + + return count; +} + +static void __sdhci_uhs2_set_timeout(struct sdhci_host *host) +{ + u8 cmd_res, dead_lock; + + sdhci_calc_timeout_uhs2(host, &cmd_res, &dead_lock); + cmd_res |= FIELD_PREP(SDHCI_UHS2_TIMER_CTRL_DEADLOCK_MASK, dead_lock); + sdhci_writeb(host, cmd_res, SDHCI_UHS2_TIMER_CTRL); +} + +void sdhci_uhs2_set_timeout(struct sdhci_host *host, struct mmc_command *cmd) +{ + __sdhci_set_timeout(host, cmd); + + if (sdhci_uhs2_mode(host)) + __sdhci_uhs2_set_timeout(host); +} +EXPORT_SYMBOL_GPL(sdhci_uhs2_set_timeout); + /*****************************************************************************\ * * * MMC callbacks * diff --git a/drivers/mmc/host/sdhci-uhs2.h b/drivers/mmc/host/sdhci-uhs2.h index 03b9f6675cdc..a58ef19c08aa 100644 --- a/drivers/mmc/host/sdhci-uhs2.h +++ b/drivers/mmc/host/sdhci-uhs2.h @@ -177,5 +177,6 @@ struct sdhci_host; void sdhci_uhs2_dump_regs(struct sdhci_host *host); bool sdhci_uhs2_mode(struct sdhci_host *host); void sdhci_uhs2_reset(struct sdhci_host *host, u16 mask); +void sdhci_uhs2_set_timeout(struct sdhci_host *host, struct mmc_command *cmd); #endif /* __SDHCI_UHS2_H */ From patchwork Tue Dec 13 09:00:37 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Victor Shih X-Patchwork-Id: 32708 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:8188:b0:89:790f:f786 with SMTP id m8csp3858038dye; Tue, 13 Dec 2022 01:04:35 -0800 (PST) X-Google-Smtp-Source: AA0mqf6EacH5n6K1gOQqOjAnK+wE4HDg/kFu+WOQt3EZIdPm6pRAoZ7aIBJE8eftLGYf5bK+o73F X-Received: by 2002:a05:6a21:9996:b0:a2:491c:15cc with SMTP id ve22-20020a056a21999600b000a2491c15ccmr29146545pzb.40.1670922274963; Tue, 13 Dec 2022 01:04:34 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1670922274; cv=none; d=google.com; s=arc-20160816; b=hsxUxTGukYn1DeF04TpdP9hljF0V39mnHdfk7EobiptjenHXPkvo0HOcO/qlrO5YEQ WhOD3ptKpmG673NkhI4UmqLp1VkY3tnpjt2gWMLUi5yja27SBu2leMaLHP7cia40KQxt jg6plPFdCzQgRZju4JVlnZYNxhnG0ee+hPapiTAtmEUjHiqnmcDYTmmw1X/p6LlQOh17 L8egeKc1VEPrJGeo/QRS5CxAMx3JVQbzjlstDzEtpjyIShPz4FqxC8iQUBR9tLTRsZZJ l7iCBy9mPel5u2Rd4Xw6iS3sRvU51fDQz4BiJSi87+GKTO0nBElqC5Y2xtFwt5qDiUFd C0ew== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=pDw/SHDyLtu1AoZL+hYcNtOe2c/7a7zkWUntPhiSPcU=; b=Bk1VAi00+lMTSJwCAAWCmNhLeM2E84Jvvsy5pjlxxskrxdHWIxmcUsmECvig2q9ocq NFfA5mAs8YPTNDu1TH6+Rw36I2YeGkZheWGe+GuUwTbzXVoF6nPqaxldxo2hhjuKEdr0 Tho6CA3EocmmTxj3OI/keuim+aZZeKLAsOG4Q2YsNN+0wf6FUou8uWfK6aD1y+E5MvhU oB2k7dpGp8Oz0kYB/w/EhSnL28Yi71yvsRJX5IDaL4tAbE7AB4eCRofdOAbg1ozp+vTw vt3PHfEuPLBVX3k19PUXHMGn3GpEVlNj0/b25thLjylr8ISwobZCr7sdDBti/577alQY Y9CQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20210112 header.b=glOVOtQi; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id m187-20020a6326c4000000b00476e9888164si12156562pgm.88.2022.12.13.01.04.21; Tue, 13 Dec 2022 01:04:34 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@gmail.com header.s=20210112 header.b=glOVOtQi; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235054AbiLMJDf (ORCPT + 99 others); Tue, 13 Dec 2022 04:03:35 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36628 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235002AbiLMJCG (ORCPT ); Tue, 13 Dec 2022 04:02:06 -0500 Received: from mail-pg1-x535.google.com (mail-pg1-x535.google.com [IPv6:2607:f8b0:4864:20::535]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 693B4E0B9; Tue, 13 Dec 2022 01:01:54 -0800 (PST) Received: by mail-pg1-x535.google.com with SMTP id r18so9967256pgr.12; Tue, 13 Dec 2022 01:01:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=pDw/SHDyLtu1AoZL+hYcNtOe2c/7a7zkWUntPhiSPcU=; b=glOVOtQidwJKZVZBqcD+XBJEfihYgs1NMCKfbLh26RUGAelFNYgndurIJZHAHVuuHU HbFH0sLsDFR35Qf9M0939ijWNRArbOcj+6oqcQ6Rf/lyCpxb+keoAI8C6hpS9t+gZVZA UQmh6yeT5o2kfbzoK/eP3HhipJbnF67kk7NFKL2mN3GqaqCru050nrfMEc5w3Gx+0/jX mG/1IuaMDNVyhKkkN9a+qaTL9c6C8yn5OSkcoPAhXqtiMD1w4wF8JNktHTtNrsyom1KX XKXbRrXN60PGpEBpbo7lgF6AeWxX0zb3GnvRQlgpOIuZwUVoQRpSE4anYlSU1aPO7lHs yzPQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=pDw/SHDyLtu1AoZL+hYcNtOe2c/7a7zkWUntPhiSPcU=; b=xblr2iQIc3skqU+isvYfFsy1C8sQwZ4QF7XpBf7pf7jHOjXVHGZqbJp61U/US4WrTk vCESzp5QMEhLaMoabjFcIk+nmxfLuaz6U44x5+6wUPXaJB+WHFksmv0P4DfZpL/uZRes Ox3G+NuwD8vRJeHpdpyAuKPUpmwbn6SygJUZ3mVaMijTJnLJBOkHj0z/eZ1W8ME3WI2r KsWS/1By7koUNq8JLd+2ujmQ3iANqUxdRd8KHXKCRQtC6zTmI2Esbv4GWTR8GQvuk58f P/mSZITPv0+0eJFPG87yM8bV+6xdZQkUZPA2+LVcMjchbIW0eN9zhDPsM4lCnpdimM01 Qcpg== X-Gm-Message-State: ANoB5pmON9yzSFRvqA3GZ0FAx3dRdVywddOuLEp21x9xrEr7+kBOZ966 omreyCcBZPgAsmj1Y8SK0/4= X-Received: by 2002:a62:e519:0:b0:575:bf29:d1e0 with SMTP id n25-20020a62e519000000b00575bf29d1e0mr21516224pff.26.1670922113880; Tue, 13 Dec 2022 01:01:53 -0800 (PST) Received: from localhost.localdomain (2001-b400-e2dc-5c03-264b-f684-a8c9-21ae.emome-ip6.hinet.net. [2001:b400:e2dc:5c03:264b:f684:a8c9:21ae]) by smtp.gmail.com with ESMTPSA id 81-20020a621954000000b0056b9ec7e2desm7141682pfz.125.2022.12.13.01.01.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 13 Dec 2022 01:01:53 -0800 (PST) From: Victor Shih X-Google-Original-From: Victor Shih To: ulf.hansson@linaro.org, adrian.hunter@intel.com Cc: linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, benchuanggli@gmail.com, HL.Liu@genesyslogic.com.tw, Greg.tu@genesyslogic.com.tw, takahiro.akashi@linaro.org, dlunev@chromium.org, Victor Shih , Ben Chuang Subject: [PATCH V6 14/24] mmc: sdhci-uhs2: add set_ios() Date: Tue, 13 Dec 2022 17:00:37 +0800 Message-Id: <20221213090047.3805-15-victor.shih@genesyslogic.com.tw> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221213090047.3805-1-victor.shih@genesyslogic.com.tw> References: <20221213090047.3805-1-victor.shih@genesyslogic.com.tw> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM, RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1752088995672266953?= X-GMAIL-MSGID: =?utf-8?q?1752088995672266953?= This is a sdhci version of mmc's set_ios operation. It covers both UHS-I and UHS-II. Signed-off-by: Ben Chuang Signed-off-by: AKASHI Takahiro Signed-off-by: Victor Shih --- drivers/mmc/host/sdhci-uhs2.c | 96 +++++++++++++++++++++++++++++++++++ drivers/mmc/host/sdhci-uhs2.h | 1 + drivers/mmc/host/sdhci.c | 53 +++++++++++-------- drivers/mmc/host/sdhci.h | 2 + 4 files changed, 131 insertions(+), 21 deletions(-) diff --git a/drivers/mmc/host/sdhci-uhs2.c b/drivers/mmc/host/sdhci-uhs2.c index 00b1b69b49ea..3d52d35a91a5 100644 --- a/drivers/mmc/host/sdhci-uhs2.c +++ b/drivers/mmc/host/sdhci-uhs2.c @@ -213,6 +213,68 @@ void sdhci_uhs2_set_timeout(struct sdhci_host *host, struct mmc_command *cmd) } EXPORT_SYMBOL_GPL(sdhci_uhs2_set_timeout); +/** + * sdhci_uhs2_clear_set_irqs - set Error Interrupt Status Enable register + * @host: SDHCI host + * @clear: bit-wise clear mask + * @set: bit-wise set mask + * + * Set/unset bits in UHS-II Error Interrupt Status Enable register + */ +void sdhci_uhs2_clear_set_irqs(struct sdhci_host *host, u32 clear, u32 set) +{ + u32 ier; + + ier = sdhci_readl(host, SDHCI_UHS2_INT_STATUS_ENABLE); + ier &= ~clear; + ier |= set; + sdhci_writel(host, ier, SDHCI_UHS2_INT_STATUS_ENABLE); + sdhci_writel(host, ier, SDHCI_UHS2_INT_SIGNAL_ENABLE); +} +EXPORT_SYMBOL_GPL(sdhci_uhs2_clear_set_irqs); + +static void __sdhci_uhs2_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) +{ + struct sdhci_host *host = mmc_priv(mmc); + u8 cmd_res, dead_lock; + u16 ctrl_2; + + /* UHS2 Timeout Control */ + sdhci_calc_timeout_uhs2(host, &cmd_res, &dead_lock); + + /* change to use calculate value */ + cmd_res |= FIELD_PREP(SDHCI_UHS2_TIMER_CTRL_DEADLOCK_MASK, dead_lock); + + sdhci_uhs2_clear_set_irqs(host, + SDHCI_UHS2_INT_CMD_TIMEOUT | + SDHCI_UHS2_INT_DEADLOCK_TIMEOUT, + 0); + sdhci_writeb(host, cmd_res, SDHCI_UHS2_TIMER_CTRL); + sdhci_uhs2_clear_set_irqs(host, 0, + SDHCI_UHS2_INT_CMD_TIMEOUT | + SDHCI_UHS2_INT_DEADLOCK_TIMEOUT); + + /* UHS2 timing */ + ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); + if (ios->timing == MMC_TIMING_SD_UHS2) + ctrl_2 |= SDHCI_CTRL_UHS2 | SDHCI_CTRL_UHS2_ENABLE; + else + ctrl_2 &= ~(SDHCI_CTRL_UHS2 | SDHCI_CTRL_UHS2_ENABLE); + sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); + + if (!(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN)) + sdhci_enable_preset_value(host, true); + + if (host->ops->set_power) + host->ops->set_power(host, ios->power_mode, ios->vdd); + else + sdhci_uhs2_set_power(host, ios->power_mode, ios->vdd); + udelay(100); + + host->timing = ios->timing; + sdhci_set_clock(host, host->clock); +} + /*****************************************************************************\ * * * MMC callbacks * @@ -234,6 +296,39 @@ static int sdhci_uhs2_start_signal_voltage_switch(struct mmc_host *mmc, return sdhci_start_signal_voltage_switch(mmc, ios); } +int sdhci_uhs2_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) +{ + struct sdhci_host *host = mmc_priv(mmc); + + if (!(host->version >= SDHCI_SPEC_400) || + !(host->mmc->flags & MMC_UHS2_SUPPORT && + host->mmc->caps2 & MMC_CAP2_SD_UHS2)) { + sdhci_set_ios(mmc, ios); + return 0; + } + + if (ios->power_mode == MMC_POWER_UNDEFINED) + return 0; + + if (host->flags & SDHCI_DEVICE_DEAD) { + if (!IS_ERR(mmc->supply.vmmc) && + ios->power_mode == MMC_POWER_OFF) + mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); + if (!IS_ERR_OR_NULL(mmc->supply.vmmc2) && + ios->power_mode == MMC_POWER_OFF) + mmc_regulator_set_ocr(mmc, mmc->supply.vmmc2, 0); + return -1; + } + + host->timing = ios->timing; + + sdhci_set_ios_common(mmc, ios); + + __sdhci_uhs2_set_ios(mmc, ios); + + return 0; +} + /*****************************************************************************\ * * * Driver init/exit * @@ -244,6 +339,7 @@ static int sdhci_uhs2_host_ops_init(struct sdhci_host *host) { host->mmc_host_ops.start_signal_voltage_switch = sdhci_uhs2_start_signal_voltage_switch; + host->mmc_host_ops.uhs2_set_ios = sdhci_uhs2_set_ios; return 0; } diff --git a/drivers/mmc/host/sdhci-uhs2.h b/drivers/mmc/host/sdhci-uhs2.h index a58ef19c08aa..184fee80253c 100644 --- a/drivers/mmc/host/sdhci-uhs2.h +++ b/drivers/mmc/host/sdhci-uhs2.h @@ -178,5 +178,6 @@ void sdhci_uhs2_dump_regs(struct sdhci_host *host); bool sdhci_uhs2_mode(struct sdhci_host *host); void sdhci_uhs2_reset(struct sdhci_host *host, u16 mask); void sdhci_uhs2_set_timeout(struct sdhci_host *host, struct mmc_command *cmd); +void sdhci_uhs2_clear_set_irqs(struct sdhci_host *host, u32 clear, u32 set); #endif /* __SDHCI_UHS2_H */ diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c index 99633a3ef549..49bbdc155b2b 100644 --- a/drivers/mmc/host/sdhci.c +++ b/drivers/mmc/host/sdhci.c @@ -47,8 +47,6 @@ static unsigned int debug_quirks = 0; static unsigned int debug_quirks2; -static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable); - static bool sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd); void sdhci_dumpregs(struct sdhci_host *host) @@ -1877,6 +1875,9 @@ static u16 sdhci_get_preset_value(struct sdhci_host *host) case MMC_TIMING_MMC_HS400: preset = sdhci_readw(host, SDHCI_PRESET_FOR_HS400); break; + case MMC_TIMING_SD_UHS2: + preset = sdhci_readw(host, SDHCI_PRESET_FOR_UHS2); + break; default: pr_warn("%s: Invalid UHS-I mode selected\n", mmc_hostname(host->mmc)); @@ -2325,24 +2326,9 @@ static bool sdhci_presetable_values_change(struct sdhci_host *host, struct mmc_i (sdhci_preset_needed(host, ios->timing) || host->drv_type != ios->drv_type); } -void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) +void sdhci_set_ios_common(struct mmc_host *mmc, struct mmc_ios *ios) { struct sdhci_host *host = mmc_priv(mmc); - bool reinit_uhs = host->reinit_uhs; - bool turning_on_clk = false; - u8 ctrl; - - host->reinit_uhs = false; - - if (ios->power_mode == MMC_POWER_UNDEFINED) - return; - - if (host->flags & SDHCI_DEVICE_DEAD) { - if (!IS_ERR(mmc->supply.vmmc) && - ios->power_mode == MMC_POWER_OFF) - mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); - return; - } /* * Reset the chip on each power off. @@ -2359,8 +2345,6 @@ void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) sdhci_enable_preset_value(host, false); if (!ios->clock || ios->clock != host->clock) { - turning_on_clk = ios->clock && !host->clock; - host->ops->set_clock(host, ios->clock); host->clock = ios->clock; @@ -2381,6 +2365,32 @@ void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) host->ops->set_power(host, ios->power_mode, ios->vdd); else sdhci_set_power(host, ios->power_mode, ios->vdd); +} +EXPORT_SYMBOL_GPL(sdhci_set_ios_common); + +void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) +{ + struct sdhci_host *host = mmc_priv(mmc); + bool reinit_uhs = host->reinit_uhs; + bool turning_on_clk = false; + u8 ctrl; + + host->reinit_uhs = false; + + if (ios->power_mode == MMC_POWER_UNDEFINED) + return; + + if (host->flags & SDHCI_DEVICE_DEAD) { + if (!IS_ERR(mmc->supply.vmmc) && + ios->power_mode == MMC_POWER_OFF) + mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); + return; + } + + sdhci_set_ios_common(mmc, ios); + + if (!ios->clock || ios->clock != host->clock) + turning_on_clk = ios->clock && !host->clock; if (host->ops->platform_send_init_74_clocks) host->ops->platform_send_init_74_clocks(host, ios->power_mode); @@ -2959,7 +2969,7 @@ int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode) } EXPORT_SYMBOL_GPL(sdhci_execute_tuning); -static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable) +void sdhci_enable_preset_value(struct sdhci_host *host, bool enable) { /* Host Controller v3.00 defines preset value registers */ if (host->version < SDHCI_SPEC_300) @@ -2987,6 +2997,7 @@ static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable) host->preset_enabled = enable; } } +EXPORT_SYMBOL_GPL(sdhci_enable_preset_value); static void sdhci_post_req(struct mmc_host *mmc, struct mmc_request *mrq, int err) diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h index df7fa0c0ebf8..c2f989dc2361 100644 --- a/drivers/mmc/host/sdhci.h +++ b/drivers/mmc/host/sdhci.h @@ -850,6 +850,8 @@ void sdhci_set_bus_width(struct sdhci_host *host, int width); void sdhci_reset(struct sdhci_host *host, u8 mask); void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing); int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode); +void sdhci_enable_preset_value(struct sdhci_host *host, bool enable); +void sdhci_set_ios_common(struct mmc_host *mmc, struct mmc_ios *ios); void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios); int sdhci_start_signal_voltage_switch(struct mmc_host *mmc, struct mmc_ios *ios); From patchwork Tue Dec 13 09:00:38 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Victor Shih X-Patchwork-Id: 32706 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:8188:b0:89:790f:f786 with SMTP id m8csp3857965dye; Tue, 13 Dec 2022 01:04:27 -0800 (PST) X-Google-Smtp-Source: AA0mqf7yooEXY3l9LuBnivsiYz4AEuLFLW5W3s7COnro0RAc2/AGtfnWBZjw0gyZXNBsm0e5iNeU X-Received: by 2002:a17:902:ebc1:b0:189:65e7:e16b with SMTP id p1-20020a170902ebc100b0018965e7e16bmr19160802plg.66.1670922266865; Tue, 13 Dec 2022 01:04:26 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1670922266; cv=none; d=google.com; s=arc-20160816; b=GpSrLUcs6nRFY+gRLVdnOyjPOQ7w63cJfhMuBZmtcS0CrumyerQ5pXlxUHOIVqXJDV cOAInBhGiINt4ru64VbUE+UCI1IXq50VTbJUPtcVvO3nhgDWFtzka0xjV5E66nYcN2sx +NIaV3s/iIAC/Qg1+VkLPtb/W2sapgqNd31hXtsVu3CkLnTYX+d49hbxJZGZ2bJL5GXT 95GzEtDeEPhVqR6R+HlOr5rEngl6QzbCNQjvDpr254C1gZRj4SsPeRM7hPNiMeBKX9mf Ru7jSlbzhrcLlaalozhPYPghoQ6GmqNJ52ktjudgrh4bZA3eiPgGlHImiXXxiuu9YeAB 25kg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=TFVqXNDoIn/bAHZecPcyJ9V854tw+X6Ejrgn0ob5b4g=; b=IGjjGOY9vUdv47ctZdizE18srh777BIaqHx/iir2ko5zBGLxCpQOpPy/ByOTJov9ZB 8l5ZuXOlBQCiC/wXtfViwX/7Tj7pm9Wjht3vTMJVE3iuhqyw66gaentQZajdDSvK8h+m dWe07y2a1EmBY7yJMUiXAhvqfbqu/yYHaj8GfctB+mQ74+NPVIT0kpX4TGdCPIYhlZJW UD7VwybmO2ciiaf/aCsaOt8tUgJdaCz7itBqXnG2H9CmJ7GWuiYhEMZR6WPxo0q+4PIM rTjznDraly3XXgPxgKQIw+2Ys7IhEHlubOJKwybOuGgTbZX+4l6MEQ8LCijfwO6DAsxe 9Zew== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20210112 header.b=bSZVwpBA; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id h19-20020a170902eed300b0017840d9d42esi11339519plb.582.2022.12.13.01.04.14; Tue, 13 Dec 2022 01:04:26 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@gmail.com header.s=20210112 header.b=bSZVwpBA; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235025AbiLMJDY (ORCPT + 99 others); Tue, 13 Dec 2022 04:03:24 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36630 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235004AbiLMJCG (ORCPT ); Tue, 13 Dec 2022 04:02:06 -0500 Received: from mail-pf1-x436.google.com (mail-pf1-x436.google.com [IPv6:2607:f8b0:4864:20::436]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 53A9C1006C; Tue, 13 Dec 2022 01:01:57 -0800 (PST) Received: by mail-pf1-x436.google.com with SMTP id 21so1740782pfw.4; Tue, 13 Dec 2022 01:01:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=TFVqXNDoIn/bAHZecPcyJ9V854tw+X6Ejrgn0ob5b4g=; b=bSZVwpBACj2KAGup5nm1UdtpOSAMEw5Bd4cX76mHf3ONMH51BPlpwwUy7RlDyF5qvI Knn+kCYgxg6J2IlwBYg2MwXeooBkA5NvD1/TxjBDYsgU2AWyx1NzhsLrHNh4qcsKHiv8 646DMyw0nXQOzPX3miBk6TTRgn/x4wlsVUPXeWz2J5UgzQ8Tt5/kxUg9fjacn8TQD3I2 kklPrGYlI+9jMFZyW0F+WAgNcGKmnh+HRtUa927ngf/0gna3FNh3mjf5jgH9G1wYO35y 1ZsSiOBEMsk3E+Qh8k8+1kWtb/MlS8zPJHNcdol6nzlp8jyN/soMuFlfP+psVxNE0AeM t6/A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=TFVqXNDoIn/bAHZecPcyJ9V854tw+X6Ejrgn0ob5b4g=; b=QngcMn63/ke/n8qTbjmD/345rcxVBxHT7qwzBFW7oafL7he2Mqlokjh+egs+AcLbYE rH7NrjY3f6te143xTHoQUTT9Gp0Y6icfdO1IodcHiIW/TCxkjtSd8ARoRRQQ6U+ejhk+ ch3t5Ro2qB+UvVjoJrx2fP1X8U9QI6HHQDLkDb2zUBYZkmdPxIv3+GtbZKywqDYOC+bu CKYddkAYylTFvDAM9QESn8G+U4MoBfQouBdGKgx+NMgy3uCiZHPgYTjnsR3dc8+wLmgO ABCCkvMbAjhtakNJd9TMIYMgJUBKzb8E1TdWpQrPvC3AjZ9v/UYaSMSHgULYqKhYi/pM t2cw== X-Gm-Message-State: ANoB5pmq7fnx0RVVYPo5T9dheXhjEhgt6cItllwDoADnMo4dpPYyGsmY dlDe3BFUrOdMnYz2iRVWizU= X-Received: by 2002:a62:19c6:0:b0:576:cd93:2b06 with SMTP id 189-20020a6219c6000000b00576cd932b06mr20591067pfz.6.1670922116688; Tue, 13 Dec 2022 01:01:56 -0800 (PST) Received: from localhost.localdomain (2001-b400-e2dc-5c03-264b-f684-a8c9-21ae.emome-ip6.hinet.net. [2001:b400:e2dc:5c03:264b:f684:a8c9:21ae]) by smtp.gmail.com with ESMTPSA id 81-20020a621954000000b0056b9ec7e2desm7141682pfz.125.2022.12.13.01.01.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 13 Dec 2022 01:01:56 -0800 (PST) From: Victor Shih X-Google-Original-From: Victor Shih To: ulf.hansson@linaro.org, adrian.hunter@intel.com Cc: linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, benchuanggli@gmail.com, HL.Liu@genesyslogic.com.tw, Greg.tu@genesyslogic.com.tw, takahiro.akashi@linaro.org, dlunev@chromium.org, Victor Shih , Ben Chuang Subject: [PATCH V6 15/24] mmc: sdhci-uhs2: add detect_init() to detect the interface Date: Tue, 13 Dec 2022 17:00:38 +0800 Message-Id: <20221213090047.3805-16-victor.shih@genesyslogic.com.tw> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221213090047.3805-1-victor.shih@genesyslogic.com.tw> References: <20221213090047.3805-1-victor.shih@genesyslogic.com.tw> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM, RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1752088986653700329?= X-GMAIL-MSGID: =?utf-8?q?1752088986653700329?= Sdhci_uhs2_do_detect_init() is a sdhci version of mmc's uhs2_detect_init operation. After detected, the host's UHS-II capabilities will be set up here and interrupts will also be enabled. Signed-off-by: Ben Chuang Signed-off-by: AKASHI Takahiro Signed-off-by: Victor Shih --- drivers/mmc/host/sdhci-uhs2.c | 117 ++++++++++++++++++++++++++++++++++ 1 file changed, 117 insertions(+) diff --git a/drivers/mmc/host/sdhci-uhs2.c b/drivers/mmc/host/sdhci-uhs2.c index 3d52d35a91a5..52587025d5e3 100644 --- a/drivers/mmc/host/sdhci-uhs2.c +++ b/drivers/mmc/host/sdhci-uhs2.c @@ -335,6 +335,123 @@ int sdhci_uhs2_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) * * \*****************************************************************************/ +static int sdhci_uhs2_interface_detect(struct sdhci_host *host) +{ + /* 100ms */ + int timeout = 100000; + u32 val; + + udelay(200); /* wait for 200us before check */ + + if (read_poll_timeout_atomic(sdhci_readl, val, (val & SDHCI_UHS2_IF_DETECT), + 100, timeout, true, host, SDHCI_PRESENT_STATE)) { + pr_warn("%s: not detect UHS2 interface in 200us.\n", mmc_hostname(host->mmc)); + sdhci_dumpregs(host); + return -EIO; + } + + /* Enable UHS2 error interrupts */ + sdhci_uhs2_clear_set_irqs(host, SDHCI_INT_ALL_MASK, SDHCI_UHS2_INT_ERROR_MASK); + + /* 150ms */ + timeout = 150000; + if (read_poll_timeout_atomic(sdhci_readl, val, (val & SDHCI_UHS2_LANE_SYNC), + 100, timeout, true, host, SDHCI_PRESENT_STATE)) { + pr_warn("%s: UHS2 Lane sync fail in 150ms.\n", mmc_hostname(host->mmc)); + sdhci_dumpregs(host); + return -EIO; + } + + DBG("%s: UHS2 Lane synchronized in UHS2 mode, PHY is initialized.\n", + mmc_hostname(host->mmc)); + return 0; +} + +static int sdhci_uhs2_init(struct sdhci_host *host) +{ + u16 caps_ptr = 0; + u32 caps_gen = 0; + u32 caps_phy = 0; + u32 caps_tran[2] = {0, 0}; + struct mmc_host *mmc = host->mmc; + + caps_ptr = sdhci_readw(host, SDHCI_UHS2_CAPS_PTR); + if (caps_ptr < 0x100 || caps_ptr > 0x1FF) { + pr_err("%s: SDHCI_UHS2_CAPS_PTR(%d) is wrong.\n", + mmc_hostname(mmc), caps_ptr); + return -ENODEV; + } + caps_gen = sdhci_readl(host, caps_ptr + SDHCI_UHS2_CAPS_OFFSET); + caps_phy = sdhci_readl(host, caps_ptr + SDHCI_UHS2_CAPS_PHY_OFFSET); + caps_tran[0] = sdhci_readl(host, caps_ptr + SDHCI_UHS2_CAPS_TRAN_OFFSET); + caps_tran[1] = sdhci_readl(host, caps_ptr + SDHCI_UHS2_CAPS_TRAN_1_OFFSET); + + /* General Caps */ + mmc->uhs2_caps.dap = caps_gen & SDHCI_UHS2_CAPS_DAP_MASK; + mmc->uhs2_caps.gap = FIELD_GET(SDHCI_UHS2_CAPS_GAP_MASK, caps_gen); + mmc->uhs2_caps.n_lanes = FIELD_GET(SDHCI_UHS2_CAPS_LANE_MASK, caps_gen); + mmc->uhs2_caps.addr64 = (caps_gen & SDHCI_UHS2_CAPS_ADDR_64) ? 1 : 0; + mmc->uhs2_caps.card_type = FIELD_GET(SDHCI_UHS2_CAPS_DEV_TYPE_MASK, caps_gen); + + /* PHY Caps */ + mmc->uhs2_caps.phy_rev = caps_phy & SDHCI_UHS2_CAPS_PHY_REV_MASK; + mmc->uhs2_caps.speed_range = FIELD_GET(SDHCI_UHS2_CAPS_PHY_RANGE_MASK, caps_phy); + mmc->uhs2_caps.n_lss_sync = FIELD_GET(SDHCI_UHS2_CAPS_PHY_N_LSS_SYN_MASK, caps_phy); + mmc->uhs2_caps.n_lss_dir = FIELD_GET(SDHCI_UHS2_CAPS_PHY_N_LSS_DIR_MASK, caps_phy); + if (mmc->uhs2_caps.n_lss_sync == 0) + mmc->uhs2_caps.n_lss_sync = 16 << 2; + else + mmc->uhs2_caps.n_lss_sync <<= 2; + if (mmc->uhs2_caps.n_lss_dir == 0) + mmc->uhs2_caps.n_lss_dir = 16 << 3; + else + mmc->uhs2_caps.n_lss_dir <<= 3; + + /* LINK/TRAN Caps */ + mmc->uhs2_caps.link_rev = caps_tran[0] & SDHCI_UHS2_CAPS_TRAN_LINK_REV_MASK; + mmc->uhs2_caps.n_fcu = FIELD_GET(SDHCI_UHS2_CAPS_TRAN_N_FCU_MASK, caps_tran[0]); + if (mmc->uhs2_caps.n_fcu == 0) + mmc->uhs2_caps.n_fcu = 256; + mmc->uhs2_caps.host_type = FIELD_GET(SDHCI_UHS2_CAPS_TRAN_HOST_TYPE_MASK, caps_tran[0]); + mmc->uhs2_caps.maxblk_len = FIELD_GET(SDHCI_UHS2_CAPS_TRAN_BLK_LEN_MASK, caps_tran[0]); + mmc->uhs2_caps.n_data_gap = caps_tran[1] & SDHCI_UHS2_CAPS_TRAN_1_N_DATA_GAP_MASK; + + return 0; +} + +static int sdhci_uhs2_do_detect_init(struct mmc_host *mmc) +{ + struct sdhci_host *host = mmc_priv(mmc); + int ret = -EIO; + + DBG("Begin do uhs2 detect init.\n"); + + if (sdhci_uhs2_interface_detect(host)) { + pr_warn("%s: cannot detect UHS2 interface.\n", + mmc_hostname(host->mmc)); + goto out; + } + + if (sdhci_uhs2_init(host)) { + pr_warn("%s: UHS2 init fail.\n", mmc_hostname(host->mmc)); + goto out; + } + + /* Init complete, do soft reset and enable UHS2 error irqs. */ + host->ops->uhs2_reset(host, SDHCI_UHS2_SW_RESET_SD); + sdhci_uhs2_clear_set_irqs(host, SDHCI_INT_ALL_MASK, SDHCI_UHS2_INT_ERROR_MASK); + /* + * N.B SDHCI_INT_ENABLE and SDHCI_SIGNAL_ENABLE was cleared + * by SDHCI_UHS2_SW_RESET_SD + */ + sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); + sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); + + ret = 0; +out: + return ret; +} + static int sdhci_uhs2_host_ops_init(struct sdhci_host *host) { host->mmc_host_ops.start_signal_voltage_switch = From patchwork Tue Dec 13 09:00:39 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Victor Shih X-Patchwork-Id: 32709 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:8188:b0:89:790f:f786 with SMTP id m8csp3858136dye; Tue, 13 Dec 2022 01:04:45 -0800 (PST) X-Google-Smtp-Source: AA0mqf4MIBmJ8xWx6yU4hq/h4DF+6ldg0Kj74U7qZ/8246andJ2efwz2tsyIJFhwq68yEX8t2Tc/ X-Received: by 2002:a17:903:40d1:b0:189:dedd:a4da with SMTP id t17-20020a17090340d100b00189dedda4damr23082150pld.34.1670922285077; Tue, 13 Dec 2022 01:04:45 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1670922285; cv=none; d=google.com; s=arc-20160816; b=WzyGqkR6sqPWt1Nt994ZvcMP3LCSYDQPb8LoGDzZO1CygxrU2abh81BGIgzRYHtIyA TtXu8A2lR1BybNZnMjzXqlnDDF2Xf9BIP/3GWEY+9rt//04N6RVfLLNJoJHpMM1Vo1X8 wMUrmY8H+HJWMdRzpOalKh6XYgOI9OufG/pYooufp/O+fpIKyjrdqkGJqt5xwLBmpWxR BL8PuPnT3gO/DhcKKwy8xx8+SyhW3AP5sn4ZzVC+/Ee2vWUbz1Gf9gi40RjOkoDiwpmz Ib+YJ3VMpFvEhRmto6AZdAYFmsp6Y+CfrkyjkPi7OOTXvyUs8Pz4Hqjvzaj8pix1dv/O 6tVw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=RqZSgcKwJJk5QRdmUrwY0usQ3tz0YwjuFkwc55K8IKE=; b=DunQgj7kXgsk+kxhwzGU1dcJixXKKHfjmVKSCLSOhX0vSr6MDraeyjyhoFNBrVrAJq RqpzlZYc/yf7m0Ed6rlnmtd2hQB2HXVJjb0QNIiN5gxKvv1iECDvkiJF17PQiGbnuQr5 10Znmm2FgpwoXvdYMj6qq+C8GIVJXMWf1JazaN0eR17nXJ4/9XPQR102bFNQO48aM90S Rhr0WWFpR2bnmeqwDbeLLFJBcjrMc2Koru1XUfI42MUUr1+OVB6qIhjchPCd427GCiSL F8MWJphl7+kA21EK5SJZGk8zl3ZBmW0gPTdE30CiD0hdqMFVz5ftnh5sx7jUa6aBK5cB 8iCw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20210112 header.b=gDyc93MY; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id p16-20020a1709027ed000b00188bee6e9f2si10846130plb.239.2022.12.13.01.04.32; Tue, 13 Dec 2022 01:04:45 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@gmail.com header.s=20210112 header.b=gDyc93MY; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235061AbiLMJDk (ORCPT + 99 others); Tue, 13 Dec 2022 04:03:40 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36072 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235005AbiLMJCH (ORCPT ); Tue, 13 Dec 2022 04:02:07 -0500 Received: from mail-pf1-x436.google.com (mail-pf1-x436.google.com [IPv6:2607:f8b0:4864:20::436]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6CF01FAD1; Tue, 13 Dec 2022 01:02:00 -0800 (PST) Received: by mail-pf1-x436.google.com with SMTP id 21so1740872pfw.4; Tue, 13 Dec 2022 01:02:00 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=RqZSgcKwJJk5QRdmUrwY0usQ3tz0YwjuFkwc55K8IKE=; b=gDyc93MYWGkYbl+NO1mcFFz1hHZMl8T0IxucPzZ3kkccFA8fY+jXaJID6yKyMH1PrX 6y5galtEGg7Ev+x2ETQISEiUXZxAIqcwhADltX+H89gOYKoQB4O10T2sF3cHVgDcD5Ml IPz8UWo+EuPClNuFIBA7TtHnrO10YVjiv7Yl8+CSqRk3ttalJDSe65/5/dnneGJlH+Kw fWy/J/+znhux+Yf8bKdp+mYhWQ28hgOGPUTxGLRW/o3N2DymA7aaQwTvkhLXP8gSTgb7 j9N0dzeuV/xOxabT6VaWPEQW04JImVJkkqMhStDHWI3vLdLcX6PtYovggYZynTLSNjwt hq6g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=RqZSgcKwJJk5QRdmUrwY0usQ3tz0YwjuFkwc55K8IKE=; b=BzPOqsaAQN9vc94Lq+wlNZAqSGuEvum/U0IpfO9ZQVPBGb9niVc8yW6Q16A/VaJnb7 sLsZA7Ak07JamGngpwdoinzsqUWGJwmLImIygv80iWELnM+ESLa6CftZYMrujEcw6hsQ dVJZ72duSc8+2JhmTMYK0LJM4PEI/kCObDkm/XpNm2y2juKJkMDNxp0mASvvrK8WB30E KbtCXjY6tOazluwwVSic737pYQJ9kEsfWEPW6vxcp7nAAQ3/4eQJaPHZ2zDTrDnGk01e 0eCm8huXvQbBD16DOFv2wLnmJ3lEx1r/FqrrfeNVczbrypePMqxAtIPNGDlFmQ2AxIFE DAXw== X-Gm-Message-State: ANoB5plk9Q6+P32g++uTZzFLdhp5BhgKpjU8MLpytAixKVnch0HrTODl 3ocQlSXTCRXerVVr8NcIJCQ= X-Received: by 2002:a62:1402:0:b0:577:d422:70bf with SMTP id 2-20020a621402000000b00577d42270bfmr20631892pfu.13.1670922119974; Tue, 13 Dec 2022 01:01:59 -0800 (PST) Received: from localhost.localdomain (2001-b400-e2dc-5c03-264b-f684-a8c9-21ae.emome-ip6.hinet.net. [2001:b400:e2dc:5c03:264b:f684:a8c9:21ae]) by smtp.gmail.com with ESMTPSA id 81-20020a621954000000b0056b9ec7e2desm7141682pfz.125.2022.12.13.01.01.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 13 Dec 2022 01:01:59 -0800 (PST) From: Victor Shih X-Google-Original-From: Victor Shih To: ulf.hansson@linaro.org, adrian.hunter@intel.com Cc: linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, benchuanggli@gmail.com, HL.Liu@genesyslogic.com.tw, Greg.tu@genesyslogic.com.tw, takahiro.akashi@linaro.org, dlunev@chromium.org, Victor Shih , Ben Chuang Subject: [PATCH V6 16/24] mmc: sdhci-uhs2: add clock operations Date: Tue, 13 Dec 2022 17:00:39 +0800 Message-Id: <20221213090047.3805-17-victor.shih@genesyslogic.com.tw> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221213090047.3805-1-victor.shih@genesyslogic.com.tw> References: <20221213090047.3805-1-victor.shih@genesyslogic.com.tw> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM, RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1752089005865733864?= X-GMAIL-MSGID: =?utf-8?q?1752089005865733864?= This is a sdhci version of mmc's uhs2_[enable|disable]_clk operations. Signed-off-by: Ben Chuang Signed-off-by: AKASHI Takahiro Signed-off-by: Victor Shih --- drivers/mmc/host/sdhci-uhs2.c | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/drivers/mmc/host/sdhci-uhs2.c b/drivers/mmc/host/sdhci-uhs2.c index 52587025d5e3..c7e411fa0a6e 100644 --- a/drivers/mmc/host/sdhci-uhs2.c +++ b/drivers/mmc/host/sdhci-uhs2.c @@ -14,6 +14,7 @@ #include #include #include +#include #include "sdhci.h" #include "sdhci-uhs2.h" @@ -329,6 +330,37 @@ int sdhci_uhs2_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) return 0; } +static int sdhci_uhs2_disable_clk(struct mmc_host *mmc) +{ + struct sdhci_host *host = mmc_priv(mmc); + u16 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); + + clk &= ~SDHCI_CLOCK_CARD_EN; + sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); + + return 0; +} + +static int sdhci_uhs2_enable_clk(struct mmc_host *mmc) +{ + struct sdhci_host *host = mmc_priv(mmc); + u16 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); + u32 val; + /* 20ms */ + int timeout_us = 20000; + + clk |= SDHCI_CLOCK_CARD_EN; + sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); + + if (read_poll_timeout_atomic(sdhci_readw, val, (val & SDHCI_CLOCK_INT_STABLE), + 10, timeout_us, true, host, SDHCI_CLOCK_CONTROL)) { + pr_err("%s: Internal clock never stabilised.\n", mmc_hostname(host->mmc)); + sdhci_dumpregs(host); + return 1; + } + return 0; +} + /*****************************************************************************\ * * * Driver init/exit * From patchwork Tue Dec 13 09:00:40 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Victor Shih X-Patchwork-Id: 32711 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:8188:b0:89:790f:f786 with SMTP id m8csp3858176dye; Tue, 13 Dec 2022 01:04:49 -0800 (PST) X-Google-Smtp-Source: AA0mqf4TUB48Nkr4m/4BxoVkEfT8kPTESJEDJ+rbCmjMrT+T+ky1G8q5Cuorzc1zr9ji2vCsnkqS X-Received: by 2002:a17:902:d54f:b0:189:76ef:a1b9 with SMTP id z15-20020a170902d54f00b0018976efa1b9mr22080983plf.5.1670922288991; Tue, 13 Dec 2022 01:04:48 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1670922288; cv=none; d=google.com; s=arc-20160816; b=WNVhNszACmaSRkcv1emobMjIxkiPbq3Hk0mqUe+g9Dmyi1OBvA3HOrcdyHrwpbmlGm LzgEtYe54cGHG59rRxXRCLe2j/6yxdRP+3ULBwXKvOIArs4rPdKKPAN70UUUw8VtcNUK h8mqwE6wC9zb0BVz2rPuSU2g8k+qiFQnBKg67Bx7t78Spben5IqH+Bifa2q5+SFc77Jf 5JAj/WvnkpQCyNxcnuMlS48KxgmoHFa3DIufOr/C+qrFsX56YuKd+x9RZxl6tHCrdK5R T3NiZuEyaqT9/ZjRFkibz1vyB+lPWd4aOhAFfd3LttKpDwe3n+vxpN7wf0oxqyI85nyz mo1w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=JbLCNFK4yUEg4Jb2vovMrI4jYY1qH30LfoBhRWLCbl0=; b=uw+QDn7nUXBLCKyJ0npGe/YyRwa93lCr2K3SzcklgmdoiZtwabKU60L5UZ6PFQdA2/ rWZ8TLH8T/xATAKGd+fECXP4s7srxAtzBSPe2Yem1H/ZSMVI+hKh6g44qo3HpkvBYvSs R7bCb5GaxjaTUegvuddpuprFAixRj2ISTDWBfZdxVv5H366cMtUJGhNHczLFOCRq4THI SNFj1rD+9PY66IogrJ3JFzaifoxtmsiwHuh0GovwMeyq45TcpndxEgJlM2g0kWtCfhZF IWcrZTxwXr5i64Fcp4BilSmzgD5VWK4/gqZil91qPROYenkHScl5nvSY9LRHE7DGCCcU z+Xg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20210112 header.b=fnkii9b6; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id q7-20020a170902eb8700b0017123d2abd5si11355810plg.457.2022.12.13.01.04.35; Tue, 13 Dec 2022 01:04:48 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@gmail.com header.s=20210112 header.b=fnkii9b6; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235068AbiLMJDr (ORCPT + 99 others); Tue, 13 Dec 2022 04:03:47 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36128 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235012AbiLMJCH (ORCPT ); Tue, 13 Dec 2022 04:02:07 -0500 Received: from mail-pj1-x102e.google.com (mail-pj1-x102e.google.com [IPv6:2607:f8b0:4864:20::102e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C902DF02E; Tue, 13 Dec 2022 01:02:03 -0800 (PST) Received: by mail-pj1-x102e.google.com with SMTP id w4-20020a17090ac98400b002186f5d7a4cso2905496pjt.0; Tue, 13 Dec 2022 01:02:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=JbLCNFK4yUEg4Jb2vovMrI4jYY1qH30LfoBhRWLCbl0=; b=fnkii9b6+rvOHo65mYRv+TUP2xVkjHg3Ql2Vq67yU7MLmBQSW6jMngG3ndKpHJDySv Bq49davB5VVZxzUomzrFSF4UCB3EfCkLhtMptUX4kkQ0qIowNR1h/lcl11pXjNwdbyWa 3HJ+jeNulBwQDoZVwSJ3x3rBLyV8x16rsw3a1nO04qO20pfHvw7H3y1L6Vc4t7SrdRjj Qi6T5R0Sfvth/dMbX82Z8lXXyxSj61M5o0TZv5Yrn//l+p7ckx/H9qvMmtU9yORQyOhs D9e8Gr3SyoW6IkMv7e3wRL28LtAdeGC+Za5cFwC+MPvvmCTL5EJsGDdhXzOn3MtjG58u BJCA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=JbLCNFK4yUEg4Jb2vovMrI4jYY1qH30LfoBhRWLCbl0=; b=qIf/ggchARo4mq52oofsAu9C2Gc0cQw0g53aLeFQQRiwzEi7jamcDZF2AZHbTz6AUm ZgsR1t12dCwrqXLfIidHXqPjOjgzxKeLqEVrTx6UungT7MvoU6KlQSL7XWgfEdnI8Adf cVSIwmDgIAh7xYT0Oeklwswg7eEqjIo5tvvzgS6JU/STJ1kqa7r/Pkzjt7bK+aEd05c+ 1+HNVilj3Ho3qZZ3uE0jNEHNxjpzPt2GZQHk6QgaVrjzurbc47P4nfea8hMPukG9uC7V +YmocddzXSHgyGKVCkU+w+yVf8cM2FcMcdInkED8WWKDddtzvircNhTEMldsTny+B3Oc TVJA== X-Gm-Message-State: ANoB5pkx0UU+LAMgFFHqgrBmfLII81qTfW6ENTxN/ZtvvSLsura3rRaL v01zv3PXFQH1+U/lRhcIjUs= X-Received: by 2002:a05:6a20:6d8a:b0:ad:a0c2:53ee with SMTP id gl10-20020a056a206d8a00b000ada0c253eemr7147746pzb.12.1670922123411; Tue, 13 Dec 2022 01:02:03 -0800 (PST) Received: from localhost.localdomain (2001-b400-e2dc-5c03-264b-f684-a8c9-21ae.emome-ip6.hinet.net. [2001:b400:e2dc:5c03:264b:f684:a8c9:21ae]) by smtp.gmail.com with ESMTPSA id 81-20020a621954000000b0056b9ec7e2desm7141682pfz.125.2022.12.13.01.02.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 13 Dec 2022 01:02:02 -0800 (PST) From: Victor Shih X-Google-Original-From: Victor Shih To: ulf.hansson@linaro.org, adrian.hunter@intel.com Cc: linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, benchuanggli@gmail.com, HL.Liu@genesyslogic.com.tw, Greg.tu@genesyslogic.com.tw, takahiro.akashi@linaro.org, dlunev@chromium.org, Victor Shih , Ben Chuang Subject: [PATCH V6 17/24] mmc: sdhci-uhs2: add uhs2_control() to initialise the interface Date: Tue, 13 Dec 2022 17:00:40 +0800 Message-Id: <20221213090047.3805-18-victor.shih@genesyslogic.com.tw> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221213090047.3805-1-victor.shih@genesyslogic.com.tw> References: <20221213090047.3805-1-victor.shih@genesyslogic.com.tw> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM, RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1752089009864447480?= X-GMAIL-MSGID: =?utf-8?q?1752089009864447480?= This is a sdhci version of mmc's uhs2_set_reg operation. UHS-II interface (related registers) will be initialised here. Signed-off-by: Ben Chuang Signed-off-by: AKASHI Takahiro Signed-off-by: Victor Shih --- drivers/mmc/host/sdhci-uhs2.c | 92 +++++++++++++++++++++++++++++++++++ drivers/mmc/host/sdhci.c | 11 +++++ 2 files changed, 103 insertions(+) diff --git a/drivers/mmc/host/sdhci-uhs2.c b/drivers/mmc/host/sdhci-uhs2.c index c7e411fa0a6e..de15a6559702 100644 --- a/drivers/mmc/host/sdhci-uhs2.c +++ b/drivers/mmc/host/sdhci-uhs2.c @@ -276,6 +276,48 @@ static void __sdhci_uhs2_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) sdhci_set_clock(host, host->clock); } +static void sdhci_uhs2_set_config(struct sdhci_host *host) +{ + u32 value; + u16 sdhci_uhs2_set_ptr = sdhci_readw(host, SDHCI_UHS2_SETTINGS_PTR); + u16 sdhci_uhs2_gen_set_reg = (sdhci_uhs2_set_ptr + 0); + u16 sdhci_uhs2_phy_set_reg = (sdhci_uhs2_set_ptr + 4); + u16 sdhci_uhs2_tran_set_reg = (sdhci_uhs2_set_ptr + 8); + u16 sdhci_uhs2_tran_set_1_reg = (sdhci_uhs2_set_ptr + 12); + + /* Set Gen Settings */ + value = FIELD_PREP(SDHCI_UHS2_GEN_SETTINGS_N_LANES_MASK, host->mmc->uhs2_caps.n_lanes_set); + sdhci_writel(host, value, sdhci_uhs2_gen_set_reg); + + /* Set PHY Settings */ + value = FIELD_PREP(SDHCI_UHS2_PHY_N_LSS_DIR_MASK, host->mmc->uhs2_caps.n_lss_dir_set) | + FIELD_PREP(SDHCI_UHS2_PHY_N_LSS_SYN_MASK, host->mmc->uhs2_caps.n_lss_sync_set); + if (host->mmc->flags & MMC_UHS2_SPEED_B) + value |= SDHCI_UHS2_PHY_SET_SPEED_B; + sdhci_writel(host, value, sdhci_uhs2_phy_set_reg); + + /* Set LINK-TRAN Settings */ + value = FIELD_PREP(SDHCI_UHS2_TRAN_RETRY_CNT_MASK, host->mmc->uhs2_caps.max_retry_set) | + FIELD_PREP(SDHCI_UHS2_TRAN_N_FCU_MASK, host->mmc->uhs2_caps.n_fcu_set); + sdhci_writel(host, value, sdhci_uhs2_tran_set_reg); + sdhci_writel(host, host->mmc->uhs2_caps.n_data_gap_set, sdhci_uhs2_tran_set_1_reg); +} + +static int sdhci_uhs2_check_dormant(struct sdhci_host *host) +{ + u32 val; + /* 100ms */ + int timeout = 100000; + + if (read_poll_timeout_atomic(sdhci_readl, val, (val & SDHCI_UHS2_IN_DORMANT_STATE), + 100, timeout, true, host, SDHCI_PRESENT_STATE)) { + pr_warn("%s: UHS2 IN_DORMANT fail in 100ms.\n", mmc_hostname(host->mmc)); + sdhci_dumpregs(host); + return -EIO; + } + return 0; +} + /*****************************************************************************\ * * * MMC callbacks * @@ -361,6 +403,55 @@ static int sdhci_uhs2_enable_clk(struct mmc_host *mmc) return 0; } +static int sdhci_uhs2_do_detect_init(struct mmc_host *mmc); + +static int sdhci_uhs2_control(struct mmc_host *mmc, enum sd_uhs2_operation op) +{ + struct sdhci_host *host = mmc_priv(mmc); + int err = 0; + u16 sdhci_uhs2_set_ptr = sdhci_readw(host, SDHCI_UHS2_SETTINGS_PTR); + u16 sdhci_uhs2_phy_set_reg = (sdhci_uhs2_set_ptr + 4); + + DBG("Begin uhs2 control, act %d.\n", op); + + switch (op) { + case UHS2_PHY_INIT: + err = sdhci_uhs2_do_detect_init(mmc); + break; + case UHS2_SET_CONFIG: + sdhci_uhs2_set_config(host); + break; + case UHS2_ENABLE_INT: + sdhci_uhs2_clear_set_irqs(host, 0, SDHCI_INT_CARD_INT); + break; + case UHS2_DISABLE_INT: + sdhci_uhs2_clear_set_irqs(host, SDHCI_INT_CARD_INT, 0); + break; + case UHS2_SET_SPEED_B: + sdhci_writeb(host, SDHCI_UHS2_PHY_SET_SPEED_B, sdhci_uhs2_phy_set_reg); + break; + case UHS2_CHECK_DORMANT: + err = sdhci_uhs2_check_dormant(host); + break; + case UHS2_DISABLE_CLK: + err = sdhci_uhs2_disable_clk(mmc); + break; + case UHS2_ENABLE_CLK: + err = sdhci_uhs2_enable_clk(mmc); + break; + case UHS2_POST_ATTACH_SD: + host->ops->uhs2_post_attach_sd(host); + break; + default: + pr_err("%s: input sd uhs2 operation %d is wrong!\n", + mmc_hostname(host->mmc), op); + err = -EIO; + break; + } + + return err; +} + /*****************************************************************************\ * * * Driver init/exit * @@ -489,6 +580,7 @@ static int sdhci_uhs2_host_ops_init(struct sdhci_host *host) host->mmc_host_ops.start_signal_voltage_switch = sdhci_uhs2_start_signal_voltage_switch; host->mmc_host_ops.uhs2_set_ios = sdhci_uhs2_set_ios; + host->mmc_host_ops.uhs2_control = sdhci_uhs2_control; return 0; } diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c index 49bbdc155b2b..3656e66fcca7 100644 --- a/drivers/mmc/host/sdhci.c +++ b/drivers/mmc/host/sdhci.c @@ -234,6 +234,17 @@ void sdhci_reset(struct sdhci_host *host, u8 mask) } EXPORT_SYMBOL_GPL(sdhci_reset); +void sdhci_clear_set_irqs(struct sdhci_host *host, u32 clear, u32 set) +{ + u32 ier; + + ier = sdhci_readl(host, SDHCI_INT_ENABLE); + ier &= ~clear; + ier |= set; + sdhci_writel(host, ier, SDHCI_INT_ENABLE); + sdhci_writel(host, ier, SDHCI_SIGNAL_ENABLE); +} + static bool sdhci_do_reset(struct sdhci_host *host, u8 mask) { if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) { From patchwork Tue Dec 13 09:00:41 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Victor Shih X-Patchwork-Id: 32712 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:8188:b0:89:790f:f786 with SMTP id m8csp3858451dye; Tue, 13 Dec 2022 01:05:19 -0800 (PST) X-Google-Smtp-Source: AA0mqf6dpiD2pJBcyBLWc6XXGy8dvqDIPdsChxSBZfig2iFs+mMCxqM+jIg9gNNORJiQjLLvVe0g X-Received: by 2002:a17:90a:510f:b0:21a:dc1:e805 with SMTP id t15-20020a17090a510f00b0021a0dc1e805mr20055335pjh.31.1670922318871; Tue, 13 Dec 2022 01:05:18 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1670922318; cv=none; d=google.com; s=arc-20160816; b=po9/2I8hZqaeOoTF0Br7/EWh5LT29ynQnMtcCULUqlyQxO4JsBO7+vgikAjzeJS4N4 4V8QyDItFUiON43ux71K8v+f0x5J2sDQvHQGCdd5cztlvENxtavAX/tfmdF5apGzP4C9 KutTF6EqyAzID3iQc8ikoOosjGde538K57twIxAHqE96fnjsGARDpYtiFW3i2kHk0fgc VzZbgmeGXJqcDypakFI7ubLLbvCTJ7/9zVDu7cd8CKS+MDPEjtyJD9gaiUf7WYwc7RiB hZqphZQE1jqXAbg9vydtqFUVHBciiu6iBsi9lf3zvwCCm+PbJBB+2kJCnyutChPlu+1X mcYQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=OTYzESb3FLleJwZkaEZR68cuWsBpXNW0+eOTPywtMdc=; b=v8OHmuGIdrxMpHah2Sx+a7vzjx5gVDNv5/Y8doXbMROgWLYHjAs7ISGlBKKb1iDbT0 NZ9YQcDmBMpJIPs+XlVbpVMj14/GK6Z8z4vyhmBrsstoJsdp78X2tXoCEl8faJWwks19 eviF2JqM+8YhK/Xsafn3veByBjlW3CRMxVYMW/2rJy28XRSI5uXiZKysgplYPozip3tb rLIIZ0cJwhAxA/C7UnnSHDd52m2aMlAL7RO1pVmlcx+GKNO6wLXoWqp4E9IHQ/6HAZ0o 0RpxxW5cZ0W7HXMdpBvvG1IAKWoNkaO1rTut1N/m/WzZM+9MUFh2t8C22ntcz6AsnWiR 0z7Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20210112 header.b=UF+ZWmuU; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id n3-20020a638f03000000b0047764bac806si11648402pgd.749.2022.12.13.01.05.05; Tue, 13 Dec 2022 01:05:18 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@gmail.com header.s=20210112 header.b=UF+ZWmuU; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234781AbiLMJDx (ORCPT + 99 others); Tue, 13 Dec 2022 04:03:53 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36492 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235020AbiLMJCK (ORCPT ); Tue, 13 Dec 2022 04:02:10 -0500 Received: from mail-pg1-x529.google.com (mail-pg1-x529.google.com [IPv6:2607:f8b0:4864:20::529]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 921DEE0CC; Tue, 13 Dec 2022 01:02:07 -0800 (PST) Received: by mail-pg1-x529.google.com with SMTP id 36so3064277pgp.10; Tue, 13 Dec 2022 01:02:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=OTYzESb3FLleJwZkaEZR68cuWsBpXNW0+eOTPywtMdc=; b=UF+ZWmuUufqRt68zfV2qk1qhlWHAk8zrkV1+2F5C4nn3gcJkIsX3VSAYYB/XhkgtbQ 7RJm0aOXdoYVJp3ce5ly4k4fYLY7pBP3/AJFpz3qk37dgrpfmwy1qXrtre7C0J1gbzyb 2s+R2AZM/Xqe+UI6E9s35FrPdjFHA6xX4uKfw0zHAUQj5qgglh7wYD5bY4MPAwTwqS/j YglNXE0jYzgiNCK5W5CYdheJo1XIk2PQK0RfONduJfyYqef+LwBfveAJ8I+OxIsHEZkD vjcdB6RIaxmnZIvL0RkvRV8Y4paVvSC5rQUDCI79f4A7G5EbWuXRWDlURZOG2OAHjyAD 71YA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=OTYzESb3FLleJwZkaEZR68cuWsBpXNW0+eOTPywtMdc=; b=3kyQR9svTXcJj+Na/cVgXcEinN+bGieS635R+Vpp5sfbNm21rVDsJkOv/Y1glO1UUW lWK57RluuoaTSe2h+oPMdoLE/FnSbuCbVA3vZQQRKv9wiivL8oi4CrG24EyMjpRPYCqd rRpFJ1Pwgsrp4golXcU+7riUM2HDMPevThE7xqARwJVhNlkUp6R7n47U8bWlKFDp/mL7 tDaZWNd9Uc9Vcjusr3rU5UziM8EhAo6H89IUCPDCRtyP0DUDolHSbjuj6xWODrcDDutV 2hMuOyHf+TgkPphdny2wn9ismjOjiKvkddShWnSIz7IISYkpuUb6WBFGPs9sJa3m4vU7 04mg== X-Gm-Message-State: ANoB5pkApu6mLeKjagHO9qrG/xU69YW67HlUmnKVWliz9tZYrSJEgXcV eQ87OnouSU4a848GvTA66M8= X-Received: by 2002:a62:cd86:0:b0:578:7e9d:97b2 with SMTP id o128-20020a62cd86000000b005787e9d97b2mr7565883pfg.3.1670922126952; Tue, 13 Dec 2022 01:02:06 -0800 (PST) Received: from localhost.localdomain (2001-b400-e2dc-5c03-264b-f684-a8c9-21ae.emome-ip6.hinet.net. [2001:b400:e2dc:5c03:264b:f684:a8c9:21ae]) by smtp.gmail.com with ESMTPSA id 81-20020a621954000000b0056b9ec7e2desm7141682pfz.125.2022.12.13.01.02.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 13 Dec 2022 01:02:06 -0800 (PST) From: Victor Shih X-Google-Original-From: Victor Shih To: ulf.hansson@linaro.org, adrian.hunter@intel.com Cc: linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, benchuanggli@gmail.com, HL.Liu@genesyslogic.com.tw, Greg.tu@genesyslogic.com.tw, takahiro.akashi@linaro.org, dlunev@chromium.org, Victor Shih , Ben Chuang Subject: [PATCH V6 18/24] mmc: sdhci-uhs2: add request() and others Date: Tue, 13 Dec 2022 17:00:41 +0800 Message-Id: <20221213090047.3805-19-victor.shih@genesyslogic.com.tw> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221213090047.3805-1-victor.shih@genesyslogic.com.tw> References: <20221213090047.3805-1-victor.shih@genesyslogic.com.tw> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM, RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1752089041048125911?= X-GMAIL-MSGID: =?utf-8?q?1752089041048125911?= This is a sdhci version of mmc's request operation. It covers both UHS-I and UHS-II. Signed-off-by: Ben Chuang Signed-off-by: AKASHI Takahiro Signed-off-by: Victor Shih --- drivers/mmc/host/sdhci-uhs2.c | 418 ++++++++++++++++++++++++++++++++++ drivers/mmc/host/sdhci.c | 78 ++++--- drivers/mmc/host/sdhci.h | 14 ++ 3 files changed, 481 insertions(+), 29 deletions(-) diff --git a/drivers/mmc/host/sdhci-uhs2.c b/drivers/mmc/host/sdhci-uhs2.c index de15a6559702..7a34f66c4215 100644 --- a/drivers/mmc/host/sdhci-uhs2.c +++ b/drivers/mmc/host/sdhci-uhs2.c @@ -15,6 +15,7 @@ #include #include #include +#include #include "sdhci.h" #include "sdhci-uhs2.h" @@ -25,6 +26,8 @@ #define SDHCI_UHS2_DUMP(f, x...) \ pr_err("%s: " DRIVER_NAME ": " f, mmc_hostname(host->mmc), ## x) +#define UHS2_ARG_IOADR_MASK 0xfff + void sdhci_uhs2_dump_regs(struct sdhci_host *host) { if (!(host->mmc->flags & MMC_UHS2_SUPPORT)) @@ -59,6 +62,11 @@ EXPORT_SYMBOL_GPL(sdhci_uhs2_dump_regs); * * \*****************************************************************************/ +static inline u16 uhs2_dev_cmd(struct mmc_command *cmd) +{ + return be16_to_cpu((__be16)cmd->uhs2_cmd->arg) & UHS2_ARG_IOADR_MASK; +} + static inline int mmc_opt_regulator_set_ocr(struct mmc_host *mmc, struct regulator *supply, unsigned short vdd_bit) @@ -452,6 +460,415 @@ static int sdhci_uhs2_control(struct mmc_host *mmc, enum sd_uhs2_operation op) return err; } +/*****************************************************************************\ + * * + * Core functions * + * * +\*****************************************************************************/ + +static void sdhci_uhs2_prepare_data(struct sdhci_host *host, + struct mmc_command *cmd) +{ + struct mmc_data *data = cmd->data; + + sdhci_initialize_data(host, data); + + sdhci_prepare_dma(host, data); + + sdhci_writew(host, data->blksz, SDHCI_UHS2_BLOCK_SIZE); + sdhci_writew(host, data->blocks, SDHCI_UHS2_BLOCK_COUNT); +} + +static void sdhci_uhs2_finish_data(struct sdhci_host *host) +{ + struct mmc_data *data = host->data; + + __sdhci_finish_data_common(host); + + __sdhci_finish_mrq(host, data->mrq); +} + +static void sdhci_uhs2_set_transfer_mode(struct sdhci_host *host, + struct mmc_command *cmd) +{ + u16 mode; + struct mmc_data *data = cmd->data; + + if (!data) { + /* clear Auto CMD settings for no data CMDs */ + if (uhs2_dev_cmd(cmd) == UHS2_DEV_CMD_TRANS_ABORT) { + mode = 0; + } else { + mode = sdhci_readw(host, SDHCI_UHS2_TRANS_MODE); + if (cmd->opcode == MMC_STOP_TRANSMISSION || cmd->opcode == MMC_ERASE) + mode |= SDHCI_UHS2_TRNS_WAIT_EBSY; + else + /* send status mode */ + if (cmd->opcode == MMC_SEND_STATUS) + mode = 0; + } + + DBG("UHS2 no data trans mode is 0x%x.\n", mode); + + sdhci_writew(host, mode, SDHCI_UHS2_TRANS_MODE); + return; + } + + WARN_ON(!host->data); + + mode = SDHCI_UHS2_TRNS_BLK_CNT_EN | SDHCI_UHS2_TRNS_WAIT_EBSY; + if (data->flags & MMC_DATA_WRITE) + mode |= SDHCI_UHS2_TRNS_DATA_TRNS_WRT; + + if (data->blocks == 1 && + data->blksz != 512 && + cmd->opcode != MMC_READ_SINGLE_BLOCK && + cmd->opcode != MMC_WRITE_BLOCK) { + mode &= ~SDHCI_UHS2_TRNS_BLK_CNT_EN; + mode |= SDHCI_UHS2_TRNS_BLK_BYTE_MODE; + } + + if (host->flags & SDHCI_REQ_USE_DMA) + mode |= SDHCI_UHS2_TRNS_DMA; + + if ((host->mmc->uhs2_ios.is_2L_HD_mode) && !cmd->uhs2_tmode0_flag) + mode |= SDHCI_UHS2_TRNS_2L_HD; + + sdhci_writew(host, mode, SDHCI_UHS2_TRANS_MODE); + + DBG("UHS2 trans mode is 0x%x.\n", mode); +} + +static void __sdhci_uhs2_send_command(struct sdhci_host *host, + struct mmc_command *cmd) +{ + int i, j; + int cmd_reg; + + i = 0; + sdhci_writel(host, + ((u32)cmd->uhs2_cmd->arg << 16) | + (u32)cmd->uhs2_cmd->header, + SDHCI_UHS2_CMD_PACKET + i); + i += 4; + + /* + * Per spec, playload (config) should be MSB before sending out. + * But we don't need convert here because had set payload as + * MSB when preparing config read/write commands. + */ + for (j = 0; j < cmd->uhs2_cmd->payload_len / sizeof(u32); j++) { + sdhci_writel(host, *(cmd->uhs2_cmd->payload + j), SDHCI_UHS2_CMD_PACKET + i); + i += 4; + } + + for ( ; i < SDHCI_UHS2_CMD_PACK_MAX_LEN; i += 4) + sdhci_writel(host, 0, SDHCI_UHS2_CMD_PACKET + i); + + DBG("UHS2 CMD packet_len = %d.\n", cmd->uhs2_cmd->packet_len); + for (i = 0; i < cmd->uhs2_cmd->packet_len; i++) + DBG("UHS2 CMD_PACKET[%d] = 0x%x.\n", i, + sdhci_readb(host, SDHCI_UHS2_CMD_PACKET + i)); + + cmd_reg = FIELD_PREP(SDHCI_UHS2_CMD_PACK_LEN_MASK, cmd->uhs2_cmd->packet_len); + if ((cmd->flags & MMC_CMD_MASK) == MMC_CMD_ADTC) + cmd_reg |= SDHCI_UHS2_CMD_DATA; + if (cmd->opcode == MMC_STOP_TRANSMISSION) + cmd_reg |= SDHCI_UHS2_CMD_CMD12; + + /* UHS2 Native ABORT */ + if ((cmd->uhs2_cmd->header & UHS2_NATIVE_PACKET) && + (uhs2_dev_cmd(cmd) == UHS2_DEV_CMD_TRANS_ABORT)) + cmd_reg |= SDHCI_UHS2_CMD_TRNS_ABORT; + + /* UHS2 Native DORMANT */ + if ((cmd->uhs2_cmd->header & UHS2_NATIVE_PACKET) && + (uhs2_dev_cmd(cmd) == UHS2_DEV_CMD_GO_DORMANT_STATE)) + cmd_reg |= SDHCI_UHS2_CMD_DORMANT; + + DBG("0x%x is set to UHS2 CMD register.\n", cmd_reg); + + sdhci_writew(host, cmd_reg, SDHCI_UHS2_CMD); +} + +static bool sdhci_uhs2_send_command(struct sdhci_host *host, + struct mmc_command *cmd) +{ + int flags; + u32 mask; + unsigned long timeout; + + WARN_ON(host->cmd); + + /* Initially, a command has no error */ + cmd->error = 0; + + if (cmd->opcode == MMC_STOP_TRANSMISSION) + cmd->flags |= MMC_RSP_BUSY; + + mask = SDHCI_CMD_INHIBIT; + + if (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) + return false; + + host->cmd = cmd; + host->data_timeout = 0; + if (sdhci_data_line_cmd(cmd)) { + WARN_ON(host->data_cmd); + host->data_cmd = cmd; + __sdhci_uhs2_set_timeout(host); + } + + if (cmd->data) + sdhci_uhs2_prepare_data(host, cmd); + + sdhci_uhs2_set_transfer_mode(host, cmd); + + if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) { + WARN_ONCE(1, "Unsupported response type!\n"); + /* + * This does not happen in practice because 136-bit response + * commands never have busy waiting, so rather than complicate + * the error path, just remove busy waiting and continue. + */ + cmd->flags &= ~MMC_RSP_BUSY; + } + + if (!(cmd->flags & MMC_RSP_PRESENT)) + flags = SDHCI_CMD_RESP_NONE; + else if (cmd->flags & MMC_RSP_136) + flags = SDHCI_CMD_RESP_LONG; + else if (cmd->flags & MMC_RSP_BUSY) + flags = SDHCI_CMD_RESP_SHORT_BUSY; + else + flags = SDHCI_CMD_RESP_SHORT; + + if (cmd->flags & MMC_RSP_CRC) + flags |= SDHCI_CMD_CRC; + if (cmd->flags & MMC_RSP_OPCODE) + flags |= SDHCI_CMD_INDEX; + + timeout = jiffies; + if (host->data_timeout) + timeout += nsecs_to_jiffies(host->data_timeout); + else if (!cmd->data && cmd->busy_timeout > 9000) + timeout += DIV_ROUND_UP(cmd->busy_timeout, 1000) * HZ + HZ; + else + timeout += 10 * HZ; + sdhci_mod_timer(host, cmd->mrq, timeout); + + __sdhci_uhs2_send_command(host, cmd); + + return true; +} + +static bool sdhci_uhs2_send_command_retry(struct sdhci_host *host, + struct mmc_command *cmd, + unsigned long flags) + __releases(host->lock) + __acquires(host->lock) +{ + struct mmc_command *deferred_cmd = host->deferred_cmd; + int timeout = 10; /* Approx. 10 ms */ + bool present; + + while (!sdhci_uhs2_send_command(host, cmd)) { + if (!timeout--) { + pr_err("%s: Controller never released inhibit bit(s).\n", + mmc_hostname(host->mmc)); + sdhci_dumpregs(host); + cmd->error = -EIO; + return false; + } + + spin_unlock_irqrestore(&host->lock, flags); + + usleep_range(1000, 1250); + + present = host->mmc->ops->get_cd(host->mmc); + + spin_lock_irqsave(&host->lock, flags); + + /* A deferred command might disappear, handle that */ + if (cmd == deferred_cmd && cmd != host->deferred_cmd) + return true; + + if (sdhci_present_error(host, cmd, present)) + return false; + } + + if (cmd == host->deferred_cmd) + host->deferred_cmd = NULL; + + return true; +} + +static void __sdhci_uhs2_finish_command(struct sdhci_host *host) +{ + struct mmc_command *cmd = host->cmd; + u8 resp; + u8 ecode; + bool bReadA0 = 0; + int i; + + if (host->mmc->card) { + if (host->mmc->card->uhs2_state & MMC_UHS2_INITIALIZED) { + resp = sdhci_readb(host, SDHCI_UHS2_RESPONSE + 2); + if (resp & UHS2_RES_NACK_MASK) { + ecode = (resp >> UHS2_RES_ECODE_POS) & UHS2_RES_ECODE_MASK; + pr_err("%s: NACK is got, ECODE=0x%x.\n", + mmc_hostname(host->mmc), ecode); + } + bReadA0 = 1; + } + } + + if (cmd->uhs2_resp && + cmd->uhs2_resp_len && cmd->uhs2_resp_len <= 20) { + /* Get whole response of some native CCMD, like + * DEVICE_INIT, ENUMERATE. + */ + for (i = 0; i < cmd->uhs2_resp_len; i++) + cmd->uhs2_resp[i] = sdhci_readb(host, SDHCI_UHS2_RESPONSE + i); + } else { + /* Get SD CMD response and Payload for some read + * CCMD, like INQUIRY_CFG. + */ + /* Per spec (p136), payload field is divided into + * a unit of DWORD and transmission order within + * a DWORD is big endian. + */ + if (!bReadA0) + sdhci_readl(host, SDHCI_UHS2_RESPONSE); + for (i = 4; i < 20; i += 4) { + cmd->resp[i / 4 - 1] = + (sdhci_readb(host, + SDHCI_UHS2_RESPONSE + i) << 24) | + (sdhci_readb(host, + SDHCI_UHS2_RESPONSE + i + 1) + << 16) | + (sdhci_readb(host, + SDHCI_UHS2_RESPONSE + i + 2) + << 8) | + sdhci_readb(host, SDHCI_UHS2_RESPONSE + i + 3); + } + } +} + +static void sdhci_uhs2_finish_command(struct sdhci_host *host) +{ + struct mmc_command *cmd = host->cmd; + + __sdhci_uhs2_finish_command(host); + + host->cmd = NULL; + + if (cmd->mrq->cap_cmd_during_tfr && cmd == cmd->mrq->cmd) + mmc_command_done(host->mmc, cmd->mrq); + + /* + * The host can send and interrupt when the busy state has + * ended, allowing us to wait without wasting CPU cycles. + * The busy signal uses DAT0 so this is similar to waiting + * for data to complete. + * + * Note: The 1.0 specification is a bit ambiguous about this + * feature so there might be some problems with older + * controllers. + */ + if (cmd->flags & MMC_RSP_BUSY) { + if (cmd->data) { + DBG("Cannot wait for busy signal when also doing a data transfer"); + } else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ) && + cmd == host->data_cmd) { + /* Command complete before busy is ended */ + return; + } + } + + /* Processed actual command. */ + if (host->data && host->data_early) + sdhci_uhs2_finish_data(host); + + if (!cmd->data) + __sdhci_finish_mrq(host, cmd->mrq); +} + +void sdhci_uhs2_request(struct mmc_host *mmc, struct mmc_request *mrq) +{ + struct sdhci_host *host = mmc_priv(mmc); + struct mmc_command *cmd; + unsigned long flags; + bool present; + + if (!(sdhci_uhs2_mode(host))) { + sdhci_request(mmc, mrq); + return; + } + + mrq->stop = NULL; + mrq->sbc = NULL; + if (mrq->data) + mrq->data->stop = NULL; + + /* Firstly check card presence */ + present = mmc->ops->get_cd(mmc); + + spin_lock_irqsave(&host->lock, flags); + + if (sdhci_present_error(host, mrq->cmd, present)) + goto out_finish; + + cmd = mrq->cmd; + + if (!sdhci_uhs2_send_command(host, cmd)) + goto out_finish; + + spin_unlock_irqrestore(&host->lock, flags); + + return; + +out_finish: + sdhci_finish_mrq(host, mrq); + spin_unlock_irqrestore(&host->lock, flags); +} +EXPORT_SYMBOL_GPL(sdhci_uhs2_request); + +int sdhci_uhs2_request_atomic(struct mmc_host *mmc, struct mmc_request *mrq) +{ + struct sdhci_host *host = mmc_priv(mmc); + struct mmc_command *cmd; + unsigned long flags; + int ret = 0; + + if (!host->mmc->flags & MMC_UHS2_SUPPORT) + return sdhci_request_atomic(mmc, mrq); + + spin_lock_irqsave(&host->lock, flags); + + if (sdhci_present_error(host, mrq->cmd, true)) { + sdhci_finish_mrq(host, mrq); + goto out_finish; + } + + cmd = mrq->cmd; + + /* + * The HSQ may send a command in interrupt context without polling + * the busy signaling, which means we should return BUSY if controller + * has not released inhibit bits to allow HSQ trying to send request + * again in non-atomic context. So we should not finish this request + * here. + */ + if (!sdhci_uhs2_send_command(host, cmd)) + ret = -EBUSY; + +out_finish: + spin_unlock_irqrestore(&host->lock, flags); + return ret; +} +EXPORT_SYMBOL_GPL(sdhci_uhs2_request_atomic); + /*****************************************************************************\ * * * Driver init/exit * @@ -581,6 +998,7 @@ static int sdhci_uhs2_host_ops_init(struct sdhci_host *host) sdhci_uhs2_start_signal_voltage_switch; host->mmc_host_ops.uhs2_set_ios = sdhci_uhs2_set_ios; host->mmc_host_ops.uhs2_control = sdhci_uhs2_control; + host->mmc_host_ops.request = sdhci_uhs2_request; return 0; } diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c index 3656e66fcca7..c547fc3b8b47 100644 --- a/drivers/mmc/host/sdhci.c +++ b/drivers/mmc/host/sdhci.c @@ -47,8 +47,6 @@ static unsigned int debug_quirks = 0; static unsigned int debug_quirks2; -static bool sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd); - void sdhci_dumpregs(struct sdhci_host *host) { SDHCI_DUMP("============ SDHCI REGISTER DUMP ===========\n"); @@ -147,10 +145,11 @@ void sdhci_enable_v4_mode(struct sdhci_host *host) } EXPORT_SYMBOL_GPL(sdhci_enable_v4_mode); -static inline bool sdhci_data_line_cmd(struct mmc_command *cmd) +bool sdhci_data_line_cmd(struct mmc_command *cmd) { return cmd->data || cmd->flags & MMC_RSP_BUSY; } +EXPORT_SYMBOL_GPL(sdhci_data_line_cmd); static void sdhci_set_card_detection(struct sdhci_host *host, bool enable) { @@ -424,7 +423,7 @@ static void __sdhci_led_activate(struct sdhci_host *host) sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); } -static void __sdhci_led_deactivate(struct sdhci_host *host) +void __sdhci_led_deactivate(struct sdhci_host *host) { u8 ctrl; @@ -435,6 +434,7 @@ static void __sdhci_led_deactivate(struct sdhci_host *host) ctrl &= ~SDHCI_CTRL_LED; sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); } +EXPORT_SYMBOL_GPL(__sdhci_led_deactivate); #if IS_REACHABLE(CONFIG_LEDS_CLASS) static void sdhci_led_control(struct led_classdev *led, @@ -513,14 +513,15 @@ static inline void sdhci_led_deactivate(struct sdhci_host *host) #endif -static void sdhci_mod_timer(struct sdhci_host *host, struct mmc_request *mrq, - unsigned long timeout) +void sdhci_mod_timer(struct sdhci_host *host, struct mmc_request *mrq, + unsigned long timeout) { if (sdhci_data_line_cmd(mrq->cmd)) mod_timer(&host->data_timer, timeout); else mod_timer(&host->timer, timeout); } +EXPORT_SYMBOL_GPL(sdhci_mod_timer); static void sdhci_del_timer(struct sdhci_host *host, struct mmc_request *mrq) { @@ -1087,8 +1088,7 @@ static void sdhci_set_timeout(struct sdhci_host *host, struct mmc_command *cmd) __sdhci_set_timeout(host, cmd); } -static void sdhci_initialize_data(struct sdhci_host *host, - struct mmc_data *data) +void sdhci_initialize_data(struct sdhci_host *host, struct mmc_data *data) { WARN_ON(host->data); @@ -1101,6 +1101,7 @@ static void sdhci_initialize_data(struct sdhci_host *host, host->data_early = 0; host->data->bytes_xfered = 0; } +EXPORT_SYMBOL_GPL(sdhci_initialize_data); static inline void sdhci_set_block_info(struct sdhci_host *host, struct mmc_data *data) @@ -1123,12 +1124,8 @@ static inline void sdhci_set_block_info(struct sdhci_host *host, } } -static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd) +void sdhci_prepare_dma(struct sdhci_host *host, struct mmc_data *data) { - struct mmc_data *data = cmd->data; - - sdhci_initialize_data(host, data); - if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) { struct scatterlist *sg; unsigned int length_mask, offset_mask; @@ -1213,6 +1210,16 @@ static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd) } sdhci_set_transfer_irqs(host); +} +EXPORT_SYMBOL_GPL(sdhci_prepare_dma); + +static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd) +{ + struct mmc_data *data = cmd->data; + + sdhci_initialize_data(host, data); + + sdhci_prepare_dma(host, data); sdhci_set_block_info(host, data); } @@ -1255,8 +1262,7 @@ static struct dma_chan *sdhci_external_dma_channel(struct sdhci_host *host, return data->flags & MMC_DATA_WRITE ? host->tx_chan : host->rx_chan; } -static int sdhci_external_dma_setup(struct sdhci_host *host, - struct mmc_command *cmd) +int sdhci_external_dma_setup(struct sdhci_host *host, struct mmc_command *cmd) { int ret, i; enum dma_transfer_direction dir; @@ -1309,8 +1315,9 @@ static int sdhci_external_dma_setup(struct sdhci_host *host, return ret; } +EXPORT_SYMBOL_GPL(sdhci_external_dma_setup); -static void sdhci_external_dma_release(struct sdhci_host *host) +void sdhci_external_dma_release(struct sdhci_host *host) { if (host->tx_chan) { dma_release_channel(host->tx_chan); @@ -1324,9 +1331,10 @@ static void sdhci_external_dma_release(struct sdhci_host *host) sdhci_switch_external_dma(host, false); } +EXPORT_SYMBOL_GPL(sdhci_external_dma_release); -static void __sdhci_external_dma_prepare_data(struct sdhci_host *host, - struct mmc_command *cmd) +void __sdhci_external_dma_prepare_data(struct sdhci_host *host, + struct mmc_command *cmd) { struct mmc_data *data = cmd->data; @@ -1337,6 +1345,7 @@ static void __sdhci_external_dma_prepare_data(struct sdhci_host *host, sdhci_set_block_info(host, data); } +EXPORT_SYMBOL(__sdhci_external_dma_prepare_data); static void sdhci_external_dma_prepare_data(struct sdhci_host *host, struct mmc_command *cmd) @@ -1351,8 +1360,8 @@ static void sdhci_external_dma_prepare_data(struct sdhci_host *host, } } -static void sdhci_external_dma_pre_transfer(struct sdhci_host *host, - struct mmc_command *cmd) +void sdhci_external_dma_pre_transfer(struct sdhci_host *host, + struct mmc_command *cmd) { struct dma_chan *chan; @@ -1363,6 +1372,7 @@ static void sdhci_external_dma_pre_transfer(struct sdhci_host *host, if (chan) dma_async_issue_pending(chan); } +EXPORT_SYMBOL_GPL(sdhci_external_dma_pre_transfer); #else @@ -1414,8 +1424,7 @@ static inline bool sdhci_auto_cmd23(struct sdhci_host *host, return mrq->sbc && (host->flags & SDHCI_AUTO_CMD23); } -static inline bool sdhci_manual_cmd23(struct sdhci_host *host, - struct mmc_request *mrq) +static inline bool sdhci_manual_cmd23(struct sdhci_host *host, struct mmc_request *mrq) { return mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23); } @@ -1530,7 +1539,7 @@ static void sdhci_set_mrq_done(struct sdhci_host *host, struct mmc_request *mrq) WARN_ON(i >= SDHCI_MAX_MRQS); } -static void __sdhci_finish_mrq(struct sdhci_host *host, struct mmc_request *mrq) +void __sdhci_finish_mrq(struct sdhci_host *host, struct mmc_request *mrq) { if (host->cmd && host->cmd->mrq == mrq) host->cmd = NULL; @@ -1554,15 +1563,17 @@ static void __sdhci_finish_mrq(struct sdhci_host *host, struct mmc_request *mrq) if (!sdhci_has_requests(host)) sdhci_led_deactivate(host); } +EXPORT_SYMBOL_GPL(__sdhci_finish_mrq); -static void sdhci_finish_mrq(struct sdhci_host *host, struct mmc_request *mrq) +void sdhci_finish_mrq(struct sdhci_host *host, struct mmc_request *mrq) { __sdhci_finish_mrq(host, mrq); queue_work(host->complete_wq, &host->complete_work); } +EXPORT_SYMBOL_GPL(sdhci_finish_mrq); -static void __sdhci_finish_data(struct sdhci_host *host, bool sw_data_timeout) +void __sdhci_finish_data_common(struct sdhci_host *host) { struct mmc_command *data_cmd = host->data_cmd; struct mmc_data *data = host->data; @@ -1596,6 +1607,14 @@ static void __sdhci_finish_data(struct sdhci_host *host, bool sw_data_timeout) data->bytes_xfered = 0; else data->bytes_xfered = data->blksz * data->blocks; +} +EXPORT_SYMBOL_GPL(__sdhci_finish_data_common); + +static void __sdhci_finish_data(struct sdhci_host *host, bool sw_data_timeout) +{ + struct mmc_data *data = host->data; + + __sdhci_finish_data_common(host); /* * Need to send CMD12 if - @@ -1681,8 +1700,6 @@ static bool sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd) sdhci_prepare_data(host, cmd); } - sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT); - sdhci_set_transfer_mode(host, cmd); if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) { @@ -1725,13 +1742,15 @@ static bool sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd) if (host->use_external_dma) sdhci_external_dma_pre_transfer(host, cmd); + sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT); + sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND); return true; } -static bool sdhci_present_error(struct sdhci_host *host, - struct mmc_command *cmd, bool present) +bool sdhci_present_error(struct sdhci_host *host, + struct mmc_command *cmd, bool present) { if (!present || host->flags & SDHCI_DEVICE_DEAD) { cmd->error = -ENOMEDIUM; @@ -1740,6 +1759,7 @@ static bool sdhci_present_error(struct sdhci_host *host, return false; } +EXPORT_SYMBOL_GPL(sdhci_present_error); static bool sdhci_send_command_retry(struct sdhci_host *host, struct mmc_command *cmd, diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h index c2f989dc2361..3b87fcae1294 100644 --- a/drivers/mmc/host/sdhci.h +++ b/drivers/mmc/host/sdhci.h @@ -831,6 +831,20 @@ static inline void sdhci_read_caps(struct sdhci_host *host) __sdhci_read_caps(host, NULL, NULL, NULL); } +bool sdhci_data_line_cmd(struct mmc_command *cmd); +void sdhci_mod_timer(struct sdhci_host *host, struct mmc_request *mrq, unsigned long timeout); +void sdhci_initialize_data(struct sdhci_host *host, struct mmc_data *data); +void sdhci_prepare_dma(struct sdhci_host *host, struct mmc_data *data); +#if IS_ENABLED(CONFIG_MMC_SDHCI_EXTERNAL_DMA) +int sdhci_external_dma_setup(struct sdhci_host *host, struct mmc_command *cmd); +void sdhci_external_dma_release(struct sdhci_host *host); +void __sdhci_external_dma_prepare_data(struct sdhci_host *host, struct mmc_command *cmd); +void sdhci_external_dma_pre_transfer(struct sdhci_host *host, struct mmc_command *cmd); +#endif +void __sdhci_finish_mrq(struct sdhci_host *host, struct mmc_request *mrq); +void sdhci_finish_mrq(struct sdhci_host *host, struct mmc_request *mrq); +void __sdhci_finish_data_common(struct sdhci_host *host); +bool sdhci_present_error(struct sdhci_host *host, struct mmc_command *cmd, bool present); u16 sdhci_calc_clk(struct sdhci_host *host, unsigned int clock, unsigned int *actual_clock); void sdhci_set_clock(struct sdhci_host *host, unsigned int clock); From patchwork Tue Dec 13 09:00:42 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Victor Shih X-Patchwork-Id: 32713 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:8188:b0:89:790f:f786 with SMTP id m8csp3858785dye; Tue, 13 Dec 2022 01:05:54 -0800 (PST) X-Google-Smtp-Source: AA0mqf5GhAkk8EBviCxx1R0KGCA8cWx4zLSMZvAtPPUwvqMW86EhXimYqt2zuY996PErZeKxcWGO X-Received: by 2002:a17:906:a3c1:b0:7ad:a2ee:f8e6 with SMTP id ca1-20020a170906a3c100b007ada2eef8e6mr16448122ejb.15.1670922354586; Tue, 13 Dec 2022 01:05:54 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1670922354; cv=none; d=google.com; s=arc-20160816; b=uQ6xs1PXvaU9EvBx8DAaH7CrLhsuiffw+5cLGhqtzXSrMnmximwAjxfHq67PYezMfJ HERkuDbHxPzFnXz0s204dvRcKIlqi09UnSlJplYEJB8jI9SwCytJCoVOYbF2XChhdvp8 jKGaRF4f0mpCJOUIVT+eXzDVm8bXq4ai5QYQgKsS1dkV9s+YROYfZVLJeJbA8/+I/Sk5 bfXnfYmA2HBNtAi1nYgLuJhWiTSpUTFYhkAzF2wNPq4dyiPQBwXY7SwzNSKCNym2Yh9X uoCsioiLKNco1cl5Icsvm+2xDd5qU3SZ9/7n+adJigVOYZF02b1fUeDhBJTRxrL7QjIs 6tjQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=dh59pYQwKDM1HDquCnxsJWwO76ld0s+zL5jEafQfMSE=; b=De0LcF5ZItBDyaIV0AN0YMMZVGU7qykE6Wgf+Te2tsmHHhup3Sa4jazYitII6zQ2HU fpskOV3ZMvto+Z2Xrj2qX3s+z/kCtfFnZw0tgvMGTogdCdttb4VjHKS1Q/rw4RnwlMPB hsBIFbGIooXNKNFg39UcX6uWGSRLUWY8iChWtwRVxPWPn0PTDmTJrlR8PQiDlwVkAsYY KLQ0YZxWW1pnT5546kY7hojmC2mq5e3nVqDbz9uiKu5Ixg05StfzpqWZNyWIARuH3jOP 9cKqudRh47q1FGyWkTKKuKRPuowUcbNaXiRODkUyiOnTZJfSUVsnjx0Peg+nVNejrEQh cMHA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20210112 header.b=DpOd3pcH; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id hz3-20020a1709072ce300b0078e11e9286csi7976144ejc.195.2022.12.13.01.05.30; Tue, 13 Dec 2022 01:05:54 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@gmail.com header.s=20210112 header.b=DpOd3pcH; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235078AbiLMJED (ORCPT + 99 others); Tue, 13 Dec 2022 04:04:03 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36152 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235028AbiLMJCM (ORCPT ); Tue, 13 Dec 2022 04:02:12 -0500 Received: from mail-pg1-x533.google.com (mail-pg1-x533.google.com [IPv6:2607:f8b0:4864:20::533]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 71185F03A; Tue, 13 Dec 2022 01:02:11 -0800 (PST) Received: by mail-pg1-x533.google.com with SMTP id f9so9975834pgf.7; Tue, 13 Dec 2022 01:02:11 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=dh59pYQwKDM1HDquCnxsJWwO76ld0s+zL5jEafQfMSE=; b=DpOd3pcH5Zaasm3Rk5pN+gIPtaKAFHGaAbZsHD5WvK0j5cHDTYQQchug78LA6gdFnl KRFHkUrGpjbjWJxeXmgEL2gsPYhjaW6bi86wc9u+WGWnvfZ4hyf/49exrOqq9IiIuvnD 7clZTtG9Sb6TuRx7mB1yBwqgLdxIE3ZJSjh717XKVJw8TZRFKXZE5K4qMs5hig/b5GVz tCqAkkOnRdh15AcwyiZFZEvbZQoFt169NwY/YN5kQndHOOBuag3I98prLPRTB9DKoyCW r0AExJCEZEu9FLM5kOdZizz5LfiUR4HYTMPfi0btbJAZIJ5NWSm6k3GgBh12t4b8CTHI GBCA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=dh59pYQwKDM1HDquCnxsJWwO76ld0s+zL5jEafQfMSE=; b=Kvxxrw/YgVjxq0mIXL8Y4tiFUOh6b07264cgLOlmL2RoDHhRnIv+segU0B1i7KoDmr 8x2zpKdJCLpHvd6M/zUOP4rkOz1r6j1rynq5hrau4lvQxoB/IecbBQ69Zx/9fLmLG9W9 CrZhli5+AllZi0wpMiUoKkc1NpDGfTai2DGjzqqRcUOB5ikxlMT/1sFFy5dPsih9GyeV plWPU4zbsn508g+Fr2Hvqo/GEP4TyromccwcSaBV/5PqCMuJvGtOPLSB7M1nngmgBhSd SAqciYOCYMnX4Y0uyXZeK4+jzkOMutUgLRPeul3oOfWdY/3wPdP1BtdtS68s+qAT7Kmo rYfw== X-Gm-Message-State: ANoB5pkx+cp92Cvyzzg4fbfG3Cwr4vMKIB53H2gZNzzbyV6bja+P4FfE CaJ4pXmwQG2X7jz4L2vDYLU= X-Received: by 2002:a05:6a00:1696:b0:566:94d0:8c96 with SMTP id k22-20020a056a00169600b0056694d08c96mr25110115pfc.26.1670922130871; Tue, 13 Dec 2022 01:02:10 -0800 (PST) Received: from localhost.localdomain (2001-b400-e2dc-5c03-264b-f684-a8c9-21ae.emome-ip6.hinet.net. [2001:b400:e2dc:5c03:264b:f684:a8c9:21ae]) by smtp.gmail.com with ESMTPSA id 81-20020a621954000000b0056b9ec7e2desm7141682pfz.125.2022.12.13.01.02.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 13 Dec 2022 01:02:09 -0800 (PST) From: Victor Shih X-Google-Original-From: Victor Shih To: ulf.hansson@linaro.org, adrian.hunter@intel.com Cc: linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, benchuanggli@gmail.com, HL.Liu@genesyslogic.com.tw, Greg.tu@genesyslogic.com.tw, takahiro.akashi@linaro.org, dlunev@chromium.org, Victor Shih , Ben Chuang Subject: [PATCH V6 19/24] mmc: sdhci-uhs2: add irq() and others Date: Tue, 13 Dec 2022 17:00:42 +0800 Message-Id: <20221213090047.3805-20-victor.shih@genesyslogic.com.tw> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221213090047.3805-1-victor.shih@genesyslogic.com.tw> References: <20221213090047.3805-1-victor.shih@genesyslogic.com.tw> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM, RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1752089078517633314?= X-GMAIL-MSGID: =?utf-8?q?1752089078517633314?= This is a UHS-II version of sdhci's request() operation. It handles UHS-II related command interrupts and errors. Signed-off-by: Ben Chuang Signed-off-by: AKASHI Takahiro Signed-off-by: Victor Shih --- drivers/mmc/host/sdhci-uhs2.c | 223 +++++++++++++++++++++++++++++++++- drivers/mmc/host/sdhci-uhs2.h | 3 + drivers/mmc/host/sdhci.c | 111 +++++++++-------- drivers/mmc/host/sdhci.h | 6 + 4 files changed, 294 insertions(+), 49 deletions(-) diff --git a/drivers/mmc/host/sdhci-uhs2.c b/drivers/mmc/host/sdhci-uhs2.c index 7a34f66c4215..769cf88b21cf 100644 --- a/drivers/mmc/host/sdhci-uhs2.c +++ b/drivers/mmc/host/sdhci-uhs2.c @@ -16,6 +16,7 @@ #include #include #include +#include #include "sdhci.h" #include "sdhci-uhs2.h" @@ -794,6 +795,226 @@ static void sdhci_uhs2_finish_command(struct sdhci_host *host) __sdhci_finish_mrq(host, cmd->mrq); } +/*****************************************************************************\ + * * + * Request done * + * * +\*****************************************************************************/ + +static bool sdhci_uhs2_request_done(struct sdhci_host *host) +{ + unsigned long flags; + struct mmc_request *mrq; + int i; + + spin_lock_irqsave(&host->lock, flags); + + for (i = 0; i < SDHCI_MAX_MRQS; i++) { + mrq = host->mrqs_done[i]; + if (mrq) + break; + } + + if (!mrq) { + spin_unlock_irqrestore(&host->lock, flags); + return true; + } + + /* + * Always unmap the data buffers if they were mapped by + * sdhci_prepare_data() whenever we finish with a request. + * This avoids leaking DMA mappings on error. + */ + if (host->flags & SDHCI_REQ_USE_DMA) + sdhci_request_done_dma(host, mrq); + + /* + * The controller needs a reset of internal state machines + * upon error conditions. + */ + if (sdhci_needs_reset(host, mrq)) { + /* + * Do not finish until command and data lines are available for + * reset. Note there can only be one other mrq, so it cannot + * also be in mrqs_done, otherwise host->cmd and host->data_cmd + * would both be null. + */ + if (host->cmd || host->data_cmd) { + spin_unlock_irqrestore(&host->lock, flags); + return true; + } + + /* Some controllers need this kick or reset won't work here */ + if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET) + /* This is to force an update */ + host->ops->set_clock(host, host->clock); + + sdhci_uhs2_reset(host, SDHCI_UHS2_SW_RESET_SD); + host->pending_reset = false; + } + + host->mrqs_done[i] = NULL; + + spin_unlock_irqrestore(&host->lock, flags); + + if (host->ops->request_done) + host->ops->request_done(host, mrq); + else + mmc_request_done(host->mmc, mrq); + + return false; +} + +static void sdhci_uhs2_complete_work(struct work_struct *work) +{ + struct sdhci_host *host = container_of(work, struct sdhci_host, + complete_work); + + if (!sdhci_uhs2_mode(host)) { + sdhci_complete_work(work); + return; + } + + while (!sdhci_uhs2_request_done(host)) + ; +} + +/*****************************************************************************\ + * * + * Interrupt handling * + * * +\*****************************************************************************/ + +static void __sdhci_uhs2_irq(struct sdhci_host *host, u32 uhs2mask) +{ + struct mmc_command *cmd = host->cmd; + + DBG("*** %s got UHS2 error interrupt: 0x%08x\n", + mmc_hostname(host->mmc), uhs2mask); + + if (uhs2mask & SDHCI_UHS2_INT_CMD_ERR_MASK) { + if (!host->cmd) { + pr_err("%s: Got cmd interrupt 0x%08x but no cmd.\n", + mmc_hostname(host->mmc), + (unsigned int)uhs2mask); + sdhci_dumpregs(host); + return; + } + host->cmd->error = -EILSEQ; + if (uhs2mask & SDHCI_UHS2_INT_CMD_TIMEOUT) + host->cmd->error = -ETIMEDOUT; + } + + if (uhs2mask & SDHCI_UHS2_INT_DATA_ERR_MASK) { + if (!host->data) { + pr_err("%s: Got data interrupt 0x%08x but no data.\n", + mmc_hostname(host->mmc), + (unsigned int)uhs2mask); + sdhci_dumpregs(host); + return; + } + + if (uhs2mask & SDHCI_UHS2_INT_DEADLOCK_TIMEOUT) { + pr_err("%s: Got deadlock timeout interrupt 0x%08x\n", + mmc_hostname(host->mmc), + (unsigned int)uhs2mask); + host->data->error = -ETIMEDOUT; + } else if (uhs2mask & SDHCI_UHS2_INT_ADMA_ERROR) { + pr_err("%s: ADMA error = 0x %x\n", + mmc_hostname(host->mmc), + sdhci_readb(host, SDHCI_ADMA_ERROR)); + host->data->error = -EIO; + } else { + host->data->error = -EILSEQ; + } + } + + if (host->data && host->data->error) + sdhci_uhs2_finish_data(host); + else + sdhci_finish_mrq(host, cmd->mrq); +} + +u32 sdhci_uhs2_irq(struct sdhci_host *host, u32 intmask) +{ + u32 mask = intmask, uhs2mask; + + if (!(host->mmc->flags & MMC_UHS2_SUPPORT)) + goto out; + + if (intmask & SDHCI_INT_ERROR) { + uhs2mask = sdhci_readl(host, SDHCI_UHS2_INT_STATUS); + if (!(uhs2mask & SDHCI_UHS2_INT_ERROR_MASK)) + goto cmd_irq; + + /* Clear error interrupts */ + sdhci_writel(host, uhs2mask & SDHCI_UHS2_INT_ERROR_MASK, + SDHCI_UHS2_INT_STATUS); + + /* Handle error interrupts */ + __sdhci_uhs2_irq(host, uhs2mask); + + /* Caller, shdci_irq(), doesn't have to care UHS-2 errors */ + intmask &= ~SDHCI_INT_ERROR; + mask &= SDHCI_INT_ERROR; + } + +cmd_irq: + if (intmask & SDHCI_INT_CMD_MASK) { + /* Clear command interrupt */ + sdhci_writel(host, intmask & SDHCI_INT_CMD_MASK, SDHCI_INT_STATUS); + + /* Handle command interrupt */ + if (intmask & SDHCI_INT_RESPONSE) + sdhci_uhs2_finish_command(host); + + /* Caller, shdci_irq(), doesn't have to care UHS-2 command */ + intmask &= ~SDHCI_INT_CMD_MASK; + mask &= SDHCI_INT_CMD_MASK; + } + + /* Clear already-handled interrupts. */ + sdhci_writel(host, mask, SDHCI_INT_STATUS); + +out: + return intmask; +} +EXPORT_SYMBOL_GPL(sdhci_uhs2_irq); + +static irqreturn_t sdhci_uhs2_thread_irq(int irq, void *dev_id) +{ + struct sdhci_host *host = dev_id; + struct mmc_command *cmd; + unsigned long flags; + u32 isr; + + if (!sdhci_uhs2_mode(host)) + return sdhci_thread_irq(irq, dev_id); + + while (!sdhci_uhs2_request_done(host)) + ; + + spin_lock_irqsave(&host->lock, flags); + + isr = host->thread_isr; + host->thread_isr = 0; + + cmd = host->deferred_cmd; + if (cmd && !sdhci_uhs2_send_command_retry(host, cmd, flags)) + sdhci_finish_mrq(host, cmd->mrq); + + spin_unlock_irqrestore(&host->lock, flags); + + if (isr & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) { + struct mmc_host *mmc = host->mmc; + + mmc->ops->card_event(mmc); + mmc_detect_change(mmc, msecs_to_jiffies(200)); + } + + return IRQ_HANDLED; +} + void sdhci_uhs2_request(struct mmc_host *mmc, struct mmc_request *mrq) { struct sdhci_host *host = mmc_priv(mmc); @@ -978,7 +1199,7 @@ static int sdhci_uhs2_do_detect_init(struct mmc_host *mmc) } /* Init complete, do soft reset and enable UHS2 error irqs. */ - host->ops->uhs2_reset(host, SDHCI_UHS2_SW_RESET_SD); + sdhci_uhs2_reset(host, SDHCI_UHS2_SW_RESET_SD); sdhci_uhs2_clear_set_irqs(host, SDHCI_INT_ALL_MASK, SDHCI_UHS2_INT_ERROR_MASK); /* * N.B SDHCI_INT_ENABLE and SDHCI_SIGNAL_ENABLE was cleared diff --git a/drivers/mmc/host/sdhci-uhs2.h b/drivers/mmc/host/sdhci-uhs2.h index 184fee80253c..64b7f356c9fc 100644 --- a/drivers/mmc/host/sdhci-uhs2.h +++ b/drivers/mmc/host/sdhci-uhs2.h @@ -179,5 +179,8 @@ bool sdhci_uhs2_mode(struct sdhci_host *host); void sdhci_uhs2_reset(struct sdhci_host *host, u16 mask); void sdhci_uhs2_set_timeout(struct sdhci_host *host, struct mmc_command *cmd); void sdhci_uhs2_clear_set_irqs(struct sdhci_host *host, u32 clear, u32 set); +void sdhci_uhs2_request(struct mmc_host *mmc, struct mmc_request *mrq); +int sdhci_uhs2_request_atomic(struct mmc_host *mmc, struct mmc_request *mrq); +u32 sdhci_uhs2_irq(struct sdhci_host *host, u32 intmask); #endif /* __SDHCI_UHS2_H */ diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c index c547fc3b8b47..6c67b79102eb 100644 --- a/drivers/mmc/host/sdhci.c +++ b/drivers/mmc/host/sdhci.c @@ -47,6 +47,8 @@ static unsigned int debug_quirks = 0; static unsigned int debug_quirks2; +static bool sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd); + void sdhci_dumpregs(struct sdhci_host *host) { SDHCI_DUMP("============ SDHCI REGISTER DUMP ===========\n"); @@ -1256,11 +1258,12 @@ static int sdhci_external_dma_init(struct sdhci_host *host) return ret; } -static struct dma_chan *sdhci_external_dma_channel(struct sdhci_host *host, - struct mmc_data *data) +struct dma_chan *sdhci_external_dma_channel(struct sdhci_host *host, + struct mmc_data *data) { return data->flags & MMC_DATA_WRITE ? host->tx_chan : host->rx_chan; } +EXPORT_SYMBOL_GPL(sdhci_external_dma_channel); int sdhci_external_dma_setup(struct sdhci_host *host, struct mmc_command *cmd) { @@ -1509,7 +1512,7 @@ static void sdhci_set_transfer_mode(struct sdhci_host *host, sdhci_writew(host, mode, SDHCI_TRANSFER_MODE); } -static bool sdhci_needs_reset(struct sdhci_host *host, struct mmc_request *mrq) +bool sdhci_needs_reset(struct sdhci_host *host, struct mmc_request *mrq) { return (!(host->flags & SDHCI_DEVICE_DEAD) && ((mrq->cmd && mrq->cmd->error) || @@ -1517,8 +1520,9 @@ static bool sdhci_needs_reset(struct sdhci_host *host, struct mmc_request *mrq) (mrq->data && mrq->data->stop && mrq->data->stop->error) || (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))); } +EXPORT_SYMBOL_GPL(sdhci_needs_reset); -static void sdhci_set_mrq_done(struct sdhci_host *host, struct mmc_request *mrq) +void sdhci_set_mrq_done(struct sdhci_host *host, struct mmc_request *mrq) { int i; @@ -1538,6 +1542,7 @@ static void sdhci_set_mrq_done(struct sdhci_host *host, struct mmc_request *mrq) WARN_ON(i >= SDHCI_MAX_MRQS); } +EXPORT_SYMBOL_GPL(sdhci_set_mrq_done); void __sdhci_finish_mrq(struct sdhci_host *host, struct mmc_request *mrq) { @@ -3122,6 +3127,55 @@ static const struct mmc_host_ops sdhci_ops = { * * \*****************************************************************************/ +void sdhci_request_done_dma(struct sdhci_host *host, struct mmc_request *mrq) +{ + struct mmc_data *data = mrq->data; + + if (data && data->host_cookie == COOKIE_MAPPED) { + if (host->bounce_buffer) { + /* + * On reads, copy the bounced data into the + * sglist + */ + if (mmc_get_dma_dir(data) == DMA_FROM_DEVICE) { + unsigned int length = data->bytes_xfered; + + if (length > host->bounce_buffer_size) { + pr_err("%s: bounce buffer is %u bytes but DMA claims to have transferred %u bytes\n", + mmc_hostname(host->mmc), + host->bounce_buffer_size, + data->bytes_xfered); + /* Cap it down and continue */ + length = host->bounce_buffer_size; + } + dma_sync_single_for_cpu( + host->mmc->parent, + host->bounce_addr, + host->bounce_buffer_size, + DMA_FROM_DEVICE); + sg_copy_from_buffer(data->sg, + data->sg_len, + host->bounce_buffer, + length); + } else { + /* No copying, just switch ownership */ + dma_sync_single_for_cpu( + host->mmc->parent, + host->bounce_addr, + host->bounce_buffer_size, + mmc_get_dma_dir(data)); + } + } else { + /* Unmap the raw data */ + dma_unmap_sg(mmc_dev(host->mmc), data->sg, + data->sg_len, + mmc_get_dma_dir(data)); + } + data->host_cookie = COOKIE_UNMAPPED; + } +} +EXPORT_SYMBOL_GPL(sdhci_request_done_dma); + static bool sdhci_request_done(struct sdhci_host *host) { unsigned long flags; @@ -3186,48 +3240,7 @@ static bool sdhci_request_done(struct sdhci_host *host) sdhci_set_mrq_done(host, mrq); } - if (data && data->host_cookie == COOKIE_MAPPED) { - if (host->bounce_buffer) { - /* - * On reads, copy the bounced data into the - * sglist - */ - if (mmc_get_dma_dir(data) == DMA_FROM_DEVICE) { - unsigned int length = data->bytes_xfered; - - if (length > host->bounce_buffer_size) { - pr_err("%s: bounce buffer is %u bytes but DMA claims to have transferred %u bytes\n", - mmc_hostname(host->mmc), - host->bounce_buffer_size, - data->bytes_xfered); - /* Cap it down and continue */ - length = host->bounce_buffer_size; - } - dma_sync_single_for_cpu( - mmc_dev(host->mmc), - host->bounce_addr, - host->bounce_buffer_size, - DMA_FROM_DEVICE); - sg_copy_from_buffer(data->sg, - data->sg_len, - host->bounce_buffer, - length); - } else { - /* No copying, just switch ownership */ - dma_sync_single_for_cpu( - mmc_dev(host->mmc), - host->bounce_addr, - host->bounce_buffer_size, - mmc_get_dma_dir(data)); - } - } else { - /* Unmap the raw data */ - dma_unmap_sg(mmc_dev(host->mmc), data->sg, - data->sg_len, - mmc_get_dma_dir(data)); - } - data->host_cookie = COOKIE_UNMAPPED; - } + sdhci_request_done_dma(host, mrq); } host->mrqs_done[i] = NULL; @@ -3242,7 +3255,7 @@ static bool sdhci_request_done(struct sdhci_host *host) return false; } -static void sdhci_complete_work(struct work_struct *work) +void sdhci_complete_work(struct work_struct *work) { struct sdhci_host *host = container_of(work, struct sdhci_host, complete_work); @@ -3250,6 +3263,7 @@ static void sdhci_complete_work(struct work_struct *work) while (!sdhci_request_done(host)) ; } +EXPORT_SYMBOL_GPL(sdhci_complete_work); static void sdhci_timeout_timer(struct timer_list *t) { @@ -3705,7 +3719,7 @@ static irqreturn_t sdhci_irq(int irq, void *dev_id) return result; } -static irqreturn_t sdhci_thread_irq(int irq, void *dev_id) +irqreturn_t sdhci_thread_irq(int irq, void *dev_id) { struct sdhci_host *host = dev_id; struct mmc_command *cmd; @@ -3735,6 +3749,7 @@ static irqreturn_t sdhci_thread_irq(int irq, void *dev_id) return IRQ_HANDLED; } +EXPORT_SYMBOL_GPL(sdhci_thread_irq); /*****************************************************************************\ * * diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h index 3b87fcae1294..4979af7cabca 100644 --- a/drivers/mmc/host/sdhci.h +++ b/drivers/mmc/host/sdhci.h @@ -840,7 +840,10 @@ int sdhci_external_dma_setup(struct sdhci_host *host, struct mmc_command *cmd); void sdhci_external_dma_release(struct sdhci_host *host); void __sdhci_external_dma_prepare_data(struct sdhci_host *host, struct mmc_command *cmd); void sdhci_external_dma_pre_transfer(struct sdhci_host *host, struct mmc_command *cmd); +struct dma_chan *sdhci_external_dma_channel(struct sdhci_host *host, struct mmc_data *data); #endif +bool sdhci_needs_reset(struct sdhci_host *host, struct mmc_request *mrq); +void sdhci_set_mrq_done(struct sdhci_host *host, struct mmc_request *mrq); void __sdhci_finish_mrq(struct sdhci_host *host, struct mmc_request *mrq); void sdhci_finish_mrq(struct sdhci_host *host, struct mmc_request *mrq); void __sdhci_finish_data_common(struct sdhci_host *host); @@ -870,6 +873,9 @@ void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios); int sdhci_start_signal_voltage_switch(struct mmc_host *mmc, struct mmc_ios *ios); void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable); +void sdhci_request_done_dma(struct sdhci_host *host, struct mmc_request *mrq); +void sdhci_complete_work(struct work_struct *work); +irqreturn_t sdhci_thread_irq(int irq, void *dev_id); void sdhci_adma_write_desc(struct sdhci_host *host, void **desc, dma_addr_t addr, int len, unsigned int cmd); From patchwork Tue Dec 13 09:00:43 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Victor Shih X-Patchwork-Id: 32716 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:8188:b0:89:790f:f786 with SMTP id m8csp3859355dye; Tue, 13 Dec 2022 01:06:50 -0800 (PST) X-Google-Smtp-Source: AA0mqf6ZjAUs24acY8/1t5qx2mBkT8QV26sx8mirx8NL/hZuxMTA19Ndl45TJKkKcgV2Z1Ee0NvS X-Received: by 2002:a17:906:698f:b0:7ad:d250:b903 with SMTP id i15-20020a170906698f00b007add250b903mr15355288ejr.56.1670922410467; Tue, 13 Dec 2022 01:06:50 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1670922410; cv=none; d=google.com; s=arc-20160816; b=DC89TorbVXSUEeX6jXHEAmIX9eM/nzTHlMdft3DuAXhO7oNFM/hlES8NiOLo2HTDHG +1aXFUTlkEa7wQADlc6IJyqrq/jbqn1DkskLILNRLDFUf+ZOuHz9vXD1feY+kH8RoK5K /KQ5Ba2oInPWmQBPn+HgPyt2WOHxyujj39xbcyVbTud6gy0+05rcOYLn/pA2abbn0TKe dZnzPKqTgs+Rh3Ysh2Cr4J1BCtKtJKOlX2I53aATpDyzpShSQm4s0WQC2c7PiHaKeDOR KsePU0pED9xtFIDS3Nx3fVbK7JgZN3a1khQGSTGzU13DRiA+szfcKshgWG85tKhlkqlX 7Lvw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=U31b18eVLHBrM5oL05iUzR4a34yZz+5o0FIdgd2Rgig=; b=U0DzktBIXF5efcK5WXUUnfupQmzce20hrv4P4kQTXH4kSW9HZjCklBhMsU/1+pWfmQ oNSU3jcrEhYcJ0DTwJAgHJkwoC2v5FsHzE/Wu67Ckzf/18ngxzavME5vzclEUpOFhh7u CImAnOeu8Xtznsg8X07lXuwCinS+tVF0L4tRWvII/n53/AbDNYj5TsglzlNL6CZX5x90 DMPzIUCpkDSfj0oYQCjIV+QO+cw49NclNja4HBduJaQEgJnCq31WClcVJ9YhCB7SSsTX Wicw7F6e3x5qQeILeiW03aWaJJvoXKKfLnTY25l4v1d0N8ZxP78wbr9VWShM1aBz9Pvy S9+w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20210112 header.b=naeeRTrq; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id u6-20020a1709063b8600b007ae814af66bsi6115643ejf.389.2022.12.13.01.06.27; Tue, 13 Dec 2022 01:06:50 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@gmail.com header.s=20210112 header.b=naeeRTrq; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235085AbiLMJEM (ORCPT + 99 others); Tue, 13 Dec 2022 04:04:12 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36724 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234819AbiLMJCR (ORCPT ); Tue, 13 Dec 2022 04:02:17 -0500 Received: from mail-pg1-x535.google.com (mail-pg1-x535.google.com [IPv6:2607:f8b0:4864:20::535]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AA57111A2F; Tue, 13 Dec 2022 01:02:14 -0800 (PST) Received: by mail-pg1-x535.google.com with SMTP id r18so9967814pgr.12; Tue, 13 Dec 2022 01:02:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=U31b18eVLHBrM5oL05iUzR4a34yZz+5o0FIdgd2Rgig=; b=naeeRTrq15fzUu6RQuQwK823GuASH2/4y/SESPfxtmc6v7dePbJ1b5h8BayZ7GDGG4 atIdbsw6MGFF+z3XWy3ZKTTXlB8w/KGQ2yw9uXH4Mbe1iYbS1/5J1as/5BHeAqlvtKzk GS8Ah4JZukvNGlGsOrLJORlTNMfHQzpkoGE6D05egV62n7g474EANXj+rTPyudZIiN51 bN39hinnm50nIEv2zshOpjUmTx0pnDR+/8rwNjcU7F3TZIOIrpPtSsC2EUtde2QQRVQI AtKPSP0anQxptwU4uTHRMSU2NypUEXoPLBSRkKZFxO+r1bWZasZATdXka/+GPD08s8pY AyJg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=U31b18eVLHBrM5oL05iUzR4a34yZz+5o0FIdgd2Rgig=; b=ZZ6vNs9Ksrhb7gcA1FkftpmU7j2qYKV3t75XQnVJEA+Wae0xTByGKaew2KzWV9yYM2 +C73ydT5ERfqqt05/ZLa7DW4hmQARdUpRjFJ2QDpEPoom5nxYkL6X/cC8rpqIC+pDDbm lj11WSVMrDfsF+8+Ma8oCPndd51G3Jnyam8O+oqy0aRrtHH9q4cO6hWComGimf41zncn W3g2dnVY1GwycDc1i2fwKdLHlrHMoOkE3MC8dowJz+EGqMPUC1amhRqOiJ6CMzAuDqQh 0QV9T9CHru+F1/d/mGvuS+OAouDLxky3x9PYv+DWE9cDwOpZgT+5q+pr5z5zeTx/i8b8 k1Qg== X-Gm-Message-State: ANoB5pkEdPzdptzVVZZ7tQAm5VMZrSiFuDa3ZfrWQgscNH3Q7bVZfL2r 64FijpR7/wzbzAYFLjlkDRw= X-Received: by 2002:aa7:90c5:0:b0:572:6e9b:9f9e with SMTP id k5-20020aa790c5000000b005726e9b9f9emr17392315pfk.19.1670922134299; Tue, 13 Dec 2022 01:02:14 -0800 (PST) Received: from localhost.localdomain (2001-b400-e2dc-5c03-264b-f684-a8c9-21ae.emome-ip6.hinet.net. [2001:b400:e2dc:5c03:264b:f684:a8c9:21ae]) by smtp.gmail.com with ESMTPSA id 81-20020a621954000000b0056b9ec7e2desm7141682pfz.125.2022.12.13.01.02.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 13 Dec 2022 01:02:13 -0800 (PST) From: Victor Shih X-Google-Original-From: Victor Shih To: ulf.hansson@linaro.org, adrian.hunter@intel.com Cc: linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, benchuanggli@gmail.com, HL.Liu@genesyslogic.com.tw, Greg.tu@genesyslogic.com.tw, takahiro.akashi@linaro.org, dlunev@chromium.org, Victor Shih , Ben Chuang Subject: [PATCH V6 20/24] mmc: sdhci-uhs2: add add_host() and others to set up the driver Date: Tue, 13 Dec 2022 17:00:43 +0800 Message-Id: <20221213090047.3805-21-victor.shih@genesyslogic.com.tw> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221213090047.3805-1-victor.shih@genesyslogic.com.tw> References: <20221213090047.3805-1-victor.shih@genesyslogic.com.tw> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM, RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1752089137389548527?= X-GMAIL-MSGID: =?utf-8?q?1752089137389548527?= This is a UHS-II version of sdhci's add_host/remove_host operation. Any sdhci drivers which are capable of handling UHS-II cards must call those functions instead of the corresponding sdhci's. Signed-off-by: Ben Chuang Signed-off-by: AKASHI Takahiro Signed-off-by: Victor Shih --- drivers/mmc/host/sdhci-uhs2.c | 171 ++++++++++++++++++++++++++++++++++ drivers/mmc/host/sdhci-uhs2.h | 2 + drivers/mmc/host/sdhci.c | 28 ++++-- drivers/mmc/host/sdhci.h | 12 +++ 4 files changed, 204 insertions(+), 9 deletions(-) diff --git a/drivers/mmc/host/sdhci-uhs2.c b/drivers/mmc/host/sdhci-uhs2.c index 769cf88b21cf..5349173b4f90 100644 --- a/drivers/mmc/host/sdhci-uhs2.c +++ b/drivers/mmc/host/sdhci-uhs2.c @@ -17,6 +17,7 @@ #include #include #include +#include #include "sdhci.h" #include "sdhci-uhs2.h" @@ -1015,6 +1016,176 @@ static irqreturn_t sdhci_uhs2_thread_irq(int irq, void *dev_id) return IRQ_HANDLED; } +/*****************************************************************************\ + * + * Device allocation/registration * + * * +\*****************************************************************************/ + +static int __sdhci_uhs2_add_host_v4(struct sdhci_host *host, u32 caps1) +{ + struct mmc_host *mmc; + u32 max_current_caps2; + + if (host->version < SDHCI_SPEC_400) + return 0; + + mmc = host->mmc; + + /* Support UHS2 */ + if (caps1 & SDHCI_SUPPORT_UHS2) + mmc->caps2 |= MMC_CAP2_SD_UHS2; + + max_current_caps2 = sdhci_readl(host, SDHCI_MAX_CURRENT_1); + + if ((caps1 & SDHCI_CAN_VDD2_180) && + !max_current_caps2 && + !IS_ERR(mmc->supply.vmmc2)) { + /* UHS2 - VDD2 */ + int curr = regulator_get_current_limit(mmc->supply.vmmc2); + + if (curr > 0) { + /* convert to SDHCI_MAX_CURRENT format */ + curr = curr / 1000; /* convert to mA */ + curr = curr / SDHCI_MAX_CURRENT_MULTIPLIER; + curr = min_t(u32, curr, SDHCI_MAX_CURRENT_LIMIT); + max_current_caps2 = curr; + } + } + + if (caps1 & SDHCI_CAN_VDD2_180) { + mmc->ocr_avail_uhs2 |= MMC_VDD2_165_195; + /* + * UHS2 doesn't require this. Only UHS-I bus needs to set + * max current. + */ + mmc->max_current_180_vdd2 = (max_current_caps2 & + SDHCI_MAX_CURRENT_VDD2_180_MASK) * + SDHCI_MAX_CURRENT_MULTIPLIER; + } else { + mmc->caps2 &= ~MMC_CAP2_SD_UHS2; + } + + return 0; +} + +static int sdhci_uhs2_host_ops_init(struct sdhci_host *host); + +static int __sdhci_uhs2_add_host(struct sdhci_host *host) +{ + unsigned int flags = WQ_UNBOUND | WQ_MEM_RECLAIM | WQ_HIGHPRI; + struct mmc_host *mmc = host->mmc; + int ret; + + if ((mmc->caps2 & MMC_CAP2_CQE) && + (host->quirks & SDHCI_QUIRK_BROKEN_CQE)) { + mmc->caps2 &= ~MMC_CAP2_CQE; + mmc->cqe_ops = NULL; + } + + host->complete_wq = alloc_workqueue("sdhci", flags, 0); + if (!host->complete_wq) + return -ENOMEM; + + INIT_WORK(&host->complete_work, host->complete_work_fn); + + timer_setup(&host->timer, sdhci_timeout_timer, 0); + timer_setup(&host->data_timer, sdhci_timeout_data_timer, 0); + + init_waitqueue_head(&host->buf_ready_int); + + sdhci_init(host, 0); + + ret = request_threaded_irq(host->irq, sdhci_irq, + host->thread_irq_fn, + IRQF_SHARED, mmc_hostname(mmc), host); + if (ret) { + pr_err("%s: Failed to request IRQ %d: %d\n", + mmc_hostname(mmc), host->irq, ret); + goto unwq; + } + + ret = mmc_add_host(mmc); + if (ret) + return 1; + + pr_info("%s: SDHCI controller on %s [%s] using %s\n", + mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)), + host->use_external_dma ? "External DMA" : + (host->flags & SDHCI_USE_ADMA) ? + (host->flags & SDHCI_USE_64_BIT_DMA) ? "ADMA 64-bit" : "ADMA" : + (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO"); + + sdhci_enable_card_detection(host); + + return 0; + +unwq: + destroy_workqueue(host->complete_wq); + + return ret; +} + +static void __sdhci_uhs2_remove_host(struct sdhci_host *host, int dead) +{ + if (!sdhci_uhs2_mode(host)) + return; + + if (!dead) + sdhci_uhs2_reset(host, SDHCI_UHS2_SW_RESET_FULL); +} + +int sdhci_uhs2_add_host(struct sdhci_host *host) +{ + struct mmc_host *mmc = host->mmc; + int ret; + + ret = sdhci_setup_host(host); + if (ret) + return ret; + + if (host->version >= SDHCI_SPEC_400) { + ret = __sdhci_uhs2_add_host_v4(host, host->caps1); + if (ret) + goto cleanup; + } + + if ((mmc->caps2 & MMC_CAP2_SD_UHS2) && !host->v4_mode) + /* host doesn't want to enable UHS2 support */ + /* FIXME: Do we have to do some cleanup here? */ + mmc->caps2 &= ~MMC_CAP2_SD_UHS2; + + /* overwrite ops */ + if (mmc->caps2 & MMC_CAP2_SD_UHS2) + sdhci_uhs2_host_ops_init(host); + + host->complete_work_fn = sdhci_uhs2_complete_work; + host->thread_irq_fn = sdhci_uhs2_thread_irq; + + ret = __sdhci_uhs2_add_host(host); + if (ret) + goto cleanup2; + + return 0; + +cleanup2: + if (host->version >= SDHCI_SPEC_400) + __sdhci_uhs2_remove_host(host, 0); +cleanup: + sdhci_cleanup_host(host); + + return ret; +} +EXPORT_SYMBOL_GPL(sdhci_uhs2_add_host); + +void sdhci_uhs2_remove_host(struct sdhci_host *host, int dead) +{ + __sdhci_uhs2_remove_host(host, dead); + + sdhci_remove_host(host, dead); +} +EXPORT_SYMBOL_GPL(sdhci_uhs2_remove_host); + void sdhci_uhs2_request(struct mmc_host *mmc, struct mmc_request *mrq) { struct sdhci_host *host = mmc_priv(mmc); diff --git a/drivers/mmc/host/sdhci-uhs2.h b/drivers/mmc/host/sdhci-uhs2.h index 64b7f356c9fc..b2048c48d056 100644 --- a/drivers/mmc/host/sdhci-uhs2.h +++ b/drivers/mmc/host/sdhci-uhs2.h @@ -182,5 +182,7 @@ void sdhci_uhs2_clear_set_irqs(struct sdhci_host *host, u32 clear, u32 set); void sdhci_uhs2_request(struct mmc_host *mmc, struct mmc_request *mrq); int sdhci_uhs2_request_atomic(struct mmc_host *mmc, struct mmc_request *mrq); u32 sdhci_uhs2_irq(struct sdhci_host *host, u32 intmask); +int sdhci_uhs2_add_host(struct sdhci_host *host); +void sdhci_uhs2_remove_host(struct sdhci_host *host, int dead); #endif /* __SDHCI_UHS2_H */ diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c index 6c67b79102eb..82ad35f4d1b4 100644 --- a/drivers/mmc/host/sdhci.c +++ b/drivers/mmc/host/sdhci.c @@ -175,10 +175,11 @@ static void sdhci_set_card_detection(struct sdhci_host *host, bool enable) sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); } -static void sdhci_enable_card_detection(struct sdhci_host *host) +void sdhci_enable_card_detection(struct sdhci_host *host) { sdhci_set_card_detection(host, true); } +EXPORT_SYMBOL_GPL(sdhci_enable_card_detection); static void sdhci_disable_card_detection(struct sdhci_host *host) { @@ -369,7 +370,7 @@ static void sdhci_config_dma(struct sdhci_host *host) sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); } -static void sdhci_init(struct sdhci_host *host, int soft) +void sdhci_init(struct sdhci_host *host, int soft) { struct mmc_host *mmc = host->mmc; unsigned long flags; @@ -395,6 +396,7 @@ static void sdhci_init(struct sdhci_host *host, int soft) mmc->ops->set_ios(mmc, &mmc->ios); } } +EXPORT_SYMBOL_GPL(sdhci_init); static void sdhci_reinit(struct sdhci_host *host) { @@ -458,7 +460,7 @@ static void sdhci_led_control(struct led_classdev *led, spin_unlock_irqrestore(&host->lock, flags); } -static int sdhci_led_register(struct sdhci_host *host) +int sdhci_led_register(struct sdhci_host *host) { struct mmc_host *mmc = host->mmc; @@ -475,14 +477,16 @@ static int sdhci_led_register(struct sdhci_host *host) return led_classdev_register(mmc_dev(mmc), &host->led); } +EXPORT_SYMBOL_GPL(sdhci_led_register); -static void sdhci_led_unregister(struct sdhci_host *host) +void sdhci_led_unregister(struct sdhci_host *host) { if (host->quirks & SDHCI_QUIRK_NO_LED) return; led_classdev_unregister(&host->led); } +EXPORT_SYMBOL_GPL(sdhci_led_unregister); static inline void sdhci_led_activate(struct sdhci_host *host) { @@ -3265,7 +3269,7 @@ void sdhci_complete_work(struct work_struct *work) } EXPORT_SYMBOL_GPL(sdhci_complete_work); -static void sdhci_timeout_timer(struct timer_list *t) +void sdhci_timeout_timer(struct timer_list *t) { struct sdhci_host *host; unsigned long flags; @@ -3286,8 +3290,9 @@ static void sdhci_timeout_timer(struct timer_list *t) spin_unlock_irqrestore(&host->lock, flags); } +EXPORT_SYMBOL_GPL(sdhci_timeout_timer); -static void sdhci_timeout_data_timer(struct timer_list *t) +void sdhci_timeout_data_timer(struct timer_list *t) { struct sdhci_host *host; unsigned long flags; @@ -3318,6 +3323,7 @@ static void sdhci_timeout_data_timer(struct timer_list *t) spin_unlock_irqrestore(&host->lock, flags); } +EXPORT_SYMBOL_GPL(sdhci_timeout_data_timer); /*****************************************************************************\ * * @@ -3577,7 +3583,7 @@ static inline bool sdhci_defer_done(struct sdhci_host *host, data->host_cookie == COOKIE_MAPPED); } -static irqreturn_t sdhci_irq(int irq, void *dev_id) +irqreturn_t sdhci_irq(int irq, void *dev_id) { struct mmc_request *mrqs_done[SDHCI_MAX_MRQS] = {0}; irqreturn_t result = IRQ_NONE; @@ -3718,6 +3724,7 @@ static irqreturn_t sdhci_irq(int irq, void *dev_id) return result; } +EXPORT_SYMBOL_GPL(sdhci_irq); irqreturn_t sdhci_thread_irq(int irq, void *dev_id) { @@ -4122,6 +4129,9 @@ struct sdhci_host *sdhci_alloc_host(struct device *dev, host->max_timeout_count = 0xE; + host->complete_work_fn = sdhci_complete_work; + host->thread_irq_fn = sdhci_thread_irq; + return host; } @@ -4874,7 +4884,7 @@ int __sdhci_add_host(struct sdhci_host *host) if (!host->complete_wq) return -ENOMEM; - INIT_WORK(&host->complete_work, sdhci_complete_work); + INIT_WORK(&host->complete_work, host->complete_work_fn); timer_setup(&host->timer, sdhci_timeout_timer, 0); timer_setup(&host->data_timer, sdhci_timeout_data_timer, 0); @@ -4883,7 +4893,7 @@ int __sdhci_add_host(struct sdhci_host *host) sdhci_init(host, 0); - ret = request_threaded_irq(host->irq, sdhci_irq, sdhci_thread_irq, + ret = request_threaded_irq(host->irq, sdhci_irq, host->thread_irq_fn, IRQF_SHARED, mmc_hostname(mmc), host); if (ret) { pr_err("%s: Failed to request IRQ %d: %d\n", diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h index 4979af7cabca..5f090b5ecc61 100644 --- a/drivers/mmc/host/sdhci.h +++ b/drivers/mmc/host/sdhci.h @@ -629,6 +629,9 @@ struct sdhci_host { struct timer_list timer; /* Timer for timeouts */ struct timer_list data_timer; /* Timer for data timeouts */ + void (*complete_work_fn)(struct work_struct *work); + irqreturn_t (*thread_irq_fn)(int irq, void *dev_id); + #if IS_ENABLED(CONFIG_MMC_SDHCI_EXTERNAL_DMA) struct dma_chan *rx_chan; struct dma_chan *tx_chan; @@ -832,6 +835,12 @@ static inline void sdhci_read_caps(struct sdhci_host *host) } bool sdhci_data_line_cmd(struct mmc_command *cmd); +void sdhci_enable_card_detection(struct sdhci_host *host); +void sdhci_init(struct sdhci_host *host, int soft); +#if IS_REACHABLE(CONFIG_LEDS_CLASS) +int sdhci_led_register(struct sdhci_host *host); +void sdhci_led_unregister(struct sdhci_host *host); +#endif void sdhci_mod_timer(struct sdhci_host *host, struct mmc_request *mrq, unsigned long timeout); void sdhci_initialize_data(struct sdhci_host *host, struct mmc_data *data); void sdhci_prepare_dma(struct sdhci_host *host, struct mmc_data *data); @@ -875,6 +884,9 @@ int sdhci_start_signal_voltage_switch(struct mmc_host *mmc, void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable); void sdhci_request_done_dma(struct sdhci_host *host, struct mmc_request *mrq); void sdhci_complete_work(struct work_struct *work); +void sdhci_timeout_timer(struct timer_list *t); +void sdhci_timeout_data_timer(struct timer_list *t); +irqreturn_t sdhci_irq(int irq, void *dev_id); irqreturn_t sdhci_thread_irq(int irq, void *dev_id); void sdhci_adma_write_desc(struct sdhci_host *host, void **desc, dma_addr_t addr, int len, unsigned int cmd); From patchwork Tue Dec 13 09:00:44 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Victor Shih X-Patchwork-Id: 32714 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:8188:b0:89:790f:f786 with SMTP id m8csp3858871dye; Tue, 13 Dec 2022 01:06:04 -0800 (PST) X-Google-Smtp-Source: AA0mqf4nTo4Z6Jw4uLiEtVlmadUutvkx+ORQIhp2z5IUMypCqmAzUFRJ/U74GPpcAVfr+SoDbsqb X-Received: by 2002:a05:6a21:3581:b0:ad:b459:2720 with SMTP id az1-20020a056a21358100b000adb4592720mr6130780pzc.20.1670922364023; Tue, 13 Dec 2022 01:06:04 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1670922364; cv=none; d=google.com; s=arc-20160816; b=nskLrYColluyXlEwFmmQ5r0KJ26tj2jnS0RV9+89AcBQwDbW5sGdWz2x8grfEckZxZ xUOXR95hSx/g7P8mqbEv30JlHXyeFOUitjeULsQqcHfFDb7pVWFczYNc47WpTTu4vEjH uYiaR/FNwEU/KY1HsqgzTcl2ZyOC/FyVoCd02gZ3jswuOZ9s+KAwWSkTn50/d9UPh+I5 nRdWZv/AqR3428pnKJVbhzEwsJ54ZILDeZGCBYcAnm7eBAqO0MSiDoIgVu1reUhv+J1i Eq9tuVaeid7cueYKRwHyMdr1Id8QxPp0W4DBrzakbAaXKrDfzlQ+RzM2CxE/oypkRn1F PvjA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=UqVdZlaw4OqprZkFV/DFABpNPHZPNiE0uwjLPDRS6Mo=; b=raI3DBWi2JQRtCmyzbagcG99O8GJx7rHq7DQhQ0r09eZUVFvVltDYvSwPLHr9cieZp o/XWmmRz3UYNNxnLgH0oPHDw48hu3QLNE2MtkXwxhh6T2/cNiRzmuicQDRwAyzZJ1xof Py8Qb76FhuBI7IS9dsoZj0bBxea7OJK7uwFRes2zKqdYxRzD2x3OHyfaW6dErm3VPT1A 7ZdJwA04umzYBG257NWK+s8epgS+xNyQurk3NI1J8zDPzH27xtH1jvmOxweI1otL7Pc2 YnjbBKm9qrE8OVdSIWijkK6FutfFG+vshUhBfR9vsRZXCJGMM4wwqbLvhHh96XJZZXsU DpsQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20210112 header.b=ppyZDN2d; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id o76-20020a62cd4f000000b0057621a4380fsi11845826pfg.64.2022.12.13.01.05.50; Tue, 13 Dec 2022 01:06:03 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@gmail.com header.s=20210112 header.b=ppyZDN2d; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235091AbiLMJES (ORCPT + 99 others); Tue, 13 Dec 2022 04:04:18 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36736 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234826AbiLMJCS (ORCPT ); Tue, 13 Dec 2022 04:02:18 -0500 Received: from mail-pg1-x531.google.com (mail-pg1-x531.google.com [IPv6:2607:f8b0:4864:20::531]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 15929101F9; Tue, 13 Dec 2022 01:02:18 -0800 (PST) Received: by mail-pg1-x531.google.com with SMTP id s196so9996552pgs.3; Tue, 13 Dec 2022 01:02:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=UqVdZlaw4OqprZkFV/DFABpNPHZPNiE0uwjLPDRS6Mo=; b=ppyZDN2dLPPCqAQgEKy5cK7IG3nBjLfoovEQkutRpbfJtJ3w7psQbnG7P4x8U7rvO/ eEe7ZvnnkCbY2o5MdDmNWyZSAyarB9Wy8EBVs8Z+uBsLlrjKZyEKiyTrajAvrXR1mJAA aGZHGFoj3H5MGhk2qCt+JGn6OosPcfIeSWRCzybF1Unuei5qqUK/RTIYXfgnrb7XZlCv +zwzNjUlbG58VnLnCLgI/Ki97UhtoEqL8UzNUEBly/7z/e2Fjcc0uyp4HStHpNbaF+QU 6dKpxkDZSXa9MehXWe5AyNEh5IoNGcxFM3tclXtBANLxC7OhYmUJOg3Vymu6YvhyS2OO ZntA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=UqVdZlaw4OqprZkFV/DFABpNPHZPNiE0uwjLPDRS6Mo=; b=DJ7TPJA4UkjELA0rXeBEkRauG71KO0LJgcVljH5Of9kE/2nplwpPfBQ6+Zzlpqclxo fY7rRn/TKrGkctB0LaTnuh6lKHzPJf8L/Q/VnIqI9fMBgUXnivIaxXyugBxFZ4c7afRO mVZ4xxhHYkfmlqL463MlrbBCwK400Gop79lbwyseR453uP/JTKfV2ScdY78ye/AoUIF6 rnJdvr/CercJOLWGRpV6W60cMytx4o6p21uNebvLEt0RopRH1qtlhL2NKAA/DRmQko7j qSRbha77THO73wMCr5Cm6a65fCyx1k+TmTjnNzzgdpcH/YGRCPdTVaihJ4BGW3npjO/H BwOA== X-Gm-Message-State: ANoB5pmhCermIh62sHqg3f1CMHkY2MyVv+mF6fNssPSKF7sRAnCE+s/N Rjz0yS9DMi25KS4DBHtwzFY= X-Received: by 2002:a62:3103:0:b0:576:14a4:b76a with SMTP id x3-20020a623103000000b0057614a4b76amr17377652pfx.34.1670922137587; Tue, 13 Dec 2022 01:02:17 -0800 (PST) Received: from localhost.localdomain (2001-b400-e2dc-5c03-264b-f684-a8c9-21ae.emome-ip6.hinet.net. [2001:b400:e2dc:5c03:264b:f684:a8c9:21ae]) by smtp.gmail.com with ESMTPSA id 81-20020a621954000000b0056b9ec7e2desm7141682pfz.125.2022.12.13.01.02.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 13 Dec 2022 01:02:17 -0800 (PST) From: Victor Shih X-Google-Original-From: Victor Shih To: ulf.hansson@linaro.org, adrian.hunter@intel.com Cc: linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, benchuanggli@gmail.com, HL.Liu@genesyslogic.com.tw, Greg.tu@genesyslogic.com.tw, takahiro.akashi@linaro.org, dlunev@chromium.org, Victor Shih , Ben Chuang Subject: [PATCH V6 21/24] mmc: sdhci-uhs2: add pre-detect_init hook Date: Tue, 13 Dec 2022 17:00:44 +0800 Message-Id: <20221213090047.3805-22-victor.shih@genesyslogic.com.tw> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221213090047.3805-1-victor.shih@genesyslogic.com.tw> References: <20221213090047.3805-1-victor.shih@genesyslogic.com.tw> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM, RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1752089089071029408?= X-GMAIL-MSGID: =?utf-8?q?1752089089071029408?= From: Victor Shih This "pre" hook for detect_init(), uhs2_pre_detect_init, will be required to enable UHS-II support, at least, on GL9755. Signed-off-by: Ben Chuang Signed-off-by: AKASHI Takahiro Signed-off-by: Victor Shih --- drivers/mmc/host/sdhci-uhs2.c | 3 +++ drivers/mmc/host/sdhci.h | 1 + 2 files changed, 4 insertions(+) diff --git a/drivers/mmc/host/sdhci-uhs2.c b/drivers/mmc/host/sdhci-uhs2.c index 5349173b4f90..1b481260885f 100644 --- a/drivers/mmc/host/sdhci-uhs2.c +++ b/drivers/mmc/host/sdhci-uhs2.c @@ -1358,6 +1358,9 @@ static int sdhci_uhs2_do_detect_init(struct mmc_host *mmc) DBG("Begin do uhs2 detect init.\n"); + if (host->ops && host->ops->uhs2_pre_detect_init) + host->ops->uhs2_pre_detect_init(host); + if (sdhci_uhs2_interface_detect(host)) { pr_warn("%s: cannot detect UHS2 interface.\n", mmc_hostname(host->mmc)); diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h index 5f090b5ecc61..e5f64b38e339 100644 --- a/drivers/mmc/host/sdhci.h +++ b/drivers/mmc/host/sdhci.h @@ -727,6 +727,7 @@ struct sdhci_ops { struct mmc_request *mrq); void (*dump_vendor_regs)(struct sdhci_host *host); void (*dump_uhs2_regs)(struct sdhci_host *host); + void (*uhs2_pre_detect_init)(struct sdhci_host *host); }; #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS From patchwork Tue Dec 13 09:00:45 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Victor Shih X-Patchwork-Id: 32715 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:8188:b0:89:790f:f786 with SMTP id m8csp3858880dye; Tue, 13 Dec 2022 01:06:04 -0800 (PST) X-Google-Smtp-Source: AA0mqf5HGP3pWkL2RQnki1bKRv3jqvi04YjMsLQnZBEbEfdyGArWbfRe+kEaJ0Nnz87C7AbYGSSX X-Received: by 2002:a05:6a20:3ca7:b0:a5:df86:eea0 with SMTP id b39-20020a056a203ca700b000a5df86eea0mr32330443pzj.34.1670922364648; Tue, 13 Dec 2022 01:06:04 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1670922364; cv=none; d=google.com; s=arc-20160816; b=VST/tLQWFik2++tFRNAAcxfwBhl3VmSkqnR/7UJtaY1lFwWqtBk+D96XeSg8+FJrJt 33kmS0A/m/gl18l6wEI8uZ/v9ls8DvJTcSkH4BUXSA6HGMwPw6QFdNl0BaFf2u8ISR45 +7ZEhZcp32Cv3JyzpMNg18Zx5Wh+hD8oOCd4pwfvG5qqOCNr5/3VuWejfAi0ehjJns5K sd34nYgw6vTUI1oS1+7stunWWkOfOuRj9H9wzaik5/USonkg91blBrzSd79ldkgF1Wfi BqylEr2rVYJZawwCmqVeYKdlQzNaF2WMrzGN9/+xv1h81qq1m60G9g1puGltTktnT5Q2 nigQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=2Kq/ZXg9ME6XTZIY0I3C/hVCMUMiXGyK0OXCfujvze4=; b=YQHX+w5Eb9ie55K6hoKua6G2tQzkYYb/0jW56SJFuiWyzM7mzWb1smXfKCdOXz1h75 kSi33yUdVMwqiyACKBGyO86om2WKEAtJaj18Z8ZRH8IipvK1nimgJAohKZaZTrOYAKwR TEcLlnFkd6SAQqD8/iUr12jUINAD5ashLgq/g86ccRkb/MKKQc7cwBbBnQDVBbhBrPWb TQYzVRuRFW5dldWR8eJ7zDch3i+XNvI631pdf+iKFht5RJac3Lu+L1GL25KTUeiONDSf r0xN/4nErYigwEMudrTq6DreaVcTWLaYoG1FtvgkO2D5GEVBJmMsKWfjhYpaFhh+Zt5W /r2g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20210112 header.b="PCZigT/k"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id f13-20020a056a0022cd00b0056e6d31b27asi12731857pfj.160.2022.12.13.01.05.52; Tue, 13 Dec 2022 01:06:04 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@gmail.com header.s=20210112 header.b="PCZigT/k"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235095AbiLMJE0 (ORCPT + 99 others); Tue, 13 Dec 2022 04:04:26 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36784 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234901AbiLMJCX (ORCPT ); Tue, 13 Dec 2022 04:02:23 -0500 Received: from mail-pf1-x42d.google.com (mail-pf1-x42d.google.com [IPv6:2607:f8b0:4864:20::42d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 96F541057D; Tue, 13 Dec 2022 01:02:21 -0800 (PST) Received: by mail-pf1-x42d.google.com with SMTP id 130so1727916pfu.8; Tue, 13 Dec 2022 01:02:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=2Kq/ZXg9ME6XTZIY0I3C/hVCMUMiXGyK0OXCfujvze4=; b=PCZigT/krisCTR5uD3N9K8HerxEPS2PQ0keSaKkk92eH+il+pE9hWS1lZAH4Rr6E08 tV55ylKX8z/8bh43cmHVZyXNV6N9pEbteplRpCoMmhkBX9zd73FJjn7leu6kLHC2J/uq nExiU9+v2tkwNuzxZaIAXxfKBa2wR8LYYgxz5BBjKp448/LmdzvtD3mxAW44mHl0Fhy5 T1XoInGXH1vVQnUs/pQ/tD0FjBPkaPBtV3txQvv1JAkphFaRZvqXx3JlmuHw/mSGoE5L FukBcZ45c8EKEqWUcobTqtA91h8OB4jhKkku4xk3or8WAGmvsJ9vWbpPjEFgK6EqXdq9 lxww== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=2Kq/ZXg9ME6XTZIY0I3C/hVCMUMiXGyK0OXCfujvze4=; b=IwQyxJ81dMpAJTFsyce4d6eLB4gYTymKewM/ffbZ5b+TNVgGSTkJKvEWm3gf/JUAKI uNRpCz5xHx6bJeHIO5Ou6huDe+PPBIFkj8w4/C8oE9B3CmSGOGIDQMtx+JwwR5edTXeO OY/bdh6wZSc1kKx05VmHDzSWY2o13MrocyJhF8/l93d6ajEVv1OvFORv+BRrkCbF6DGA ZTfUvG5rk9pwgBu+blc3lN31fUdp/5KCFASdxGRR1fK3nhNgq3NjXmhgTMdPpZ5X0s2P Xmb9R5ewEtDTt7Q663UH71AzpVwwQtBQk3oJqISz2IVW2kgpl8C9eXbqwFREPgoPNXhY kFMQ== X-Gm-Message-State: ANoB5pklafeymbFA7nkJtJTnsWDpim2geKDZ1EMfPT/0uRr04u0dt46S m3r5SxOKd9FD/ThMaFWLqUI= X-Received: by 2002:aa7:93da:0:b0:576:de1:cd32 with SMTP id y26-20020aa793da000000b005760de1cd32mr20411121pff.0.1670922140695; Tue, 13 Dec 2022 01:02:20 -0800 (PST) Received: from localhost.localdomain (2001-b400-e2dc-5c03-264b-f684-a8c9-21ae.emome-ip6.hinet.net. [2001:b400:e2dc:5c03:264b:f684:a8c9:21ae]) by smtp.gmail.com with ESMTPSA id 81-20020a621954000000b0056b9ec7e2desm7141682pfz.125.2022.12.13.01.02.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 13 Dec 2022 01:02:20 -0800 (PST) From: Victor Shih X-Google-Original-From: Victor Shih To: ulf.hansson@linaro.org, adrian.hunter@intel.com Cc: linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, benchuanggli@gmail.com, HL.Liu@genesyslogic.com.tw, Greg.tu@genesyslogic.com.tw, takahiro.akashi@linaro.org, dlunev@chromium.org, Victor Shih , Ben Chuang Subject: [PATCH V6 22/24] mmc: sdhci-uhs2: add post-mmc_attach_sd hook Date: Tue, 13 Dec 2022 17:00:45 +0800 Message-Id: <20221213090047.3805-23-victor.shih@genesyslogic.com.tw> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221213090047.3805-1-victor.shih@genesyslogic.com.tw> References: <20221213090047.3805-1-victor.shih@genesyslogic.com.tw> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM, RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1752089089418857852?= X-GMAIL-MSGID: =?utf-8?q?1752089089418857852?= From: Ben Chuang This "post" hook for mmc_attach_sd(), uhs2_post_attach_sd, will be required to enable UHS-II support, at least, on GL9755. Signed-off-by: Ben Chuang Signed-off-by: AKASHI Takahiro --- drivers/mmc/host/sdhci.h | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h index e5f64b38e339..4aac22b58d79 100644 --- a/drivers/mmc/host/sdhci.h +++ b/drivers/mmc/host/sdhci.h @@ -728,6 +728,7 @@ struct sdhci_ops { void (*dump_vendor_regs)(struct sdhci_host *host); void (*dump_uhs2_regs)(struct sdhci_host *host); void (*uhs2_pre_detect_init)(struct sdhci_host *host); + void (*uhs2_post_attach_sd)(struct sdhci_host *host); }; #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS From patchwork Tue Dec 13 09:00:46 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Victor Shih X-Patchwork-Id: 32717 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:8188:b0:89:790f:f786 with SMTP id m8csp3859571dye; Tue, 13 Dec 2022 01:07:14 -0800 (PST) X-Google-Smtp-Source: AA0mqf7Ubgd1DUZwirnlob8xP5OLfy0LWQbgh9QTRdZgJ/Mu8ZXZTRXBn1HKZlCgXIvyRCEv5iul X-Received: by 2002:a17:907:770e:b0:7bf:3627:df32 with SMTP id kw14-20020a170907770e00b007bf3627df32mr17768435ejc.75.1670922434519; Tue, 13 Dec 2022 01:07:14 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1670922434; cv=none; d=google.com; s=arc-20160816; b=RUiKfqvnbI0zspV7dT4uEGCdPhcK57r6kXhCPA38r98Y1Lq7VvnILZvM+MYJp/KNOh KuFhj0K0oIwm748Oy/XHuaJgir2Kr6KqtuAOL7yQjlWOG4aeCwsIAwW4etIFbOvpmM6Y nMM1xalt7vnpCGlA4yf/GTvqG12DPgodBzlqhlav24T7DQ4R4X7VVMPJ5wBEwH6kcLVg Pwnz1PT2UVKUmEh6P+i6dekI33izr7EcvbwA8xyjY6heyCDe16LEPdDURYsLNgo3CXSh XutzKIYyeAqrvvE8raRJXZVaJQjyM5f+IN5sp7vgT7oLou4WdreAzqkAgxZ/L6IEyi0x C5qw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=7PSAbNdm4Wrohy+JHyHxEY4NshP0fU0POYqHyU8D18A=; b=1K0WlP61kEH8Fsl7l2VqVc/TDxHcl30qWM8SEawdFvDptAB+4/XAe6G+p3r9O6gaXY pogSw36Vqx6L4mR+ukp72bN0+m+5Y2L1TjQLt8aHegSkD9WhDyDzMAolwx0emnjwcjGX flYp3SMkWdWsWLWByX30IiyCdV4KRcen3KOQ6rDMoesA/hShqsZFn1WrV0SaysbmtSYx 03lOYjzc6VUJHyFchuULiBsEpzGwL0Vdlk81OYd0OxoHYeThNoWq2wPsiRDiBkKkrP9m dsUYjHasCDxNxw/feMThqfdMa//oQQvRcukZKRWQu/V5LpdBdLCJR4PkjBky7KQohl52 EzRA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20210112 header.b=krFazrf7; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id dr14-20020a170907720e00b00791910ecd0fsi7908480ejc.540.2022.12.13.01.06.50; Tue, 13 Dec 2022 01:07:14 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@gmail.com header.s=20210112 header.b=krFazrf7; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235103AbiLMJEb (ORCPT + 99 others); Tue, 13 Dec 2022 04:04:31 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36802 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234847AbiLMJC1 (ORCPT ); Tue, 13 Dec 2022 04:02:27 -0500 Received: from mail-pg1-x529.google.com (mail-pg1-x529.google.com [IPv6:2607:f8b0:4864:20::529]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 58D4910FD4; Tue, 13 Dec 2022 01:02:24 -0800 (PST) Received: by mail-pg1-x529.google.com with SMTP id 79so969854pgf.11; Tue, 13 Dec 2022 01:02:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=7PSAbNdm4Wrohy+JHyHxEY4NshP0fU0POYqHyU8D18A=; b=krFazrf7dGtFk+7vHofXgXt2Z/htty3CQxH7IBofnscwhO3J9a0CDEedllYhdeq8WA zbnZxsFpF2fZA51uBmocp3g+oKn3WWnUNd1xk0ffuN4pcL6I9JBwNi3pUdMpzAraCRRH 61P+RHPhIcK+JVTG4ZYTr9d1eNEWaVPM7OxKt/UKcZFWrRj3JUhtAuhz35FoA5Ua8Od8 0gCqsEbsoLJGx3ktVqFJHkDsEaTQ80oXkF4RZ54R07K82rkh7eu8kf0P0DoVtS8lEQBM eGuvx79U0IFm5F1w/oes3TlRnQH1dy458dT0vh7m5sE+yz9qnBgw3gLCxyjh0MUSPiXy l/jw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=7PSAbNdm4Wrohy+JHyHxEY4NshP0fU0POYqHyU8D18A=; b=3x4Fgk5B3/EwArT8N7ce/49tLlobmMLgDaw9z/4xL2kJctS2391Vwe/JeAQ36yI/5/ 9hmNsJIrKtIzofl9VmrUWzWKnw4qBMeEfFNYAm7FFeWWREN0XRezg67Uve9/Ll1GjnHv rAo3IE8iRan/OqUEIzIt6gXEy5gQ08obuMezc7wwCxG0k35tkQeIbjaxnUV1y9lqmafu YCwdQeqU1jmrkYY60lpvH4MZJtdXJk4iiGEREA0GbsAtDAhuNIfOQ9EIivHN6znV6uKu McKASmXZd8/KqEIdpUpEVisyDj72j2Bi8NjPgd6HBmN97TbFos9uN2viW73TsVw3UOrx c8iA== X-Gm-Message-State: ANoB5pnt2QnilWRavO4tzmWbG12LhHJRBbEbLOEjGRa7Y/e8OlJOSTPs tk8kn/UymMbyL7jhEqZE1os= X-Received: by 2002:a05:6a00:26f7:b0:577:5913:5b25 with SMTP id p55-20020a056a0026f700b0057759135b25mr20871182pfw.22.1670922144172; Tue, 13 Dec 2022 01:02:24 -0800 (PST) Received: from localhost.localdomain (2001-b400-e2dc-5c03-264b-f684-a8c9-21ae.emome-ip6.hinet.net. [2001:b400:e2dc:5c03:264b:f684:a8c9:21ae]) by smtp.gmail.com with ESMTPSA id 81-20020a621954000000b0056b9ec7e2desm7141682pfz.125.2022.12.13.01.02.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 13 Dec 2022 01:02:23 -0800 (PST) From: Victor Shih X-Google-Original-From: Victor Shih To: ulf.hansson@linaro.org, adrian.hunter@intel.com Cc: linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, benchuanggli@gmail.com, HL.Liu@genesyslogic.com.tw, Greg.tu@genesyslogic.com.tw, takahiro.akashi@linaro.org, dlunev@chromium.org, Victor Shih , Ben Chuang Subject: [PATCH V6 23/24] mmc: sdhci-pci: add UHS-II support framework Date: Tue, 13 Dec 2022 17:00:46 +0800 Message-Id: <20221213090047.3805-24-victor.shih@genesyslogic.com.tw> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221213090047.3805-1-victor.shih@genesyslogic.com.tw> References: <20221213090047.3805-1-victor.shih@genesyslogic.com.tw> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM, RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1752089162308276441?= X-GMAIL-MSGID: =?utf-8?q?1752089162308276441?= From: AKASHI Takahiro This patch prepares for adding UHS-II support at a specific UHS-II capable sdhci-pci controller, GL9755 for now. Signed-off-by: Ben Chuang Signed-off-by: AKASHI Takahiro --- drivers/mmc/host/sdhci-pci-core.c | 16 +++++++++++++++- drivers/mmc/host/sdhci-pci.h | 3 +++ 2 files changed, 18 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/host/sdhci-pci-core.c b/drivers/mmc/host/sdhci-pci-core.c index c359f867df0a..248f13b163b0 100644 --- a/drivers/mmc/host/sdhci-pci-core.c +++ b/drivers/mmc/host/sdhci-pci-core.c @@ -40,6 +40,7 @@ #include "sdhci.h" #include "sdhci-cqhci.h" #include "sdhci-pci.h" +#include "sdhci-uhs2.h" static void sdhci_pci_hw_reset(struct sdhci_host *host); @@ -2153,7 +2154,10 @@ static void sdhci_pci_remove_slot(struct sdhci_pci_slot *slot) if (scratch == (u32)-1) dead = 1; - sdhci_remove_host(slot->host, dead); + if (slot->chip->fixes && slot->chip->fixes->remove_host) + slot->chip->fixes->remove_host(slot, dead); + else + sdhci_remove_host(slot->host, dead); if (slot->chip->fixes && slot->chip->fixes->remove_slot) slot->chip->fixes->remove_slot(slot, dead); @@ -2161,6 +2165,16 @@ static void sdhci_pci_remove_slot(struct sdhci_pci_slot *slot) sdhci_free_host(slot->host); } +int sdhci_pci_uhs2_add_host(struct sdhci_pci_slot *slot) +{ + return sdhci_uhs2_add_host(slot->host); +} + +void sdhci_pci_uhs2_remove_host(struct sdhci_pci_slot *slot, int dead) +{ + sdhci_uhs2_remove_host(slot->host, dead); +} + static void sdhci_pci_runtime_pm_allow(struct device *dev) { pm_suspend_ignore_children(dev, 1); diff --git a/drivers/mmc/host/sdhci-pci.h b/drivers/mmc/host/sdhci-pci.h index 3661a224fb04..7f4a981c0e63 100644 --- a/drivers/mmc/host/sdhci-pci.h +++ b/drivers/mmc/host/sdhci-pci.h @@ -140,6 +140,7 @@ struct sdhci_pci_fixes { int (*probe_slot) (struct sdhci_pci_slot *); int (*add_host) (struct sdhci_pci_slot *); void (*remove_slot) (struct sdhci_pci_slot *, int); + void (*remove_host) (struct sdhci_pci_slot *, int); #ifdef CONFIG_PM_SLEEP int (*suspend) (struct sdhci_pci_chip *); @@ -184,6 +185,8 @@ static inline void *sdhci_pci_priv(struct sdhci_pci_slot *slot) return (void *)slot->private; } +int sdhci_pci_uhs2_add_host(struct sdhci_pci_slot *slot); +void sdhci_pci_uhs2_remove_host(struct sdhci_pci_slot *slot, int dead); #ifdef CONFIG_PM_SLEEP int sdhci_pci_resume_host(struct sdhci_pci_chip *chip); #endif From patchwork Tue Dec 13 09:00:47 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Victor Shih X-Patchwork-Id: 32718 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:8188:b0:89:790f:f786 with SMTP id m8csp3859743dye; Tue, 13 Dec 2022 01:07:33 -0800 (PST) X-Google-Smtp-Source: AA0mqf5WGTkqEzDgQpyt+F19bdAa3ia56RAx8XxmjhquKFGP05CEPBTz+QzDm1KxdgFBqi4pfSAm X-Received: by 2002:a17:90a:de82:b0:219:d1eb:b895 with SMTP id n2-20020a17090ade8200b00219d1ebb895mr19716978pjv.12.1670922453686; Tue, 13 Dec 2022 01:07:33 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1670922453; cv=none; d=google.com; s=arc-20160816; b=o/xA1xR6ix/3X/4tR4dGJMq7JrOfTbvMEUpPJUkLT2xJQQIPIKQXgzemTxyU5pyu6I qXtWJ2qZMcVQIZnJUEfUdzlNGYmQsEQnBcww3Jbd5c4T0e8NpewEXTD8nQMmKw+/YMHY o0IiR20Whh1i1LVH7A30S1sLMfM5Fu245+LtWmy2ncPx9ZjbyR2zz9d+T/LcZn/Qtd0t ODgjwIIEvMcMeCct7qVXOerRMD2N8hqPaGazvnintRLk35EofHvXWjkGraQRquBRQUYW xwgdGw3lvrssurxhR5HqOWO45AqkiemEyvbxJgUfjrSfl3U+S9ppSnc6pl4uZstM04NV kStw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=0vUiCKrnfqeQs9gnEJdyYPTIDeFBBzCx55obNP/Mlto=; b=eWvVoU3p9Nvz613gA8tGUupaApLkEtnthHXnZI38yUFh6/eZkUDmH1YAZaBNrRaVXF tV5Av9oVF2t6W70TMHjv6L6gsNmiUOGLKKykUGqMTFoLnjPWvQ4nfZ9KGnwoP3W6bSAN xSBQ/98ptHbbp3IBDZHH1hpeM2eKhnW9/4Amh5/se3Dq0l/V/O3edmEMqdUOgAn406wC VHGDwpsgL/lt5fDZPrIczZJLbmXMSAbbmtNxmdKR1Kka+ZhZtlKKWhcPPtOBLgA4oSC5 pLjv5J92EapnpnA2lqP6IIt4rjmbzYUyaBcHeGj7IpJHefRwrKe+6Rh5FThUpR93/kP9 y20w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20210112 header.b=kl4H6BsC; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id d7-20020a63d707000000b004541962a9basi12051183pgg.701.2022.12.13.01.07.19; Tue, 13 Dec 2022 01:07:33 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@gmail.com header.s=20210112 header.b=kl4H6BsC; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234940AbiLMJEh (ORCPT + 99 others); Tue, 13 Dec 2022 04:04:37 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36814 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234913AbiLMJCa (ORCPT ); Tue, 13 Dec 2022 04:02:30 -0500 Received: from mail-pg1-x529.google.com (mail-pg1-x529.google.com [IPv6:2607:f8b0:4864:20::529]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9D5AF101DD; Tue, 13 Dec 2022 01:02:27 -0800 (PST) Received: by mail-pg1-x529.google.com with SMTP id 79so969925pgf.11; Tue, 13 Dec 2022 01:02:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=0vUiCKrnfqeQs9gnEJdyYPTIDeFBBzCx55obNP/Mlto=; b=kl4H6BsCs5jps4AeupoC/jrTVkxVy0DmlolAps0qwJoQXyjelOoR6GZTw5PUbGtpdG 6IDffelR6IHL1oBhdKMvHJd0VoEdiIQcYu8WmkDalYy6jPuO5UqHfj1kHOwArGkp12m2 INJ3rxkfofBhiyM7NFEu+QdG4quqD8sugeeBh33vdkJtdMakm55R9MDEKgVcs7fFYsEW uYFeaGl4KH8NMQNNigh/QNWN45+TBFy+qz6U/zyhDHspkuwTs9krMv9PPxPGWSOpLLSy IlLomKnv82sunoKW1bfEyG5YOJwf9lQOnMJl5/EKSc+ifPotGuWkwstmRCIJXDVj/KbC BViw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=0vUiCKrnfqeQs9gnEJdyYPTIDeFBBzCx55obNP/Mlto=; b=zptwbX3CHHTrSzmphp19qmq28SaVvDXF3YHTBVTrcNedcF9xyOF/9v/1plIUKxzCWP j1vr6Ab28AYRcoduqAO32gTLR4wCKvkER7E77NZO6HnKkOCg9sYrxYvUblBMbeBq+x9F uDDLPK+ZwKbQTLy5zEgFrfgd8V34OMPrWLrZhSAUhesIlU00MW6k+u89enRirOpL2p8d X86GUe2boJg3m6Q/SnV6kmOZXqPo55miyrFR2fgkr8vpbsgrvDGanM3dmzu7EFHV8/4t SWoRLiWCKXkFFMYH9FiMw+TGP1v6SqHejnFIaDEsuKzqJE6nLBt9kVfel/190cdduUo5 4JtA== X-Gm-Message-State: ANoB5pmlrDHJnduuJyL7Ahc4aXYDJsYCbhbnQT0KP9jg1Y7g+a3/eh9v OWfjZI6fzsICr0Wr+MUIf0Y= X-Received: by 2002:a62:6495:0:b0:56e:d365:f96d with SMTP id y143-20020a626495000000b0056ed365f96dmr17553024pfb.5.1670922147287; Tue, 13 Dec 2022 01:02:27 -0800 (PST) Received: from localhost.localdomain (2001-b400-e2dc-5c03-264b-f684-a8c9-21ae.emome-ip6.hinet.net. [2001:b400:e2dc:5c03:264b:f684:a8c9:21ae]) by smtp.gmail.com with ESMTPSA id 81-20020a621954000000b0056b9ec7e2desm7141682pfz.125.2022.12.13.01.02.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 13 Dec 2022 01:02:26 -0800 (PST) From: Victor Shih X-Google-Original-From: Victor Shih To: ulf.hansson@linaro.org, adrian.hunter@intel.com Cc: linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, benchuanggli@gmail.com, HL.Liu@genesyslogic.com.tw, Greg.tu@genesyslogic.com.tw, takahiro.akashi@linaro.org, dlunev@chromium.org, Victor Shih , Ben Chuang Subject: [PATCH V6 24/24] mmc: sdhci-pci-gli: enable UHS-II mode for GL9755 Date: Tue, 13 Dec 2022 17:00:47 +0800 Message-Id: <20221213090047.3805-25-victor.shih@genesyslogic.com.tw> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221213090047.3805-1-victor.shih@genesyslogic.com.tw> References: <20221213090047.3805-1-victor.shih@genesyslogic.com.tw> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM, RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1752089182752418939?= X-GMAIL-MSGID: =?utf-8?q?1752089182752418939?= Changes are: * Disable GL9755 overcurrent interrupt when power on/off on UHS-II. * Enable the internal clock when do reset on UHS-II mode. * Set ZC to 0x0 for Sandisk cards and set ZC to 0xB for others. * Increase timeout value before detecting UHS-II interface. * Add vendor settings fro UHS-II mode. Signed-off-by: Ben Chuang Signed-off-by: AKASHI Takahiro Signed-off-by: Victor Shih --- drivers/mmc/host/Kconfig | 1 + drivers/mmc/host/sdhci-pci-gli.c | 309 ++++++++++++++++++++++++++++++- 2 files changed, 309 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig index 9c22370fb778..e68cdcb72cba 100644 --- a/drivers/mmc/host/Kconfig +++ b/drivers/mmc/host/Kconfig @@ -111,6 +111,7 @@ config MMC_SDHCI_PCI tristate "SDHCI support on PCI bus" depends on MMC_SDHCI && PCI select MMC_CQHCI + select MMC_SDHCI_UHS2 select IOSF_MBI if X86 select MMC_SDHCI_IO_ACCESSORS help diff --git a/drivers/mmc/host/sdhci-pci-gli.c b/drivers/mmc/host/sdhci-pci-gli.c index 633a8ee8f8c5..384f47ed15d9 100644 --- a/drivers/mmc/host/sdhci-pci-gli.c +++ b/drivers/mmc/host/sdhci-pci-gli.c @@ -18,6 +18,7 @@ #include "sdhci-cqhci.h" #include "sdhci-pci.h" #include "cqhci.h" +#include "sdhci-uhs2.h" /* Genesys Logic extra registers */ #define SDHCI_GLI_9750_WT 0x800 @@ -139,9 +140,36 @@ #define PCI_GLI_9755_PLLSSC 0x68 #define PCI_GLI_9755_PLLSSC_PPM GENMASK(15, 0) +#define PCI_GLI_9755_PLLSSC_RTL BIT(24) +#define GLI_9755_PLLSSC_RTL_VALUE 0x1 +#define PCI_GLI_9755_PLLSSC_TRANS_PASS BIT(27) +#define GLI_9755_PLLSSC_TRANS_PASS_VALUE 0x1 +#define PCI_GLI_9755_PLLSSC_RECV GENMASK(29, 28) +#define GLI_9755_PLLSSC_RECV_VALUE 0x3 +#define PCI_GLI_9755_PLLSSC_TRAN GENMASK(31, 30) +#define GLI_9755_PLLSSC_TRAN_VALUE 0x3 + +#define PCI_GLI_9755_UHS2_PLL 0x6C +#define PCI_GLI_9755_UHS2_PLL_SSC GENMASK(9, 8) +#define GLI_9755_UHS2_PLL_SSC_VALUE 0x0 +#define PCI_GLI_9755_UHS2_PLL_DELAY BIT(18) +#define GLI_9755_UHS2_PLL_DELAY_VALUE 0x1 +#define PCI_GLI_9755_UHS2_PLL_PDRST BIT(27) +#define GLI_9755_UHS2_PLL_PDRST_VALUE 0x1 #define PCI_GLI_9755_SerDes 0x70 +#define PCI_GLI_9755_UHS2_SERDES_INTR GENMASK(2, 0) +#define GLI_9755_UHS2_SERDES_INTR_VALUE 0x3 +#define PCI_GLI_9755_UHS2_SERDES_ZC1 BIT(3) +#define GLI_9755_UHS2_SERDES_ZC1_VALUE 0x0 +#define PCI_GLI_9755_UHS2_SERDES_ZC2 GENMASK(7, 4) +#define GLI_9755_UHS2_SERDES_ZC2_DEFAULT 0xB +#define GLI_9755_UHS2_SERDES_ZC2_SANDISK 0x0 #define PCI_GLI_9755_SCP_DIS BIT(19) +#define PCI_GLI_9755_UHS2_SERDES_TRAN GENMASK(27, 24) +#define GLI_9755_UHS2_SERDES_TRAN_VALUE 0xC +#define PCI_GLI_9755_UHS2_SERDES_RECV GENMASK(31, 28) +#define GLI_9755_UHS2_SERDES_RECV_VALUE 0xF #define PCI_GLI_9755_MISC 0x78 #define PCI_GLI_9755_MISC_SSC_OFF BIT(26) @@ -693,6 +721,276 @@ static void gl9755_hw_setting(struct sdhci_pci_slot *slot) gl9755_wt_off(pdev); } +static void gl9755_vendor_init(struct sdhci_host *host) +{ + struct sdhci_pci_slot *slot = sdhci_priv(host); + struct pci_dev *pdev = slot->chip->pdev; + u32 serdes; + u32 pllssc; + u32 uhs2_pll; + + gl9755_wt_on(pdev); + + pci_read_config_dword(pdev, PCI_GLI_9755_SerDes, &serdes); + serdes &= ~PCI_GLI_9755_UHS2_SERDES_TRAN; + serdes |= FIELD_PREP(PCI_GLI_9755_UHS2_SERDES_TRAN, + GLI_9755_UHS2_SERDES_TRAN_VALUE); + serdes &= ~PCI_GLI_9755_UHS2_SERDES_RECV; + serdes |= FIELD_PREP(PCI_GLI_9755_UHS2_SERDES_RECV, + GLI_9755_UHS2_SERDES_RECV_VALUE); + serdes &= ~PCI_GLI_9755_UHS2_SERDES_INTR; + serdes |= FIELD_PREP(PCI_GLI_9755_UHS2_SERDES_INTR, + GLI_9755_UHS2_SERDES_INTR_VALUE); + serdes &= ~PCI_GLI_9755_UHS2_SERDES_ZC1; + serdes |= FIELD_PREP(PCI_GLI_9755_UHS2_SERDES_ZC1, + GLI_9755_UHS2_SERDES_ZC1_VALUE); + serdes &= ~PCI_GLI_9755_UHS2_SERDES_ZC2; + serdes |= FIELD_PREP(PCI_GLI_9755_UHS2_SERDES_ZC2, + GLI_9755_UHS2_SERDES_ZC2_DEFAULT); + pci_write_config_dword(pdev, PCI_GLI_9755_SerDes, serdes); + + pci_read_config_dword(pdev, PCI_GLI_9755_UHS2_PLL, &uhs2_pll); + uhs2_pll &= ~PCI_GLI_9755_UHS2_PLL_SSC; + uhs2_pll |= FIELD_PREP(PCI_GLI_9755_UHS2_PLL_SSC, + GLI_9755_UHS2_PLL_SSC_VALUE); + uhs2_pll &= ~PCI_GLI_9755_UHS2_PLL_DELAY; + uhs2_pll |= FIELD_PREP(PCI_GLI_9755_UHS2_PLL_DELAY, + GLI_9755_UHS2_PLL_DELAY_VALUE); + uhs2_pll &= ~PCI_GLI_9755_UHS2_PLL_PDRST; + uhs2_pll |= FIELD_PREP(PCI_GLI_9755_UHS2_PLL_PDRST, + GLI_9755_UHS2_PLL_PDRST_VALUE); + pci_write_config_dword(pdev, PCI_GLI_9755_UHS2_PLL, uhs2_pll); + + pci_read_config_dword(pdev, PCI_GLI_9755_PLLSSC, &pllssc); + pllssc &= ~PCI_GLI_9755_PLLSSC_RTL; + pllssc |= FIELD_PREP(PCI_GLI_9755_PLLSSC_RTL, + GLI_9755_PLLSSC_RTL_VALUE); + pllssc &= ~PCI_GLI_9755_PLLSSC_TRANS_PASS; + pllssc |= FIELD_PREP(PCI_GLI_9755_PLLSSC_TRANS_PASS, + GLI_9755_PLLSSC_TRANS_PASS_VALUE); + pllssc &= ~PCI_GLI_9755_PLLSSC_RECV; + pllssc |= FIELD_PREP(PCI_GLI_9755_PLLSSC_RECV, + GLI_9755_PLLSSC_RECV_VALUE); + pllssc &= ~PCI_GLI_9755_PLLSSC_TRAN; + pllssc |= FIELD_PREP(PCI_GLI_9755_PLLSSC_TRAN, + GLI_9755_PLLSSC_TRAN_VALUE); + pci_write_config_dword(pdev, PCI_GLI_9755_PLLSSC, pllssc); + + gl9755_wt_off(pdev); +} + +static void gl9755_pre_detect_init(struct sdhci_host *host) +{ + /* GL9755 need more time on UHS2 detect flow */ + sdhci_writeb(host, 0xA7, SDHCI_UHS2_TIMER_CTRL); +} + +static void gl9755_post_attach_sd(struct sdhci_host *host) +{ + struct pci_dev *pdev; + struct sdhci_pci_chip *chip; + struct sdhci_pci_slot *slot; + u32 serdes; + + slot = sdhci_priv(host); + chip = slot->chip; + pdev = chip->pdev; + + gl9755_wt_on(pdev); + + pci_read_config_dword(pdev, PCI_GLI_9755_SerDes, &serdes); + serdes &= ~PCI_GLI_9755_UHS2_SERDES_ZC1; + serdes &= ~PCI_GLI_9755_UHS2_SERDES_ZC2; + serdes |= FIELD_PREP(PCI_GLI_9755_UHS2_SERDES_ZC1, + GLI_9755_UHS2_SERDES_ZC1_VALUE); + + /* the manfid of sandisk card is 0x3 */ + if (host->mmc->card->cid.manfid == 0x3) + serdes |= FIELD_PREP(PCI_GLI_9755_UHS2_SERDES_ZC2, + GLI_9755_UHS2_SERDES_ZC2_SANDISK); + else + serdes |= FIELD_PREP(PCI_GLI_9755_UHS2_SERDES_ZC2, + GLI_9755_UHS2_SERDES_ZC2_DEFAULT); + + pci_write_config_dword(pdev, PCI_GLI_9755_SerDes, serdes); + + gl9755_wt_off(pdev); +} + +static void gl9755_overcurrent_event_enable(struct sdhci_host *host, + bool enable) +{ + u32 mask; + + mask = sdhci_readl(host, SDHCI_SIGNAL_ENABLE); + if (enable) + mask |= SDHCI_INT_BUS_POWER; + else + mask &= ~SDHCI_INT_BUS_POWER; + + sdhci_writel(host, mask, SDHCI_SIGNAL_ENABLE); + + mask = sdhci_readl(host, SDHCI_INT_ENABLE); + if (enable) + mask |= SDHCI_INT_BUS_POWER; + else + mask &= ~SDHCI_INT_BUS_POWER; + + sdhci_writel(host, mask, SDHCI_INT_ENABLE); +} + +static void gl9755_set_power(struct sdhci_host *host, unsigned char mode, + unsigned short vdd) +{ + u8 pwr = 0; + + if (mode != MMC_POWER_OFF) { + switch (1 << vdd) { + case MMC_VDD_165_195: + /* + * Without a regulator, SDHCI does not support 2.0v + * so we only get here if the driver deliberately + * added the 2.0v range to ocr_avail. Map it to 1.8v + * for the purpose of turning on the power. + */ + case MMC_VDD_20_21: + pwr = SDHCI_POWER_180; + break; + case MMC_VDD_29_30: + case MMC_VDD_30_31: + pwr = SDHCI_POWER_300; + break; + case MMC_VDD_32_33: + case MMC_VDD_33_34: + pwr = SDHCI_POWER_330; + break; + default: + WARN(1, "%s: Invalid vdd %#x\n", + mmc_hostname(host->mmc), vdd); + break; + } + + pwr |= SDHCI_VDD2_POWER_180; + } + + if (host->pwr == pwr) + return; + + host->pwr = pwr; + + if (pwr == 0) { + gl9755_overcurrent_event_enable(host, false); + sdhci_writeb(host, 0, SDHCI_POWER_CONTROL); + } else { + gl9755_overcurrent_event_enable(host, false); + sdhci_writeb(host, 0, SDHCI_POWER_CONTROL); + + pwr |= (SDHCI_POWER_ON | SDHCI_VDD2_POWER_ON); + + sdhci_writeb(host, pwr & 0xf, SDHCI_POWER_CONTROL); + /* wait stable */ + mdelay(5); + sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL); + /* wait stable */ + mdelay(5); + gl9755_overcurrent_event_enable(host, true); + } +} + +static bool sdhci_wait_clock_stable(struct sdhci_host *host) +{ + u16 clk = 0; + ktime_t timeout; + + /* Wait max 20 ms */ + timeout = ktime_add_ms(ktime_get(), 20); + while (1) { + bool timedout = ktime_after(ktime_get(), timeout); + + clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); + if (clk & SDHCI_CLOCK_INT_STABLE) + break; + if (timedout) { + pr_err("%s: Internal clock never stabilised.\n", + mmc_hostname(host->mmc)); + sdhci_dumpregs(host); + return false; + } + udelay(10); + } + return true; +} + +static void gl9755_uhs2_reset_sd_tran(struct sdhci_host *host) +{ + /* do this on UHS2 mode */ + if (host->mmc->flags & MMC_UHS2_INITIALIZED) { + sdhci_uhs2_reset(host, SDHCI_UHS2_SW_RESET_SD); + sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); + sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); + sdhci_uhs2_clear_set_irqs(host, + SDHCI_INT_ALL_MASK, + SDHCI_UHS2_INT_ERROR_MASK); + } +} + +static void sdhci_gl9755_reset(struct sdhci_host *host, u8 mask) +{ + ktime_t timeout; + u16 ctrl2; + u16 clk_ctrl; + + /* need internal clock */ + if (mask & SDHCI_RESET_ALL) { + ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); + clk_ctrl = sdhci_readw(host, SDHCI_CLOCK_CONTROL); + + if ((ctrl2 & SDHCI_CTRL_V4_MODE) && + (ctrl2 & SDHCI_CTRL_UHS2_ENABLE)) { + sdhci_writew(host, + SDHCI_CLOCK_INT_EN, + SDHCI_CLOCK_CONTROL); + } else { + sdhci_writew(host, + SDHCI_CLOCK_INT_EN, + SDHCI_CLOCK_CONTROL); + sdhci_wait_clock_stable(host); + sdhci_writew(host, + SDHCI_CTRL_V4_MODE, + SDHCI_HOST_CONTROL2); + } + } + + sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET); + + /* reset sd-tran on UHS2 mode if need to reset cmd/data */ + if ((mask & SDHCI_RESET_CMD) | (mask & SDHCI_RESET_DATA)) + gl9755_uhs2_reset_sd_tran(host); + + if (mask & SDHCI_RESET_ALL) + host->clock = 0; + + /* Wait max 100 ms */ + timeout = ktime_add_ms(ktime_get(), 100); + + /* hw clears the bit when it's done */ + while (1) { + bool timedout = ktime_after(ktime_get(), timeout); + + if (!(sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask)) + break; + if (timedout) { + pr_err("%s: Reset 0x%x never completed.\n", + mmc_hostname(host->mmc), (int)mask); + sdhci_dumpregs(host); + /* manual clear */ + sdhci_writeb(host, 0, SDHCI_SOFTWARE_RESET); + return; + } + udelay(10); + } +} + static int gli_probe_slot_gl9750(struct sdhci_pci_slot *slot) { struct sdhci_host *host = slot->host; @@ -713,6 +1011,7 @@ static int gli_probe_slot_gl9755(struct sdhci_pci_slot *slot) gli_pcie_enable_msi(slot); slot->host->mmc->caps2 |= MMC_CAP2_NO_SDIO; sdhci_enable_v4_mode(host); + gl9755_vendor_init(host); return 0; } @@ -1085,17 +1384,25 @@ static const struct sdhci_ops sdhci_gl9755_ops = { .read_w = sdhci_gli_readw, .read_b = sdhci_gli_readb, .set_clock = sdhci_gl9755_set_clock, + .set_power = gl9755_set_power, .enable_dma = sdhci_pci_enable_dma, .set_bus_width = sdhci_set_bus_width, - .reset = sdhci_reset, + .reset = sdhci_gl9755_reset, .set_uhs_signaling = sdhci_set_uhs_signaling, .voltage_switch = sdhci_gli_voltage_switch, + .dump_uhs2_regs = sdhci_uhs2_dump_regs, + .set_timeout = sdhci_uhs2_set_timeout, + .irq = sdhci_uhs2_irq, + .uhs2_pre_detect_init = gl9755_pre_detect_init, + .uhs2_post_attach_sd = gl9755_post_attach_sd, }; const struct sdhci_pci_fixes sdhci_gl9755 = { .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, .quirks2 = SDHCI_QUIRK2_BROKEN_DDR50, .probe_slot = gli_probe_slot_gl9755, + .add_host = sdhci_pci_uhs2_add_host, + .remove_host = sdhci_pci_uhs2_remove_host, .ops = &sdhci_gl9755_ops, #ifdef CONFIG_PM_SLEEP .resume = sdhci_pci_gli_resume,