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[2620:137:e000::1:20]) by mx.google.com with ESMTP id y4-20020a626404000000b0056ee105315fsi9765998pfb.178.2022.12.12.08.39.10; Mon, 12 Dec 2022 08:39:27 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=BPUDlXKW; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232837AbiLLQii (ORCPT + 99 others); Mon, 12 Dec 2022 11:38:38 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40860 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232620AbiLLQiG (ORCPT ); Mon, 12 Dec 2022 11:38:06 -0500 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 769DC1648C; Mon, 12 Dec 2022 08:36:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1670863007; x=1702399007; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=pAKxK37YXhqrsUkc+3DMZ5ZEleN2hTTXdA9Gs5kqlbU=; b=BPUDlXKWsO1zlmfZ6c/25xJ8za8/wwB1EB7AGNs4WszDhQmcX4/NfoVm y27N0cF3ca+/6sBbvaDF19rjCCgLrCu9zfZO86rzXB9lpKHETEFMzakIf s558zbp+oD1NdhFkLz7fBKm6zIm3QDxPQ2I/SbNC5Mm8a4f/uBbZ7Mebd p1bXS/MX7JMxYXJ2G+VEvjKLERkOeQQ/E91u4bv6yKG+b0yzS/aduMm97 Oue804JCn067EH+aWIwikqhypizNvUpdc8GIXRCir9GLt/B9U5F0+WtDl rSshXm1UFRzfJjQG2CsxUFAxUnlsL1RFJELPFCI3YZ2Szys5/jVM1tke8 Q==; X-IronPort-AV: E=Sophos;i="5.96,238,1665471600"; d="scan'208";a="127727121" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 12 Dec 2022 09:36:37 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.16; Mon, 12 Dec 2022 09:36:36 -0700 Received: from localhost.localdomain (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.16 via Frontend Transport; Mon, 12 Dec 2022 09:36:34 -0700 From: Claudiu Beznea To: , , , , , , , CC: , , , , Claudiu Beznea Subject: [PATCH v2 1/4] ASoC: dt-bindings: microchip: use proper naming syntax Date: Mon, 12 Dec 2022 18:41:50 +0200 Message-ID: <20221212164153.78677-2-claudiu.beznea@microchip.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20221212164153.78677-1-claudiu.beznea@microchip.com> References: <20221212164153.78677-1-claudiu.beznea@microchip.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1752027016739241031?= X-GMAIL-MSGID: =?utf-8?q?1752027016739241031?= Use the following syntax for Microchip ASoC YAML files: vendor,device.yaml Signed-off-by: Claudiu Beznea --- .../bindings/sound/mchp,i2s-mcc.yaml | 108 ------------------ ...,pdmc.yaml => microchip,sama7g5-pdmc.yaml} | 0 ...rx.yaml => microchip,sama7g5-spdifrx.yaml} | 0 ...tx.yaml => microchip,sama7g5-spdiftx.yaml} | 0 4 files changed, 108 deletions(-) delete mode 100644 Documentation/devicetree/bindings/sound/mchp,i2s-mcc.yaml rename Documentation/devicetree/bindings/sound/{microchip,pdmc.yaml => microchip,sama7g5-pdmc.yaml} (100%) rename Documentation/devicetree/bindings/sound/{mchp,spdifrx.yaml => microchip,sama7g5-spdifrx.yaml} (100%) rename Documentation/devicetree/bindings/sound/{mchp,spdiftx.yaml => microchip,sama7g5-spdiftx.yaml} (100%) diff --git a/Documentation/devicetree/bindings/sound/mchp,i2s-mcc.yaml b/Documentation/devicetree/bindings/sound/mchp,i2s-mcc.yaml deleted file mode 100644 index 0481315cb5f2..000000000000 --- a/Documentation/devicetree/bindings/sound/mchp,i2s-mcc.yaml +++ /dev/null @@ -1,108 +0,0 @@ -# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) -%YAML 1.2 ---- -$id: http://devicetree.org/schemas/sound/mchp,i2s-mcc.yaml# -$schema: http://devicetree.org/meta-schemas/core.yaml# - -title: Microchip I2S Multi-Channel Controller - -maintainers: - - Codrin Ciubotariu - -description: - The I2SMCC complies with the Inter-IC Sound (I2S) bus specification and - supports a Time Division Multiplexed (TDM) interface with external - multi-channel audio codecs. It consists of a receiver, a transmitter and a - common clock generator that can be enabled separately to provide Adapter, - Client or Controller modes with receiver and/or transmitter active. - On later I2SMCC versions (starting with Microchip's SAMA7G5) I2S - multi-channel is supported by using multiple data pins, output and - input, without TDM. - -properties: - "#sound-dai-cells": - const: 0 - - compatible: - enum: - - microchip,sam9x60-i2smcc - - microchip,sama7g5-i2smcc - - reg: - maxItems: 1 - - interrupts: - maxItems: 1 - - clocks: - items: - - description: Peripheral Bus Clock - - description: Generic Clock (Optional). Should be set mostly when Master - Mode is required. - minItems: 1 - - clock-names: - items: - - const: pclk - - const: gclk - minItems: 1 - - dmas: - items: - - description: TX DMA Channel - - description: RX DMA Channel - - dma-names: - items: - - const: tx - - const: rx - - microchip,tdm-data-pair: - description: - Represents the DIN/DOUT pair pins that are used to receive/send - TDM data. It is optional and it is only needed if the controller - uses the TDM mode. - $ref: /schemas/types.yaml#/definitions/uint8 - enum: [0, 1, 2, 3] - default: 0 - -if: - properties: - compatible: - const: microchip,sam9x60-i2smcc -then: - properties: - microchip,tdm-data-pair: false - -required: - - "#sound-dai-cells" - - compatible - - reg - - interrupts - - clocks - - clock-names - - dmas - - dma-names - -additionalProperties: false - -examples: - - | - #include - #include - - i2s@f001c000 { - #sound-dai-cells = <0>; - compatible = "microchip,sam9x60-i2smcc"; - reg = <0xf001c000 0x100>; - interrupts = <34 IRQ_TYPE_LEVEL_HIGH 7>; - dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(36))>, - <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(37))>; - dma-names = "tx", "rx"; - clocks = <&i2s_clk>, <&i2s_gclk>; - clock-names = "pclk", "gclk"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2s_default>; - }; diff --git a/Documentation/devicetree/bindings/sound/microchip,pdmc.yaml b/Documentation/devicetree/bindings/sound/microchip,sama7g5-pdmc.yaml similarity index 100% rename from Documentation/devicetree/bindings/sound/microchip,pdmc.yaml rename to Documentation/devicetree/bindings/sound/microchip,sama7g5-pdmc.yaml diff --git a/Documentation/devicetree/bindings/sound/mchp,spdifrx.yaml b/Documentation/devicetree/bindings/sound/microchip,sama7g5-spdifrx.yaml similarity index 100% rename from Documentation/devicetree/bindings/sound/mchp,spdifrx.yaml rename to Documentation/devicetree/bindings/sound/microchip,sama7g5-spdifrx.yaml diff --git a/Documentation/devicetree/bindings/sound/mchp,spdiftx.yaml b/Documentation/devicetree/bindings/sound/microchip,sama7g5-spdiftx.yaml similarity index 100% rename from Documentation/devicetree/bindings/sound/mchp,spdiftx.yaml rename to Documentation/devicetree/bindings/sound/microchip,sama7g5-spdiftx.yaml From patchwork Mon Dec 12 16:41:51 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 32448 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp2343614wrr; Mon, 12 Dec 2022 08:39:32 -0800 (PST) X-Google-Smtp-Source: AA0mqf4Y8cQ736xQ4NqBUySURHtHKwFO9BGvJyi0CBFS0lIa8CrRZBgROnIQG2lZjBhb6kOZluN8 X-Received: by 2002:a17:90a:b281:b0:219:e761:97e0 with SMTP id c1-20020a17090ab28100b00219e76197e0mr16906332pjr.33.1670863172392; Mon, 12 Dec 2022 08:39:32 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1670863172; cv=none; d=google.com; s=arc-20160816; b=OCs9ktYo2xIdx6C4aNJF4zacDxNENIiK61BjMwWq0r7EcztwrpThsQVFUQKroQwxKB IWq5cxjLSrMiw5FEEMGyF5xOyJhK5AT4ICRIR8WKYtLA5N0vuTML4S/vJcZuJXTfP38j 6Eci8oXKM9bg8BF3GsKgzQS6GBH8uwSkJqkWRwQIZXzmEOdoLTp9chYaIXYkM/cLuRwI 7+XHX6SgkjAaxfgNv7mnX7OgNqi5eXBrkPuAHI7ImYAkMXJT9LvNEU5ZjGjTh14BETL4 +BiIwygpCa8jELtw7iFSofsCxGCZPbe07KuClysWGOYn/OHYGE2uRRKDE0Po5Kpb/DXY bSug== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=Ymwlfg+g/R1B/g2LMEfSu800Oe+qA/h93KtekGTD9vg=; b=f7LfChjGhwFMpffnqjMou14nZGo1jbyTssWKJ9zkefqhBVU4IwTjKBtxOl54tHuscn xfMmdKvBOzLRcKeVvsaZvlkAmhUhVwceV7bJJBp8ulkkos2sGfXhB8QiBGRsstCDZq6s Y1ALBzvCmhIYzT64wzCHSdTvh9sTf5HVEt+SLLIu5hZBakriXZlxnohR516LN5F19Xwn Y28i09XFn4EWIPslqJ8XvdLX5eWsYOAybEEPXGHeezbTnPx6wpqxedb7U6b3yKLzHBqD gNDZ2gXc48ba0XNW233b7g3rPwkasTzkcNKstFMLWFQS+nWH30B65ee8B4eEJPk37bQ1 MF/Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=t9BpWsKC; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: from out1.vger.email (out1.vger.email. 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This simplifies the code and allow using the same infrastructure for suspend to RAM functionalities. Signed-off-by: Claudiu Beznea --- sound/soc/atmel/mchp-pdmc.c | 126 ++++++++++++++++++++++++------------ 1 file changed, 84 insertions(+), 42 deletions(-) diff --git a/sound/soc/atmel/mchp-pdmc.c b/sound/soc/atmel/mchp-pdmc.c index 44aefbd5b62c..f184404e74e5 100644 --- a/sound/soc/atmel/mchp-pdmc.c +++ b/sound/soc/atmel/mchp-pdmc.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include @@ -115,7 +116,6 @@ struct mchp_pdmc { int mic_no; int sinc_order; bool audio_filter_en; - u8 gclk_enabled:1; }; static const char *const mchp_pdmc_sinc_filter_order_text[] = { @@ -454,13 +454,6 @@ static int mchp_pdmc_startup(struct snd_pcm_substream *substream, struct snd_soc_dai *dai) { struct mchp_pdmc *dd = snd_soc_dai_get_drvdata(dai); - int ret; - - ret = clk_prepare_enable(dd->pclk); - if (ret) { - dev_err(dd->dev, "failed to enable the peripheral clock: %d\n", ret); - return ret; - } regmap_write(dd->regmap, MCHP_PDMC_CR, MCHP_PDMC_CR_SWRST); @@ -470,14 +463,6 @@ static int mchp_pdmc_startup(struct snd_pcm_substream *substream, return 0; } -static void mchp_pdmc_shutdown(struct snd_pcm_substream *substream, - struct snd_soc_dai *dai) -{ - struct mchp_pdmc *dd = snd_soc_dai_get_drvdata(dai); - - clk_disable_unprepare(dd->pclk); -} - static int mchp_pdmc_dai_probe(struct snd_soc_dai *dai) { struct mchp_pdmc *dd = snd_soc_dai_get_drvdata(dai); @@ -594,11 +579,6 @@ static int mchp_pdmc_hw_params(struct snd_pcm_substream *substream, cfgr_val |= MCHP_PDMC_CFGR_BSSEL(i); } - if (dd->gclk_enabled) { - clk_disable_unprepare(dd->gclk); - dd->gclk_enabled = 0; - } - for (osr_start = dd->audio_filter_en ? 64 : 8; osr_start <= 256 && best_diff_rate; osr_start *= 2) { long round_rate; @@ -620,8 +600,12 @@ static int mchp_pdmc_hw_params(struct snd_pcm_substream *substream, return -EINVAL; } + /* CLK is enabled by runtime PM. */ + clk_disable_unprepare(dd->gclk); + /* set the rate */ ret = clk_set_rate(dd->gclk, gclk_rate); + clk_prepare_enable(dd->gclk); if (ret) { dev_err(comp->dev, "unable to set rate %lu to GCLK: %d\n", gclk_rate, ret); @@ -636,9 +620,6 @@ static int mchp_pdmc_hw_params(struct snd_pcm_substream *substream, mr_val |= MCHP_PDMC_MR_CHUNK(dd->addr.maxburst); dev_dbg(comp->dev, "maxburst set to %d\n", dd->addr.maxburst); - clk_prepare_enable(dd->gclk); - dd->gclk_enabled = 1; - snd_soc_component_update_bits(comp, MCHP_PDMC_MR, MCHP_PDMC_MR_OSR_MASK | MCHP_PDMC_MR_SINCORDER_MASK | @@ -650,19 +631,6 @@ static int mchp_pdmc_hw_params(struct snd_pcm_substream *substream, return 0; } -static int mchp_pdmc_hw_free(struct snd_pcm_substream *substream, - struct snd_soc_dai *dai) -{ - struct mchp_pdmc *dd = snd_soc_dai_get_drvdata(dai); - - if (dd->gclk_enabled) { - clk_disable_unprepare(dd->gclk); - dd->gclk_enabled = 0; - } - - return 0; -} - static int mchp_pdmc_trigger(struct snd_pcm_substream *substream, int cmd, struct snd_soc_dai *dai) { @@ -711,9 +679,7 @@ static int mchp_pdmc_trigger(struct snd_pcm_substream *substream, static const struct snd_soc_dai_ops mchp_pdmc_dai_ops = { .set_fmt = mchp_pdmc_set_fmt, .startup = mchp_pdmc_startup, - .shutdown = mchp_pdmc_shutdown, .hw_params = mchp_pdmc_hw_params, - .hw_free = mchp_pdmc_hw_free, .trigger = mchp_pdmc_trigger, }; @@ -864,6 +830,7 @@ static const struct regmap_config mchp_pdmc_regmap_config = { .readable_reg = mchp_pdmc_readable_reg, .writeable_reg = mchp_pdmc_writeable_reg, .precious_reg = mchp_pdmc_precious_reg, + .cache_type = REGCACHE_FLAT, }; static int mchp_pdmc_dt_init(struct mchp_pdmc *dd) @@ -970,6 +937,49 @@ static struct snd_dmaengine_pcm_config mchp_pdmc_config = { .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config, }; +static int mchp_pdmc_runtime_suspend(struct device *dev) +{ + struct mchp_pdmc *dd = dev_get_drvdata(dev); + + regcache_cache_only(dd->regmap, true); + + clk_disable_unprepare(dd->gclk); + clk_disable_unprepare(dd->pclk); + + return 0; +} + +static int mchp_pdmc_runtime_resume(struct device *dev) +{ + struct mchp_pdmc *dd = dev_get_drvdata(dev); + int ret; + + ret = clk_prepare_enable(dd->pclk); + if (ret) { + dev_err(dd->dev, + "failed to enable the peripheral clock: %d\n", ret); + return ret; + } + ret = clk_prepare_enable(dd->gclk); + if (ret) { + dev_err(dd->dev, + "failed to enable generic clock: %d\n", ret); + goto disable_pclk; + } + + regcache_cache_only(dd->regmap, false); + regcache_mark_dirty(dd->regmap); + ret = regcache_sync(dd->regmap); + if (ret) { + regcache_cache_only(dd->regmap, true); + clk_disable_unprepare(dd->gclk); +disable_pclk: + clk_disable_unprepare(dd->pclk); + } + + return ret; +} + static int mchp_pdmc_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; @@ -1039,18 +1049,25 @@ static int mchp_pdmc_probe(struct platform_device *pdev) dd->addr.addr = (dma_addr_t)res->start + MCHP_PDMC_RHR; platform_set_drvdata(pdev, dd); + pm_runtime_enable(dd->dev); + if (!pm_runtime_enabled(dd->dev)) { + ret = mchp_pdmc_runtime_resume(dd->dev); + if (ret) + return ret; + } + /* register platform */ ret = devm_snd_dmaengine_pcm_register(dev, &mchp_pdmc_config, 0); if (ret) { dev_err(dev, "could not register platform: %d\n", ret); - return ret; + goto pm_runtime_suspend; } ret = devm_snd_soc_register_component(dev, &mchp_pdmc_dai_component, &mchp_pdmc_dai, 1); if (ret) { dev_err(dev, "could not register CPU DAI: %d\n", ret); - return ret; + goto pm_runtime_suspend; } /* print IP version */ @@ -1059,6 +1076,25 @@ static int mchp_pdmc_probe(struct platform_device *pdev) version & MCHP_PDMC_VER_VERSION); return 0; + +pm_runtime_suspend: + if (!pm_runtime_status_suspended(dd->dev)) + mchp_pdmc_runtime_suspend(dd->dev); + pm_runtime_disable(dd->dev); + + return ret; +} + +static int mchp_pdmc_remove(struct platform_device *pdev) +{ + struct mchp_pdmc *dd = platform_get_drvdata(pdev); + + if (!pm_runtime_status_suspended(dd->dev)) + mchp_pdmc_runtime_suspend(dd->dev); + + pm_runtime_disable(dd->dev); + + return 0; } static const struct of_device_id mchp_pdmc_of_match[] = { @@ -1070,13 +1106,19 @@ static const struct of_device_id mchp_pdmc_of_match[] = { }; MODULE_DEVICE_TABLE(of, mchp_pdmc_of_match); +static const struct dev_pm_ops mchp_pdmc_pm_ops = { + RUNTIME_PM_OPS(mchp_pdmc_runtime_suspend, mchp_pdmc_runtime_resume, + NULL) +}; + static struct platform_driver mchp_pdmc_driver = { .driver = { .name = "mchp-pdmc", .of_match_table = of_match_ptr(mchp_pdmc_of_match), - .pm = &snd_soc_pm_ops, + .pm = pm_ptr(&mchp_pdmc_pm_ops), }, .probe = mchp_pdmc_probe, + .remove = mchp_pdmc_remove, }; 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[2620:137:e000::1:20]) by mx.google.com with ESMTP id j19-20020a170902f25300b0018907d64909si8965307plc.325.2022.12.12.08.39.36; Mon, 12 Dec 2022 08:39:51 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=QNE4m9Hh; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232648AbiLLQjL (ORCPT + 99 others); Mon, 12 Dec 2022 11:39:11 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40864 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232834AbiLLQih (ORCPT ); Mon, 12 Dec 2022 11:38:37 -0500 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 95ABA14082; Mon, 12 Dec 2022 08:37:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1670863023; x=1702399023; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=skGTs2WvA6zYDm87dHeVl8kymrVloAz2yV13MCgFbvY=; b=QNE4m9Hhklw3C6QukjmsmcT5GFMtEST0RLHlLnBI0T6OXZuBGHdAYmPn r6xKExGic848lAYnnpi6xmf1bzfwXSpdDPMdMicxG1RooPcLzAIsUZvh3 tOKo3m/87XYZAavTq5l2xQz278O+k3WfRbyPNxzKhU4KD4CeSOr5Uj5Fr t8uzrOMvQg4ACyp0i+vNp+bBsJdUKdQlCLtq3dgclmSbG/IIzacwAd8BC 5OtYJnUsS3qjnCd6RJNuO+chhf3K9nGM/qfqN5j3fBDRu86EHojy6gliY IIaOF5EP5rua/3A4LQcbxYqHEToD35qeR0pKg2G8nTE9T7sJoZIz7pv3I w==; X-IronPort-AV: E=Sophos;i="5.96,238,1665471600"; d="scan'208";a="191263893" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa2.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 12 Dec 2022 09:36:46 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.16; Mon, 12 Dec 2022 09:36:43 -0700 Received: from localhost.localdomain (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.16 via Frontend Transport; Mon, 12 Dec 2022 09:36:40 -0700 From: Claudiu Beznea To: , , , , , , , CC: , , , , Claudiu Beznea Subject: [PATCH v2 3/4] ASoC: mchp-pdmc: add support for suspend to RAM Date: Mon, 12 Dec 2022 18:41:52 +0200 Message-ID: <20221212164153.78677-4-claudiu.beznea@microchip.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20221212164153.78677-1-claudiu.beznea@microchip.com> References: <20221212164153.78677-1-claudiu.beznea@microchip.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1752027042385948264?= X-GMAIL-MSGID: =?utf-8?q?1752027042385948264?= Add support for suspend to RAM by re-aranging the lines in switch..case from mchp_pdmc_trigger() and saving/restoring the enabled interrupts. These are necessary as AT91 devices has a special power saving mode (called backup and self-refresh) where most of the SoC parts are powered off and thus we need to reconfigure the PDMC on resume. Signed-off-by: Claudiu Beznea --- sound/soc/atmel/mchp-pdmc.c | 19 +++++++++++++------ 1 file changed, 13 insertions(+), 6 deletions(-) diff --git a/sound/soc/atmel/mchp-pdmc.c b/sound/soc/atmel/mchp-pdmc.c index f184404e74e5..cf4084dcbd5e 100644 --- a/sound/soc/atmel/mchp-pdmc.c +++ b/sound/soc/atmel/mchp-pdmc.c @@ -113,6 +113,7 @@ struct mchp_pdmc { struct clk *pclk; struct clk *gclk; u32 pdmcen; + u32 suspend_irq; int mic_no; int sinc_order; bool audio_filter_en; @@ -641,22 +642,27 @@ static int mchp_pdmc_trigger(struct snd_pcm_substream *substream, #endif switch (cmd) { - case SNDRV_PCM_TRIGGER_START: case SNDRV_PCM_TRIGGER_RESUME: - case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: + case SNDRV_PCM_TRIGGER_START: /* Enable overrun and underrun error interrupts */ - regmap_write(dd->regmap, MCHP_PDMC_IER, + regmap_write(dd->regmap, MCHP_PDMC_IER, dd->suspend_irq | MCHP_PDMC_IR_RXOVR | MCHP_PDMC_IR_RXUDR); + dd->suspend_irq = 0; + fallthrough; + case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: snd_soc_component_update_bits(cpu, MCHP_PDMC_MR, MCHP_PDMC_MR_PDMCEN_MASK, dd->pdmcen); break; - case SNDRV_PCM_TRIGGER_STOP: case SNDRV_PCM_TRIGGER_SUSPEND: - case SNDRV_PCM_TRIGGER_PAUSE_PUSH: + regmap_read(dd->regmap, MCHP_PDMC_IMR, &dd->suspend_irq); + fallthrough; + case SNDRV_PCM_TRIGGER_STOP: /* Disable overrun and underrun error interrupts */ - regmap_write(dd->regmap, MCHP_PDMC_IDR, + regmap_write(dd->regmap, MCHP_PDMC_IDR, dd->suspend_irq | MCHP_PDMC_IR_RXOVR | MCHP_PDMC_IR_RXUDR); + fallthrough; + case SNDRV_PCM_TRIGGER_PAUSE_PUSH: snd_soc_component_update_bits(cpu, MCHP_PDMC_MR, MCHP_PDMC_MR_PDMCEN_MASK, 0); break; @@ -1107,6 +1113,7 @@ static const struct of_device_id mchp_pdmc_of_match[] = { MODULE_DEVICE_TABLE(of, mchp_pdmc_of_match); static const struct dev_pm_ops mchp_pdmc_pm_ops = { + SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, pm_runtime_force_resume) RUNTIME_PM_OPS(mchp_pdmc_runtime_suspend, mchp_pdmc_runtime_resume, NULL) }; From patchwork Mon Dec 12 16:41:53 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 32450 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp2343774wrr; Mon, 12 Dec 2022 08:39:57 -0800 (PST) X-Google-Smtp-Source: AA0mqf4ER1ecWROugJaYX0TINPR7dLmojEYfAy2oxOamYkmAh218rGrm+r4ckigKMrTrntWhzbHM X-Received: by 2002:a05:6a00:4510:b0:578:2e3b:4728 with SMTP id cw16-20020a056a00451000b005782e3b4728mr9225053pfb.33.1670863197410; Mon, 12 Dec 2022 08:39:57 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1670863197; cv=none; d=google.com; s=arc-20160816; b=R+2N8ir2F1XtG/smrt+lgJXSBij5forugVYHUFZOCZtLzHp0BBsyA26R68J4PPy66V A0o7b4YQNPbFPBEI/zn7CgvYArb/T2pA0q2bIbPZnYW77r1qqQ15ItEJUWUlmzqDe1jq mkiLX/1zU1AIeCJdbJ77H81wwPsJxFxKKfIToA/UBf0sUeIyTdh8IG6APPd33V5Vrxfu sufZbyif0ZjLBFI2gtoB6c4HiNZCEyxH+quIrdjeQeuqg/+jv+3G+yblsbwzOTjT3UJC esWMiJij6tVx6c8xVuL7wf56UQsw+SGNT8EtL6uwTezgIp7Uc+XgHqdJDX5pOoiGpPnJ dVvQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=JQfTsK396DLPhAuSdGWTTzRM+D52T/OtNrP7M1VMPqQ=; b=WaFmqQUVQGxy4rf5IfTUgya4L67325fCu6QFRiXoR1bwD1WUAXfuyHGFvVSxqqlUsk Mzvf4mku2CwnI68pao40H/0h2HkZVwkQxbL1oCzKsBB3k7DmEh78P1ty98MmcZ6AR8N5 t+xKmx4FQoeiHgikZAzca901IFLkY6kLvMgO2AyC6DUJtNABcAUaTZT2ztb6CE94vBqL ADe4Shy8h0gHgw8/Fylet/lM23Y/JpQ1T5N5WU4LgzLjqUkNGpTxHub2QkPGeiP11Be7 fbViwdb9NEpVG4uP7HXLu/2BNXdfxD9H1W0IYJ98vHfyvoPm9b9obYlMZewpRCBxjJQG kRsQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b="vdm/CoXv"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id e7-20020a056a001a8700b00574250bd73dsi10280305pfv.321.2022.12.12.08.39.40; Mon, 12 Dec 2022 08:39:57 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b="vdm/CoXv"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232885AbiLLQjO (ORCPT + 99 others); Mon, 12 Dec 2022 11:39:14 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39922 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232847AbiLLQik (ORCPT ); Mon, 12 Dec 2022 11:38:40 -0500 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 15B5D1573F; Mon, 12 Dec 2022 08:37:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1670863025; x=1702399025; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=5xjzRZVtRE1cVlsbZZS0eIcjhBI2JgzIzQmwqEVYM3I=; b=vdm/CoXvOhoO+S1gDgdOuk2/aKmVmQRLXuKrjlfGj8FyP8I2zHPKGELv CSRJiLxu0xPMGiYSmPZtKSze374qBHRGW2i0QwbNZGzxDbACm8CjD+0j9 RTmca2fboJVP11defix7L2/zfOlABbo9AW7OPSHrqpxjAmSgMisCHH1ub KKNkJXzgbWQOLHleM0CsC3GfBP8mCmE6vpWOubX4UMpxWr3seZxO7H09m oF1bq2r4mIJFm8AvHJSgTSrvjGY2XkcQfDd96xS0TQeF4wns9IBUAQTJk SBtL5PohqMMcjnjg0vboFt4nTBdsXiP+3KzhvNQZVB36ZR+BkwBhTDVX4 Q==; X-IronPort-AV: E=Sophos;i="5.96,238,1665471600"; d="scan'208";a="192721522" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa3.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 12 Dec 2022 09:36:47 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.16; Mon, 12 Dec 2022 09:36:46 -0700 Received: from localhost.localdomain (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.16 via Frontend Transport; Mon, 12 Dec 2022 09:36:43 -0700 From: Claudiu Beznea To: , , , , , , , CC: , , , , Claudiu Beznea Subject: [PATCH v2 4/4] ASoC: mchp-spdiftx: use FIELD_PREP() where possible Date: Mon, 12 Dec 2022 18:41:53 +0200 Message-ID: <20221212164153.78677-5-claudiu.beznea@microchip.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20221212164153.78677-1-claudiu.beznea@microchip.com> References: <20221212164153.78677-1-claudiu.beznea@microchip.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1752027048094875820?= X-GMAIL-MSGID: =?utf-8?q?1752027048094875820?= Use FIELD_PREP() in macro definitions. Signed-off-by: Claudiu Beznea --- sound/soc/atmel/mchp-spdiftx.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/sound/soc/atmel/mchp-spdiftx.c b/sound/soc/atmel/mchp-spdiftx.c index dc96a6fbf514..20d135c718b0 100644 --- a/sound/soc/atmel/mchp-spdiftx.c +++ b/sound/soc/atmel/mchp-spdiftx.c @@ -6,6 +6,7 @@ // // Author: Codrin Ciubotariu +#include #include #include #include @@ -71,11 +72,11 @@ /* Valid Bits per Sample */ #define SPDIFTX_MR_VBPS_MASK GENMASK(13, 8) -#define SPDIFTX_MR_VBPS(bps) (((bps) << 8) & SPDIFTX_MR_VBPS_MASK) +#define SPDIFTX_MR_VBPS(bps) FIELD_PREP(SPDIFTX_MR_VBPS_MASK, bps) /* Chunk Size */ #define SPDIFTX_MR_CHUNK_MASK GENMASK(19, 16) -#define SPDIFTX_MR_CHUNK(size) (((size) << 16) & SPDIFTX_MR_CHUNK_MASK) +#define SPDIFTX_MR_CHUNK(size) FIELD_PREP(SPDIFTX_MR_CHUNK_MASK, size) /* Validity Bits for Channels 1 and 2 */ #define SPDIFTX_MR_VALID1 BIT(24) @@ -88,8 +89,7 @@ /* Bytes per Sample */ #define SPDIFTX_MR_BPS_MASK GENMASK(29, 28) -#define SPDIFTX_MR_BPS(bytes) \ - ((((bytes) - 1) << 28) & SPDIFTX_MR_BPS_MASK) +#define SPDIFTX_MR_BPS(bytes) FIELD_PREP(SPDIFTX_MR_BPS_MASK, (bytes - 1)) /* * ---- Interrupt Enable/Disable/Mask/Status Register (Write/Read-only) ----