From patchwork Sun Dec 11 01:47:27 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Kumaravel Thiagarajan X-Patchwork-Id: 32021 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp1306654wrr; Sat, 10 Dec 2022 05:14:31 -0800 (PST) X-Google-Smtp-Source: AA0mqf68I0zoM5FmVYl6yzbdD8iVnpweCm71OGHU5AVqe3UkSDvkF411+ar9/4yCa8LSKu9y140J X-Received: by 2002:a05:6402:2408:b0:467:6a1a:d994 with SMTP id t8-20020a056402240800b004676a1ad994mr8742362eda.7.1670678070836; Sat, 10 Dec 2022 05:14:30 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1670678070; cv=none; d=google.com; s=arc-20160816; b=ns9AVRKJdeZuKSLvCoA9nrvRiUoiqAZxtvC8pS9JEaLp4Ma8WDOFZP4fsnStnuKrpa wXPcC0ppwSIxNGNmN1ZLiPW3OoobCTe55rssxaHWklObEZUXZGaHhkqe2V4Siry+hjiH VT2NfdQtT1pSH5aSKlo3J+D/nHa3i7pesusG1jxBAF8QTjGie72OPsli9+FN+6m6blTK 5Mig/ML0rjav3XQTaFt1Z7cJVOmhy3unkjJET5WiZXVck0hD9toZQ7s9HVMtvN/EWsBz OiLMMIaYVghS4GB2ig0UWRs4euyPo6tvifwFOsFu0cF7p2vRCNpFkYOKQQIkeaZqe/qm BNsQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=TXsejilNleNWdUTD7ki/L0MkXDF51omXt8DLO0yV8Xk=; b=lxQhuvY682i14cAme1f7OjuTqg23l5utVb05n+TeKuumspBGACQodegRo8u7GY+TOG 2W8YLTZ9MAXYM8LMeOdqDg1Oe51rCOxBQHOXHZ6ERG3TPCJWrTMS5wFBnB9x26SbdFp6 VTQrOecQlfxtbstiXWxHFXJLHoMRrIT65EtfeCdqwvVZzu+EnK5FHzOm2e7LCo6ZyLGa W56ZlA5Rd+I2Y7rvrPFeOMRJP36iohHhsGgiiBcA2V0npLAS73ln9f5HOjDAfTBGFcYa qK2IEArO90ptC8+Qk65679TexPXaSkNMLstCsIQuosEFFXDDIuI0qgYQ2CHWKbzvoVvN gnYw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=XLTcEgvg; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id g10-20020a056402090a00b0045c97cb9027si4295191edz.421.2022.12.10.05.14.07; Sat, 10 Dec 2022 05:14:30 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=XLTcEgvg; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229805AbiLJNNU (ORCPT + 99 others); Sat, 10 Dec 2022 08:13:20 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52432 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229634AbiLJNNF (ORCPT ); Sat, 10 Dec 2022 08:13:05 -0500 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B9AACEE0D; Sat, 10 Dec 2022 05:13:02 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1670677982; x=1702213982; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=J0cDZjfgb9QtBEeL+5fiJ3N+bzN0LSv55hnEj+yf8QE=; b=XLTcEgvgANxVfD748pFtdQbiz5VK2lmorwZc6c1WDd9d8alPyQ4/XC6D dxSWeSwArpVPxFzhqeVRGfYb0yBPHMu/UCgJMvT3zyW0VaYv98oHwqQ2J 0dr67nL3FkX93x4W1h9lzr1gQMoqcv2J0+dd41+kwUWr4BOhg8RhQqOMC 5yqMoLYz+cTm2rrV7rixDINzg6wNFcpu7Tx5YGRIk0+8Y1MVqVGwPYOQU p4VxXG0lEb/TVl1mpnkIRwHuXt0cDyWFY23BiuqHJrZNlX0fBdY74mAcG qRXEyLbHkva01DLhZD1FchsfaLx4bRc98KIQ1f69IBInA4jzcBf1+Gznx w==; X-IronPort-AV: E=Sophos;i="5.96,234,1665471600"; d="scan'208";a="191021575" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa2.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 10 Dec 2022 06:12:52 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Sat, 10 Dec 2022 06:12:52 -0700 Received: from CHE-LT-UNGSOFTWARE.microchip.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.16 via Frontend Transport; Sat, 10 Dec 2022 06:12:47 -0700 From: Kumaravel Thiagarajan To: CC: , , , , , , , , , , , , , , , , , Tharun Kumar P Subject: [PATCH v8 tty-next 1/4] serial: 8250_pci: Add serial8250_pci_setup_port definition in 8250_pcilib.c Date: Sun, 11 Dec 2022 07:17:27 +0530 Message-ID: <20221211014730.1233272-2-kumaravel.thiagarajan@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221211014730.1233272-1-kumaravel.thiagarajan@microchip.com> References: <20221211014730.1233272-1-kumaravel.thiagarajan@microchip.com> MIME-Version: 1.0 X-Spam-Status: No, score=-1.2 required=5.0 tests=BAYES_00,DATE_IN_FUTURE_12_24, DKIMWL_WL_HIGH,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF, RCVD_IN_DNSWL_MED,SPF_HELO_PASS,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1751832929016111657?= X-GMAIL-MSGID: =?utf-8?q?1751832929016111657?= Move implementation of setup_port func() to serial8250_pci_setup_port. Co-developed-by: Tharun Kumar P Signed-off-by: Tharun Kumar P Signed-off-by: Kumaravel Thiagarajan Reviewed-by: Ilpo Järvinen Reviewed-by: Andy Shevchenko --- Changes in v8: - Moved SERIAL_8250_PCILIB above 8250_PCI Changes in v7: - Used namespace 'SERIAL_8250_PCI' while exporting and importing symbols - Included structures used in function declaration in 8250_pcilib.h file Changes in v6: - Made this patch first patch of the patch series Changes in v5: - This is the new patch added in v5 version of this patchset - Moved implementation of setup_port from 8250_pci.c to 8250_pcilib.c --- drivers/tty/serial/8250/8250_pci.c | 25 +++--------------- drivers/tty/serial/8250/8250_pcilib.c | 38 +++++++++++++++++++++++++++ drivers/tty/serial/8250/8250_pcilib.h | 15 +++++++++++ drivers/tty/serial/8250/Kconfig | 4 +++ drivers/tty/serial/8250/Makefile | 1 + 5 files changed, 61 insertions(+), 22 deletions(-) create mode 100644 drivers/tty/serial/8250/8250_pcilib.c create mode 100644 drivers/tty/serial/8250/8250_pcilib.h diff --git a/drivers/tty/serial/8250/8250_pci.c b/drivers/tty/serial/8250/8250_pci.c index 6f66dc2ebacc..58cc9e19bd20 100644 --- a/drivers/tty/serial/8250/8250_pci.c +++ b/drivers/tty/serial/8250/8250_pci.c @@ -24,6 +24,7 @@ #include #include "8250.h" +#include "8250_pcilib.h" /* * init function returns: @@ -89,28 +90,7 @@ static int setup_port(struct serial_private *priv, struct uart_8250_port *port, u8 bar, unsigned int offset, int regshift) { - struct pci_dev *dev = priv->dev; - - if (bar >= PCI_STD_NUM_BARS) - return -EINVAL; - - if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) { - if (!pcim_iomap(dev, bar, 0) && !pcim_iomap_table(dev)) - return -ENOMEM; - - port->port.iotype = UPIO_MEM; - port->port.iobase = 0; - port->port.mapbase = pci_resource_start(dev, bar) + offset; - port->port.membase = pcim_iomap_table(dev)[bar] + offset; - port->port.regshift = regshift; - } else { - port->port.iotype = UPIO_PORT; - port->port.iobase = pci_resource_start(dev, bar) + offset; - port->port.mapbase = 0; - port->port.membase = NULL; - port->port.regshift = 0; - } - return 0; + return serial8250_pci_setup_port(priv->dev, port, bar, offset, regshift); } /* @@ -5759,3 +5739,4 @@ module_pci_driver(serial_pci_driver); MODULE_LICENSE("GPL"); MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module"); MODULE_DEVICE_TABLE(pci, serial_pci_tbl); +MODULE_IMPORT_NS(SERIAL_8250_PCI); diff --git a/drivers/tty/serial/8250/8250_pcilib.c b/drivers/tty/serial/8250/8250_pcilib.c new file mode 100644 index 000000000000..090385172a09 --- /dev/null +++ b/drivers/tty/serial/8250/8250_pcilib.c @@ -0,0 +1,38 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * 8250 PCI library. + * + * Copyright (C) 2001 Russell King, All Rights Reserved. + */ +#include +#include +#include +#include + +#include "8250.h" + +int serial8250_pci_setup_port(struct pci_dev *dev, struct uart_8250_port *port, + u8 bar, unsigned int offset, int regshift) +{ + if (bar >= PCI_STD_NUM_BARS) + return -EINVAL; + + if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) { + if (!pcim_iomap(dev, bar, 0) && !pcim_iomap_table(dev)) + return -ENOMEM; + + port->port.iotype = UPIO_MEM; + port->port.iobase = 0; + port->port.mapbase = pci_resource_start(dev, bar) + offset; + port->port.membase = pcim_iomap_table(dev)[bar] + offset; + port->port.regshift = regshift; + } else { + port->port.iotype = UPIO_PORT; + port->port.iobase = pci_resource_start(dev, bar) + offset; + port->port.mapbase = 0; + port->port.membase = NULL; + port->port.regshift = 0; + } + return 0; +} +EXPORT_SYMBOL_NS_GPL(serial8250_pci_setup_port, SERIAL_8250_PCI); diff --git a/drivers/tty/serial/8250/8250_pcilib.h b/drivers/tty/serial/8250/8250_pcilib.h new file mode 100644 index 000000000000..1aaf1b50ce9c --- /dev/null +++ b/drivers/tty/serial/8250/8250_pcilib.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * 8250 PCI library header file. + * + * Copyright (C) 2001 Russell King, All Rights Reserved. + */ + +#include + +struct pci_dev; + +struct uart_8250_port; + +int serial8250_pci_setup_port(struct pci_dev *dev, struct uart_8250_port *port, u8 bar, + unsigned int offset, int regshift); diff --git a/drivers/tty/serial/8250/Kconfig b/drivers/tty/serial/8250/Kconfig index d0b49e15fbf5..768b73d5cb9a 100644 --- a/drivers/tty/serial/8250/Kconfig +++ b/drivers/tty/serial/8250/Kconfig @@ -129,9 +129,13 @@ config SERIAL_8250_DMA This builds DMA support that can be used with 8250/16650 compatible UART controllers that support DMA signaling. +config SERIAL_8250_PCILIB + bool + config SERIAL_8250_PCI tristate "8250/16550 PCI device support" depends on SERIAL_8250 && PCI + select SERIAL_8250_PCILIB default SERIAL_8250 help This builds standard PCI serial support. You may be able to diff --git a/drivers/tty/serial/8250/Makefile b/drivers/tty/serial/8250/Makefile index bee908f99ea0..b9179d1f104b 100644 --- a/drivers/tty/serial/8250/Makefile +++ b/drivers/tty/serial/8250/Makefile @@ -12,6 +12,7 @@ obj-$(CONFIG_SERIAL_8250) += 8250.o 8250_base.o 8250_base-$(CONFIG_SERIAL_8250_DMA) += 8250_dma.o 8250_base-$(CONFIG_SERIAL_8250_DWLIB) += 8250_dwlib.o 8250_base-$(CONFIG_SERIAL_8250_FINTEK) += 8250_fintek.o +8250_base-$(CONFIG_SERIAL_8250_PCILIB) += 8250_pcilib.o obj-$(CONFIG_SERIAL_8250_GSC) += 8250_gsc.o obj-$(CONFIG_SERIAL_8250_PCI) += 8250_pci.o obj-$(CONFIG_SERIAL_8250_EXAR) += 8250_exar.o From patchwork Sun Dec 11 01:47:28 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kumaravel Thiagarajan X-Patchwork-Id: 32020 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp1306513wrr; Sat, 10 Dec 2022 05:14:12 -0800 (PST) X-Google-Smtp-Source: AA0mqf6JI1raLH5UE5WFM6Gqo9DO9OlPi1/MexOiXatJi58wJvdbFZnSVJF6A76kT/hnpS32WvM5 X-Received: by 2002:a05:6402:3609:b0:461:8be6:1ac5 with SMTP id el9-20020a056402360900b004618be61ac5mr7918523edb.3.1670678052011; Sat, 10 Dec 2022 05:14:12 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1670678051; cv=none; d=google.com; s=arc-20160816; b=SmLuuYW4BZ6bI72/z6kz1iMJlINZ1hQZCqIBeRaCCL5Eh15AZAAh4MOjZG3JL19Rw/ F0k29S4ygZU7kMbrYwL3zPa7OiJ9lnpwI5JmN/O4O3ZCPzFIRYYEpLfWQoon+fo9HpEq pN1QnTBAERCyls9GCup1DDnsNFaMX9v++R8l8loCni8vqcrUfMy+iBaJUp/wElvFrRlH 3/gcoHGtHeqzsopHHemDalqaucNBx/vMmF+fA8B67gjQrl7FzJUQLCJUzkX1As98uhMh oLSmZzjzkPE0a4T/6X9q6zYPvF4MFXSP9CzJWrfmGb19OdKdfe1llrIYG4pXwl81Lj/m Q6jw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=NX99xO++Ej+kr2CX6hwHv1dpAckc1ItMlhTrsIhLIps=; b=att32arP8iqZYPzZtIeLxJzZ7iN1TBE2TPfPRaKX+LMLjfbEPRcvYN1XiiQLFEm7jo XO7jMKoVnyFtngGsC3PYP6CJKZcOH32oJs3lzJigLgagpYzfDOqns+6Tz8o2jogHrNca gG29BgMiC4h0DsHOmsFx0l3v0dV0cYufZVFMynqHiDqD8HwaiJ+wOZshx8/xPpqWr1QV vFKPmGWAqtpY1CA2Us6PHCw47U+jhJg/Rt8JyyEsWZsEPEX6v9mjoMi/5pWjTKXuPmri 0FBanXq+ciRmRuufACd13Y5BPfFqC38/pZEZMjl3pQCT2Lu9Qhx6gEPZgiyAVYvK2rpM pLCA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=XRBI0r7p; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id z16-20020a05640235d000b00469274348b5si3911055edc.263.2022.12.10.05.13.48; Sat, 10 Dec 2022 05:14:11 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=XRBI0r7p; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229750AbiLJNNM (ORCPT + 99 others); Sat, 10 Dec 2022 08:13:12 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52506 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229637AbiLJNNF (ORCPT ); Sat, 10 Dec 2022 08:13:05 -0500 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B98C5B1EF; Sat, 10 Dec 2022 05:13:02 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1670677984; x=1702213984; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=l23KLNgFtpVwRJaGmZ3+ufXkb9Ltll9kUIsr5WsyVjE=; b=XRBI0r7pPi/mVOU2TeIRdI4Duf60hkF2hE9BIp0+Up/fD5Cj3hvM0EXS ttysjUwyEvsnDwMXLbHpMb9Z68Ok22g3zLwRMlOyL9FTjqClHE7Ol+0ep 3i9HxMAF90oykG1DyBHGkg/0boPK1AZQefRB+2jg5l+VlsK9D95dyrxPv /RohmcXipmtsB/pfAI7xvZyuDmApEbasBIyGRQFaN7MJzhdN4lQCEQKOa 9yTfIORItjySkAYYiWA/3+2SoZOmHMorbkqjprYbSiRn1d8b+fxPIpZLa HQm2a0B6BgyQXyv/eKU9nKNKjnkCB/XJ6AyWM5S7MZqavpRuHu5xcJqy7 Q==; X-IronPort-AV: E=Sophos;i="5.96,234,1665471600"; d="scan'208";a="192508836" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa5.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 10 Dec 2022 06:13:02 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.16; Sat, 10 Dec 2022 06:13:01 -0700 Received: from CHE-LT-UNGSOFTWARE.microchip.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.16 via Frontend Transport; Sat, 10 Dec 2022 06:12:55 -0700 From: Kumaravel Thiagarajan To: CC: , , , , , , , , , , , , , , , , , Tharun Kumar P Subject: [PATCH v8 tty-next 2/4] serial: 8250_pci1xxxx: Add driver for quad-uart support Date: Sun, 11 Dec 2022 07:17:28 +0530 Message-ID: <20221211014730.1233272-3-kumaravel.thiagarajan@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221211014730.1233272-1-kumaravel.thiagarajan@microchip.com> References: <20221211014730.1233272-1-kumaravel.thiagarajan@microchip.com> MIME-Version: 1.0 X-Spam-Status: No, score=-1.2 required=5.0 tests=BAYES_00,DATE_IN_FUTURE_12_24, DKIMWL_WL_HIGH,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF, RCVD_IN_DNSWL_MED,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1751832909212854085?= X-GMAIL-MSGID: =?utf-8?q?1751832909212854085?= pci1xxxx is a PCIe switch with a multi-function endpoint on one of its downstream ports. Quad-uart is one of the functions in the multi-function endpoint. This driver loads for the quad-uart and enumerates single or multiple instances of uart based on the PCIe subsystem device ID. Co-developed-by: Tharun Kumar P Signed-off-by: Tharun Kumar P Signed-off-by: Kumaravel Thiagarajan --- Changes in v8: - Requested only required number of interrupt vectors in pci_alloc_irq_vectors API based on sub-device id Changes in v7: - Used appropriate error codes - Moved logical_to_physical_port_idx array to a function Changes in v6: - Removed un-necessary paranthesis - Used array and removed switch cases to reduce complexity - Handled failure case of pcim_iomap Changes in v5: - Used tabs instead of spaces in MACRO definitions for readability - Removed assignments that are not required - Removed redundant blank lines Changes in v4: - Renamed pci_setup_port to serial8250_pci_setup_port - Added Copyright information to 8250_pcilib.c Changes in v3: - Used NSEC_PER_SEC, HZ_PER_MHZ, FIELD_PREP, FIELD_GET MACROs wherever necessary - Handled failure case of serial8250_register_8250_port properly - Moved pci_setup_port to 8250_pcilib.c Changes in v2: - Use only the 62.5 MHz for baud clock. - Define custom implementation for get_divisor and set_divisor. - Use BOTHER instead of UPF_SPD_CUST for non standard baud rates (untested). - Correct indentation in clock divisor computation. - Remove unnecessary call to pci_save_state in probe function. - Fix null pointer dereference in probe function. - Move pci1xxxx_rs485_config to a separate patch. - Depends on SERIAL_8250_PCI & default to SERIAL_8250. - Change PORT_MCHP16550A to 100 from 124. --- MAINTAINERS | 7 + drivers/tty/serial/8250/8250_pci1xxxx.c | 337 ++++++++++++++++++++++++ drivers/tty/serial/8250/8250_port.c | 8 + drivers/tty/serial/8250/Kconfig | 11 + drivers/tty/serial/8250/Makefile | 1 + include/uapi/linux/serial_core.h | 3 + 6 files changed, 367 insertions(+) create mode 100644 drivers/tty/serial/8250/8250_pci1xxxx.c diff --git a/MAINTAINERS b/MAINTAINERS index d30f26e07cd3..aa98deaba249 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -13434,6 +13434,13 @@ F: Documentation/devicetree/bindings/nvmem/microchip,sama7g5-otpc.yaml F: drivers/nvmem/microchip-otpc.c F: include/dt-bindings/nvmem/microchip,sama7g5-otpc.h +MICROCHIP PCIe UART DRIVER +M: Kumaravel Thiagarajan +M: Tharun Kumar P +L: linux-serial@vger.kernel.org +S: Maintained +F: drivers/tty/serial/8250/8250_pci1xxxx.c + MICROCHIP PWM DRIVER M: Claudiu Beznea L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) diff --git a/drivers/tty/serial/8250/8250_pci1xxxx.c b/drivers/tty/serial/8250/8250_pci1xxxx.c new file mode 100644 index 000000000000..05d1bd386f07 --- /dev/null +++ b/drivers/tty/serial/8250/8250_pci1xxxx.c @@ -0,0 +1,337 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Probe module for 8250/16550-type MCHP PCI serial ports. + * + * Based on drivers/tty/serial/8250/8250_pci.c, + * + * Copyright (C) 2022 Microchip Technology Inc., All Rights Reserved. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "8250.h" +#include "8250_pcilib.h" + +#define PCI_DEVICE_ID_EFAR_PCI12000 0xa002 +#define PCI_DEVICE_ID_EFAR_PCI11010 0xa012 +#define PCI_DEVICE_ID_EFAR_PCI11101 0xa022 +#define PCI_DEVICE_ID_EFAR_PCI11400 0xa032 +#define PCI_DEVICE_ID_EFAR_PCI11414 0xa042 + +#define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_4p 0x0001 +#define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_3p012 0x0002 +#define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_3p013 0x0003 +#define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_3p023 0x0004 +#define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_3p123 0x0005 +#define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_2p01 0x0006 +#define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_2p02 0x0007 +#define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_2p03 0x0008 +#define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_2p12 0x0009 +#define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_2p13 0x000a +#define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_2p23 0x000b +#define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_1p0 0x000c +#define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_1p1 0x000d +#define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_1p2 0x000e +#define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_1p3 0x000f + +#define PCI_SUBDEVICE_ID_EFAR_PCI12000 PCI_DEVICE_ID_EFAR_PCI12000 +#define PCI_SUBDEVICE_ID_EFAR_PCI11010 PCI_DEVICE_ID_EFAR_PCI11010 +#define PCI_SUBDEVICE_ID_EFAR_PCI11101 PCI_DEVICE_ID_EFAR_PCI11101 +#define PCI_SUBDEVICE_ID_EFAR_PCI11400 PCI_DEVICE_ID_EFAR_PCI11400 +#define PCI_SUBDEVICE_ID_EFAR_PCI11414 PCI_DEVICE_ID_EFAR_PCI11414 + +#define UART_ACTV_REG 0x11 +#define UART_BLOCK_SET_ACTIVE BIT(0) + +#define UART_PCI_CTRL_REG 0x80 +#define UART_PCI_CTRL_SET_MULTIPLE_MSI BIT(4) +#define UART_PCI_CTRL_D3_CLK_ENABLE BIT(0) + +#define ADCL_CFG_REG 0x40 +#define ADCL_CFG_POL_SEL BIT(2) +#define ADCL_CFG_PIN_SEL BIT(1) +#define ADCL_CFG_EN BIT(0) + +#define UART_BIT_SAMPLE_CNT 16 +#define BAUD_CLOCK_DIV_INT_MSK GENMASK(31, 8) +#define ADCL_CFG_RTS_DELAY_MASK GENMASK(11, 8) +#define UART_CLOCK_DEFAULT (62500 * HZ_PER_KHZ) + +#define UART_WAKE_REG 0x8C +#define UART_WAKE_MASK_REG 0x90 +#define UART_WAKE_N_PIN BIT(2) +#define UART_WAKE_NCTS BIT(1) +#define UART_WAKE_INT BIT(0) +#define UART_WAKE_SRCS \ + (UART_WAKE_N_PIN | UART_WAKE_NCTS | UART_WAKE_INT) + +#define UART_BAUD_CLK_DIVISOR_REG 0x54 + +#define UART_RESET_REG 0x94 +#define UART_RESET_D3_RESET_DISABLE BIT(16) + +#define MAX_PORTS 4 + +struct pci1xxxx_8250 { + struct pci_dev *pdev; + unsigned int nr; + void __iomem *membase; + int line[]; +}; + +static int pci1xxxx_get_num_ports(struct pci_dev *dev) +{ + switch (dev->subsystem_device) { + case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_1p0: + case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_1p1: + case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_1p2: + case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_1p3: + case PCI_SUBDEVICE_ID_EFAR_PCI12000: + case PCI_SUBDEVICE_ID_EFAR_PCI11010: + case PCI_SUBDEVICE_ID_EFAR_PCI11101: + case PCI_SUBDEVICE_ID_EFAR_PCI11400: + default: + return 1; + case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_2p01: + case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_2p02: + case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_2p03: + case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_2p12: + case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_2p13: + case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_2p23: + return 2; + case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_3p012: + case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_3p123: + case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_3p013: + case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_3p023: + return 3; + case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_4p: + case PCI_SUBDEVICE_ID_EFAR_PCI11414: + return 4; + } +} + +static unsigned int pci1xxxx_get_divisor(struct uart_port *port, + unsigned int baud, unsigned int *frac) +{ + unsigned int quot; + + /* + * Calculate baud rate sampling period in nanoseconds. + * Fractional part x denotes x/255 parts of a nanosecond. + */ + quot = NSEC_PER_SEC / (baud * UART_BIT_SAMPLE_CNT); + *frac = (NSEC_PER_SEC - quot * baud * UART_BIT_SAMPLE_CNT) * + 255 / UART_BIT_SAMPLE_CNT / baud; + + return quot; +} + +static void pci1xxxx_set_divisor(struct uart_port *port, unsigned int baud, + unsigned int quot, unsigned int frac) +{ + writel(FIELD_PREP(BAUD_CLOCK_DIV_INT_MSK, quot) | frac, + port->membase + UART_BAUD_CLK_DIVISOR_REG); +} + +static int pci1xxxx_setup(struct pci1xxxx_8250 *priv, + struct uart_8250_port *port, int port_idx) +{ + int ret; + + port->port.flags |= UPF_FIXED_TYPE | UPF_SKIP_TEST; + port->port.type = PORT_MCHP16550A; + port->port.set_termios = serial8250_do_set_termios; + port->port.get_divisor = pci1xxxx_get_divisor; + port->port.set_divisor = pci1xxxx_set_divisor; + + ret = serial8250_pci_setup_port(priv->pdev, port, 0, port_idx * 256, 0); + if (ret < 0) + return ret; + + writeb(UART_BLOCK_SET_ACTIVE, port->port.membase + UART_ACTV_REG); + writeb(UART_WAKE_SRCS, port->port.membase + UART_WAKE_REG); + writeb(UART_WAKE_N_PIN, port->port.membase + UART_WAKE_MASK_REG); + + return 0; +} + +static int pci1xxxx_get_max_port(int subsys_dev) +{ + static int max_port[] = { + 1,/* PCI12000 PCI11010 PCI11101 PCI11400 */ + 4,/* PCI4p */ + 3,/* PCI3p012 */ + 4,/* PCI3p013 */ + 4,/* PCI3p023 */ + 4,/* PCI3p123 */ + 2,/* PCI2p01 */ + 3,/* PCI2p02 */ + 4,/* PCI2p03 */ + 3,/* PCI2p12 */ + 4,/* PCI2p13 */ + 4,/* PCI2p23 */ + 1,/* PCI1p0 */ + 2,/* PCI1p1 */ + 3,/* PCI1p2 */ + 4,/* PCI1p3 */ + }; + + if (subsys_dev > PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_1p3) + if (subsys_dev != PCI_SUBDEVICE_ID_EFAR_PCI11414) + return max_port[0]; + else + return 4; + else + return max_port[subsys_dev]; + +} + +static int pci1xxxx_logical_to_physical_port_translate(int subsys_dev, int port) +{ + static int logical_to_physical_port_idx[][MAX_PORTS] = { + {0, 1, 2, 3},/* PCI12000 PCI11010 PCI11101 PCI11400 PCI11414 */ + {0, 1, 2, 3},/* PCI4p */ + {0, 1, 2, -1},/* PCI3p012 */ + {0, 1, 3, -1},/* PCI3p013 */ + {0, 2, 3, -1},/* PCI3p023 */ + {1, 2, 3, -1},/* PCI3p123 */ + {0, 1, -1, -1},/* PCI2p01 */ + {0, 2, -1, -1},/* PCI2p02 */ + {0, 3, -1, -1},/* PCI2p03 */ + {1, 2, -1, -1},/* PCI2p12 */ + {1, 3, -1, -1},/* PCI2p13 */ + {2, 3, -1, -1},/* PCI2p23 */ + {0, -1, -1, -1},/* PCI1p0 */ + {1, -1, -1, -1},/* PCI1p1 */ + {2, -1, -1, -1},/* PCI1p2 */ + {3, -1, -1, -1},/* PCI1p3 */ + }; + + if (subsys_dev > PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_1p3) + return logical_to_physical_port_idx[0][port]; + else + return logical_to_physical_port_idx[subsys_dev][port]; +} + +static int pci1xxxx_serial_probe(struct pci_dev *pdev, + const struct pci_device_id *id) +{ + struct device *dev = &pdev->dev; + struct pci1xxxx_8250 *priv; + struct uart_8250_port uart; + unsigned int nr_ports, i; + int max_vec_reqd; + int num_vectors; + int subsys_dev; + int port_idx; + int rc; + + rc = pcim_enable_device(pdev); + if (rc) + return rc; + + nr_ports = pci1xxxx_get_num_ports(pdev); + + priv = devm_kzalloc(dev, struct_size(priv, line, nr_ports), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->membase = pcim_iomap(pdev, 0, 0); + if (!priv->membase) + return -ENOMEM; + + priv->pdev = pdev; + subsys_dev = priv->pdev->subsystem_device; + priv->nr = nr_ports; + pci_set_master(pdev); + max_vec_reqd = pci1xxxx_get_max_port(subsys_dev); + num_vectors = pci_alloc_irq_vectors(pdev, 1, max_vec_reqd, + PCI_IRQ_ALL_TYPES); + if (num_vectors < 0) + return num_vectors; + + memset(&uart, 0, sizeof(uart)); + uart.port.flags = UPF_SHARE_IRQ | UPF_FIXED_PORT; + uart.port.uartclk = UART_CLOCK_DEFAULT; + uart.port.dev = dev; + + if (num_vectors == max_vec_reqd) + writeb(UART_PCI_CTRL_SET_MULTIPLE_MSI, + priv->membase + UART_PCI_CTRL_REG); + + for (i = 0; i < nr_ports; i++) + priv->line[i] = -ENODEV; + + for (i = 0; i < nr_ports; i++) { + port_idx = pci1xxxx_logical_to_physical_port_translate(subsys_dev, i); + + if (num_vectors == max_vec_reqd) + uart.port.irq = pci_irq_vector(priv->pdev, port_idx); + else + uart.port.irq = pci_irq_vector(pdev, 0); + + rc = pci1xxxx_setup(priv, &uart, port_idx); + if (rc) { + dev_warn(dev, "Failed to setup port %u\n", i); + continue; + } + + priv->line[i] = serial8250_register_8250_port(&uart); + if (priv->line[i] < 0) { + dev_warn(dev, + "Couldn't register serial port %lx, irq %d, type %d, error %d\n", + uart.port.iobase, uart.port.irq, uart.port.iotype, + priv->line[i]); + } + } + + pci_set_drvdata(pdev, priv); + + return 0; +} + +static void pci1xxxx_serial_remove(struct pci_dev *dev) +{ + struct pci1xxxx_8250 *priv = pci_get_drvdata(dev); + int i; + + for (i = 0; i < priv->nr; i++) { + if (priv->line[i] >= 0) + serial8250_unregister_port(priv->line[i]); + } +} + +static const struct pci_device_id pci1xxxx_pci_tbl[] = { + { PCI_DEVICE(PCI_VENDOR_ID_EFAR, PCI_DEVICE_ID_EFAR_PCI11010) }, + { PCI_DEVICE(PCI_VENDOR_ID_EFAR, PCI_DEVICE_ID_EFAR_PCI11101) }, + { PCI_DEVICE(PCI_VENDOR_ID_EFAR, PCI_DEVICE_ID_EFAR_PCI11400) }, + { PCI_DEVICE(PCI_VENDOR_ID_EFAR, PCI_DEVICE_ID_EFAR_PCI11414) }, + { PCI_DEVICE(PCI_VENDOR_ID_EFAR, PCI_DEVICE_ID_EFAR_PCI12000) }, + {} +}; +MODULE_DEVICE_TABLE(pci, pci1xxxx_pci_tbl); + +static struct pci_driver pci1xxxx_pci_driver = { + .name = "pci1xxxx serial", + .probe = pci1xxxx_serial_probe, + .remove = pci1xxxx_serial_remove, + .id_table = pci1xxxx_pci_tbl, +}; +module_pci_driver(pci1xxxx_pci_driver); + +MODULE_DESCRIPTION("Microchip Technology Inc. PCIe to UART module"); +MODULE_AUTHOR("Kumaravel Thiagarajan "); +MODULE_AUTHOR("Tharun Kumar P "); +MODULE_LICENSE("GPL"); diff --git a/drivers/tty/serial/8250/8250_port.c b/drivers/tty/serial/8250/8250_port.c index 1d2a43214b48..ec2fe5fd7b02 100644 --- a/drivers/tty/serial/8250/8250_port.c +++ b/drivers/tty/serial/8250/8250_port.c @@ -313,6 +313,14 @@ static const struct serial8250_config uart_config[] = { .rxtrig_bytes = {1, 4, 8, 14}, .flags = UART_CAP_FIFO, }, + [PORT_MCHP16550A] = { + .name = "MCHP16550A", + .fifo_size = 256, + .tx_loadsz = 256, + .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01, + .rxtrig_bytes = {2, 66, 130, 194}, + .flags = UART_CAP_FIFO, + }, }; /* Uart divisor latch read */ diff --git a/drivers/tty/serial/8250/Kconfig b/drivers/tty/serial/8250/Kconfig index 768b73d5cb9a..588a73c0f4e8 100644 --- a/drivers/tty/serial/8250/Kconfig +++ b/drivers/tty/serial/8250/Kconfig @@ -295,6 +295,17 @@ config SERIAL_8250_HUB6 To compile this driver as a module, choose M here: the module will be called 8250_hub6. +config SERIAL_8250_PCI1XXXX + tristate "Microchip 8250 based serial port" + depends on SERIAL_8250 && PCI + select SERIAL_8250_PCILIB + default SERIAL_8250 + help + Select this option if you have a setup with Microchip PCIe + Switch with serial port enabled and wish to enable 8250 + serial driver for the serial interface. This driver support + will ensure to support baud rates upto 1.5Mpbs. + # # Misc. options/drivers. # diff --git a/drivers/tty/serial/8250/Makefile b/drivers/tty/serial/8250/Makefile index b9179d1f104b..98202fdf39f8 100644 --- a/drivers/tty/serial/8250/Makefile +++ b/drivers/tty/serial/8250/Makefile @@ -27,6 +27,7 @@ obj-$(CONFIG_SERIAL_8250_ACCENT) += 8250_accent.o obj-$(CONFIG_SERIAL_8250_BOCA) += 8250_boca.o obj-$(CONFIG_SERIAL_8250_EXAR_ST16C554) += 8250_exar_st16c554.o obj-$(CONFIG_SERIAL_8250_HUB6) += 8250_hub6.o +obj-$(CONFIG_SERIAL_8250_PCI1XXXX) += 8250_pci1xxxx.o obj-$(CONFIG_SERIAL_8250_FSL) += 8250_fsl.o obj-$(CONFIG_SERIAL_8250_MEN_MCB) += 8250_men_mcb.o obj-$(CONFIG_SERIAL_8250_DW) += 8250_dw.o diff --git a/include/uapi/linux/serial_core.h b/include/uapi/linux/serial_core.h index 3ba34d8378bd..281fa286555c 100644 --- a/include/uapi/linux/serial_core.h +++ b/include/uapi/linux/serial_core.h @@ -207,6 +207,9 @@ /* Atheros AR933X SoC */ #define PORT_AR933X 99 +/* MCHP 16550A UART with 256 byte FIFOs */ +#define PORT_MCHP16550A 100 + /* ARC (Synopsys) on-chip UART */ #define PORT_ARC 101 From patchwork Sun Dec 11 01:47:29 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Kumaravel Thiagarajan X-Patchwork-Id: 32022 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp1306728wrr; Sat, 10 Dec 2022 05:14:40 -0800 (PST) X-Google-Smtp-Source: AA0mqf5SG2vg4SNPTqyMuvgajLmpFsPbOV63TsXeN9um/F8nVs1zT1jXd/Q/WLDYKpDJddm9FHtM X-Received: by 2002:a17:906:2ad6:b0:7ae:31a0:571c with SMTP id m22-20020a1709062ad600b007ae31a0571cmr8126251eje.57.1670678080353; Sat, 10 Dec 2022 05:14:40 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1670678080; cv=none; d=google.com; s=arc-20160816; b=xNZ1mx8e7ziZ1HqVFagjrU6i5K0tOKJ/BiJzkvV2plY/e/s5Eh6F7jYeXyB8Io0j68 fyd8lAyX1Nzbme1cj+MYTiyiYKNgbiY1NkBBcJJrDTAUvPRgxWldqVOPR+pf+K5lTHRl etNpEESQi/9+MO6F1LuBuIJNM/xCLv5XXEWhTC8q3DXrHZU6bxfIbD/padS55ilCgEBq DGElwqRbGqDTUBELMPsUANx4qsluVvynTPeOkXgcRMaKQYyVBFtO1AlUJYKV3oMQo48y UZTUoksK1FwqRYT1dENLqL1Rpx9GfS9ttmezPHVz9QlEFCjPkJqU6tVlB5mvHuy7+HkF gNIA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=BjpYkWs6HLnbdt4189do7q5Nsb1cS7uWg3yxrvFOug8=; b=SP4pCzkTcf8HBEgFWnCPi3In6v+tsznIjtS8dKEKnJFOsJezYFw/U95v3y3YIQzO64 zaNrvUoSpo05u9BWrQLtcnQYEJixpSgw4JYKg/GM9+G1HvcCG3+ntjNqUGuof9OetDkq I9Orwx+S5BfzMwMN6smbV1ez4djpSjNQh9YcBfNrneU34yiAbnq+yCIndcu1inNXaVx/ BJMAyvr5CQRL9hzkmnxg9wG+PQQFXGgKm8AlF1gLmuIgw7jzkSYDwWsOzwIucQw5NvIS 2Sc6VCQ2Le6dwElbiu3CLXp8DvZOyR9wNZY8JsYmnJ6OwxDVWY2FMUD1nAh4KqivraPh UW8w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b="DGbrMH/T"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id oz13-20020a1709077d8d00b007b863be7bb1si2693516ejc.531.2022.12.10.05.14.17; Sat, 10 Dec 2022 05:14:40 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b="DGbrMH/T"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229879AbiLJNNh (ORCPT + 99 others); Sat, 10 Dec 2022 08:13:37 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52506 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229746AbiLJNNL (ORCPT ); Sat, 10 Dec 2022 08:13:11 -0500 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 23E1BE019; Sat, 10 Dec 2022 05:13:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1670677990; x=1702213990; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=mrkqcNvltIR0FVDb8leL5+vBXxZP/C/rJqlshPmIueA=; b=DGbrMH/Tnh0OaLu2zCZiwGrLD4F0NLVAwq8w6yQPaDlKH03Gut0MeNeM 7NfneroDBQxzLVxOobZdYvJh45TaN4JpE23KlQre+tTWOqX9dgFPHLGrQ fP5A/EYMCWS2AzO2+iQ/Ha2+UAx9QMe2qC5AIOArRUi0eABmJobmLuKnm /b24LNmrsB71Y8P6ECtGN/RMym//fnZe7ceA1l4ofwjt+Na6wWdNTsQ8O bfkiiKKq748WDAyxJf6OvMNXcjA5esi2x3nnNMTeXe825zom+po46RXig qj4Vee2g9Xc6YQYLXkfOZ3hv149OtF9EJoeqvf2ktZn5XUnve87Bn6rhO Q==; X-IronPort-AV: E=Sophos;i="5.96,234,1665471600"; d="scan'208";a="191021807" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa2.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 10 Dec 2022 06:13:09 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Sat, 10 Dec 2022 06:13:09 -0700 Received: from CHE-LT-UNGSOFTWARE.microchip.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.16 via Frontend Transport; Sat, 10 Dec 2022 06:13:03 -0700 From: Kumaravel Thiagarajan To: CC: , , , , , , , , , , , , , , , , , Tharun Kumar P Subject: [PATCH v8 tty-next 3/4] serial: 8250_pci1xxxx: Add RS485 support to quad-uart driver Date: Sun, 11 Dec 2022 07:17:29 +0530 Message-ID: <20221211014730.1233272-4-kumaravel.thiagarajan@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221211014730.1233272-1-kumaravel.thiagarajan@microchip.com> References: <20221211014730.1233272-1-kumaravel.thiagarajan@microchip.com> MIME-Version: 1.0 X-Spam-Status: No, score=-1.2 required=5.0 tests=BAYES_00,DATE_IN_FUTURE_12_24, DKIMWL_WL_HIGH,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF, RCVD_IN_DNSWL_MED,SPF_HELO_PASS,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1751832938772901191?= X-GMAIL-MSGID: =?utf-8?q?1751832938772901191?= pci1xxxx uart supports RS485 mode of operation in the hardware with auto-direction control with configurable delay for releasing RTS after the transmission. This patch adds support for the RS485 mode. Co-developed-by: Tharun Kumar P Signed-off-by: Tharun Kumar P Signed-off-by: Kumaravel Thiagarajan Reviewed-by: Ilpo Järvinen --- Changes in v8: - Modified datatype of delay_in_baud_periods to u32 Changes in v7: - No Change Changes in v6: - Modified datatype of delay_in_baud_periods to u64 to avoid overflows Changes in v5: - Removed unnecessary assignments - Corrected styling issues in comments Changes in v4: - No Change Changes in v3: - Remove flags sanitization in driver which is taken care in core Changes in v2: - move pci1xxxx_rs485_config to a separate patch with pci1xxxx_rs485_supported. --- drivers/tty/serial/8250/8250_pci1xxxx.c | 50 +++++++++++++++++++++++++ 1 file changed, 50 insertions(+) diff --git a/drivers/tty/serial/8250/8250_pci1xxxx.c b/drivers/tty/serial/8250/8250_pci1xxxx.c index 05d1bd386f07..c4e44bfbd9e2 100644 --- a/drivers/tty/serial/8250/8250_pci1xxxx.c +++ b/drivers/tty/serial/8250/8250_pci1xxxx.c @@ -145,6 +145,54 @@ static void pci1xxxx_set_divisor(struct uart_port *port, unsigned int baud, port->membase + UART_BAUD_CLK_DIVISOR_REG); } +static int pci1xxxx_rs485_config(struct uart_port *port, + struct ktermios *termios, + struct serial_rs485 *rs485) +{ + u32 delay_in_baud_periods; + u32 baud_period_in_ns; + u32 mode_cfg = 0; + u32 clock_div; + + /* + * pci1xxxx's uart hardware supports only RTS delay after + * Tx and in units of bit times to a maximum of 15 + */ + if (rs485->flags & SER_RS485_ENABLED) { + mode_cfg = ADCL_CFG_EN | ADCL_CFG_PIN_SEL; + + if (!(rs485->flags & SER_RS485_RTS_ON_SEND)) + mode_cfg |= ADCL_CFG_POL_SEL; + + if (rs485->delay_rts_after_send) { + clock_div = readl(port->membase + UART_BAUD_CLK_DIVISOR_REG); + baud_period_in_ns = + FIELD_GET(BAUD_CLOCK_DIV_INT_MSK, clock_div) * + UART_BIT_SAMPLE_CNT; + delay_in_baud_periods = + rs485->delay_rts_after_send * NSEC_PER_MSEC / + baud_period_in_ns; + delay_in_baud_periods = + min_t(u32, delay_in_baud_periods, + FIELD_MAX(ADCL_CFG_RTS_DELAY_MASK)); + mode_cfg |= FIELD_PREP(ADCL_CFG_RTS_DELAY_MASK, + delay_in_baud_periods); + rs485->delay_rts_after_send = + baud_period_in_ns * delay_in_baud_periods / + NSEC_PER_MSEC; + } + } + writel(mode_cfg, port->membase + ADCL_CFG_REG); + return 0; +} + +static const struct serial_rs485 pci1xxxx_rs485_supported = { + .flags = SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND | + SER_RS485_RTS_AFTER_SEND, + .delay_rts_after_send = 1, + /* Delay RTS before send is not supported */ +}; + static int pci1xxxx_setup(struct pci1xxxx_8250 *priv, struct uart_8250_port *port, int port_idx) { @@ -155,6 +203,8 @@ static int pci1xxxx_setup(struct pci1xxxx_8250 *priv, port->port.set_termios = serial8250_do_set_termios; port->port.get_divisor = pci1xxxx_get_divisor; port->port.set_divisor = pci1xxxx_set_divisor; + port->port.rs485_config = pci1xxxx_rs485_config; + port->port.rs485_supported = pci1xxxx_rs485_supported; ret = serial8250_pci_setup_port(priv->pdev, port, 0, port_idx * 256, 0); if (ret < 0) From patchwork Sun Dec 11 01:47:30 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kumaravel Thiagarajan X-Patchwork-Id: 32024 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp1308473wrr; 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[2620:137:e000::1:20]) by mx.google.com with ESMTP id q9-20020a056402518900b00458264c2df2si4457395edd.164.2022.12.10.05.17.37; Sat, 10 Dec 2022 05:18:01 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=h0zbt7U7; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229815AbiLJNNm (ORCPT + 99 others); Sat, 10 Dec 2022 08:13:42 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52616 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229785AbiLJNNT (ORCPT ); Sat, 10 Dec 2022 08:13:19 -0500 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1FA3CEE00; Sat, 10 Dec 2022 05:13:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1670677998; x=1702213998; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=cKTLdomiXShuiVZb7T/R0fh5k4rDBEVPYzeUoRr66wQ=; b=h0zbt7U7CtDs0BwtY9I3UVzDLilZhZGv1r/1LJh+FR+Wq25AkxbVx/s7 74emvTZ1x0Ap3HXVdL98yH+e66l6JQYGYobQEewNGqwY4lO/pJmA/E5oa dn4n7qwcSboCy2UwDoXv8kAjEocevCRklZi7nBAwU+YoytTJen2eXJl6R QgpZZyCYhJY3PvH/HuPUDNoQYdw1ewVFn5gbPDszk2MZBu1X5y+/ZuFg5 sgTehCCebCcrsRXXvniIs2EymRQqYRFN4UHVgeJkp37Q7092HJFADD9jp Rg5WndnMgfpOvpogGM+kqfn3FHA1mqjvHvFT+5Clyw6/lnX7vbCnQGt/e w==; X-IronPort-AV: E=Sophos;i="5.96,234,1665471600"; d="scan'208";a="187511491" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa4.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 10 Dec 2022 06:13:17 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Sat, 10 Dec 2022 06:13:17 -0700 Received: from CHE-LT-UNGSOFTWARE.microchip.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.16 via Frontend Transport; Sat, 10 Dec 2022 06:13:11 -0700 From: Kumaravel Thiagarajan To: CC: , , , , , , , , , , , , , , , , , Tharun Kumar P Subject: [PATCH v8 tty-next 4/4] serial: 8250_pci1xxxx: Add power management functions to quad-uart driver Date: Sun, 11 Dec 2022 07:17:30 +0530 Message-ID: <20221211014730.1233272-5-kumaravel.thiagarajan@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221211014730.1233272-1-kumaravel.thiagarajan@microchip.com> References: <20221211014730.1233272-1-kumaravel.thiagarajan@microchip.com> MIME-Version: 1.0 X-Spam-Status: No, score=-1.2 required=5.0 tests=BAYES_00,DATE_IN_FUTURE_12_24, DKIMWL_WL_HIGH,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF, RCVD_IN_DNSWL_MED,SPF_HELO_PASS,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1751833149709076790?= X-GMAIL-MSGID: =?utf-8?q?1751833149709076790?= pci1xxxx's quad-uart function has the capability to wake up UART from suspend state. Enable wakeup before entering into suspend and disable wakeup on resume. Co-developed-by: Tharun Kumar P Signed-off-by: Tharun Kumar P Signed-off-by: Kumaravel Thiagarajan --- Changes in v8: - No Change Changes in v7: - No Change Changes in v6: - No Change Changes in v5: - Corrected commit message Changes in v4: - No Change Changes in v3: - Handled race condition in suspend and resume callbacks Changes in v2: - Use DEFINE_SIMPLE_DEV_PM_OPS instead of SIMPLE_DEV_PM_OPS. - Use pm_sleep_ptr instead of CONFIG_PM_SLEEP. - Change the return data type of pci1xxxx_port_suspend to bool from int. --- drivers/tty/serial/8250/8250_pci1xxxx.c | 115 ++++++++++++++++++++++++ 1 file changed, 115 insertions(+) diff --git a/drivers/tty/serial/8250/8250_pci1xxxx.c b/drivers/tty/serial/8250/8250_pci1xxxx.c index c4e44bfbd9e2..2dffa1b1f148 100644 --- a/drivers/tty/serial/8250/8250_pci1xxxx.c +++ b/drivers/tty/serial/8250/8250_pci1xxxx.c @@ -193,6 +193,116 @@ static const struct serial_rs485 pci1xxxx_rs485_supported = { /* Delay RTS before send is not supported */ }; +static bool pci1xxxx_port_suspend(int line) +{ + struct uart_8250_port *up = serial8250_get_port(line); + struct uart_port *port = &up->port; + struct tty_port *tport = &port->state->port; + unsigned long flags; + bool ret = false; + u8 wakeup_mask; + + mutex_lock(&tport->mutex); + if (port->suspended == 0 && port->dev) { + wakeup_mask = readb(up->port.membase + UART_WAKE_MASK_REG); + + spin_lock_irqsave(&port->lock, flags); + port->mctrl &= ~TIOCM_OUT2; + port->ops->set_mctrl(port, port->mctrl); + spin_unlock_irqrestore(&port->lock, flags); + + ret = (wakeup_mask & UART_WAKE_SRCS) != UART_WAKE_SRCS; + } + + writeb(UART_WAKE_SRCS, port->membase + UART_WAKE_REG); + mutex_unlock(&tport->mutex); + + return ret; +} + +static void pci1xxxx_port_resume(int line) +{ + struct uart_8250_port *up = serial8250_get_port(line); + struct uart_port *port = &up->port; + struct tty_port *tport = &port->state->port; + unsigned long flags; + + mutex_lock(&tport->mutex); + writeb(UART_BLOCK_SET_ACTIVE, port->membase + UART_ACTV_REG); + writeb(UART_WAKE_SRCS, port->membase + UART_WAKE_REG); + + if (port->suspended == 0) { + spin_lock_irqsave(&port->lock, flags); + port->mctrl |= TIOCM_OUT2; + port->ops->set_mctrl(port, port->mctrl); + spin_unlock_irqrestore(&port->lock, flags); + } + mutex_unlock(&tport->mutex); +} + +static int pci1xxxx_suspend(struct device *dev) +{ + struct pci1xxxx_8250 *priv = dev_get_drvdata(dev); + struct pci_dev *pcidev = to_pci_dev(dev); + bool wakeup = false; + unsigned int data; + void __iomem *p; + int i; + + for (i = 0; i < priv->nr; i++) { + if (priv->line[i] >= 0) { + serial8250_suspend_port(priv->line[i]); + wakeup |= pci1xxxx_port_suspend(priv->line[i]); + } + } + + p = pci_ioremap_bar(pcidev, 0); + if (!p) { + dev_err(dev, "remapping of bar 0 memory failed"); + return -ENOMEM; + } + + data = readl(p + UART_RESET_REG); + writel(data | UART_RESET_D3_RESET_DISABLE, p + UART_RESET_REG); + + if (wakeup) + writeb(UART_PCI_CTRL_D3_CLK_ENABLE, p + UART_PCI_CTRL_REG); + + iounmap(p); + device_set_wakeup_enable(dev, true); + pci_wake_from_d3(pcidev, true); + + return 0; +} + +static int pci1xxxx_resume(struct device *dev) +{ + struct pci1xxxx_8250 *priv = dev_get_drvdata(dev); + struct pci_dev *pcidev = to_pci_dev(dev); + unsigned int data; + void __iomem *p; + int i; + + p = pci_ioremap_bar(pcidev, 0); + if (!p) { + dev_err(dev, "remapping of bar 0 memory failed"); + return -ENOMEM; + } + + data = readl(p + UART_RESET_REG); + writel(data & ~UART_RESET_D3_RESET_DISABLE, p + UART_RESET_REG); + iounmap(p); + + for (i = 0; i < priv->nr; i++) { + if (priv->line[i] >= 0) { + pci1xxxx_port_resume(priv->line[i]); + serial8250_resume_port(priv->line[i]); + } + } + + return 0; +} + static int pci1xxxx_setup(struct pci1xxxx_8250 *priv, struct uart_8250_port *port, int port_idx) { @@ -363,6 +473,8 @@ static void pci1xxxx_serial_remove(struct pci_dev *dev) } } +static DEFINE_SIMPLE_DEV_PM_OPS(pci1xxxx_pm_ops, pci1xxxx_suspend, pci1xxxx_resume); + static const struct pci_device_id pci1xxxx_pci_tbl[] = { { PCI_DEVICE(PCI_VENDOR_ID_EFAR, PCI_DEVICE_ID_EFAR_PCI11010) }, { PCI_DEVICE(PCI_VENDOR_ID_EFAR, PCI_DEVICE_ID_EFAR_PCI11101) }, @@ -377,6 +489,9 @@ static struct pci_driver pci1xxxx_pci_driver = { .name = "pci1xxxx serial", .probe = pci1xxxx_serial_probe, .remove = pci1xxxx_serial_remove, + .driver = { + .pm = pm_sleep_ptr(&pci1xxxx_pm_ops), + }, .id_table = pci1xxxx_pci_tbl, }; module_pci_driver(pci1xxxx_pci_driver);