From patchwork Fri Dec 9 15:04:35 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 31808 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp829345wrr; Fri, 9 Dec 2022 07:08:02 -0800 (PST) X-Google-Smtp-Source: AA0mqf4a3wd59tYdH72fTO+kDauYVOg8dEIrRjSxlEwa3ZKNeIivKHzx1OL4EV7kn8cI0nIh2BCW X-Received: by 2002:a17:902:b282:b0:189:efe8:1e with SMTP id u2-20020a170902b28200b00189efe8001emr6425324plr.68.1670598481740; Fri, 09 Dec 2022 07:08:01 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1670598481; cv=none; d=google.com; s=arc-20160816; b=DS8yBruXV3iHcA4GLdvpZEONkK4rnfOW5ch1+U4uRohLrUGpKxLz9QMJAgP2eRMp99 zIk72a6t/auyqQDrQy1OnBkf2SuTASG7br29Wo6DzPDN9Wnn2rsygknYyRdXYgMMRzD9 F/vFyKZjHSotDkXFhkKnjyfeanTBXVAmrWT8k+hp75p+6kBu60HHXekKnC2jUnQp/G0e d9tpYvuLiR/5OZdpolmSUGwPviSe6UAiBpCk/d/oR8FyuxPSh2aGl9NojpmC1GopVNOx TYF3/V0I05esefZxEqgGgRBky32Tyd/x6MbezEdS4OmMR/3GEg7uGKr2IYSw2cs3G+RG VbJw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:feedback-id:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from; bh=4WprwKT0QVbWicmJEJaEsVb+uaZy35nruhoEX4mlQLE=; b=slayjMWAvCJj0KvTvJuKA2lrbMbxjK54T0OBJkepdF8+VD2XC3UtAmvliNAaFnyd6Z QjexnCw1LTbAEqU75ZVxxloA6/JpqXAkWQgo3deBHytezMkyoYhjsi3Dp5YKbPrhfNrG OCiLELyEWPy5ibENSXAtz7kSR3WhYbrVXoRyTqi8VH/QKZf9aJF9nUPa8/ylEy4GK6Zy WxuFEkgdwXCf7YDjjSymtWMZ35H6NZSBtH5BlsaN+KAf0NGjosByFKSHiO5EWOdG92Qr Uf/2m4ifb5Ny6vrBi2WctyZCryMi0FklK8nK3vbz3A2gxKjhxrcknXMt6LAkZRpL9Guq Sp7A== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. 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( [111.196.135.79]) by bizesmtp.qq.com (ESMTP) with id ; Fri, 09 Dec 2022 23:04:41 +0800 (CST) X-QQ-SSF: 01200000002000B0C000B00A0000000 X-QQ-FEAT: znfcQSa1hKZEkVEo5KsJPnztRM+YmWhuMP5lhz0A261j6bY6bsUz696ZFniYc IU03XC1wSi2mTpJ4Oj7Nff0Mv/eMawGUQSZLZVoQMPCrpyyWZ45AOCUMkImiFB7XXhf4GPo a4C1mosVhQKwwMj2rbWMSAz4HZoPpkuO2pn1BK3GOMlRTHgOhhbziFZ3fgK1f8z25438B/v NhmUnGbLWn6VF9J+Oa6QZvy/nu/rKuzaAkhseY4+t0ypw7NT/Yqhovc9tG3jynzpXmE6+6g NG4Qoz10dv3AG5/zN4SQRBb1AmUEmB+TLgvJnFXYCmlwI3Dghgs3w87u62UiIMuchUdvmWt FOONZXRgMzi5ce4r0xcY4MuIdqC031oicLhrpoGk00mYjUHVWk= X-QQ-GoodBg: 0 From: Bin Meng To: linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, linux-serial@vger.kernel.org Cc: Catalin Marinas , Greg Kroah-Hartman , Jiri Slaby , Russell King , Will Deacon , linux-arm-kernel@lists.infradead.org Subject: [PATCH v3 1/3] serial: earlycon-arm-semihost: Move smh_putc() variants in respective arch's semihost.h Date: Fri, 9 Dec 2022 23:04:35 +0800 Message-Id: <20221209150437.795918-2-bmeng@tinylab.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221209150437.795918-1-bmeng@tinylab.org> References: <20221209150437.795918-1-bmeng@tinylab.org> MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:tinylab.org:qybglogicsvr:qybglogicsvr3 X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,RCVD_IN_MSPIKE_H2, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1751749473433652050?= X-GMAIL-MSGID: =?utf-8?q?1751749473433652050?= Move smh_putc() variants in respective arch/*/include/asm/semihost.h, in preparation to add RISC-V support. Signed-off-by: Bin Meng --- Changes in v3: - add #ifdef in the header to prevent from multiple inclusion - add forward-declare struct uart_port Changes in v2: - new patch: "serial: earlycon-arm-semihost: Move smh_putc() variants in respective arch's semihost.h" arch/arm/include/asm/semihost.h | 30 ++++++++++++++++++++++ arch/arm64/include/asm/semihost.h | 24 +++++++++++++++++ drivers/tty/serial/earlycon-arm-semihost.c | 25 +----------------- 3 files changed, 55 insertions(+), 24 deletions(-) create mode 100644 arch/arm/include/asm/semihost.h create mode 100644 arch/arm64/include/asm/semihost.h diff --git a/arch/arm/include/asm/semihost.h b/arch/arm/include/asm/semihost.h new file mode 100644 index 000000000000..f365787e7c23 --- /dev/null +++ b/arch/arm/include/asm/semihost.h @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2012 ARM Ltd. + * Author: Marc Zyngier + * + * Adapted for ARM and earlycon: + * Copyright (C) 2014 Linaro Ltd. + * Author: Rob Herring + */ + +#ifndef _ARM_SEMIHOST_H_ +#define _ARM_SEMIHOST_H_ + +#ifdef CONFIG_THUMB2_KERNEL +#define SEMIHOST_SWI "0xab" +#else +#define SEMIHOST_SWI "0x123456" +#endif + +struct uart_port; + +static inline void smh_putc(struct uart_port *port, unsigned char c) +{ + asm volatile("mov r1, %0\n" + "mov r0, #3\n" + "svc " SEMIHOST_SWI "\n" + : : "r" (&c) : "r0", "r1", "memory"); +} + +#endif /* _ARM_SEMIHOST_H_ */ diff --git a/arch/arm64/include/asm/semihost.h b/arch/arm64/include/asm/semihost.h new file mode 100644 index 000000000000..87e353dab868 --- /dev/null +++ b/arch/arm64/include/asm/semihost.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2012 ARM Ltd. + * Author: Marc Zyngier + * + * Adapted for ARM and earlycon: + * Copyright (C) 2014 Linaro Ltd. + * Author: Rob Herring + */ + +#ifndef _ARM64_SEMIHOST_H_ +#define _ARM64_SEMIHOST_H_ + +struct uart_port; + +static inline void smh_putc(struct uart_port *port, unsigned char c) +{ + asm volatile("mov x1, %0\n" + "mov x0, #3\n" + "hlt 0xf000\n" + : : "r" (&c) : "x0", "x1", "memory"); +} + +#endif /* _ARM64_SEMIHOST_H_ */ diff --git a/drivers/tty/serial/earlycon-arm-semihost.c b/drivers/tty/serial/earlycon-arm-semihost.c index fcdec5f42376..e4692a8433f9 100644 --- a/drivers/tty/serial/earlycon-arm-semihost.c +++ b/drivers/tty/serial/earlycon-arm-semihost.c @@ -11,30 +11,7 @@ #include #include #include - -#ifdef CONFIG_THUMB2_KERNEL -#define SEMIHOST_SWI "0xab" -#else -#define SEMIHOST_SWI "0x123456" -#endif - -/* - * Semihosting-based debug console - */ -static void smh_putc(struct uart_port *port, unsigned char c) -{ -#ifdef CONFIG_ARM64 - asm volatile("mov x1, %0\n" - "mov x0, #3\n" - "hlt 0xf000\n" - : : "r" (&c) : "x0", "x1", "memory"); -#else - asm volatile("mov r1, %0\n" - "mov r0, #3\n" - "svc " SEMIHOST_SWI "\n" - : : "r" (&c) : "r0", "r1", "memory"); -#endif -} +#include static void smh_write(struct console *con, const char *s, unsigned n) { From patchwork Fri Dec 9 15:04:36 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 31810 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp830860wrr; Fri, 9 Dec 2022 07:10:16 -0800 (PST) X-Google-Smtp-Source: AA0mqf5tEFeXZEfG3PqrkPWyzxU6A4qWF6BCyYTJ3O+Rb8PvFqY+5MoHVzq9ZQU6Ao1Vv7vTYBNz X-Received: by 2002:a05:6a20:c18a:b0:9d:efc0:8d with SMTP id bg10-20020a056a20c18a00b0009defc0008dmr8258207pzb.53.1670598615777; Fri, 09 Dec 2022 07:10:15 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1670598615; cv=none; d=google.com; s=arc-20160816; b=jRbDOmPaLU0GCxgX/qUH43hr6gdyLK7uKExmZ0GEySYaZ4dXP504xf7OQNdLC+FH38 bu80XuHePPo5Qkq6miu5i6BWRck3KVDO3vEmmq++z27ixf8zTUyNJ8EBWzYPWSiP/wsX 0e4BbPNkBWnURHLSKmh4KdygA+3EjuPgbOhF/3T6fKGK2pkwU8LMzAGhFm5khWSuNsFV GAF2PQPO2fkqBiJOUxZOZYhKMASpVSbO012UBrr7dbbQNotYQaIlxvZVRpvyhiEHGisd /qq7eDVXcdCf/u40lp5BTZn8L2hfHVPWBtT7CU984o1Rb+ekNtEbCQk5mhCIEDqI9yHt ivhw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:feedback-id:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from; bh=D6jvOglZ10kS7auLRqcoWq8Q52TLaM2Tl0YT9hi0HdQ=; b=f4BlwZV9z+tfjRv2L14XQI1lUzs2NOKcfvzCRH6uTRCWhhrS4ZcrIHxVMmXqw5+Duy Kknf54IoUMv2C6jffw76hO3Z6XqyzBBHGkYUV7zoBEhDMTRgp0XZoIhxqSwoG9zd7HV7 fDkVrq3rzgM8e/fa7bwl4lyyStqXxfbnDa5KcpJaOwLDIvd55NBZX6ZOA+penZCPTd5H gZP5/VxnqrS9dPCi56oKl3T8rieIw+H7dFn2ArVj1jo5LN/Va2uP92V/ZA4D5Kre7irY qKeH2XVKqU6ixHsOTpAHz1LVPKA1H80qPMPhDuuQAFGSydUcOPyD9R0AtiBWVKPF7IzR 0wOg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. 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( [111.196.135.79]) by bizesmtp.qq.com (ESMTP) with id ; Fri, 09 Dec 2022 23:04:44 +0800 (CST) X-QQ-SSF: 01200000002000B0C000B00A0000000 X-QQ-FEAT: eSZ1CZgv+JDxI3bkYMKbTdjkw3HK7jXPhTCSg7Rm3gGAzVEQh3qZVDk772x62 RcnlQ3TCDQBKpL4HEXYtAYBq+s10VpGHenajCYPlmnRYkDW1cCyvU28bP3dGoFJzt/NnAAi 9pbziDhkypc8rcrRB2SXSoQ9okkCAjY0JDno58pfyZqblYWybP98pprywYy6WnA30twSSkk HtUjsUs0pEf3XziNrqPZPNwjWhRxgNggsCplY7mQcxnOAKQawZmsOycyzYMOeAirqYRIVT6 f0vj/eey25M+7iykhR5ifMsDFZiAAyU+ULt91TPKJ7Y3MhD+QWQEG0xfqPE7M5sWLXpuFjU BkP38Blu5oPle1WhiJqDtKkDcUCCyCD7fzWHdV0BNU0Wonfe/4= X-QQ-GoodBg: 0 From: Bin Meng To: linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, linux-serial@vger.kernel.org Cc: Albert Ou , Greg Kroah-Hartman , Jiri Slaby , Palmer Dabbelt , Paul Walmsley Subject: [PATCH v3 2/3] riscv: Implement semihost.h for earlycon semihost driver Date: Fri, 9 Dec 2022 23:04:36 +0800 Message-Id: <20221209150437.795918-3-bmeng@tinylab.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221209150437.795918-1-bmeng@tinylab.org> References: <20221209150437.795918-1-bmeng@tinylab.org> MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:tinylab.org:qybglogicsvr:qybglogicsvr3 X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,RCVD_IN_MSPIKE_H2, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1751749614209776172?= X-GMAIL-MSGID: =?utf-8?q?1751749614209776172?= Per RISC-V semihosting spec [1], implement semihost.h for the existing Arm semihosting earlycon driver to work on RISC-V. Link: https://github.com/riscv/riscv-semihosting-spec/blob/main/riscv-semihosting-spec.adoc [1] Signed-off-by: Bin Meng --- Changes in v3: - add #ifdef in the header to prevent from multiple inclusion - add forward-declare struct uart_port - add a Link tag in the commit message Changes in v2: - Move the RISC-V implementation to semihost.h arch/riscv/include/asm/semihost.h | 26 ++++++++++++++++++++++++++ drivers/tty/serial/Kconfig | 2 +- 2 files changed, 27 insertions(+), 1 deletion(-) create mode 100644 arch/riscv/include/asm/semihost.h diff --git a/arch/riscv/include/asm/semihost.h b/arch/riscv/include/asm/semihost.h new file mode 100644 index 000000000000..557a34938193 --- /dev/null +++ b/arch/riscv/include/asm/semihost.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2022 tinylab.org + * Author: Bin Meng + */ + +#ifndef _RISCV_SEMIHOST_H_ +#define _RISCV_SEMIHOST_H_ + +struct uart_port; + +static inline void smh_putc(struct uart_port *port, unsigned char c) +{ + asm volatile("addi a1, %0, 0\n" + "addi a0, zero, 3\n" + ".balign 16\n" + ".option push\n" + ".option norvc\n" + "slli zero, zero, 0x1f\n" + "ebreak\n" + "srai zero, zero, 0x7\n" + ".option pop\n" + : : "r" (&c) : "a0", "a1", "memory"); +} + +#endif /* _RISCV_SEMIHOST_H_ */ diff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig index 434f83168546..e94d1265151c 100644 --- a/drivers/tty/serial/Kconfig +++ b/drivers/tty/serial/Kconfig @@ -75,7 +75,7 @@ config SERIAL_AMBA_PL011_CONSOLE config SERIAL_EARLYCON_ARM_SEMIHOST bool "Early console using ARM semihosting" - depends on ARM64 || ARM + depends on ARM64 || ARM || RISCV select SERIAL_CORE select SERIAL_CORE_CONSOLE select SERIAL_EARLYCON From patchwork Fri Dec 9 15:04:37 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 31812 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp832426wrr; Fri, 9 Dec 2022 07:12:49 -0800 (PST) X-Google-Smtp-Source: AA0mqf4kVjHYl6Zbeg0jD3ha3Vd81v1UVv80k2NNTC636D4Co2WhGrdZ5mMM/HKfoJ8KPJGDB65b X-Received: by 2002:a17:903:260d:b0:189:6ab3:9e64 with SMTP id jd13-20020a170903260d00b001896ab39e64mr6573297plb.34.1670598769557; Fri, 09 Dec 2022 07:12:49 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1670598769; cv=none; d=google.com; s=arc-20160816; b=wg03QjD2sOq3zDp8rCAWq++pzz6pT6O+rNWChkiSKbW2eCE19mB+9klLlqMJ/JlmmO IZQmpnXHqyhSWV51728Li8el+8jkS/JcCU7O12HL1ruaUhp5GKGOvcfZitUcq5XahcgN 4XGd+k6WbZ8TC5/AX6qd4HJvbMbb7/3VUBz2fkN/L1yWUxaZ82LBzcMvohmAgAOhV66S IzdcMB9T5wFr+aTUjpKYOZPa5z1q+3+kyzOMPUdG5PYw6ol5VDWAEBnNM+H9P1ohSH5I khGzC8EjIAlA3qPp4pNbVEUEF7SBgLZHS0zv72PJCBUYHPOqss80a5IhOXp43AMymg2D HAxQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:feedback-id:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from; bh=s6ALYND/IPX0ndZNPugEnkt+c8H7XD+usIJXgCmz6HQ=; b=OwFhDsHAGTPXKPZve7sUNuGE951oGj47rA5rp19UQvNqGc1Qjsus6kP1yv+DFF0kUb ivHhol17akMvVHqdbtqRzIBx0Ukm7ZdS9UcJk/v2O6epjXCGzFPgkWEwJZkSP2cMWfyq 7VoGPJfB6PLSWm2IZsDq2cfvIdv2CwyFUSmnErGj0jKJgprewc4r9pGHEaYG3PB7M3n3 g8AyiEzBYRmtzJX5KxdzDrZlxGVjGKuoBt++vNgm3ad9Qb2hz4cIpmBPdqAnrdQwqY0L nMJCqPfGEsS9iZfx8tpOoU8JQidOiaq2Tru4R9VeP0fjz26oMZL/nGMFSxqkjRd1wyiE 1j5w== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. 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( [111.196.135.79]) by bizesmtp.qq.com (ESMTP) with id ; Fri, 09 Dec 2022 23:04:47 +0800 (CST) X-QQ-SSF: 01200000002000B0C000B00A0000000 X-QQ-FEAT: ILHsT53NKPjG5kfsWPlb/E4DO94OjvdDf9wn6ttYvvCNpDY9/TDM9Ur27ag7K a+Ax5aohk1b980KZ412GaxQBoChRTv+AMSpc0cjPxse+3RraLnlsCU639j5CVj+BPHJJori Vbt2DGkCowbiBYA8NLOLGZJx6Z4e+EsHC6q48OfHeGuT3aDyUXYLgD5QC9lojnGNJv5HnnM kx7xPEIQBZTjAEoA3RfLlTZr/mtVCE+AO/IG0Kgu7uyUxaFrmX+6fDEebWyg5ObPm4nKRfs 4sjlFW1iSHbVdyKJ+YuUNwEmbLfyVO/HuUj/iS7HnGCJuh+m8uyEXkwmL1/sKtrr5peQ3iT v2BAZ+mqbzzGar3pYaRaxGHVuiPBILmUZyoUiia X-QQ-GoodBg: 0 From: Bin Meng To: linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, linux-serial@vger.kernel.org Cc: Greg Kroah-Hartman , Jiri Slaby Subject: [PATCH v3 3/3] serial: Rename earlycon semihost driver Date: Fri, 9 Dec 2022 23:04:37 +0800 Message-Id: <20221209150437.795918-4-bmeng@tinylab.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221209150437.795918-1-bmeng@tinylab.org> References: <20221209150437.795918-1-bmeng@tinylab.org> MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:tinylab.org:qybglogicsvr:qybglogicsvr3 X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,RCVD_IN_MSPIKE_H2, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1751749775072550540?= X-GMAIL-MSGID: =?utf-8?q?1751749775072550540?= Now that earlycon semihost driver works on RISC-V too, let's use a much more generic name for the driver. Signed-off-by: Bin Meng --- (no changes since v1) drivers/tty/serial/Kconfig | 12 ++++++------ drivers/tty/serial/Makefile | 2 +- .../{earlycon-arm-semihost.c => earlycon-semihost.c} | 0 3 files changed, 7 insertions(+), 7 deletions(-) rename drivers/tty/serial/{earlycon-arm-semihost.c => earlycon-semihost.c} (100%) diff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig index e94d1265151c..a3779472edf6 100644 --- a/drivers/tty/serial/Kconfig +++ b/drivers/tty/serial/Kconfig @@ -73,17 +73,17 @@ config SERIAL_AMBA_PL011_CONSOLE your boot loader (lilo or loadlin) about how to pass options to the kernel at boot time.) -config SERIAL_EARLYCON_ARM_SEMIHOST - bool "Early console using ARM semihosting" +config SERIAL_EARLYCON_SEMIHOST + bool "Early console using Arm compatible semihosting" depends on ARM64 || ARM || RISCV select SERIAL_CORE select SERIAL_CORE_CONSOLE select SERIAL_EARLYCON help - Support for early debug console using ARM semihosting. This enables - the console before standard serial driver is probed. This is enabled - with "earlycon=smh" on the kernel command line. The console is - enabled when early_param is processed. + Support for early debug console using Arm compatible semihosting. + This enables the console before standard serial driver is probed. + This is enabled with "earlycon=smh" on the kernel command line. + The console is enabled when early_param is processed. config SERIAL_EARLYCON_RISCV_SBI bool "Early console using RISC-V SBI" diff --git a/drivers/tty/serial/Makefile b/drivers/tty/serial/Makefile index 238a9557b487..cd9afd9e3018 100644 --- a/drivers/tty/serial/Makefile +++ b/drivers/tty/serial/Makefile @@ -6,7 +6,7 @@ obj-$(CONFIG_SERIAL_CORE) += serial_core.o obj-$(CONFIG_SERIAL_EARLYCON) += earlycon.o -obj-$(CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST) += earlycon-arm-semihost.o +obj-$(CONFIG_SERIAL_EARLYCON_SEMIHOST) += earlycon-semihost.o obj-$(CONFIG_SERIAL_EARLYCON_RISCV_SBI) += earlycon-riscv-sbi.o # These Sparc drivers have to appear before others such as 8250 diff --git a/drivers/tty/serial/earlycon-arm-semihost.c b/drivers/tty/serial/earlycon-semihost.c similarity index 100% rename from drivers/tty/serial/earlycon-arm-semihost.c rename to drivers/tty/serial/earlycon-semihost.c