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[95.49.125.53]) by smtp.gmail.com with ESMTPSA id bi35-20020a0565120ea300b004ac6a444b26sm3466428lfb.141.2022.12.08.12.14.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 08 Dec 2022 12:14:11 -0800 (PST) From: Konrad Dybcio To: linux-arm-msm@vger.kernel.org, andersson@kernel.org, agross@kernel.org, krzysztof.kozlowski@linaro.org Cc: patches@linaro.org, Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Iskren Chernev , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 1/5] arm64: dts: qcom: sm6115: Fix UFS node Date: Thu, 8 Dec 2022 21:13:57 +0100 Message-Id: <20221208201401.530555-1-konrad.dybcio@linaro.org> X-Mailer: git-send-email 2.38.1 MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1751678658760538672?= X-GMAIL-MSGID: =?utf-8?q?1751678658760538672?= In its current form, UFS did not even probe successfully - it failed when trying to set XO (ref_clk) to 300 MHz instead of doing so to the ICE clk. Moreover, the missing reg-names prevented ICE from working or being discovered at all. Fix both of these issues. As a sidenote, the log reveals that this SoC uses UFS ICE v3.1.0. Fixes: 97e563bf5ba1 ("arm64: dts: qcom: sm6115: Add basic soc dtsi") Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sm6115.dtsi | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qcom/sm6115.dtsi index 572bf04adf90..3f4017bc667d 100644 --- a/arch/arm64/boot/dts/qcom/sm6115.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi @@ -704,6 +704,7 @@ opp-202000000 { ufs_mem_hc: ufs@4804000 { compatible = "qcom,sm6115-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; reg = <0x04804000 0x3000>, <0x04810000 0x8000>; + reg-names = "std", "ice"; interrupts = ; phys = <&ufs_mem_phy_lanes>; phy-names = "ufsphy"; @@ -736,10 +737,10 @@ ufs_mem_hc: ufs@4804000 { <0 0>, <0 0>, <37500000 150000000>, - <75000000 300000000>, <0 0>, <0 0>, - <0 0>; + <0 0>, + <75000000 300000000>; status = "disabled"; }; From patchwork Thu Dec 8 20:13:58 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 31485 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp404570wrr; Thu, 8 Dec 2022 12:20:49 -0800 (PST) X-Google-Smtp-Source: AA0mqf7VMtyLvXq9AjJaDXV+LWVJ17UVIWdyA3vXJfD/Voa4SP4AsP2KVJuAsU8E8BrogQbxaZRu X-Received: by 2002:a05:6402:370d:b0:462:1a67:75ef with SMTP id ek13-20020a056402370d00b004621a6775efmr67348532edb.16.1670530849430; Thu, 08 Dec 2022 12:20:49 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1670530849; cv=none; d=google.com; s=arc-20160816; b=KVfzkq1V/MNUnSSRZlYPYviovrGj/DLr//u48f85wxinysvEtU11Qpud0Bl3kqQhuX EuYwXzW1fVtb7xrYv9h+1+xa/g8Oe+JtAE10zB1zKONk9kxgDwhNil6vA5EJqzTiWdWQ okU3Xcvp3Ja/MhlrqDrJxxK+bRnjrmFR3acvpTm88fLZZzSlA1dGzlVTWE2Blx3+NS09 9SYhFWxwBjz1A0N90EnkKZvZrjP+J6JAyB2S9UhSF4mh9+KexSTsoyGkAFDTjy7w+Ft2 MLLYft36U6V2KPTFLSwGg2RdwFLSvVS+FW2lGEDQ7y0ThfyWfyXnvBw7aZuuFvNOcqnu XRzQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=4naixU0W2mwEQuuHUmas2VUjFasO06w6Uoh0J7hj7Xs=; b=YoXVWccjitnNvpnuFpMdzk7c++N3QwYRIA8amCK0fyEKgSaDQ0t6SQXiw6PZDVbork py4QsdKju/lC/3N4zsfJe+kQmA/3za1XW6wr8CieIc2VywVQizavlnCvXR9fB73kK1Ww FwGylZZpX8rqMREljTkL0QdX5lHHCBIkBVWkxYG99YyhG//aS4hU9ueUpuBFOh7r5Sg7 y8Z6R/qOeicqSBPUJ5Ptuuqw0/tzyiHPRKW9nEwIXn5kEHJak/wG7WljRhZt5hXxLYHF jlYskMDcu2Xdzk92rKqtPaCKq7mqNi0ZH1RqZaIRKg/eZ8wsoO0iDdlBRZKIA8czt/SC ZsCw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=AwwRLN88; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. 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[95.49.125.53]) by smtp.gmail.com with ESMTPSA id bi35-20020a0565120ea300b004ac6a444b26sm3466428lfb.141.2022.12.08.12.14.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 08 Dec 2022 12:14:13 -0800 (PST) From: Konrad Dybcio To: linux-arm-msm@vger.kernel.org, andersson@kernel.org, agross@kernel.org, krzysztof.kozlowski@linaro.org Cc: patches@linaro.org, Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Iskren Chernev , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Adam Skladowski Subject: [PATCH 2/5] arm64: dts: qcom: sm6115: Provide xo clk to rpmcc Date: Thu, 8 Dec 2022 21:13:58 +0100 Message-Id: <20221208201401.530555-2-konrad.dybcio@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221208201401.530555-1-konrad.dybcio@linaro.org> References: <20221208201401.530555-1-konrad.dybcio@linaro.org> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1751678555855696191?= X-GMAIL-MSGID: =?utf-8?q?1751678555855696191?= rpmcc used to rely on global clock lookup (and still does so for backwards compat reasons) of "xo_board", which was common back when we did not care about things like underscores in node names. Nowadays it expects to be fed a reference to the fixed clock. Satisfy that requirement to make sure rpm clock rates are not all stuck at zero. Fixes: 97e563bf5ba1 ("arm64: dts: qcom: sm6115: Add basic soc dtsi") Reported-by: Adam Skladowski Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sm6115.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qcom/sm6115.dtsi index 3f4017bc667d..81523ab7ff60 100644 --- a/arch/arm64/boot/dts/qcom/sm6115.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi @@ -296,6 +296,8 @@ rpm_requests: rpm-requests { rpmcc: clock-controller { compatible = "qcom,rpmcc-sm6115", "qcom,rpmcc"; + clocks = <&xo_board>; + clock-names = "xo"; #clock-cells = <1>; }; From patchwork Thu Dec 8 20:13:59 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 31486 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp404968wrr; Thu, 8 Dec 2022 12:21:52 -0800 (PST) X-Google-Smtp-Source: AA0mqf4lZF2lLTVzaYs89z1yYwJtuvnQCGUQGxOKj8+DMXO4WpK+vifjJyI8uLtKCt72Sent0OXd X-Received: by 2002:aa7:c548:0:b0:46d:cf59:c3df with SMTP id s8-20020aa7c548000000b0046dcf59c3dfmr162884edr.388.1670530912533; Thu, 08 Dec 2022 12:21:52 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1670530912; cv=none; d=google.com; s=arc-20160816; b=TMUirnV0DBEeX2c41m3jRQIYXSQ/TBSgFkjMwFZAPD1l9MWzajKIqfKrFsveWO6CEe wcY0QbAdcYx5yj5LHnrkS7E4IVRmyLdrqE9zcW1nfn2H7HaSGcBLPmm7TcJRGzqu9SxM dPkBhW+sdd1gX0ZwIvA47cxgP6ow4I6419oRDqkhcYK5ta7K4p5dUJEkAXzse/UtcepW JoZlz1ibEcSy/FCVXcOAI925yvQ454DZBgMELKQKO1FzAGAPNIJdFKqEvCTu6mjb58++ bkpj8NA5FYdqVnG6+Crh+hx37WFF2j54cLSV09WwLV6qrGHKIln3Rw5K9yoO4WA+yoVp pn7A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=qU1DfEK+semHpOcnJabZifeAfzgBN5cQVOW2r9R0JGg=; b=jDJ5Z+ZLdUZK2mtjSTxsJEfyLUaLwthlz08hCxeIas5DSc99wzv8U/NTKYDXNeTmVI BIMImW1CJ1sSqlNZqdh5r5eJIV4Fm9fvP57Xm8XV1NFtdii9OWI6uEYZzF5GEjqcQNxX BXch/nWNTNRk3YK/9aKnOVyKifHN6sEUQaB+Z+Nc1dH0RI33S1MWDQKNR9Dbd91b+McL IasUn8zLrP06MYbziKBqccnkh9CyU+YlgzMOyZjkLt6Tp7Lp+OH+RR0nDI5xrsW0DrsO Mxa8h79c2frRPm/nEpUjjc6jorgq8Tug989RaAu8FFL0aS+QURHl9A9/dLNPCVzXHgPa vakg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ter0SaBg; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. 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[95.49.125.53]) by smtp.gmail.com with ESMTPSA id bi35-20020a0565120ea300b004ac6a444b26sm3466428lfb.141.2022.12.08.12.14.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 08 Dec 2022 12:14:16 -0800 (PST) From: Konrad Dybcio To: linux-arm-msm@vger.kernel.org, andersson@kernel.org, agross@kernel.org, krzysztof.kozlowski@linaro.org Cc: patches@linaro.org, Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Iskren Chernev , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 3/5] arm64: dts: qcom: sm6115: Provide real SMD RPM XO to SDC1/2 Date: Thu, 8 Dec 2022 21:13:59 +0100 Message-Id: <20221208201401.530555-3-konrad.dybcio@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221208201401.530555-1-konrad.dybcio@linaro.org> References: <20221208201401.530555-1-konrad.dybcio@linaro.org> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1751678622089525986?= X-GMAIL-MSGID: =?utf-8?q?1751678622089525986?= Since we have a functioning RPM clock driver, let's make use of it and provide the real XO clock to clients, instead of the fixed-clock stub. Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sm6115.dtsi | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qcom/sm6115.dtsi index 81523ab7ff60..0c6d57a17bfc 100644 --- a/arch/arm64/boot/dts/qcom/sm6115.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi @@ -650,7 +650,7 @@ sdhc_1: mmc@4744000 { clocks = <&gcc GCC_SDCC1_AHB_CLK>, <&gcc GCC_SDCC1_APPS_CLK>, - <&xo_board>, + <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GCC_SDCC1_ICE_CORE_CLK>; clock-names = "iface", "core", "xo", "ice"; @@ -671,7 +671,9 @@ sdhc_2: mmc@4784000 { ; interrupt-names = "hc_irq", "pwr_irq"; - clocks = <&gcc GCC_SDCC2_AHB_CLK>, <&gcc GCC_SDCC2_APPS_CLK>, <&xo_board>; + clocks = <&gcc GCC_SDCC2_AHB_CLK>, + <&gcc GCC_SDCC2_APPS_CLK>, + <&rpmcc RPM_SMD_XO_CLK_SRC>; clock-names = "iface", "core", "xo"; pinctrl-0 = <&sdc2_state_on>; From patchwork Thu Dec 8 20:14:00 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 31487 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp405175wrr; Thu, 8 Dec 2022 12:22:19 -0800 (PST) X-Google-Smtp-Source: AA0mqf78lFzP8+8xp6qIAUbmMwzbqTASEzqOFVtTxIpLqXULEx/MVY+cCIAF6pXwTVBwHrl2u8rt X-Received: by 2002:a17:902:7c82:b0:189:760d:c5f2 with SMTP id y2-20020a1709027c8200b00189760dc5f2mr59534505pll.90.1670530939524; Thu, 08 Dec 2022 12:22:19 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1670530939; cv=none; d=google.com; s=arc-20160816; b=nnVxd9BkBXauM/XpYuErxxsk86wcTrSs7E6R3yvZGVzG4vT6t4q30h0j1c811PA3// mBFSdXVGwiDOhL/eh7nmMLoEyIrqi0QkfAQkwWRS2iAy+W0a812WqZkpvx4qX+gttTLh +Zayg0Q2VKvmW08tdg1BGr2oiW+jS0iqj2kVkQeLzKNlenZmqH94WpnXGpG4rpcP0Qbn YcSs+TaQiymkecloJk6hPMmlq/Qxhe2rO39R57BiqMdtXvczSp9LdlL2rP3pLonaNZ4O /MvUj+Kt9Qhqu4Fn2Bzxii5cQbd2BZdgIaPT1K37qdHygXE7yYHDwtiHOoeOQuq7bePR 7gzQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=tFihLnj80m7OVKSWSB5T98Aozczh+fP/nRP+nyh9qbw=; b=MKZAZffXw1XQK2QIpYnQtO2ffzDagc0YAIFd5vixdu22zc/Wpx0IZWKCCB3ouaO9So Nzg9uqMe8qPygVPXOmcilwl4Lw9piZiHXIqW4ZAZ4oZ7migD6stbqVSUvct4sTnJdjqF 5WGpWzTIfCvclnr5b4axYdQR6PXJ3xso+BORyibteZbxGg1T5lfNB2akf5WabNYTff1T 0yW9oSMTUPEq1lVLIDhYV/EirOk64PXB7iC6ZF2JnxZIJz1itECmWywCyjdQw8PpyZT3 iF87kQqULgcbkxRyeVVXVN+eKNpz1YzsOfAgP+JETMore4Z99+p0uqXmrYpEEcOqHTdm MLrQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=N1vZRVEW; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. 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[95.49.125.53]) by smtp.gmail.com with ESMTPSA id bi35-20020a0565120ea300b004ac6a444b26sm3466428lfb.141.2022.12.08.12.14.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 08 Dec 2022 12:14:18 -0800 (PST) From: Konrad Dybcio To: linux-arm-msm@vger.kernel.org, andersson@kernel.org, agross@kernel.org, krzysztof.kozlowski@linaro.org Cc: patches@linaro.org, Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Iskren Chernev , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 4/5] dt-bindings: arm: qcom: Add SM6115(P) and Lenovo Tab P11 Date: Thu, 8 Dec 2022 21:14:00 +0100 Message-Id: <20221208201401.530555-4-konrad.dybcio@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221208201401.530555-1-konrad.dybcio@linaro.org> References: <20221208201401.530555-1-konrad.dybcio@linaro.org> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1751678650562828007?= X-GMAIL-MSGID: =?utf-8?q?1751678650562828007?= Document SM6115P, an APQ version of SM6115, which in turn is more or less a beefier version of SM4250. Document Lenovo Tab P11 (J606F) as a SM6115P device. Add SM6115 to the msm-id list of shame. Signed-off-by: Konrad Dybcio Acked-by: Krzysztof Kozlowski Reviewed-by: Bhupesh Sharma --- Documentation/devicetree/bindings/arm/qcom.yaml | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index 27063a045bd0..0c7ad00586fa 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -62,6 +62,7 @@ description: | sdx65 sm4250 sm6115 + sm6115p sm6125 sm6350 sm6375 @@ -790,6 +791,12 @@ properties: - oneplus,billie2 - const: qcom,sm4250 + - items: + - enum: + - lenovo,j606f + - const: qcom,sm6115p + - const: qcom,sm6115 + - items: - enum: - sony,pdx201 @@ -931,6 +938,7 @@ allOf: - qcom,sdm845 - qcom,sdx55 - qcom,sdx65 + - qcom,sm6115 - qcom,sm6125 - qcom,sm6350 - qcom,sm7225 From patchwork Thu Dec 8 20:14:01 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 31489 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp405385wrr; Thu, 8 Dec 2022 12:22:44 -0800 (PST) X-Google-Smtp-Source: AA0mqf5BtqSS4cVxGaij/0nX3ARuiHxYC4kQJDT+6QwPyAk8tI+4pu5s853t1v7bOGDngBGOB+aF X-Received: by 2002:a63:1054:0:b0:42b:9219:d14e with SMTP id 20-20020a631054000000b0042b9219d14emr67859341pgq.176.1670530964327; Thu, 08 Dec 2022 12:22:44 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1670530964; cv=none; d=google.com; s=arc-20160816; b=EG6V/KCHMOimvhI/f4ah/3Zp1OV4ViLMSUHrRmb4a4PNb4ik3Ufx+4M0XvWkqU0PYt hhcJQp47FlGDFr2zNGlNNBg0euxxB/B1Ljq1NaigQZ+21NXbupNsUiQ2YAz1aO6JPMf0 Intk6SlUe8rAfjhwkO/bl1hvPU+NvzAhdfU6CPXpfVedgFlO30Hb9MBSN7GCi9ix7agU e0ArGRA5Bo8OpLzTNnekDVbERN0yddcbn/shrBRLopMpzNCcTSDMgKMf408STX1/eFsT 8Iciwryz7+fLY4sQ2fVg8iv3ZQqtjegFOVNAlfZsV7MOBec4j0NaVm328e1KdkWO+wn+ YvlA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=QE/MPVWrPkQi2tEjQtLjQ0ec0nKxppkiun4hqaN8bS0=; b=yYhNDCWAVa0Wkudd72XjcOSWj8GwZmrK8fy8fhtv7qZUYXiEs0p0LmaP2xhT/2fdtb oIjJs11gxMnrvCrC0OwoghSbywVtZOcOd0pRYtmIFnDsNnAHsJWjlggU1nFUEQshx03J 2UV8ZQ4uY2llJ8kCbs7kB1r3f60Zdx/FK4CCWysSkLptoOVzOZ3Pv9S/5HX2MuUUjH3V iB1cA1wx5ZKo9TrU4bqE/vBpWX9MhjMr4x6AO/eQzksDRt8iouFMaDsqatmfJfSZN7pW OdiGo/HNpze6TsGCezEqdA07kfsa1kPFfjWeSe+3G7HxhMNqWH9c8R5S7Jh2emg10OTF LqNg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=VfiUnEVp; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. 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[95.49.125.53]) by smtp.gmail.com with ESMTPSA id bi35-20020a0565120ea300b004ac6a444b26sm3466428lfb.141.2022.12.08.12.14.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 08 Dec 2022 12:14:20 -0800 (PST) From: Konrad Dybcio To: linux-arm-msm@vger.kernel.org, andersson@kernel.org, agross@kernel.org, krzysztof.kozlowski@linaro.org Cc: patches@linaro.org, Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Iskren Chernev , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 5/5] arm64: dts: qcom: Add Lenovo Tab P11 (J606F/XiaoXin Pad) dts Date: Thu, 8 Dec 2022 21:14:01 +0100 Message-Id: <20221208201401.530555-5-konrad.dybcio@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221208201401.530555-1-konrad.dybcio@linaro.org> References: <20221208201401.530555-1-konrad.dybcio@linaro.org> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1751678676421217646?= X-GMAIL-MSGID: =?utf-8?q?1751678676421217646?= Add an initial device tree for the Lenovo Tab P11. Currently it enables: - simplefb - SD Card slot via SDHCI2 - gpio-keys & PON keys - UFS - RPM regulators - USB2 This has been validated with a rev (62) device. You can check yours next to the serial no. on the sticker in the lower portion of the back side of your tablet. To get a successful boot run: cat arch/arm64/boot/Image.gz arch/arm64/boot/dts/qcom/\ sm6115p-lenovo-j606f.dtb > .Image.gz-dtb ~/mkbootimg/mkbootimg.py \ --kernel .Image.gz-dtb \ --ramdisk some/initrd.img \ --pagesize 4096 \ --base 0x0 \ --kernel_offset 0x8000 \ --ramdisk_offset 0x1000000 \ --tags_offset 0x100 \ --cmdline 'SOME_CMDLINE' \ --dtb_offset 0x1f00000 \ --header_version 1 \ --os_version 11 \ --os_patch_level 2022-11 \ -o j606f.img fastboot flash boot j606f.img fastboot flash dtbo empty.img fastboot flash recovery empty.img fastboot reboot Where empty.img is 2 zero-bytes. Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/Makefile | 1 + .../boot/dts/qcom/sm6115p-lenovo-j606f.dts | 290 ++++++++++++++++++ 2 files changed, 291 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sm6115p-lenovo-j606f.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 3e79496292e7..5d281436172d 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -156,6 +156,7 @@ dtb-$(CONFIG_ARCH_QCOM) += sdm845-shift-axolotl.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm850-lenovo-yoga-c630.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm850-samsung-w737.dtb dtb-$(CONFIG_ARCH_QCOM) += sm4250-oneplus-billie2.dtb +dtb-$(CONFIG_ARCH_QCOM) += sm6115p-lenovo-j606f.dtb dtb-$(CONFIG_ARCH_QCOM) += sm6125-sony-xperia-seine-pdx201.dtb dtb-$(CONFIG_ARCH_QCOM) += sm6350-sony-xperia-lena-pdx213.dtb dtb-$(CONFIG_ARCH_QCOM) += sm6375-sony-xperia-murray-pdx225.dtb diff --git a/arch/arm64/boot/dts/qcom/sm6115p-lenovo-j606f.dts b/arch/arm64/boot/dts/qcom/sm6115p-lenovo-j606f.dts new file mode 100644 index 000000000000..102730dd49a7 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sm6115p-lenovo-j606f.dts @@ -0,0 +1,290 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (c) 2022 Linaro Limited + */ + +/dts-v1/; + +#include "sm6115.dtsi" +#include "pm6125.dtsi" + +/ { + model = "Lenovo Tab P11"; + compatible = "lenovo,j606f", "qcom,sm6115p", "qcom,sm6115"; + chassis-type = "tablet"; + + /* required for bootloader to select correct board */ + qcom,msm-id = <445 0x10000>, <420 0x10000>; + qcom,board-id = <34 3>; + + aliases { + mmc0 = &sdhc_2; + }; + + chosen { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + framebuffer0: framebuffer@5c000000 { + compatible = "simple-framebuffer"; + reg = <0 0x5c000000 0 (2000 * 1200 * 4)>; + width = <1200>; + height = <2000>; + stride = <(1200 * 4)>; + format = "a8r8g8b8"; + clocks = <&gcc GCC_DISP_HF_AXI_CLK>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + label = "gpio-keys"; + + pinctrl-names = "default"; + pinctrl-0 = <&vol_up_n>; + + key-volume-up { + label = "Volume Up"; + linux,code = ; + gpios = <&pm6125_gpio 5 GPIO_ACTIVE_LOW>; + debounce-interval = <15>; + linux,can-disable; + gpio-key,wakeup; + }; + }; +}; + +&dispcc { + /* HACK: disable until a panel driver is ready to retain simplefb */ + status = "disabled"; +}; + +&pm6125_gpio { + vol_up_n: vol-up-n-state { + pins = "gpio5"; + function = "normal"; + power-source = <0>; + bias-pull-up; + input-enable; + }; +}; + +&pon_pwrkey { + status = "okay"; +}; + +&pon_resin { + linux,code = ; + status = "okay"; +}; + +&rpm_requests { + regulators-0 { + compatible = "qcom,rpm-pm6125-regulators"; + + pm6125_s6: s6 { + regulator-min-microvolt = <304000>; + regulator-max-microvolt = <1456000>; + }; + + pm6125_s7: s7 { + regulator-min-microvolt = <1280000>; + regulator-max-microvolt = <2080000>; + }; + + pm6125_s8: s8 { + regulator-min-microvolt = <1064000>; + regulator-max-microvolt = <1304000>; + }; + + pm6125_l1: l1 { + regulator-min-microvolt = <952000>; + regulator-max-microvolt = <1152000>; + }; + + pm6125_l4: l4 { + regulator-min-microvolt = <488000>; + regulator-max-microvolt = <1000000>; + }; + + pm6125_l5: l5 { + regulator-min-microvolt = <1648000>; + /* 3.056V capped to 2.96V for SDHCI */ + regulator-max-microvolt = <2960000>; + regulator-allow-set-load; + /* Broken hw, this one can't be turned off or SDHCI will break! */ + regulator-always-on; + }; + + pm6125_l6: l6 { + regulator-min-microvolt = <576000>; + regulator-max-microvolt = <656000>; + }; + + pm6125_l7: l7 { + /* 1.2V-1.304V fixed at 1.256V for SDHCI bias */ + regulator-min-microvolt = <1256000>; + regulator-max-microvolt = <1256000>; + /* + * TODO: SDHCI seems to also work with this one turned off, however + * there exists a possibility that it may not work with some very + * specific SDCard types, perhaps validating this against a wide + * range of models could rule that out, saving some power would + * certainly be nice.. + */ + regulator-always-on; + }; + + pm6125_l8: l8 { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <728000>; + }; + + pm6125_l9: l9 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2000000>; + }; + + pm6125_l10: l10 { + regulator-min-microvolt = <1704000>; + regulator-max-microvolt = <1904000>; + }; + + pm6125_l11: l11 { + regulator-min-microvolt = <1704000>; + regulator-max-microvolt = <1952000>; + }; + + pm6125_l12: l12 { + regulator-min-microvolt = <1624000>; + regulator-max-microvolt = <1984000>; + }; + + pm6125_l13: l13 { + regulator-min-microvolt = <1504000>; + regulator-max-microvolt = <1952000>; + }; + + pm6125_l14: l14 { + regulator-min-microvolt = <1704000>; + regulator-max-microvolt = <1904000>; + }; + + pm6125_l15: l15 { + regulator-min-microvolt = <2920000>; + regulator-max-microvolt = <3232000>; + }; + + pm6125_l16: l16 { + regulator-min-microvolt = <1704000>; + regulator-max-microvolt = <1904000>; + }; + + pm6125_l17: l17 { + regulator-min-microvolt = <1152000>; + regulator-max-microvolt = <1384000>; + }; + + pm6125_l18: l18 { + regulator-min-microvolt = <1104000>; + regulator-max-microvolt = <1312000>; + }; + + pm6125_l19: l19 { + regulator-min-microvolt = <1624000>; + regulator-max-microvolt = <3304000>; + }; + + pm6125_l20: l20 { + regulator-min-microvolt = <1624000>; + regulator-max-microvolt = <3304000>; + }; + + pm6125_l21: l21 { + regulator-min-microvolt = <2400000>; + regulator-max-microvolt = <3600000>; + }; + + pm6125_l22: l22 { + regulator-min-microvolt = <2952000>; + /* 3.304V capped to 2.96V for SDHCI */ + regulator-max-microvolt = <2960000>; + regulator-allow-set-load; + /* Broken hw, this one can't be turned off or SDHCI will break! */ + regulator-always-on; + }; + + pm6125_l23: l23 { + regulator-min-microvolt = <3200000>; + regulator-max-microvolt = <3400000>; + }; + + pm6125_l24: l24 { + regulator-min-microvolt = <2704000>; + regulator-max-microvolt = <3600000>; + }; + }; +}; + +&sdhc_2 { + cd-gpios = <&tlmm 88 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc2_state_on &sdc2_gate_pin>; + pinctrl-1 = <&sdc2_state_off>; + vmmc-supply = <&pm6125_l22>; + vqmmc-supply = <&pm6125_l5>; + no-sdio; + no-mmc; + status = "okay"; +}; + +&sleep_clk { + clock-frequency = <32764>; +}; + +&tlmm { + gpio-reserved-ranges = <14 4>; + + /* + * This is a wholly undocumented pin (other than a single vague "pwr-gpios" reference) + * that needs to be toggled for the SD Card slot to work properly.. + */ + sdc2_gate_pin: sdc2-gate-state { + pins = "gpio45"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + output-high; + }; +}; + +&ufs_mem_hc { + vcc-supply = <&pm6125_l24>; + vcc-max-microamp = <600000>; + vccq2-supply = <&pm6125_l11>; + vccq2-max-microamp = <600000>; + status = "okay"; +}; + +&ufs_mem_phy { + vdda-phy-supply = <&pm6125_l4>; + vdda-pll-supply = <&pm6125_l12>; + vddp-ref-clk-supply = <&pm6125_l18>; + status = "okay"; +}; + +&usb_1 { + status = "okay"; +}; + +&usb_1_hsphy { + vdd-supply = <&pm6125_l4>; + vdda-pll-supply = <&pm6125_l12>; + vdda-phy-dpdm-supply = <&pm6125_l15>; + status = "okay"; +}; + +&xo_board { + clock-frequency = <19200000>; +};