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[2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id s15-20020a508d0f000000b0044e946787a1si13261710eds.115.2022.09.25.19.05.43 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 25 Sep 2022 19:05:43 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 36F443858010 for ; Mon, 26 Sep 2022 02:05:41 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from loongson.cn (mail.loongson.cn [114.242.206.163]) by sourceware.org (Postfix) with ESMTP id E5AF33858CDA for ; Mon, 26 Sep 2022 02:05:14 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org E5AF33858CDA Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=loongson.cn Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=loongson.cn Received: from 5.5.5 (unknown [10.2.5.5]) by localhost.localdomain (Coremail) with SMTP id AQAAf8AxFeLTCDFjAf8hAA--.62649S2; Mon, 26 Sep 2022 10:05:11 +0800 (CST) From: Lulu Cheng To: gcc-patches@gcc.gnu.org, mliska@suse.cz Subject: [PATCH] LoongArch: Libitm add LoongArch support. Date: Mon, 26 Sep 2022 10:05:04 +0800 Message-Id: <20220926020504.791159-1-chenglulu@loongson.cn> X-Mailer: git-send-email 2.31.1 MIME-Version: 1.0 X-CM-TRANSID: AQAAf8AxFeLTCDFjAf8hAA--.62649S2 X-Coremail-Antispam: 1UD129KBjvJXoW3JF15GF45tw1DWr17tF4fZrb_yoWfGFyrpF WxAr45Gr48KrW3G3s7JrWYgF15Gas5ZFykJr1agry2vrW5C3W0vFn3KFy3Ka9Yq3WrGryj va4F934DuFnruFJanT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUkq14x267AKxVWUJVW8JwAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2ocxC64kIII0Yj41l84x0c7CEw4AK67xGY2AK02 1l84ACjcxK6xIIjxv20xvE14v26ryj6F1UM28EF7xvwVC0I7IYx2IY6xkF7I0E14v26r4U JVWxJr1l84ACjcxK6I8E87Iv67AKxVW8Jr0_Cr1UM28EF7xvwVC2z280aVCY1x0267AKxV WxJr0_GcWle2I262IYc4CY6c8Ij28IcVAaY2xG8wAqx4xG64xvF2IEw4CE5I8CrVC2j2Wl Yx0E2Ix0cI8IcVAFwI0_JrI_JrylYx0Ex4A2jsIE14v26r1j6r4UMcvjeVCFs4IE7xkEbV WUJVW8JwACjcxG0xvY0x0EwIxGrwACjI8F5VA0II8E6IAqYI8I648v4I1lc2xSY4AK6svP MxAIw28IcxkI7VAKI48JMxC20s026xCaFVCjc4AY6r1j6r4UMI8I3I0E5I8CrVAFwI0_Jr 0_Jr4lx2IqxVCjr7xvwVAFwI0_JrI_JrWlx4CE17CEb7AF67AKxVWUAVWUtwCIc40Y0x0E wIxGrwCI42IY6xIIjxv20xvE14v26r1j6r1xMIIF0xvE2Ix0cI8IcVCY1x0267AKxVW8JV WxJwCI42IY6xAIw20EY4v20xvaj40_Jr0_JF4lIxAIcVC2z280aVAFwI0_Jr0_Gr1lIxAI cVC2z280aVCY1x0267AKxVW8JVW8JrUvcSsGvfC2KfnxnUUI43ZEXa7VUbWCJPUUUUU== X-CM-SenderInfo: xfkh0wpoxo3qxorr0wxvrqhubq/ X-Spam-Status: No, score=-12.6 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_SHORT, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Lulu Cheng , xuchenghua@loongson.cn Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1744996080136107971?= X-GMAIL-MSGID: =?utf-8?q?1744996080136107971?= Co-Authored-By: Yang Yujie libitm/ChangeLog: * configure.tgt: Add loongarch support. * config/loongarch/asm.h: New file. * config/loongarch/sjlj.S: New file. * config/loongarch/target.h: New file. --- libitm/config/loongarch/asm.h | 54 +++++++++++++ libitm/config/loongarch/sjlj.S | 127 +++++++++++++++++++++++++++++++ libitm/config/loongarch/target.h | 50 ++++++++++++ libitm/configure.tgt | 2 + 4 files changed, 233 insertions(+) create mode 100644 libitm/config/loongarch/asm.h create mode 100644 libitm/config/loongarch/sjlj.S create mode 100644 libitm/config/loongarch/target.h diff --git a/libitm/config/loongarch/asm.h b/libitm/config/loongarch/asm.h new file mode 100644 index 00000000000..a8e3304bb19 --- /dev/null +++ b/libitm/config/loongarch/asm.h @@ -0,0 +1,54 @@ +/* Copyright (C) 2022 Free Software Foundation, Inc. + Contributed by Loongson Co. Ltd. + + This file is part of the GNU Transactional Memory Library (libitm). + + Libitm is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + Libitm is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. See the GNU General Public License for + more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + . */ + +#ifndef _LA_ASM_H +#define _LA_ASM_H + +#if defined(__loongarch_lp64) +# define GPR_L ld.d +# define GPR_S st.d +# define SZ_GPR 8 +# define ADDSP(si) addi.d $sp, $sp, si +#elif defined(__loongarch64_ilp32) +# define GPR_L ld.w +# define GPR_S st.w +# define SZ_GPR 4 +# define ADDSP(si) addi.w $sp, $sp, si +#else +# error Unsupported GPR size (must be 64-bit or 32-bit). +#endif + +#if defined(__loongarch_double_float) +# define FPR_L fld.d +# define FPR_S fst.d +# define SZ_FPR 8 +#elif defined(__loongarch_single_float) +# define FPR_L fld.s +# define FPR_S fst.s +# define SZ_FPR 4 +#else +# define SZ_FPR 0 +#endif + +#endif /* _LA_ASM_H */ diff --git a/libitm/config/loongarch/sjlj.S b/libitm/config/loongarch/sjlj.S new file mode 100644 index 00000000000..a5f9fadde34 --- /dev/null +++ b/libitm/config/loongarch/sjlj.S @@ -0,0 +1,127 @@ +/* Copyright (C) 2022 Free Software Foundation, Inc. + Contributed by Loongson Co. Ltd. + + This file is part of the GNU Transactional Memory Library (libitm). + + Libitm is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + Libitm is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + . */ + +#include "asmcfi.h" +#include "asm.h" + + .text + .align 2 + .global _ITM_beginTransaction + .type _ITM_beginTransaction, @function + +_ITM_beginTransaction: + cfi_startproc + move $r5, $sp + ADDSP(-(12*SZ_GPR+8*SZ_FPR)) + cfi_adjust_cfa_offset(12*SZ_GPR+8*SZ_FPR) + + /* Frame Pointer */ + GPR_S $fp, $sp, 0*SZ_GPR + cfi_rel_offset(22, 0) + + /* Return Address */ + GPR_S $r1, $sp, 1*SZ_GPR + cfi_rel_offset(1, SZ_GPR) + + /* Caller's $sp */ + GPR_S $r5, $sp, 2*SZ_GPR + + /* Callee-saved scratch GPRs (r23-r31) */ + GPR_S $s0, $sp, 3*SZ_GPR + GPR_S $s1, $sp, 4*SZ_GPR + GPR_S $s2, $sp, 5*SZ_GPR + GPR_S $s3, $sp, 6*SZ_GPR + GPR_S $s4, $sp, 7*SZ_GPR + GPR_S $s5, $sp, 8*SZ_GPR + GPR_S $s6, $sp, 9*SZ_GPR + GPR_S $s7, $sp, 10*SZ_GPR + GPR_S $s8, $sp, 11*SZ_GPR + +#if !defined(__loongarch_soft_float) + /* Callee-saved scratch FPRs (f24-f31) */ + FPR_S $f24, $sp, 12*SZ_GPR + 0*SZ_FPR + FPR_S $f25, $sp, 12*SZ_GPR + 1*SZ_FPR + FPR_S $f26, $sp, 12*SZ_GPR + 2*SZ_FPR + FPR_S $f27, $sp, 12*SZ_GPR + 3*SZ_FPR + FPR_S $f28, $sp, 12*SZ_GPR + 4*SZ_FPR + FPR_S $f29, $sp, 12*SZ_GPR + 5*SZ_FPR + FPR_S $f30, $sp, 12*SZ_GPR + 6*SZ_FPR + FPR_S $f31, $sp, 12*SZ_GPR + 7*SZ_FPR +#endif + move $fp, $sp + + /* Invoke GTM_begin_transaction with the struct we've just built. */ + move $r5, $sp + bl %plt(GTM_begin_transaction) + + /* Return. (no call-saved scratch reg needs to be restored here) */ + GPR_L $fp, $sp, 0*SZ_GPR + cfi_restore(22) + GPR_L $r1, $sp, 1*SZ_GPR + cfi_restore(1) + + ADDSP(12*SZ_GPR+8*SZ_FPR) + cfi_adjust_cfa_offset(-(12*SZ_GPR+8*SZ_FPR)) + + jr $r1 + cfi_endproc + .size _ITM_beginTransaction, . - _ITM_beginTransaction + + .align 2 + .global GTM_longjmp + .hidden GTM_longjmp + .type GTM_longjmp, @function + +GTM_longjmp: + cfi_startproc + GPR_L $s0, $r5, 3*SZ_GPR + GPR_L $s1, $r5, 4*SZ_GPR + GPR_L $s2, $r5, 5*SZ_GPR + GPR_L $s3, $r5, 6*SZ_GPR + GPR_L $s4, $r5, 7*SZ_GPR + GPR_L $s5, $r5, 8*SZ_GPR + GPR_L $s6, $r5, 9*SZ_GPR + GPR_L $s7, $r5, 10*SZ_GPR + GPR_L $s8, $r5, 11*SZ_GPR + + FPR_L $f24, $r5, 12*SZ_GPR + 0*SZ_FPR + FPR_L $f25, $r5, 12*SZ_GPR + 1*SZ_FPR + FPR_L $f26, $r5, 12*SZ_GPR + 2*SZ_FPR + FPR_L $f27, $r5, 12*SZ_GPR + 3*SZ_FPR + FPR_L $f28, $r5, 12*SZ_GPR + 4*SZ_FPR + FPR_L $f29, $r5, 12*SZ_GPR + 5*SZ_FPR + FPR_L $f30, $r5, 12*SZ_GPR + 6*SZ_FPR + FPR_L $f31, $r5, 12*SZ_GPR + 7*SZ_FPR + + GPR_L $r7, $r5, 2*SZ_GPR + GPR_L $fp, $r5, 0*SZ_GPR + GPR_L $r1, $r5, 1*SZ_GPR + cfi_def_cfa(5, 0) + move $sp, $r7 + jr $r1 + cfi_endproc + .size GTM_longjmp, . - GTM_longjmp + +#ifdef __linux__ +.section .note.GNU-stack, "", @progbits +#endif diff --git a/libitm/config/loongarch/target.h b/libitm/config/loongarch/target.h new file mode 100644 index 00000000000..0c5cf3ada57 --- /dev/null +++ b/libitm/config/loongarch/target.h @@ -0,0 +1,50 @@ +/* Copyright (C) 2022 Free Software Foundation, Inc. + Contributed by Loongson Co. Ltd. + + This file is part of the GNU Transactional Memory Library (libitm). + + Libitm is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + Libitm is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. See the GNU General Public License for + more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + . */ + +namespace GTM HIDDEN { + +typedef struct gtm_jmpbuf + { + long int fp; /* Frame Pointer: r22 */ + long int pc; /* Return Address: r1 */ + void *cfa; /* CFA: r3 */ + long int gpr[9]; /* Callee-saved scratch GPRs: r23(s0)-r31(s8) */ + + /* Callee-saved scratch FPRs: f24-f31 */ +#if defined(__loongarch_double_float) + double fpr[8]; +#elif defined(__loongarch_single_float) + float fpr[8]; +#endif + } gtm_jmpbuf; + +#define HW_CACHELINE_SIZE 128 + +static inline void +cpu_relax (void) +{ + __asm__ volatile ("" : : : "memory"); +} + +} // namespace GTM diff --git a/libitm/configure.tgt b/libitm/configure.tgt index 06e90973ef3..4c0e78cff42 100644 --- a/libitm/configure.tgt +++ b/libitm/configure.tgt @@ -80,6 +80,8 @@ EOF ARCH=x86 ;; + loongarch*) ARCH=loongarch ;; + sh*) ARCH=sh ;; sparc)